Semiconductor memory

Abstract

To provide a semiconductor memory device with superior characteristics. [Solution] The semiconductor memory device of the embodiment comprises a semiconductor layer extending in a first direction, a first gate electrode layer, a second gate electrode layer provided spaced apart from the first gate electrode layer in the first direction, a gate insulating layer provided between the first gate electrode layer and the semiconductor layer and containing hafnium (Hf) and oxygen (O), and containing a first crystal in an orthorhombic or trigonal system, and a metal silicide layer provided between the first gate electrode layer and the gate insulating layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices.

Background Art

[0002] Ferroelectric memories have attracted attention as non-volatile memories. For example, there is a three-terminal Ferroelectric FET (FeFET) type memory in which a ferroelectric layer is applied to the gate insulating layer of a Field Effect Transistor (FET) type transistor to modulate the threshold voltage of the transistor. The threshold voltage of the transistor is modulated by changing the polarization state of the ferroelectric layer.

[0003] A three-dimensional NAND flash memory in which memory cells are arranged three-dimensionally realizes high integration and low cost. In a three-dimensional NAND flash memory, for example, memory holes penetrating the stacked body are formed in a stacked body in which a plurality of insulating layers and a plurality of gate electrode layers are alternately stacked. As a memory cell of the three-dimensional NAND flash memory, a three-terminal type memory of the FeFET type can be applied.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device with excellent characteristics.

Means for Solving the Problems

[0006] The semiconductor memory device of the embodiment includes a semiconductor layer extending in a first direction, a first gate electrode layer, a second gate electrode layer provided spaced apart from the first gate electrode layer in the first direction, a gate insulating layer provided between the first gate electrode layer and the semiconductor layer, comprising hafnium (Hf) and oxygen (O), and including a first crystal in an orthorhombic or trigonal system, and a metal silicide layer provided between the first gate electrode layer and the gate insulating layer. [Brief explanation of the drawing]

[0007] [Figure 1] Circuit diagram of a memory cell array of a semiconductor memory device according to the first embodiment. [Figure 2] A schematic cross-sectional view of a memory cell array of a semiconductor memory device according to the first embodiment. [Figure 3] A schematic cross-sectional view of a memory cell of a semiconductor memory device according to the first embodiment. [Figure 4] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 5] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 6] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 7] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 8] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 9] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 10] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 11] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 12] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 13] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 14]Schematic cross-sectional view of a memory cell array of a semiconductor memory device of a comparative example. [Figure 15] Schematic cross-sectional view of a memory cell of a semiconductor memory device of a comparative example. [Figure 16] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of a comparative example. [Figure 17] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of a comparative example. [Figure 18] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of a comparative example. [Figure 19] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of a comparative example. [Figure 20] Schematic cross-sectional view of a memory cell array of a semiconductor memory device of a modified example of the first embodiment. [Figure 21] Schematic cross-sectional view of a memory cell of a semiconductor memory device of a modified example of the first embodiment. [Figure 22] Schematic cross-sectional view of a memory cell array of a semiconductor memory device of the second embodiment. [Figure 23] Schematic cross-sectional view of a memory cell of a semiconductor memory device of the second embodiment. [Figure 24] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 25] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 26] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 27] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 28] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 29] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 30] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 31] Schematic cross-sectional view showing a manufacturing method of a semiconductor memory device of the second embodiment. [Figure 32]A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 33] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 34] A schematic cross-sectional view showing a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 35] Circuit diagram of a memory cell array of a semiconductor memory device according to the third embodiment. [Figure 36] A schematic cross-sectional view of a memory cell array of a semiconductor memory device according to the third embodiment. [Figure 37] A schematic cross-sectional view of a memory cell array of a semiconductor memory device according to the third embodiment. [Figure 38] A schematic cross-sectional view of a memory cell of a semiconductor memory device according to the third embodiment. [Figure 39] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 40] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 41] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 42] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 43] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 44] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 45] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 46] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 47] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 48] A schematic cross-sectional view showing a semiconductor memory device manufacturing method according to the third embodiment. [Figure 49] A diagram illustrating the operation and effects of the semiconductor memory device according to the third embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numeral, and components that have already been described may be omitted from the description as appropriate.

[0009] Furthermore, for convenience, the terms "upper" or "lower" may be used in this specification. "Upper" or "lower" are terms that indicate relative positions within the drawings and do not define positions relative to gravity.

[0010] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor memory device described herein can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or electron energy loss spectroscopy (EELS). Furthermore, measurements of the thickness of the components constituting the semiconductor memory device, the distance between components, etc., can be performed, for example, by a transmission electron microscope (TEM). Furthermore, the crystal structure of the constituent materials of semiconductor memory devices and the relative abundance of these crystal structures can be identified and determined using methods such as transmission electron microscopy, X-ray diffraction (XRD), electron beam diffraction (EBD), X-ray photoelectron spectroscopy (XPS), or synchrotron radiation X-ray absorption fine structure (XAFS). The crystal structure of the constituent materials of semiconductor memory devices and the relative abundance of these crystal structures can also be identified and determined using methods such as Automated Crystal Orientation and Phase Mapping in TEM (ACOM-TEM) using a TEM.

[0011] In this specification, "ferroelectric" refers to a material that exhibits spontaneous polarization (autovoltaic polarization) even without an externally applied electric field, and whose polarization reverses when an externally applied electric field is applied. In this specification, "paraelectric" refers to a material that exhibits polarization when an electric field is applied, and whose polarization disappears when the electric field is removed.

[0012] (First Embodiment) The semiconductor memory device of the first embodiment includes a semiconductor layer extending in a first direction, a first gate electrode layer, a second gate electrode layer provided spaced apart from the first gate electrode layer in the first direction, a gate insulating layer provided between the first gate electrode layer and the semiconductor layer and containing hafnium (Hf) and oxygen (O), and containing a first crystal in an orthorhombic or trigonal system, and a metal silicide layer provided between the first gate electrode layer and the gate insulating layer.

[0013] The semiconductor memory device of the first embodiment is a three-dimensional NAND flash memory having memory cells with a Metal Ferroelectrics Semiconductor structure (MFS structure).

[0014] Figure 1 is a circuit diagram of a memory cell array of a semiconductor memory device according to the first embodiment.

[0015] The memory cell array 100 of the three-dimensional NAND flash memory of the first embodiment comprises a plurality of word lines WL, a common source line CSL, a source selection gate line SGS, a plurality of channel layers CL, a plurality of drain selection gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS, as shown in Figure 1.

[0016] The z-direction in Figure 1 is an example of the first direction. The y-direction in Figure 1 is an example of the second direction. The x-direction in Figure 1 is an example of the third direction. Note that the first direction is a concept that includes the z-direction and its inverse direction. Also, the second direction is a concept that includes the y-direction and its inverse direction. Also, the third direction is a concept that includes the x-direction and its inverse direction.

[0017] Multiple word lines WL are stacked in the z direction. Multiple word lines WL are spaced apart in the z direction. Multiple channel layers CL extend in the z direction. Multiple bit lines BL extend in the x direction.

[0018] As shown in Figure 1, a memory string MS consists of a source selection transistor SST connected in series between a common source line CSL and a bit line BL, multiple memory cell transistors MT, and a drain selection transistor SDT. One memory string MS is selected by the bit line BL and the drain selection gate line SGD, and one memory cell transistor MT can be selected by the word line WL.

[0019] Figures 2(a) and 2(b) are schematic cross-sectional views of a memory cell array of a semiconductor memory device according to the first embodiment. Figures 2(a) and 2(b) show cross-sections of multiple memory cells in a single memory string MS enclosed by a dotted line, for example, within the memory cell array 100 of Figure 1.

[0020] Figure 2(a) is a yz cross-sectional view of the memory cell array 100. Figure 2(a) is the BB' cross-section of Figure 2(b). Figure 2(b) is an xy cross-sectional view of the memory cell array 100. Figure 2(b) is the AA' cross-section of Figure 2(a). In Figure 2(a), the area enclosed by the dashed line represents a single memory cell.

[0021] Figure 3 is a schematic cross-sectional view of a memory cell of a semiconductor memory device according to the first embodiment. Figure 3 is an enlarged cross-sectional view of a portion of two memory cells.

[0022] As shown in Figures 2(a) and 2(b), the memory cell array 100 comprises multiple word lines WL, a semiconductor layer 10, a gate insulating layer 12, a metal silicide layer 13, a first interface insulating layer 14, a second interface insulating layer 16, and multiple interlayer insulating layers 18. The multiple word lines WL and the multiple interlayer insulating layers 18 constitute a laminate 30. The word lines WL include a barrier metal film 41 and a metal region 42.

[0023] The interlayer insulating layer 18 is an example of a first insulating layer. The barrier metal film 41 is an example of a conductive film.

[0024] As shown in Figure 3, the two memory cells comprise a first word line WL1, a second word line WL2, a semiconductor layer 10, a gate insulating layer 12, a metal silicide layer 13, a first interface insulating layer 14, a second interface insulating layer 16, and a plurality of interlayer insulating layers 18.

[0025] The first word line WL1 is one of several word lines. The first word line WL1 is an example of the first gate electrode layer. The second word line WL2 is one of several word lines. The second word line WL2 is an example of the second gate electrode layer.

[0026] The word line WL and the interlayer insulating layer 18 are provided, for example, on a semiconductor substrate (not shown). The word line WL and the interlayer insulating layer 18 are provided, for example, in the z direction with respect to the semiconductor substrate (not shown).

[0027] Word lines WL and interlayer insulating layers 18 are alternately stacked on a semiconductor substrate in the z direction. The word lines WL are spaced apart in the z direction. For example, a second word line WL2 is provided spaced apart in the z direction from the first word line WL1. Multiple word lines WL and multiple interlayer insulating layers 18 constitute a laminate 30.

[0028] The word line WL is a plate-shaped conductor. The word line WL is, for example, a metal, a metal nitride, a metal carbide, or a semiconductor. The word line WL includes, for example, a barrier metal film 41 and a metal region 42. The barrier metal film 41 is provided between the metal region 42 and the gate insulating layer 12.

[0029] The barrier metal film 41 includes, for example, a metal, a metal nitride, or a metal carbide. The barrier metal film 41 includes, for example, titanium nitride, tungsten nitride, or tantalum nitride. The barrier metal film 41 is, for example, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.

[0030] The metallic region 42 is a metal. The metallic region 42 includes, for example, tungsten (W) or molybdenum (Mo). The metallic region 42 is, for example, a tungsten layer or a molybdenum layer. The metallic region 42 includes, for example, a different metallic element from the barrier metal film 41.

[0031] The word line WL functions as a control electrode for the memory cell transistor MT.

[0032] The length of the word line WL in the z direction is, for example, between 5 nm and 40 nm.

[0033] The interlayer insulating layer 18 separates word wires WL from each other. For example, the interlayer insulating layer 18 separates the first word wire WL1 from the second word wire WL2. The interlayer insulating layer 18 is, for example, an oxide, an oxynitride, or a nitride. For example, the interlayer insulating layer 18 is silicon oxide.

[0034] The length of the interlayer insulating layer 18 in the z direction is, for example, between 5 nm and 40 nm.

[0035] The semiconductor layer 10 is provided within the laminate 30. The semiconductor layer 10 extends in the z direction. The semiconductor layer 10 penetrates the laminate 30. The semiconductor layer 10 is, for example, cylindrical or cylindrical. The semiconductor layer 10 corresponds to the channel layer CL. For example, an insulating film may be provided inside the cylindrical semiconductor layer 10. The insulating film is, for example, silicon oxide.

[0036] The semiconductor layer 10 is, for example, a polycrystalline semiconductor. The semiconductor layer 10 is, for example, polycrystalline silicon. The semiconductor layer 10 functions as the channel of the memory cell transistor MT.

[0037] The gate insulating layer 12 is provided between the word line WL and the semiconductor layer 10. The gate insulating layer 12 is provided between the first word line WL1 and the semiconductor layer 10. The gate insulating layer 12 is provided between the second word line WL2 and the semiconductor layer 10.

[0038] The gate insulating layer 12 contains hafnium (Hf) and oxygen (O). For example, among the atomic concentrations of elements other than oxygen (O) contained in the gate insulating layer 12, the atomic concentration of hafnium (Hf) is the highest. The proportion of the atomic concentration of hafnium (Hf) in the total atomic concentrations of elements other than oxygen (O) contained in the gate insulating layer 12 is, for example, 90% or more.

[0039] The gate insulating layer 12 contains hafnium oxide. For example, the gate insulating layer 12 is mainly composed of hafnium oxide. When we say that the gate insulating layer 12 is mainly composed of hafnium oxide, it means that hafnium oxide has the highest molar ratio among the substances contained in the gate insulating layer 12. For example, the molar ratio of hafnium oxide contained in the gate insulating layer 12 is 90% or more.

[0040] The gate insulating layer 12 contains a ferroelectric material. The gate insulating layer 12 is, for example, a ferroelectric layer.

[0041] The gate insulating layer 12 is crystalline. The gate insulating layer 12 contains a first crystal in the orthorhombic or trigonal system. The first crystal is hafnium oxide. Hafnium oxide is ferroelectric when it is in the orthorhombic or trigonal system. Hafnium oxide is ferroelectric when it is in the orthorhombic or trigonal system. The first crystal is ferroelectric.

[0042] Hafnium oxide exhibits ferroelectric properties, for example, when it is a crystal in the orthorhombic III system (space group Pbc21, space group number 29) or the trigonal system (space group R3m or P3 or R3, space group number 160 or 143 or 146).

[0043] Hafnium oxide does not possess ferroelectric properties when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. Hafnium oxide is paraelectric when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. Crystal systems other than orthorhombic or trigonal include cubic, hexagonal, tetragonal, monoclinic, and triclinic systems.

[0044] The gate insulating layer 12 includes, for example, a second crystal of a cubic, hexagonal, tetragonal, monoclinic, or triclinic crystal system. The second crystal is a paraelectric material.

[0045] The gate insulating layer 12 primarily consists of a first crystal of the orthorhombic or trigonal system. Having a first crystal of the orthorhombic or trigonal system as the primary constituent means that, among the materials constituting the gate insulating layer 12, the first crystal of the orthorhombic or trigonal system exhibits the largest proportion. In other words, among the materials constituting the gate insulating layer 12, there is no material that exhibits a larger proportion than the first crystal of the orthorhombic or trigonal system. For example, among the materials constituting the gate insulating layer 12, the first crystal of the ferroelectric system has a larger proportion than the second crystal of the paraelectric system. Also, for example, among the crystals constituting the gate insulating layer 12, the first crystal of the ferroelectric system has the largest proportion.

[0046] The gate insulating layer 12 is composed primarily of a ferroelectric material, for example. The proportion of ferroelectric material in the gate insulating layer 12 is greater than the proportion of paraelectric material in the gate insulating layer 12.

[0047] The gate insulating layer 12 contains at least one additive element selected from the group consisting of, for example, silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Ru). The hafnium oxide contained in the gate insulating layer 12 contains the above-mentioned additive element. For example, the inclusion of the above-mentioned additive element in hafnium oxide makes it easier for ferroelectricity to be exhibited in hafnium oxide.

[0048] The first interface insulating layer 14 is provided between the first word line WL1 and the semiconductor layer 10. The first interface insulating layer 14 is provided between the second word line WL2 and the semiconductor layer 10. The first interface insulating layer 14 is provided between the gate insulating layer 12 and the semiconductor layer 10.

[0049] The material of the first interface insulating layer 14 is, for example, different from the material of the gate insulating layer 12. The first interface insulating layer 14 is, for example, an oxide, an oxynitride, or a nitride. The first interface insulating layer 14 is, for example, silicon oxide.

[0050] It is also possible to omit the first interface insulating layer 14 and have a structure in which the gate insulating layer 12 is in direct contact with the semiconductor layer 10.

[0051] The second interface insulating layer 16 is provided between the first word wire WL1 and the gate insulating layer 12. The second interface insulating layer 16 is provided between the second word wire WL2 and the gate insulating layer 12. The second interface insulating layer 16 is provided between the metal silicide layer 13 and the gate insulating layer 12.

[0052] The material of the second interface insulating layer 16 is, for example, different from the material of the gate insulating layer 12. The second interface insulating layer 16 is, for example, an oxide, an oxynitride, or a nitride. The second interface insulating layer 16 is, for example, silicon oxide or aluminum oxide.

[0053] It is also possible to omit the second interface insulating layer 16 and have a structure in which the gate insulating layer 12 is in direct contact with the metal silicide layer 13.

[0054] The metal silicide layer 13 is provided between the first word wire WL1 and the gate insulating layer 12. The metal silicide layer 13 is provided between the second word wire WL2 and the gate insulating layer 12. The metal silicide layer 13 is provided between the first word wire WL1 and the second interface insulating layer 16. The metal silicide layer 13 is provided between the second word wire WL2 and the second interface insulating layer 16.

[0055] The metal silicide layer 13 is in contact with, for example, the first word wire WL1. The metal silicide layer 13 is in contact with, for example, the second word wire WL2. The metal silicide layer 13 is in contact with, for example, the second interface insulating layer 16.

[0056] The metal silicide layer 13 is divided in the z direction. The metal silicide layer 13 provided between the first word wire WL1 and the gate insulating layer 12 and the metal silicide layer 13 provided between the second word wire WL2 and the gate insulating layer 12 are separated in the z direction. An interlayer insulating layer 18 is provided between the metal silicide layer 13 provided between the first word wire WL1 and the gate insulating layer 12 and the metal silicide layer 13 provided between the second word wire WL2 and the gate insulating layer 12.

[0057] The metal silicide layer 13 is not provided between the interlayer insulating layer 18 and the semiconductor layer 10 in the y-direction. The metal silicide layer 13 is not provided between the interlayer insulating layer 18 and the gate insulating layer 12 in the y-direction. The metal silicide layer 13 is not provided between the interlayer insulating layer 18 and the second interface insulating layer 16 in the y-direction. The metal silicide layer 13 is in contact with the interlayer insulating layer 18, for example, in the z-direction.

[0058] The metal silicide layer 13 surrounds the gate insulating layer 12 in a cross-section perpendicular to the z-direction. The metal silicide layer 13 surrounds the semiconductor layer 10 in a cross-section perpendicular to the z-direction.

[0059] The metal silicide layer 13 contains metal silicide. The metal silicide layer 13 contains silicon (Si) and a metal element. The metal element is, for example, titanium (Ti) or tungsten (W). The metal silicide layer 13 contains, for example, titanium silicide or tungsten silicide. The metal silicide layer 13 is, for example, a titanium silicide layer or a tungsten silicide layer.

[0060] In the memory cell of the first embodiment, for example, the polarization reversal state of the ferroelectric material contained in the gate insulating layer 12 is controlled by a voltage applied between the first word line WL1 and the semiconductor layer 10. The polarization reversal state of the gate insulating layer 12 changes the threshold voltage of the memory cell transistor MT. As the threshold voltage of the memory cell transistor MT changes, the on-current of the memory cell transistor MT changes. For example, if a state with a high threshold voltage and low on-current is defined as data "0", and a state with a low threshold voltage and high on-current is defined as data "1", the memory cell can store 1-bit data of "0" and "1".

[0061] Next, an example of a method for manufacturing a semiconductor memory device according to the first embodiment will be described. Figures 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to the first embodiment. Figures 4 to 13 each show a cross-section corresponding to Figure 2(a). Figures 4 to 13 show an example of a method for manufacturing a memory cell array 100 of a semiconductor memory device.

[0062] First, silicon oxide layers 50 and polycrystalline silicon layers 52 are alternately stacked on a semiconductor substrate (not shown) (Figure 4). The silicon oxide layers 50 and polycrystalline silicon layers 52 form a laminate 30. The silicon oxide layers 50 and polycrystalline silicon layers 52 are formed, for example, by the Chemical Vapor Deposition (CVD) method. A portion of the silicon oxide layer 50 eventually becomes an interlayer insulating layer 18.

[0063] Next, openings 54 are formed in the silicon oxide layer 50 and the polycrystalline silicon layer 52 (Figure 5). The openings 54 are formed, for example, by lithography and reactive ion etching (RIE).

[0064] Next, a titanium film 56 is formed inside the opening 54 (Figure 6). The titanium film 56 is formed, for example, by a CVD method.

[0065] Next, a heat treatment is performed to react the polycrystalline silicon layer 52 with the titanium film 56 to form a titanium silicide layer 58 (Figure 7). The heat treatment is carried out, for example, in an inert gas atmosphere at a temperature between 600°C and 800°C. The titanium silicide layer 58 ultimately becomes a metal silicide layer 13.

[0066] Next, the unreacted titanium film 56 is removed (Figure 8). The titanium film 56 is removed, for example, by a wet etching method.

[0067] Next, a first silicon oxide film 60 is formed inside the opening 54 (Figure 9). The first silicon oxide film 60 is formed, for example, by a CVD method. The first silicon oxide film 60 ultimately becomes the second interface insulating layer 16.

[0068] Next, a hafnium oxide film 62 is formed in the opening 54 (Figure 10). The hafnium oxide film 62 is formed, for example, by the Atomic Layer Deposition (ALD) method. For example, silicon (Si) is added as an additive element to the hafnium oxide film 62. The hafnium oxide film 62 ultimately becomes the gate insulating layer 12.

[0069] Next, a second silicon oxide film 64 is formed on the inner surface of the opening 54. The second silicon oxide film 64 is formed, for example, by a CVD method. The second silicon oxide film 64 ultimately becomes the first interface insulating layer 14.

[0070] Next, a polycrystalline silicon film 66 is formed in the opening 54 to fill the opening 54 (Figure 11). The polycrystalline silicon film 66 is formed, for example, by the CVD method. The polycrystalline silicon film 66 ultimately becomes the semiconductor layer 10.

[0071] Next, the hafnium oxide film 62 is subjected to heat treatment to crystallize it. This heat treatment is known as crystallization annealing. By crystallizing the hafnium oxide film 62, a first crystal of the orthorhombic or trigonal system is formed within the hafnium oxide film 62. The heat treatment is carried out, for example, in an inert gas atmosphere at a temperature between 800°C and 1000°C.

[0072] Next, the polycrystalline silicon layer 52 is selectively removed by wet etching using etching grooves (not shown) (Figure 12).

[0073] Next, a titanium nitride film 68 and a tungsten film 70 are formed on the titanium silicide layer 58 (Figure 13). The titanium nitride film 68 and the tungsten film 70 are formed, for example, by the CVD method. The titanium nitride film 68 and the tungsten film 70 ultimately become word lines WL. The titanium nitride film 68 ultimately becomes a barrier metal film 41. The tungsten film 70 ultimately becomes a metallic region 42.

[0074] Furthermore, the heat treatment to crystallize the hafnium oxide film 62 can also be performed, for example, immediately after the formation of the second silicon oxide film 64. The heat treatment to crystallize the hafnium oxide film 62 can be performed, for example, between the formation of the second silicon oxide film 64 and before the removal of the polycrystalline silicon layer 52.

[0075] The semiconductor memory device of the first embodiment is manufactured by the manufacturing method described above.

[0076] Next, the operation and effects of the semiconductor memory device according to the first embodiment will be described.

[0077] Figures 14(a) and 14(b) are schematic cross-sectional views of the memory cell array of the comparative example semiconductor memory device. Figure 14(a) is a yz cross-sectional view of the memory cell array 900 of the comparative example. Figure 14(a) is the BB' cross-section of Figure 14(b). Figure 14(b) is an xy cross-sectional view of the memory cell array 900. Figure 14(b) is the AA' cross-section of Figure 14(a). In Figure 14(a), the area enclosed by the dashed line is a single memory cell. Figures 14(a) and 14(b) correspond to Figures 2(a) and 2(b) of the first embodiment.

[0078] Figure 15 is a schematic cross-sectional view of a memory cell of a comparative example semiconductor memory device. Figure 15 is an enlarged cross-sectional view of a portion of two memory cells. Figure 15 corresponds to Figure 3 of the first embodiment.

[0079] The memory cell of the comparative example semiconductor memory device differs from the memory cell of the first embodiment in that a metal silicide layer 13 is not provided between the first word line WL1 and the gate insulating layer 12, and between the second word line WL2 and the gate insulating layer 12.

[0080] Next, an example of a method for manufacturing a semiconductor memory device of the comparative example will be described. Figures 16, 17, 18, and 19 are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device of the comparative example. Figures 16 to 19 each show a cross-section corresponding to Figure 14(a). Figures 16 to 19 show an example of a method for manufacturing the memory cell array 900 of the semiconductor memory device of the comparative example.

[0081] The manufacturing method of the semiconductor memory device in the comparative example is the same as the manufacturing method of the semiconductor memory device in the first embodiment up to the point of forming an opening 54 in the silicon oxide layer 50 and the polycrystalline silicon layer 52.

[0082] Next, a first silicon oxide film 60 is formed within the opening 54. The first silicon oxide film 60 is formed, for example, by a CVD method. The first silicon oxide film 60 ultimately becomes the second interface insulating layer 16.

[0083] Next, a hafnium oxide film 62 is formed in the opening 54 (Figure 16). The hafnium oxide film 62 is formed, for example, by the ALD method. For example, silicon (Si) is added to the hafnium oxide film 62 as an additive element. The hafnium oxide film 62 ultimately becomes the gate insulating layer 12.

[0084] Next, a second silicon oxide film 64 is formed on the inner surface of the opening 54. The second silicon oxide film 64 is formed, for example, by a CVD method. The second silicon oxide film 64 ultimately becomes the first interface insulating layer 14.

[0085] Next, a polycrystalline silicon film 66 is formed in the opening 54 to fill the opening 54 (Figure 17). The polycrystalline silicon film 66 is formed, for example, by the CVD method. The polycrystalline silicon film 66 ultimately becomes the semiconductor layer 10.

[0086] Next, the hafnium oxide film 62 is subjected to heat treatment to crystallize it. This heat treatment is known as crystallization annealing. By crystallizing the hafnium oxide film 62, a first crystal of the orthorhombic or trigonal system is formed within the hafnium oxide film 62. The heat treatment is carried out, for example, in an inert gas atmosphere at a temperature between 800°C and 1000°C.

[0087] Next, the polycrystalline silicon layer 52 is selectively removed by wet etching using etching grooves (not shown) (Figure 18).

[0088] Next, a titanium nitride film 68 and a tungsten film 70 are formed on the first silicon oxide film 60 (Figure 19). The titanium nitride film 68 and the tungsten film 70 are formed, for example, by the CVD method. The titanium nitride film 68 and the tungsten film 70 ultimately become word lines WL. The titanium nitride film 68 ultimately becomes a barrier metal film 41. The tungsten film 70 ultimately becomes a metallic region 42.

[0089] The semiconductor memory device of the comparative example is manufactured by the above manufacturing method.

[0090] The manufacturing method of the semiconductor memory device in the comparative example differs from the manufacturing method of the semiconductor memory device in the first embodiment in that the titanium silicide layer 58 is not formed.

[0091] In the comparative example of a semiconductor memory device manufacturing method, the hafnium oxide film 62 is crystallized by crystallization annealing. By crystallizing the hafnium oxide film 62, a first crystal of the orthorhombic or trigonal system is formed within the hafnium oxide film 62. In other words, a ferroelectric material is formed in the hafnium oxide film 62.

[0092] During crystallization annealing, the hafnium oxide film 62 is sandwiched between the polycrystalline silicon layer 52 and the polycrystalline silicon film 66. Performing crystallization annealing while sandwiched between the polycrystalline silicon layer 52 and the polycrystalline silicon film 66 promotes the formation of a ferroelectric material within the hafnium oxide film 62. The formation of the ferroelectric material within the hafnium oxide film 62 is thought to be promoted by the stress applied to the hafnium oxide film 62 by the polycrystalline silicon layer 52 and the polycrystalline silicon film 66.

[0093] In the comparative example of the semiconductor memory device manufacturing method, the polycrystalline silicon layer 52 is removed after crystallization annealing, and then the titanium nitride film 68 and the tungsten film 70 are formed. The inventors' investigation revealed that removing the polycrystalline silicon layer 52 after crystallization annealing reduces the ferroelectric material formed in the hafnium oxide film 62.

[0094] This is thought to be because the removal of the polycrystalline silicon layer 52 reduces the stress applied to the hafnium oxide film 62, causing the metastable orthorhombic or trigonal first crystal to change into a stable cubic, hexagonal, tetragonal, monoclinic, or triclinic second crystal. In other words, it is thought that the ferroelectric first crystal changes into a paraelectric second crystal.

[0095] In the comparative semiconductor memory device, the ferroelectric properties of the gate insulating layer 12 weaken as the proportion of ferroelectric material in the gate insulating layer 12 decreases. In the comparative semiconductor memory device, the weakening of the ferroelectric properties of the gate insulating layer 12 leads to, for example, a deterioration in the rewrite endurance of the memory cell. Consequently, for example, the reliability of the comparative semiconductor memory device decreases. Therefore, the characteristics of the comparative semiconductor memory device deteriorate.

[0096] The semiconductor memory device of the first embodiment includes a metal silicide layer 13 between the word line WL and the gate insulating layer 12. In the manufacturing method of the semiconductor memory device of the first embodiment, when crystallization annealing is performed, the hafnium oxide film 62 is sandwiched between a titanium silicide layer 58, which will eventually become the metal silicide layer 13, and a polycrystalline silicon film 66. By performing crystallization annealing while sandwiched between the titanium silicide layer 58 and the polycrystalline silicon film 66, the formation of a ferroelectric material within the hafnium oxide film 62 is promoted.

[0097] In particular, when the hafnium oxide film 62 is sandwiched between the titanium silicide layer 58 and the polycrystalline silicon film 66, the formation of the ferroelectric component of the hafnium oxide film 62 is further promoted than in the comparative example. This is thought to be because when the hafnium oxide film 62 is sandwiched between the titanium silicide layer 58 and the polycrystalline silicon film 66, the stress applied to the hafnium oxide film 62 is greater than when it is sandwiched between the polycrystalline silicon layer 52 and the polycrystalline silicon film 66.

[0098] In the manufacturing method of the semiconductor memory device of the first embodiment, similar to the comparative example, the polycrystalline silicon layer 52 is removed after crystallization annealing, and then the titanium nitride film 68 and the tungsten film 70 are formed. However, unlike the comparative example, the titanium silicide layer 58 remains even after the polycrystalline silicon layer 52 is removed. Therefore, the decrease in stress applied to the hafnium oxide film 62 after the removal of the polycrystalline silicon layer 52 is suppressed, and the decrease in the ferroelectric material formed in the hafnium oxide film 62 is suppressed. Consequently, the ferroelectricity of the gate insulating layer 12 is strengthened, which suppresses the deterioration of the rewrite endurance of the memory cell. As a result, for example, the reliability of the semiconductor memory device of the first embodiment is improved. Thus, the characteristics of the semiconductor memory device of the first embodiment are improved.

[0099] (modified version) The semiconductor memory device of the modified embodiment differs from the semiconductor memory device of the first embodiment in that a gate insulating layer is not provided between the first insulating layer and the semiconductor layer.

[0100] Figures 20(a) and 20(b) are schematic cross-sectional views of a memory cell array of a semiconductor memory device of a modified example of the first embodiment. Figure 20(a) is a yz cross-sectional view of the modified memory cell array 110. Figure 20(a) is the BB' cross-section of Figure 20(b). Figure 20(b) is an xy cross-sectional view of the memory cell array 110. Figure 20(b) is the AA' cross-section of Figure 20(a). In Figure 20(a), the area enclosed by the dashed line is a single memory cell. Figures 20(a) and 20(b) correspond to Figures 2(a) and 2(b) of the first embodiment.

[0101] Figure 21 is a schematic cross-sectional view of a memory cell of a semiconductor memory device of a modified example of the first embodiment. Figure 21 is an enlarged cross-sectional view of a portion of two memory cells. Figure 21 corresponds to Figure 3 of the first embodiment.

[0102] The modified memory cell of the first embodiment differs from the memory cell of the semiconductor memory device of the first embodiment in that a gate insulating layer 12 is not provided between the interlayer insulating layer 18 and the semiconductor layer 10.

[0103] According to the modified semiconductor memory device of the first embodiment, similar to the first embodiment, the provision of a metal silicide layer 13 suppresses the degradation of the rewrite endurance of the memory cell, thereby improving the reliability of the modified semiconductor memory device of the first embodiment, for example. Therefore, the characteristics of the modified semiconductor memory device of the first embodiment are improved.

[0104] Furthermore, in the semiconductor memory device of the modified embodiment of the first embodiment, a gate insulating layer 12 is not provided between the interlayer insulating layer 18 and the semiconductor layer 10. As a result, compared to the case in which a gate insulating layer 12 is provided between the interlayer insulating layer 18 and the semiconductor layer 10, for example, the data read characteristics of the memory cell become more stable. This is because the data read characteristics of the memory cell are not affected by the polarization state of the gate insulating layer 12 between the interlayer insulating layer 18 and the semiconductor layer 10.

[0105] As described above, according to the semiconductor memory device and its modifications in the first embodiment, the ferroelectricity of the gate insulating layer 12 is strengthened by the inclusion of a metal silicide layer 13 in the memory cell. Therefore, a semiconductor memory device with superior characteristics can be realized.

[0106] (Second embodiment) The semiconductor memory device of the second embodiment includes a semiconductor layer extending in a first direction, a first gate electrode layer, a second gate electrode layer provided spaced apart from the first gate electrode layer in the first direction, a first insulating layer provided between the first gate electrode layer and the second gate electrode layer, a gate insulating layer provided between the first gate electrode layer and the semiconductor layer, containing hafnium (Hf) and oxygen (O), and including a first crystal in an orthorhombic or trigonal system, and a metal layer provided between the first gate electrode layer and the gate insulating layer. In a second direction perpendicular to the first direction, no gate insulating layer is provided between the first insulating layer and the semiconductor layer, and the first thickness in the second direction at both ends of the metal layer in the first direction is greater than the second thickness in the second direction at the middle portion of the metal layer in the first direction. The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in that a metal layer is provided instead of a metal silicide layer, and the first thickness in the second direction at both ends in the first direction is thicker than the second thickness in the second direction at the middle portion of the metal layer in the first direction. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0107] The semiconductor memory device of the second embodiment is a three-dimensional NAND flash memory having memory cells with an MFS structure.

[0108] The semiconductor memory device of the second embodiment has a circuit configuration similar to that of the memory cell array of the semiconductor memory device of the first embodiment shown in Figure 1.

[0109] Figures 22(a) and 22(b) are schematic cross-sectional views of a memory cell array of a semiconductor memory device according to a second embodiment. Figures 22(a) and 22(b) show cross-sections of multiple memory cells within the memory cell array 200.

[0110] Figure 22(a) is a yz cross-sectional view of the memory cell array 200. Figure 22(a) is the BB' cross-section of Figure 22(b). Figure 22(b) is an xy cross-sectional view of the memory cell array 200. Figure 22(b) is the AA' cross-section of Figure 22(a). In Figure 22(a), the area enclosed by the dashed line represents a single memory cell.

[0111] Figure 23 is a schematic cross-sectional view of a memory cell of a semiconductor memory device according to the second embodiment. Figure 23 is an enlarged cross-sectional view of a portion of two memory cells.

[0112] As shown in Figures 22(a) and 22(b), the memory cell array 200 comprises multiple word lines WL, a semiconductor layer 10, a gate insulating layer 12, a first interface insulating layer 14, a metal layer 15, a second interface insulating layer 16, and multiple interlayer insulating layers 18. The multiple word lines WL and the multiple interlayer insulating layers 18 constitute a laminate 30. The word lines WL include a barrier metal film 41 and a metal region 42.

[0113] The interlayer insulating layer 18 is an example of a first insulating layer. The barrier metal film 41 is an example of a conductive film.

[0114] As shown in Figure 23, the two memory cells comprise a first word line WL1, a second word line WL2, a semiconductor layer 10, a gate insulating layer 12, a first interface insulating layer 14, a metal layer 15, a second interface insulating layer 16, and a plurality of interlayer insulating layers 18.

[0115] The gate insulating layer 12 is provided between the word line WL and the semiconductor layer 10. The gate insulating layer 12 is provided between the first word line WL1 and the semiconductor layer 10. The gate insulating layer 12 is provided between the second word line WL2 and the semiconductor layer 10. The gate insulating layer 12 is provided, for example, between the second interface insulating layer 16 and the first interface insulating layer 14.

[0116] The gate insulating layer 12 is not provided between the interlayer insulating layer 18 and the semiconductor layer 10 in the y-direction. The gate insulating layer 12 is not provided between the second interface insulating layer 16 and the first interface insulating layer 14 in the y-direction.

[0117] The gate insulating layer 12 is divided in the z direction. The gate insulating layer 12 provided between the first word line WL1 and the semiconductor layer 10 and the gate insulating layer 12 provided between the second word line WL2 and the semiconductor layer 10 are separated in the z direction. A second interface insulating layer 16 is provided between the gate insulating layer 12 provided between the first word line WL1 and the semiconductor layer 10 and the gate insulating layer 12 provided between the second word line WL2 and the semiconductor layer 10.

[0118] The gate insulating layer 12 contains hafnium (Hf) and oxygen (O). Among the atomic concentrations of elements other than oxygen (O) contained in the gate insulating layer 12, the atomic concentration of hafnium (Hf) is the highest. The proportion of the atomic concentration of hafnium (Hf) in the total atomic concentrations of elements other than oxygen (O) contained in the gate insulating layer 12 is, for example, 90% or more.

[0119] The gate insulating layer 12 contains hafnium oxide. For example, the gate insulating layer 12 is mainly composed of hafnium oxide. When we say that the gate insulating layer 12 is mainly composed of hafnium oxide, it means that hafnium oxide has the highest molar ratio among the substances contained in the gate insulating layer 12. For example, the molar ratio of hafnium oxide contained in the gate insulating layer 12 is 90% or more.

[0120] The gate insulating layer 12 contains a ferroelectric material. The gate insulating layer 12 is, for example, a ferroelectric layer. The gate insulating layer 12 is crystalline.

[0121] The gate insulating layer 12 contains a first crystal in an orthorhombic or trigonal system. The first crystal is hafnium oxide. Hafnium oxide is ferroelectric when it is in an orthorhombic or trigonal system. Therefore, the first crystal is a ferroelectric.

[0122] Hafnium oxide exhibits ferroelectric properties, for example, when it is a crystal in the orthorhombic III system (space group Pbc21, space group number 29) or the trigonal system (space group R3m or P3 or R3, space group number 160 or 143 or 146).

[0123] Hafnium oxide does not possess ferroelectric properties when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. Hafnium oxide is paraelectric when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. Crystal systems other than orthorhombic or trigonal include cubic, hexagonal, tetragonal, monoclinic, and triclinic systems.

[0124] The gate insulating layer 12 includes, for example, a second crystal of a cubic, hexagonal, tetragonal, monoclinic, or triclinic crystal system. The second crystal is a paraelectric material.

[0125] The gate insulating layer 12 primarily consists of a first crystal of the orthorhombic or trigonal system. This means that, among the materials constituting the gate insulating layer 12, the first crystal of the orthorhombic or trigonal system has the largest proportion. In other words, among the materials constituting the gate insulating layer 12, there is no material that has a larger proportion than the first crystal of the orthorhombic or trigonal system. For example, among the materials constituting the gate insulating layer 12, the proportion of the first ferroelectric crystal is greater than that of the second paraelectric crystal. In other words, among the materials constituting the gate insulating layer 12, the first ferroelectric crystal has the largest proportion.

[0126] The gate insulating layer 12 is composed primarily of a ferroelectric material, for example. The proportion of ferroelectric material in the gate insulating layer 12 is greater than the proportion of paraelectric material in the gate insulating layer 12.

[0127] The gate insulating layer 12 contains at least one additive element selected from the group consisting of, for example, silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Ru). The hafnium oxide contained in the gate insulating layer 12 contains the above-mentioned additive element. For example, the inclusion of the above-mentioned additive element in hafnium oxide makes it easier for ferroelectricity to be exhibited in hafnium oxide.

[0128] The first interface insulating layer 14 is provided between the first word line WL1 and the semiconductor layer 10. The first interface insulating layer 14 is provided between the second word line WL2 and the semiconductor layer 10. The first interface insulating layer 14 is provided between the gate insulating layer 12 and the semiconductor layer 10.

[0129] The second interface insulating layer 16 is provided between the first word wire WL1 and the gate insulating layer 12. The second interface insulating layer 16 is provided between the second word wire WL2 and the gate insulating layer 12. The second interface insulating layer 16 is provided between the metal layer 15 and the gate insulating layer 12.

[0130] The metal layer 15 is provided between the first word wire WL1 and the gate insulating layer 12. The metal layer 15 is provided between the second word wire WL2 and the gate insulating layer 12. The metal layer 15 is provided between the first word wire WL1 and the second interface insulating layer 16. The metal layer 15 is provided between the second word wire WL2 and the second interface insulating layer 16.

[0131] The metal layer 15 is in contact with, for example, the first word line WL1. The metal layer 15 is in contact with, for example, the second word line WL2. The metal layer 15 is in contact with, for example, the second interface insulating layer 16.

[0132] The metal layer 15 is divided in the z direction. The metal layer 15 provided between the first word wire WL1 and the gate insulating layer 12 and the metal layer 15 provided between the second word wire WL2 and the gate insulating layer 12 are separated in the z direction. An interlayer insulating layer 18 is provided between the metal layer 15 provided between the first word wire WL1 and the gate insulating layer 12 and the metal layer 15 provided between the second word wire WL2 and the gate insulating layer 12.

[0133] The metal layer 15 is not provided between the interlayer insulating layer 18 and the semiconductor layer 10 in the y-direction. The metal layer 15 is not provided between the interlayer insulating layer 18 and the gate insulating layer 12 in the y-direction. The metal layer 15 is not provided between the interlayer insulating layer 18 and the second interface insulating layer 16 in the y-direction. The metal layer 15 is in contact with the interlayer insulating layer 18, for example, in the z-direction.

[0134] The metal layer 15 is not provided between the first word wire WL1 and the interlayer insulating layer 18 in the z direction. The metal layer 15 is not provided between the second word wire WL2 and the interlayer insulating layer 18 in the z direction. In the z direction, the first word wire WL1 and the interlayer insulating layer 18 are in contact. In the z direction, the second word wire WL2 and the interlayer insulating layer 18 are in contact.

[0135] The first thickness in the y-direction perpendicular to the z-direction at both ends of the metal layer 15 in the z-direction (t1 in Figure 23) is greater than the second thickness in the y-direction at the middle portion of the metal layer 15 in the z-direction (t2 in Figure 23). For example, the first thickness t1 is between 1.1 and 3 times the second thickness t2.

[0136] The first distance in the y direction (d1 in Figure 23) between the ends of the metal layer 15 in the z direction and the semiconductor layer 10 is smaller than the second distance in the y direction (d2 in Figure 23) between the middle portion of the metal layer 15 in the z direction and the semiconductor layer 10. The first distance d1 is, for example, 10% to 90% of the second distance d2.

[0137] The length of the metal layer 15 in the z direction is longer than the length of the gate insulating layer 12 in the z direction.

[0138] The metal layer 15 surrounds the gate insulating layer 12 in a cross-section perpendicular to the z-direction. The metal layer 15 surrounds the semiconductor layer 10 in a cross-section perpendicular to the z-direction.

[0139] The metal layer 15 contains a metal element. The metal layer 15 contains, for example, a metal, a metal nitride, a metal carbide, or a metal semiconductor compound. The metal layer 15 contains, for example, titanium (Ti), tungsten (W), or tantalum (Ta). The metal layer 15 contains, for example, titanium, tungsten, titanium nitride, tungsten nitride, tantalum nitride, titanium silicide, or tungsten silicide. The metal layer 15 is, for example, a titanium layer, a tungsten layer, a titanium nitride layer, a tungsten nitride layer, a tantalum nitride layer, a titanium silicide layer, or a tungsten silicide layer.

[0140] For example, the material of the metal layer 15 and the material of the word line WL are different. For example, the material of the metal layer 15 and the material of the barrier metal film 41 are different. For example, the material of the metal layer 15 and the material of the metal region 42 are different.

[0141] For example, the chemical composition of the metal layer 15 and the chemical composition of the word line WL are different. For example, the chemical composition of the metal layer 15 and the chemical composition of the barrier metal film 41 are different. For example, the chemical composition of the metal layer 15 and the chemical composition of the metal region 42 are different. For example, the word line WL contains different metal elements than the metal layer 15.

[0142] Next, an example of a method for manufacturing a semiconductor memory device according to the second embodiment will be described. Figures 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, and 34 are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to the second embodiment. Figures 24 to 34 each show a cross-section corresponding to Figure 22(a). Figures 24 to 34 show an example of a method for manufacturing a memory cell array 200 of a semiconductor memory device.

[0143] First, silicon oxide layers 50 and silicon nitride layers 53 are alternately stacked on a semiconductor substrate (not shown) (Figure 24). The silicon oxide layers 50 and silicon nitride layers 53 form a laminate 30. The silicon oxide layers 50 and silicon nitride layers 53 are formed, for example, by the CVD method. A portion of the silicon oxide layer 50 eventually becomes an interlayer insulating layer 18.

[0144] Next, openings 54 are formed in the silicon oxide layer 50 and the silicon nitride layer 53 (Figure 25). The openings 54 are formed, for example, by lithography and RIE.

[0145] Next, the silicon nitride layer 53 exposed on the inner surface of the opening 54 is selectively recessed by wet etching (Figure 26). For wet etching, for example, a phosphoric acid solution is used to selectively etch the silicon nitride layer 53 relative to the silicon oxide layer 50. The silicon nitride layer 53 on the inner surface of the opening 54 is recessed, and a recess is formed.

[0146] Next, a first titanium nitride film 57 is formed inside the opening 54 (Figure 27). The first titanium nitride film 57 is formed, for example, by a CVD method. The first titanium nitride film 57 is formed on the inner surface of the opening 54, and on the upper, side, and lower surfaces of the recess of the opening 54.

[0147] Next, the first titanium nitride film 57 on the inner surface of the opening 54 is removed by etching (Figure 28). The first titanium nitride film 57 is removed using the RIE method or the wet etching method.

[0148] A portion of the first titanium nitride film 57 remains in the recess formed by the recession of the silicon nitride layer 53. Etching is controlled so that the thickness in the y-direction at both ends of the first titanium nitride film 57 in the z-direction of the recess is greater than the thickness in the y-direction of the middle portion of the first titanium nitride film 57 in the z-direction of the recess.

[0149] Next, a first silicon oxide film 60 is formed inside the opening 54 (Figure 29). The first silicon oxide film 60 is formed, for example, by a CVD method. The first silicon oxide film 60 ultimately becomes the second interface insulating layer 16.

[0150] Next, a hafnium oxide film 62 is formed in the opening 54 (Figure 30). The hafnium oxide film 62 is formed, for example, by the ALD method. For example, silicon (Si) is added to the hafnium oxide film 62 as an additive element. A portion of the hafnium oxide film 62 ultimately becomes the gate insulating layer 12.

[0151] Next, the hafnium oxide film 62 on the inner surface of the opening 54 is removed by etching (Figure 31). The hafnium oxide film 62 is removed, for example, using the RIE method. A portion of the hafnium oxide film 62 remains in the recess formed by the recession of the silicon nitride layer 53.

[0152] Next, a second silicon oxide film 64 is formed on the inner surface of the opening 54. The second silicon oxide film 64 is formed, for example, by a CVD method. The second silicon oxide film 64 ultimately becomes the first interface insulating layer 14.

[0153] Next, a polycrystalline silicon film 66 is formed in the opening 54 to fill the opening 54 (Figure 32). The polycrystalline silicon film 66 is formed, for example, by the CVD method. The polycrystalline silicon film 66 ultimately becomes the semiconductor layer 10.

[0154] Next, the hafnium oxide film 62 is subjected to heat treatment to crystallize it. This heat treatment is known as crystallization annealing. By crystallizing the hafnium oxide film 62, a first crystal of the orthorhombic or trigonal system is formed within the hafnium oxide film 62. The heat treatment is carried out, for example, in an inert gas atmosphere at a temperature between 800°C and 1000°C.

[0155] Next, the silicon nitride layer 53 is selectively removed by wet etching using etching grooves (not shown) (Figure 33).

[0156] Next, a second titanium nitride film 69 and a tungsten film 70 are formed on the first titanium nitride film 57 (Figure 34). The second titanium nitride film 69 and the tungsten film 70 are formed, for example, by the CVD method. The second titanium nitride film 69 and the tungsten film 70 ultimately become word lines WL. The second titanium nitride film 69 ultimately becomes a barrier metal film 41. The tungsten film 70 ultimately becomes a metallic region 42.

[0157] Furthermore, the heat treatment to crystallize the hafnium oxide film 62 can also be performed, for example, immediately after the formation of the second silicon oxide film 64. The heat treatment to crystallize the hafnium oxide film 62 can be performed, for example, between the formation of the second silicon oxide film 64 and before the removal of the silicon nitride layer 53.

[0158] The semiconductor memory device of the second embodiment is manufactured by the manufacturing method described above.

[0159] Next, the operation and effects of the semiconductor memory device of the second embodiment will be described.

[0160] The semiconductor memory device of the second embodiment includes a metal layer 15 between the word line WL and the gate insulating layer 12. In the manufacturing method of the semiconductor memory device of the second embodiment, when crystallization annealing is performed, the hafnium oxide film 62 is sandwiched between the first titanium nitride film 57 and the polycrystalline silicon film 66. By performing crystallization annealing while the hafnium oxide film 62 is sandwiched between the first titanium nitride film 57 and the polycrystalline silicon film 66, the formation of the ferroelectric material of the hafnium oxide film 62 is promoted for the same reasons as in the first embodiment.

[0161] In particular, the placement of the hafnium oxide film 62 between the first titanium nitride film 57 and the polycrystalline silicon film 66 further promotes the formation of the ferroelectric material of the hafnium oxide film 62 for the same reasons as in the first embodiment.

[0162] In the semiconductor memory device manufacturing method of the second embodiment, the silicon nitride layer 53 is removed after crystallization annealing, and then the second titanium nitride film 69 and the tungsten film 70 are formed. The first titanium nitride film 57 remains even after the silicon nitride layer 53 is removed. Therefore, the decrease in stress applied to the hafnium oxide film 62 after the removal of the silicon nitride layer 53 is suppressed, and the decrease in the ferroelectric material formed in the hafnium oxide film 62 is suppressed.

[0163] In the semiconductor memory device of the second embodiment, the first thickness in the y-direction perpendicular to the z-direction at both ends of the metal layer 15 in the z-direction (t1 in Figure 23) is greater than the second thickness in the y-direction at the middle portion of the metal layer 15 in the z-direction (t2 in Figure 23). Therefore, in the manufacturing method of the semiconductor memory device of the second embodiment, the first titanium nitride film 57 has a shape that covers the corners of the hafnium oxide film 62 which becomes the gate insulating layer 12. Because the first titanium nitride film 57 has a shape that covers the corners of the hafnium oxide film 62, the stress applied to the hafnium oxide film 62 during crystallization annealing becomes stronger. Therefore, the formation of a ferroelectric material in the hafnium oxide film 62 is promoted. In addition, the decrease in stress applied to the hafnium oxide film 62 after the silicon nitride layer 53 is removed is further suppressed, and the decrease in the ferroelectric material in the hafnium oxide film 62 is suppressed.

[0164] According to the semiconductor memory device of the second embodiment, the ferroelectricity of the gate insulating layer 12 is strengthened, which suppresses the degradation of the rewrite endurance of the memory cell, and for example, improves the reliability of the semiconductor memory device of the second embodiment. Therefore, the characteristics of the semiconductor memory device of the second embodiment are improved.

[0165] Furthermore, in the semiconductor memory device of the second embodiment, since the gate insulating layer 12 is not provided between the interlayer insulating layer 18 and the semiconductor layer 10, the data read characteristics of the memory cell are more stable compared to the case in which the gate insulating layer 12 is provided between the interlayer insulating layer 18 and the semiconductor layer 10. This is because the data read characteristics of the memory cell are not affected by the polarization state of the gate insulating layer 12 between the interlayer insulating layer 18 and the semiconductor layer 10.

[0166] As described above, according to the semiconductor memory device of the second embodiment, similar to the first embodiment, the ferroelectricity of the gate insulating layer 12 is strengthened by the inclusion of a metal layer 15 in the memory cell. Therefore, a semiconductor memory device with superior characteristics can be realized.

[0167] (Third embodiment) The semiconductor memory device of the third embodiment comprises: a semiconductor layer extending in a first direction; a first gate electrode layer; a second gate electrode layer provided in the first direction and spaced apart from the first gate electrode layer; a gate insulating layer provided between the first gate electrode layer and the semiconductor layer, containing hafnium (Hf) and oxygen (O), and including a first crystal of the orthorhombic or trigonal system; a first insulating layer provided between the first gate electrode layer and the second gate electrode layer; and a second insulating layer provided between the first gate electrode layer and the second gate electrode layer, and between the first insulating layer and the gate insulating layer, having a different chemical composition from the first insulating layer, and containing at least one of the elements aluminum (Al) or tantalum (Ta) and oxygen (O).

[0168] The semiconductor memory device of the third embodiment is a three-dimensional NAND flash memory having memory cells with an MFS structure.

[0169] Figure 35 is a circuit diagram of a memory cell array of a semiconductor memory device according to the third embodiment.

[0170] The memory cell array 300 of the third embodiment of the three-dimensional NAND flash memory comprises a plurality of word lines WL, a common source line CSL, a source selection gate line SGS, a plurality of channel layers CL, a plurality of drain selection gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS, as shown in Figure 35.

[0171] The z-direction in Figure 35 is an example of the first direction. The y-direction in Figure 35 is an example of the second direction. The x-direction in Figure 35 is an example of the third direction. Note that the first direction is a concept that includes the z-direction and its inverse direction. The second direction is a concept that includes the y-direction and its inverse direction. The third direction is a concept that includes the x-direction and its inverse direction.

[0172] Multiple word lines WL are stacked in the z direction. Multiple word lines WL are spaced apart in the z direction. Multiple channel layers CL extend in the z direction. Multiple bit lines BL extend in the x direction.

[0173] As shown in Figure 35, a memory string MS consists of a source selection transistor SST connected in series between a common source line CSL and a bit line BL, multiple memory cell transistors MT, and a drain selection transistor SDT. One memory string MS is selected by the bit line BL and the drain selection gate line SGD, and one memory cell transistor MT can be selected by the word line WL.

[0174] Figures 36(a), 36(b), and 37 are schematic cross-sectional views of a memory cell array of a semiconductor memory device according to a third embodiment. Figures 36(a), 36(b), and 37 show cross-sections of multiple memory cells in a single memory string MS enclosed by a dotted line, for example, within the memory cell array 300 of Figure 35.

[0175] Figure 36(a) is a yz cross-sectional view of the memory cell array 300. Figure 36(a) is the BB' cross-section of Figure 36(b). Figure 36(b) is an xy cross-sectional view of the memory cell array 300. Figure 36(b) is the AA' cross-section of 36(a). Figure 37 is an xy cross-sectional view of the memory cell array 300. Figure 37 is the CC' cross-section of 36(a). In Figure 36(a), the area enclosed by the dashed line represents a single memory cell.

[0176] Figure 38 is a schematic cross-sectional view of a memory cell of a semiconductor memory device according to the third embodiment. Figure 38 is an enlarged cross-sectional view of a portion of two memory cells.

[0177] As shown in Figures 36(a) and 36(b), the memory cell array 300 comprises a plurality of word lines WL, a semiconductor layer 10, a gate insulating layer 12, a first interface insulating layer 14, a second interface insulating layer 16, a plurality of first interlayer insulating layers 17, and a plurality of second interlayer insulating layers 19. The plurality of word lines WL, the plurality of first interlayer insulating layers 17, and the plurality of second interlayer insulating layers 19 constitute a laminate 30. The word lines WL include a barrier metal film 41 and a metal region 42.

[0178] The first interlayer insulating layer 17 is an example of a first insulating layer. The second interlayer insulating layer 19 is an example of a second insulating layer. The barrier metal film 41 is an example of a conductive film.

[0179] As shown in Figure 38, the two memory cells comprise a first word line WL1, a second word line WL2, a semiconductor layer 10, a gate insulating layer 12, a first interface insulating layer 14, a second interface insulating layer 16, a plurality of first interlayer insulating layers 17, and a plurality of second interlayer insulating layers 19.

[0180] The first word line WL1 is one of several word lines. The first word line WL1 is an example of the first gate electrode layer. The second word line WL2 is one of several word lines. The second word line WL2 is an example of the second gate electrode layer.

[0181] The word line WL, the first interlayer insulating layer 17, and the second interlayer insulating layer 19 are provided, for example, on a semiconductor substrate (not shown). The word line WL, the first interlayer insulating layer 17, and the second interlayer insulating layer 19 are provided, for example, in the z direction with respect to a semiconductor substrate (not shown).

[0182] Word lines WL and the first interlayer insulating layer 17, and word lines WL and the second interlayer insulating layer 19 are alternately stacked on a semiconductor substrate in the z direction. The word lines WL are arranged spaced apart in the z direction. For example, the second word line WL2 is provided spaced apart in the z direction from the first word line WL1. Multiple word lines WL, multiple first interlayer insulating layers 17, and multiple second interlayer insulating layers 19 constitute a laminate 30.

[0183] The word line WL is a plate-shaped conductor. The word line WL is, for example, a metal, a metal nitride, a metal carbide, or a semiconductor. The word line WL includes, for example, a barrier metal film 41 and a metal region 42. The barrier metal film 41 is provided between the metal region 42 and the gate insulating layer 12.

[0184] The barrier metal film 41 includes, for example, a metal, a metal nitride, or a metal carbide. The barrier metal film 41 includes, for example, titanium nitride, tungsten nitride, or tantalum nitride. The barrier metal film 41 is, for example, a titanium nitride film.

[0185] The metallic region 42 is a metal. The metallic region 42 includes, for example, tungsten (W) or molybdenum (Mo). The metallic region 42 is, for example, a tungsten layer or a molybdenum layer. The metallic region 42 includes, for example, a different metallic element from the barrier metal film 41.

[0186] The word line WL functions as a control electrode for the memory cell transistor MT.

[0187] The length of the word line WL in the z direction is, for example, between 5 nm and 40 nm.

[0188] The first interlayer insulating layer 17 is provided between word wires WL and word wires WL. For example, the first interlayer insulating layer 17 is provided between a first word wire WL1 and a second word wire WL2.

[0189] The first interlayer insulating layer 17 separates word wire WL from word wire WL. The first interlayer insulating layer 17 separates, for example, the first word wire WL1 from the second word wire WL2. The first interlayer insulating layer 17 is, for example, an oxide, an oxynitride, or a nitride. The first interlayer insulating layer 17 contains, for example, silicon (Si) and oxygen (O). The first interlayer insulating layer 17 is, for example, silicon oxide.

[0190] The length of the first interlayer insulating layer 17 in the z direction is, for example, 5 nm or more and 40 nm or less.

[0191] The second interlayer insulating layer 19 is provided between word wires WL and WL. The second interlayer insulating layer 19 is provided, for example, between the first word wire WL1 and the second word wire WL2. The second interlayer insulating layer 19 is in contact with the word wire WL, for example, in the z direction. The second interlayer insulating layer 19 is in contact with the first word wire WL1 and the second word wire WL2, for example, in the z direction.

[0192] The second interlayer insulating layer 19 separates word wire WL from word wire WL. For example, the second interlayer insulating layer 19 separates the first word wire WL1 from the second word wire WL2.

[0193] The second interlayer insulating layer 19 is provided between the first interlayer insulating layer 17 and the semiconductor layer 10. The second interlayer insulating layer 19 is in contact with, for example, the first interlayer insulating layer 17. The second interlayer insulating layer 19 is provided between, for example, the first interlayer insulating layer 17 and the second interface insulating layer 16. The second interlayer insulating layer 19 is in contact with, for example, the second interface insulating layer 16.

[0194] As shown in Figure 37, the second interlayer insulating layer 19 surrounds the semiconductor layer 10 in a cross-section perpendicular to the z-direction. As shown in Figure 37, the second interlayer insulating layer 19 surrounds the gate insulating layer 12 in a cross-section perpendicular to the z-direction.

[0195] The second interlayer insulating layer 19 is an insulator. The chemical composition of the second interlayer insulating layer 19 is different from the chemical composition of the first interlayer insulating layer 17. The second interlayer insulating layer 19 contains at least one of the elements aluminum (Al) or tantalum (Ta) and oxygen (O). The second interlayer insulating layer 19 contains, for example, aluminum oxide or tantalum oxide. The second interlayer insulating layer 19 is, for example, aluminum oxide or tantalum oxide.

[0196] The density of amorphous aluminum oxide is lower than that of crystalline aluminum oxide. When amorphous aluminum oxide crystallizes, its volume is reduced to approximately 81%. The volume of aluminum oxide shrinks during crystallization.

[0197] The density of amorphous tantalum oxide is lower than that of crystalline tantalum oxide. When amorphous tantalum oxide crystallizes, its volume is reduced to approximately 89%. When amorphous tantalum oxide crystallizes, its volume shrinks.

[0198] The crystallization temperature of the material contained in the second interlayer insulating layer 19 is, for example, lower than the crystallization temperature of the material contained in the first interlayer insulating layer 17. The crystallization temperatures of aluminum oxide and tantalum oxide are, for example, lower than the crystallization temperature of silicon oxide.

[0199] The length of the second interlayer insulating layer 19 in the z direction is, for example, 5 nm or more and 40 nm or less.

[0200] The first length of the second interlayer insulating layer 19 in the y-direction (L1 in Figure 38) is greater than, for example, the thickness of the gate insulating layer 12 in the y-direction (tx in Figure 38). The first length of the second interlayer insulating layer 19 in the y-direction (L1 in Figure 38) is greater than, for example, the first length of the second interlayer insulating layer 19 in the z-direction (L2 in Figure 38).

[0201] The semiconductor layer 10 is provided within the laminate 30. The semiconductor layer 10 extends in the z direction. The semiconductor layer 10 penetrates the laminate 30. The semiconductor layer 10 is, for example, cylindrical or cylindrical. The semiconductor layer 10 corresponds to the channel layer CL. For example, an insulating film may be provided inside the cylindrical semiconductor layer 10. The insulating film is, for example, silicon oxide.

[0202] The semiconductor layer 10 is, for example, a polycrystalline semiconductor. The semiconductor layer 10 is, for example, polycrystalline silicon. The semiconductor layer 10 functions as the channel of the memory cell transistor MT.

[0203] The gate insulating layer 12 is provided between the word line WL and the semiconductor layer 10. The gate insulating layer 12 is provided between the first word line WL1 and the semiconductor layer 10. The gate insulating layer 12 is provided between the second word line WL2 and the semiconductor layer 10.

[0204] The gate insulating layer 12 is provided between the first interlayer insulating layer 17 and the semiconductor layer 10. The gate insulating layer 12 is provided between the second interlayer insulating layer 19 and the semiconductor layer 10.

[0205] The gate insulating layer 12 contains hafnium (Hf) and oxygen (O). For example, among the atomic concentrations of elements other than oxygen (O) contained in the gate insulating layer 12, the atomic concentration of hafnium (Hf) is the highest. The proportion of the atomic concentration of hafnium (Hf) in the total atomic concentrations of elements other than oxygen (O) contained in the gate insulating layer 12 is, for example, 90% or more.

[0206] The gate insulating layer 12 contains hafnium oxide. For example, the gate insulating layer 12 is mainly composed of hafnium oxide. When we say that the gate insulating layer 12 is mainly composed of hafnium oxide, it means that hafnium oxide has the highest molar ratio among the substances contained in the gate insulating layer 12. For example, the molar ratio of hafnium oxide contained in the gate insulating layer 12 is 90% or more.

[0207] The gate insulating layer 12 contains a ferroelectric material. The gate insulating layer 12 is, for example, a ferroelectric layer. The gate insulating layer 12 is crystalline.

[0208] The gate insulating layer 12 contains a first crystal in the orthorhombic or trigonal system. The first crystal is hafnium oxide. Hafnium oxide is ferroelectric when it is in the orthorhombic or trigonal system. Hafnium oxide is ferroelectric when it is in the orthorhombic or trigonal system. The first crystal is ferroelectric.

[0209] Hafnium oxide exhibits ferroelectric properties, for example, when it is a crystal in the orthorhombic III system (space group Pbc21, space group number 29) or the trigonal system (space group R3m or P3 or R3, space group number 160 or 143 or 146).

[0210] Hafnium oxide does not possess ferroelectric properties when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. Hafnium oxide is paraelectric when it is in a crystal system other than orthorhombic or trigonal, or when it is amorphous. Crystal systems other than orthorhombic or trigonal include cubic, hexagonal, tetragonal, monoclinic, and triclinic systems.

[0211] The gate insulating layer 12 includes, for example, a second crystal of a cubic, hexagonal, tetragonal, monoclinic, or triclinic crystal system. The second crystal is a paraelectric material.

[0212] The gate insulating layer 12 primarily consists of a first crystal of the orthorhombic or trigonal system. This means that, among the materials constituting the gate insulating layer 12, the first crystal of the orthorhombic or trigonal system has the largest proportion. In other words, among the materials constituting the gate insulating layer 12, there is no material whose proportion is greater than that of the first crystal of the orthorhombic or trigonal system. For example, among the materials constituting the gate insulating layer 12, the proportion of the first ferroelectric crystal is greater than that of the second paraelectric crystal. In other words, among the crystals constituting the gate insulating layer 12, the first ferroelectric crystal has the largest proportion.

[0213] The gate insulating layer 12 is composed primarily of a ferroelectric material, for example. The proportion of ferroelectric material in the gate insulating layer 12 is greater than the proportion of paraelectric material in the gate insulating layer 12.

[0214] For example, the proportion of the first crystal in the crystal contained in the gate insulating layer 12 between the second interlayer insulating layer 19 and the semiconductor layer 10 is smaller than the proportion of the first crystal in the material crystal contained in the gate insulating layer 12 between the first word line WL1 and the semiconductor layer 10. For example, the proportion of the first crystal relative to the second crystal contained in the gate insulating layer 12 between the second interlayer insulating layer 19 and the semiconductor layer 10 is smaller than the proportion of the first crystal relative to the second crystal contained in the gate insulating layer 12 between the first word line WL1 and the semiconductor layer 10. For example, the proportion of the ferroelectric material in the material contained in the gate insulating layer 12 between the second interlayer insulating layer 19 and the semiconductor layer 10 is smaller than the proportion of the ferroelectric material in the material contained in the gate insulating layer 12 between the first word line WL1 and the semiconductor layer 10.

[0215] The gate insulating layer 12 contains at least one additive element selected from the group consisting of, for example, silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Ru). The hafnium oxide contained in the gate insulating layer 12 contains the above-mentioned additive element. For example, the inclusion of the above-mentioned additive element in hafnium oxide makes it easier for ferroelectricity to be exhibited in hafnium oxide.

[0216] The first interface insulating layer 14 is provided between the first word line WL1 and the semiconductor layer 10. The first interface insulating layer 14 is provided between the second word line WL2 and the semiconductor layer 10. The first interface insulating layer 14 is provided between the gate insulating layer 12 and the semiconductor layer 10. The first interface insulating layer 14 is provided between the second interlayer insulating layer 19 and the semiconductor layer 10.

[0217] The material of the first interface insulating layer 14 is, for example, different from the material of the gate insulating layer 12. The first interface insulating layer 14 is, for example, an oxide, an oxynitride, or a nitride. The first interface insulating layer 14 is, for example, silicon oxide.

[0218] It is also possible to omit the first interface insulating layer 14 and have a structure in which the gate insulating layer 12 is in direct contact with the semiconductor layer 10.

[0219] The second interface insulating layer 16 is provided between the first word line WL1 and the gate insulating layer 12. The second interface insulating layer 16 is provided between the second word line WL2 and the gate insulating layer 12. The second interface insulating layer 16 is provided between the second interlayer insulating layer 19 and the semiconductor layer 10.

[0220] The material of the second interface insulating layer 16 is, for example, different from the material of the gate insulating layer 12. The second interface insulating layer 16 is, for example, an oxide, an oxynitride, or a nitride. The second interface insulating layer 16 is, for example, silicon oxide or aluminum oxide.

[0221] It is also possible to omit the second interface insulating layer 16 and have a structure in which the gate insulating layer 12 is in direct contact with the word wire WL.

[0222] In the memory cell of the third embodiment, for example, the polarization reversal state of the ferroelectric material contained in the gate insulating layer 12 is controlled by a voltage applied between the first word line WL1 and the semiconductor layer 10. The polarization reversal state of the gate insulating layer 12 changes the threshold voltage of the memory cell transistor MT. As the threshold voltage of the memory cell transistor MT changes, the on-current of the memory cell transistor MT changes. For example, if a state with a high threshold voltage and low on-current is defined as data "0", and a state with a low threshold voltage and high on-current is defined as data "1", the memory cell can store 1-bit data of "0" and "1".

[0223] Next, an example of a method for manufacturing a semiconductor memory device according to the third embodiment will be described. Figures 39, 40, 41, 42, 43, 44, 45, 46, 47, and 48 are schematic cross-sectional views showing a method for manufacturing a semiconductor memory device according to the third embodiment. Figures 39 to 48 each show a cross-section corresponding to Figure 36(a). Figures 39 to 48 show an example of a method for manufacturing a memory cell array 300 of a semiconductor memory device.

[0224] First, silicon oxide layers 50 and silicon nitride layers 53 are alternately stacked on a semiconductor substrate (not shown) (Figure 39). The silicon oxide layers 50 and silicon nitride layers 53 form a laminate 30. The silicon oxide layers 50 and silicon nitride layers 53 are formed, for example, by CVD. A portion of the silicon oxide layer 50 eventually becomes the first interlayer insulating layer 17. The silicon oxide layer 50 is amorphous.

[0225] Next, openings 54 are formed in the silicon oxide layer 50 and the silicon nitride layer 53 (Figure 40). The openings 54 are formed, for example, by lithography and RIE.

[0226] Next, the silicon oxide layer 50 exposed on the inner surface of the opening 54 is selectively recessed by wet etching (Figure 41). For wet etching, for example, a buffered hydrofluoric acid solution is used to selectively etch the silicon oxide layer 50 relative to the silicon nitride layer 53. The silicon oxide layer 50 on the inner surface of the opening 54 is recessed, and a recess is formed.

[0227] Next, an aluminum oxide film 55 is formed inside the opening 54 (Figure 42). The aluminum oxide film 55 is formed, for example, by the CVD method. The aluminum oxide film 55 is amorphous. The aluminum oxide film 55 is formed on the inner surface of the opening 54 and in the recesses of the opening 54. A portion of the aluminum oxide film 55 eventually becomes the second interlayer insulating layer 19.

[0228] Next, the aluminum oxide film 55 on the inner surface of the opening 54 is removed by etching (Figure 43). The aluminum oxide film 55 is removed using the RIE method or the wet etching method. A portion of the aluminum oxide film 55 remains in the recess formed by the recession of the silicon oxide layer 50.

[0229] Next, a first silicon oxide film 60 is formed inside the opening 54 (Figure 44). The first silicon oxide film 60 is formed, for example, by a CVD method. The first silicon oxide film 60 ultimately becomes the second interface insulating layer 16.

[0230] Next, a hafnium oxide film 62 is formed in the opening 54 (Figure 45). The hafnium oxide film 62 is formed, for example, by the ALD method. For example, silicon (Si) is added to the hafnium oxide film 62 as an additive element. The hafnium oxide film 62 ultimately becomes the gate insulating layer 12.

[0231] Next, a second silicon oxide film 64 is formed on the inner surface of the opening 54. The second silicon oxide film 64 is formed, for example, by a CVD method. The second silicon oxide film 64 ultimately becomes the first interface insulating layer 14.

[0232] Next, a polycrystalline silicon film 66 is formed in the opening 54 to fill the opening 54 (Figure 46). The polycrystalline silicon film 66 is formed, for example, by the CVD method. The polycrystalline silicon film 66 ultimately becomes the semiconductor layer 10.

[0233] Next, the silicon nitride layer 53 is selectively removed by wet etching using etching grooves (not shown) (Figure 47).

[0234] Next, a titanium nitride film 68 and a tungsten film 70 are formed on the first silicon oxide film 60 (Figure 48). The titanium nitride film 68 and the tungsten film 70 are formed, for example, by the CVD method. The titanium nitride film 68 and the tungsten film 70 ultimately become word lines WL. The titanium nitride film 68 ultimately becomes a barrier metal film 41. The tungsten film 70 ultimately becomes a metallic region 42.

[0235] Next, the hafnium oxide film 62 is subjected to heat treatment to crystallize it. This heat treatment is known as crystallization annealing. By crystallizing the hafnium oxide film 62, a first crystal of the orthorhombic or trigonal system is formed within the hafnium oxide film 62. The heat treatment is carried out, for example, in an inert gas atmosphere at a temperature between 800°C and 1000°C.

[0236] The amorphous aluminum oxide film 55 also crystallizes due to the heat treatment. This crystallization of the amorphous aluminum oxide film 55 causes a volume contraction. However, the amorphous silicon oxide layer 50 does not crystallize due to the heat treatment.

[0237] The semiconductor memory device of the third embodiment is manufactured by the manufacturing method described above.

[0238] Next, the operation and effects of the semiconductor memory device according to the third embodiment will be described.

[0239] In the third embodiment of the semiconductor memory device manufacturing method, the hafnium oxide film 62 is crystallized by performing crystallization annealing on the hafnium oxide film 62. By crystallizing the hafnium oxide film 62, a first crystal of the orthorhombic or trigonal system is formed within the hafnium oxide film 62. In other words, a ferroelectric material is formed within the hafnium oxide film 62.

[0240] The formation of ferroelectric materials within the hafnium oxide film 62 is promoted by the stress applied to the hafnium oxide film 62 during crystallization annealing. When tensile stress is applied to the hafnium oxide film 62 during crystallization annealing, the formation of ferroelectric materials is promoted. On the other hand, when compressive stress is applied to the hafnium oxide film 62 during crystallization annealing, the formation of ferroelectric materials is suppressed.

[0241] Figure 49 is an explanatory diagram of the operation and effects of the semiconductor memory device of the third embodiment. Figure 49 is an explanatory diagram of the stress applied to the hafnium oxide film 62 during crystallization annealing. Figure 49 is an enlarged view corresponding to Figure 48.

[0242] During crystallization annealing, the amorphous aluminum oxide film 55 shrinks in volume due to crystallization, as shown by the dotted arrow in Figure 49. Therefore, as shown by the solid arrow in Figure 49, tensile stress is applied to the hafnium oxide film 62 between the titanium nitride film 68 and tungsten film 70, which form the word line WL, and the polycrystalline silicon film 66, which forms the semiconductor layer 10. On the other hand, compressive stress is applied to the hafnium oxide film 62 between the aluminum oxide film 55, which forms the second interlayer insulating layer 19, and the polycrystalline silicon film 66.

[0243] In areas where tensile stress is applied to the hafnium oxide film 62, the formation of a ferroelectric material is promoted. Therefore, the ferroelectricity of the gate insulating layer 12 between the word line WL and the semiconductor layer 10 becomes stronger. On the other hand, in areas where compressive stress is applied to the hafnium oxide film 62, the formation of a ferroelectric material is suppressed. Therefore, the ferroelectricity of the gate insulating layer 12 between the second interlayer insulating layer 19 and the semiconductor layer 10 becomes weaker.

[0244] The ferroelectricity of the gate insulating layer 12 between the word line WL and the semiconductor layer 10 is strengthened, which improves the rewrite endurance of the memory cell, for example, and thus improves the reliability of the semiconductor memory device of the third embodiment. Therefore, the characteristics of the semiconductor memory device of the third embodiment are improved.

[0245] Furthermore, in the semiconductor memory device of the third embodiment, the ferroelectricity of the gate insulating layer 12 between the second interlayer insulating layer 19 and the semiconductor layer 10 is weakened. In other words, the ferroelectricity of the gate insulating layer 12 located between two vertically adjacent word lines WL is weakened. Therefore, for example, the data read characteristics of the memory cell become more stable. This is because the data read characteristics of the memory cell are less affected by the polarization state of the gate insulating layer 12 located between the word lines WL.

[0246] From the viewpoint of strengthening the ferroelectricity of the gate insulating layer 12, it is preferable that the first length of the second interlayer insulating layer 19 in the y direction (L1 in Figure 38) is greater than the thickness of the gate insulating layer 12 in the y direction (tx in Figure 38). Also from the viewpoint of strengthening the ferroelectricity of the gate insulating layer 12, it is preferable that the first length of the second interlayer insulating layer 19 in the y direction (L1 in Figure 38) is greater than the first length of the second interlayer insulating layer 19 in the z direction (L2 in Figure 38). As the volume of the second interlayer insulating layer 19 increases, the stress applied to the hafnium oxide film 62 during crystallization annealing increases.

[0247] As described above, in the semiconductor memory device of the third embodiment, the ferroelectricity of the gate insulating layer 12 is strengthened by the inclusion of a second interlayer insulating layer 19 in the memory cell. Therefore, a semiconductor memory device with superior characteristics can be realized.

[0248] In the first to third embodiments, the case in which the word line WL is a plate-shaped conductor and the semiconductor layer 10 is surrounded by the word line WL was described as an example. However, it is also possible to have a memory cell array structure in which, for example, the word line WL is linear and extends in the y direction, and a part of the semiconductor layer 10 and the word line WL face each other. It is also possible to have a structure in which an insulating layer extending in the z direction is provided inside the semiconductor layer 10, and this insulating layer is surrounded by the semiconductor layer 10. For example, silicon oxide can be used as the material for this insulating layer.

[0249] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent materials of one embodiment may be replaced or changed with those of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0250] 10 Semiconductor Layers 12 Gate Insulation Layer 13 Metal silicide layer 14. First interfacial insulating layer 15 metal layer 17. First interlayer insulating layer (first insulating layer) 18. Interlayer insulating layer (first insulating layer) 19. Second interlayer insulating layer (second insulating layer) 41. Barrier metal film (conductive film) 42 Metal area WL1 First ward line (first gate electrode layer) WL2 Second ward line (second gate electrode layer) L1 First length L2 Second length d1 First distance d2 Second distance t1 First thickness t2 Second thickness tx thickness

Claims

1. A semiconductor layer extending in a first direction, The first gate electrode layer, A second gate electrode layer is provided spaced apart from the first gate electrode layer in the first direction, A gate insulating layer is provided between the first gate electrode layer and the semiconductor layer, and comprises hafnium (Hf) and oxygen (O), and includes a first crystal in the orthorhombic or trigonal system. A metal silicide layer is provided between the first gate electrode layer and the gate insulating layer, A semiconductor memory device equipped with the following features.

2. The present invention further comprises a first insulating layer provided between the first gate electrode layer and the second gate electrode layer, The semiconductor memory device according to claim 1, wherein the metal silicide layer is not provided between the first gate electrode layer and the first insulating layer.

3. The semiconductor memory device according to claim 2, wherein the metal silicide layer is not provided between the first insulating layer and the semiconductor layer.

4. The semiconductor memory device according to claim 2, wherein the gate insulating layer is not provided between the first insulating layer and the semiconductor layer.

5. The semiconductor memory device according to claim 1, wherein the first gate electrode layer contains a different metal element from the metal silicide layer.

6. The semiconductor memory device according to claim 1, wherein the metal silicide layer surrounds the gate insulating layer in a cross section perpendicular to the first direction.

7. The semiconductor memory device according to claim 1, wherein the metal silicide layer comprises titanium silicide or tungsten silicide.

8. The semiconductor memory device according to claim 2, wherein the first gate electrode layer includes a metal region and a conductive film provided between the metal region and the metal silicide layer, and between the metal region and the first insulating layer.

9. The semiconductor memory device according to claim 2, wherein the gate insulating layer includes a ferroelectric material.

10. The semiconductor memory device according to claim 1, wherein the gate insulating layer contains at least one element selected from the group consisting of silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Ru).

11. A semiconductor layer extending in a first direction, The first gate electrode layer, A second gate electrode layer is provided spaced apart from the first gate electrode layer in the first direction, A first insulating layer provided between the first gate electrode layer and the second gate electrode layer, A gate insulating layer is provided between the first gate electrode layer and the semiconductor layer, and comprises hafnium (Hf) and oxygen (O), and includes a first crystal in the orthorhombic or trigonal system. A metal layer provided between the first gate electrode layer and the gate insulating layer, Equipped with, In a second direction perpendicular to the first direction, the gate insulating layer is not provided between the first insulating layer and the semiconductor layer. A semiconductor memory device wherein the first thickness in the second direction at both ends of the metal layer in the first direction is greater than the second thickness in the second direction at the intermediate portion of the metal layer in the first direction.

12. The semiconductor memory device according to claim 11, wherein the first distance in the second direction between the two ends and the semiconductor layer is smaller than the second distance in the second direction between the intermediate portion and the semiconductor layer.

13. The semiconductor memory device according to claim 11, wherein the metal layer is not provided between the first gate electrode layer and the first insulating layer.

14. The semiconductor memory device according to claim 11, wherein the first gate electrode layer contains a different metal element from the metal layer.

15. The semiconductor memory device according to claim 11, wherein the metal layer surrounds the gate insulating layer in a cross section perpendicular to the first direction.

16. The semiconductor memory device according to claim 11, wherein the metal layer surrounds the semiconductor layer in a cross-section perpendicular to the first direction.

17. The semiconductor memory device according to claim 11, wherein the metal layer comprises titanium (Ti) or tungsten (W).

18. The semiconductor memory device according to claim 11, wherein the first gate electrode layer includes a metal region and a conductive film provided between the metal region and the metal layer, and between the metal region and the first insulating layer.

19. The semiconductor memory device according to claim 12, wherein the gate insulating layer includes a ferroelectric material.

20. The semiconductor memory device according to claim 11, wherein the gate insulating layer contains at least one element selected from the group consisting of silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Ru).

21. A semiconductor layer extending in a first direction, The first gate electrode layer, A second gate electrode layer is provided spaced apart from the first gate electrode layer in the first direction, A gate insulating layer is provided between the first gate electrode layer and the semiconductor layer, and comprises hafnium (Hf) and oxygen (O), and includes a first crystal in the orthorhombic or trigonal system. A first insulating layer is provided between the first gate electrode layer and the second gate electrode layer, A second insulating layer is provided between the first gate electrode layer and the second gate electrode layer, and between the first insulating layer and the gate insulating layer, and has a different chemical composition from the first insulating layer, and contains at least one of the elements aluminum (Al) or tantalum (Ta) and oxygen (O), A semiconductor memory device equipped with the following features.

22. The semiconductor memory device according to claim 21, wherein the first insulating layer comprises silicon (Si) and oxygen (O).

23. The semiconductor memory device according to claim 21, wherein the proportion of the first crystals in the crystals contained in the gate insulating layer between the second insulating layer and the semiconductor layer is smaller than the proportion of the first crystals in the crystals contained in the gate insulating layer between the first gate electrode layer and the semiconductor layer.

24. The semiconductor memory device according to claim 21, wherein the first length of the second insulating layer in a second direction perpendicular to the first direction is greater than the thickness of the gate insulating layer in the second direction.

25. The semiconductor memory device according to claim 21, wherein the first length of the second insulating layer in a second direction perpendicular to the first direction is greater than the second length of the second insulating layer in the first direction.

26. The semiconductor memory device according to claim 21, wherein the second insulating layer surrounds the gate insulating layer in a cross section perpendicular to the first direction.

27. The semiconductor memory device according to claim 21, wherein the gate insulating layer contains a ferroelectric material.

28. The semiconductor memory device according to claim 21, wherein the gate insulating layer contains at least one element selected from the group consisting of silicon (Si), scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), aluminum (Al), strontium (Sr), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Ru).

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