Memory controller, method for controlling the memory controller, and program

Abstract

The present invention provides a memory controller, a method for controlling the memory controller, and a program that return a response to a larger number of initiators without waiting for a period during which the DRAM cannot process the transfer. [Solution] The memory controller includes an access holding circuit that holds memory access requests, an alert signal receiving circuit that receives alert signals from the DRAM, and a control means that, when an alert signal is received, prioritizes a specific memory access request from among the memory access requests held by the access holding circuit for a predetermined period and issues a command to the DRAM.

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