Semiconductor device and method for manufacturing a semiconductor device

Abstract

To improve the voltage resistance of semiconductor devices. [Solution] The semiconductor device according to this embodiment includes a semiconductor layer and first to third field plate (FP) insulating films provided columnarly within a first semiconductor region of a first conductivity type in the semiconductor layer, each containing first to third FP electrodes. The second FP insulating film is aligned with the first FP insulating film along a second direction perpendicular to a first direction toward the second main surface of the semiconductor layer. The third FP insulating film is aligned with the first FP insulating film along a third direction perpendicular to the first direction and different from the second direction. The first distance between the first FP electrode and the second FP electrode is smaller than the second distance between the first FP electrode and the third FP electrode. The first FP insulating film includes a first portion located on a line connecting the first FP electrode and the second FP electrode, and a second portion located on a line connecting the first FP electrode and the third FP electrode, having a higher dielectric constant than the first portion.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] So-called dot-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are known, which have multiple columnar field plate electrodes (FP electrodes). In semiconductor devices such as MOSFETs, a high breakdown voltage is desirable. However, in dot-type MOSFETs, the distance between the FP electrode and the gate electrode is not constant. Therefore, in areas where the distance from the FP electrode to the gate electrode is relatively long, the drift region may not be sufficiently depleted compared to areas where the distance is relatively short, and the target breakdown voltage may not be achieved. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-47742 [Patent Document 2] Japanese Patent Publication No. 2019-165182 [Patent Document 3] Japanese Patent Publication No. 2021-52054 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a semiconductor device that can improve voltage resistance. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment comprises a semiconductor layer, a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, a first field plate insulating film, a second field plate insulating film, and a third field plate insulating film. The semiconductor layer comprises a first main surface and a second main surface. The first electrode is provided on the first main surface. The second electrode is provided on the second main surface. The first semiconductor region is provided within the semiconductor layer and is electrically connected to the first electrode. The second semiconductor region is provided within the semiconductor layer and is located above the first semiconductor region. The third semiconductor region is provided within the semiconductor layer and is located above the second semiconductor region. The gate electrode is provided within the second semiconductor region via a gate insulating film. The first field plate insulating film is provided in a columnar shape within the first semiconductor region, and the first field plate electrode is disposed inside it. The second field plate insulating film is provided in a columnar shape within the first semiconductor region, with the second field plate electrode positioned inside, and is aligned with the first field plate insulating film along a second direction perpendicular to the first direction toward the second main surface from the first main surface. The third field plate insulating film is provided in a columnar shape within the first semiconductor region, with the third field plate electrode positioned inside, and is aligned with the first field plate insulating film along a third direction perpendicular to the first direction and different from the second direction. The first distance between the first field plate electrode and the second field plate electrode is smaller than the second distance between the first field plate electrode and the third field plate electrode. The first field plate insulating film comprises a first portion located on a line connecting the first field plate electrode and the second field plate electrode, and a second portion located on a line connecting the first field plate electrode and the third field plate electrode. The dielectric constant of the second portion of the first field plate insulating film is higher than the dielectric constant of the first portion of the first field plate insulating film. [Brief explanation of the drawing]

[0006] [Figure 1] It is a plan view of a semiconductor device according to the first embodiment. [Figure 2] It is an enlarged view of FIG. 1. [Figure 3] It is a cross-sectional view along the U-axis direction of FIG. 1 in the semiconductor device according to the first embodiment. [Figure 4] It is a cross-sectional view along the V-axis direction of FIG. 1 in the semiconductor device according to the first embodiment. [Figure 5A] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment. [Figure 5B] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5A. [Figure 5C] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5B. [Figure 5D] It is a schematic plan view of the semiconductor device according to the first embodiment in the manufacturing process shown in FIG. 5C. [Figure 5E] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5C. [Figure 5F] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5E. [Figure 5G] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5F. [Figure 5H] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5G. [Figure 5I] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to the first embodiment, following FIG. 5H. [Figure 6] It is a cross-sectional view along the U-axis direction of FIG. 1 in the semiconductor device according to a modification of the first embodiment. [Figure 7] It is a cross-sectional view for explaining an example of the manufacturing process of the semiconductor device according to a modification of the first embodiment. [Figure 8] It is a plan view of a semiconductor device according to the second embodiment. [Figure 9] This is an enlarged view of Figure 8. [Figure 10] This is a cross-sectional view of the semiconductor device according to the second embodiment, along the U-axis direction in Figure 8. [Figure 11] This is a cross-sectional view of the semiconductor device according to the second embodiment, along the V-axis direction in Figure 8. [Figure 12A] This is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the second embodiment. [Figure 12B] Figure 12A is a schematic plan view of the semiconductor device according to the second embodiment in the manufacturing process shown. [Figure 12C] Figure 12A is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the first embodiment. [Figure 12D] Figure 12C is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the first embodiment. [Figure 12E] Figure 12D is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the first embodiment. [Figure 12F] Figure 12E is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the first embodiment. [Figure 13] This is a cross-sectional view of the semiconductor device according to the third embodiment, along the U-axis direction in Figure 8. [Figure 14] This is a cross-sectional view illustrating an example of the manufacturing process for a semiconductor device according to the third embodiment. [Figure 15] This is a plan view of a semiconductor device according to another modified example of the embodiment 1. [Figure 16] This is a plan view of a semiconductor device according to another modified example of the embodiment (part 2). [Figure 17] This is a plan view of a semiconductor device according to another modified example 3 of the embodiment. [Figure 18] This is a plan view of a semiconductor device according to another modified example 4 of the embodiment. [Figure 19] This is a plan view of a semiconductor device according to another modified example 5 of the embodiment.

Best Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the existing drawings, and the detailed description will be omitted as appropriate.

[0008] Also, in the following description, in order to represent the relative high and low of the impurity concentration in each conductivity type, n + , n, n - , and, p + , p, p - may be used in the notation. That is, n + indicates that the n-type impurity concentration is relatively higher than n, and n - indicates that the n-type impurity concentration is relatively lower than n. Also, p + indicates that the p-type impurity concentration is relatively higher than p, and p - indicates that the p-type impurity concentration is relatively lower than p. These notations represent the relative high and low of the net impurity concentration after these impurities compensate for each other when both p-type impurities and n-type impurities are included in each region. The n-type, n + type and n - type are an example of the first conductivity type in the claims. The p-type, p + type and p - type are an example of the second conductivity type in the claims. In the following description, the n-type and p-type may be reversed. That is, the first conductivity type may be p-type.

[0009] Also, the impurity concentration of the semiconductor region can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative high and low of the impurity concentration can be determined, for example, from the high and low of the carrier concentration obtained by Scanning Capacitance Microscopy (SCM).

[0010] Furthermore, dimensions such as the thickness of the field plate insulating film can be measured, for example, by surface and / or cross-sectional analysis using a transmission electron microscope (TEM), energy dispersive X-ray spectroscopy (EDX), or scanning electron microscope (SEM).

[0011] Furthermore, the composition of the field plate insulating film can be analyzed, for example, by X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry.

[0012] In this specification, terms such as "identical," "same," and "equal," as well as dimensions and physical property values ​​used to specify shape, geometric conditions, physical properties, and their degrees, shall not be strictly interpreted, but shall be interpreted to include a range that allows for the expectation of similar functionality.

[0013] (First Embodiment) A semiconductor device 1 according to the first embodiment will be described with reference to Figures 1 to 4. Figure 1 is a plan view of the semiconductor device 1 according to the first embodiment. In Figure 1, the U-axis direction is the direction from FP trench FT1 to FP trench FT2. The V-axis direction is the direction from FP trench FT1 to FP trench FT3. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device 1. Both the U-axis direction and the V-axis direction are perpendicular to the Z-axis direction. Note that within the Z-axis direction, the source electrode side is also called "up" and the drain electrode side is also called "down". However, this expression is for convenience and is unrelated to the direction of gravity. The Z-axis direction is the first direction in the claims. The U-axis direction is the second direction in the claims. The V-axis direction is the third direction in the claims. Also, in Figure 1, the source electrode 12, source region 24 and interlayer insulating film 60 are omitted. Figure 2 is an enlarged view of Figure 1, showing an enlarged view of the area around FP trenches FT1, FT2, and FT3. Figure 3 is a cross-sectional view of the semiconductor device 1 according to the first embodiment, along the U-axis direction of Figure 1. Figure 4 is a cross-sectional view of the semiconductor device 1 according to the first embodiment, along the V-axis direction of Figure 1. In Figure 3, FP electrodes 31 and 32 are shown as FP electrodes 30, and in Figure 4, FP electrodes 31 and 33 are shown as FP electrodes 30.

[0014] The semiconductor device 1 is, for example, a MOSFET. More specifically, the semiconductor device 1 is a so-called dot-type MOSFET having a plurality of field plate electrodes (FP electrodes) arranged in a columnar shape, i.e., extending in the Z-axis direction. The semiconductor device 1 may also be a dot-type IGBT (Insulated Gate Bipolar Transistor), etc.

[0015] As shown in Figure 1, the semiconductor device 1 includes a plurality of field plate trenches (FP trenches) FT. Within each FP trench FT, there is an FP electrode 30 and a field plate insulating film (FP insulating film) 40 surrounding the FP electrode 30. As will be described in more detail later, each FP insulating film 40 comprises a first portion 40a and a second portion 40b having a higher dielectric constant than the first portion 40a.

[0016] Furthermore, a semiconductor region (for example, a base region 23) is arranged around the FP insulating film 40, and a gate insulating film 50 is arranged around the semiconductor region. A mesh-like gate electrode 13, which is coupled to itself, is provided around the gate insulating film 50.

[0017] Next, the cross-sectional structure of the semiconductor device 1 according to this embodiment will be described.

[0018] In the following description, we will refer to FP trench FT1, FP trench FT2, and FP trench FT3, among the multiple FP trenches FT shown in Figure 1. In this embodiment, the multiple FP trenches FT, such as FP trenches FT1, FT2, and FT3, all have the same configuration.

[0019] Furthermore, as shown in Figure 2, in the following explanation, in order to distinguish the FP electrodes 30 within each FP trench FT1, FT2, and FT3, the FP electrodes 30 within FP trenches FT1, FT2, and FT3 will be referred to as FP electrodes 31, 32, and 33, respectively. Similarly, the FP insulating films 40 within FP trenches FT1, FT2, and FT3 will be referred to as FP insulating films 41, 42, and 43, respectively. Also, the first portions 40a within FP insulating films 41, 42, and 43 will be referred to as first portions 41a, 42a, and 43a, respectively. Similarly, the second portions 40b within FP insulating films 41, 42, and 43 will be referred to as second portions 41b, 42b, and 43b, respectively.

[0020] As shown in Figures 3 and 4, the semiconductor device 1 according to this embodiment comprises a semiconductor layer 2, a drain electrode 11, and a source electrode 12.

[0021] The semiconductor layer 2 is provided between the drain electrode 11 and the source electrode 12. The semiconductor layer 2 has a bottom surface (first main surface) 2a and an upper surface (second main surface) 2b opposite to the bottom surface 2a. Various semiconductor regions, which will be described later, are provided within the semiconductor layer 2.

[0022] The semiconductor layer 2 may be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate with an epitaxial layer disposed thereon. In this embodiment, the semiconductor layer 2 is silicon (Si). In this case, for example, arsenic (As), phosphorus (P), or antimony (Sb) can be used as the n-type impurity, and for example, boron (B) can be used as the p-type impurity. The semiconductor layer 2 may also be made of a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

[0023] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is provided on the lower surface 2a of the semiconductor layer 2. The drain electrode 11 is in contact with the drain region 22, and for example, it is in ohmic contact with the drain region 22. The drain electrode 11 is an example of the first electrode in the claims. The drain electrode 11 includes, for example, at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al).

[0024] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is provided on the upper surface 2b of the semiconductor layer 2. The source electrode 12 is in contact with the source region 24, for example, and makes ohmic contact with the source region 24. The source electrode 12 is an example of the second electrode in the claims. The source electrode 12 includes, for example, at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al).

[0025] The following describes the structure within semiconductor layer 2.

[0026] Within the semiconductor layer 2, for example, there is a drift region 21, a drain region 22, a base region 23, a source region 24, a gate electrode 13, FP electrodes 30 (FP electrodes 31, 32, 33), FP insulating film 40 (FP insulating film 41, 42, 43), a gate insulating film 50, and an interlayer insulating film 60.

[0027] The drift region 21 functions as the drift region of the MOSFET. The drift region 21 is located above the drain region 22 (above the drain electrode 11). The drift region 21 is, for example, n - This is a semiconductor region of a certain shape. The n-type impurity concentration in the drift region 21 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 16 cm -3 The following applies:

[0028] The drain region 22 functions as the drain region of the MOSFET. The drain region 22 is located above the drain electrode 11 and is positioned between the drift region 21 and the drain electrode 11. The drain region 22 is in contact with the drain electrode 11 and is electrically connected to the drain electrode 11. The drain region 22 is, for example, n + This is a semiconductor region of a certain type. The n-type impurity concentration in the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0029] The drift region 21 and the drain region 22 are both examples of the first semiconductor region in the claims. The drain region 22 is optional. In this case, the drift region 21 is provided directly on the drain electrode 11, and the drain electrode 11 is electrically connected to the drift region 21. Alternatively, the drift region 21 is also optional. In this case, for example, the drain region 22 may also be provided at the location of the drift region 21.

[0030] The base region 23 functions as the base region of the MOSFET. The base region 23 is located above the drift region 21. The base region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration in the base region 23 is, for example, 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 20 cm -3 The following applies: Base region 23 is an example of a second semiconductor region in the claims.

[0031] The source region 24 functions as the source region of the MOSFET. The source region 24 is located on top of the base region 23. The source region 24 is in contact with the source electrode 12 and is electrically connected to the source electrode 12. The source region 24 is, for example, n + This is a semiconductor region of a certain type. The n-type impurity concentration in the source region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3 The following is true: Source region 24 is an example of a third semiconductor region in the claims.

[0032] The gate electrode 13 functions as the gate electrode of the MOSFET. The gate electrode 13 is located within the base region 23 via a gate insulating film 50. The gate electrode 13 is electrically insulated from the semiconductor layer 2 by the gate insulating film 50. The gate electrode 13 is made of, for example, polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 13, a channel is formed in the base region 23, and carriers flow between the drift region 21 and the source region 24. This turns the MOSFET on.

[0033] The FP electrode 30 is provided in a columnar shape within the drift region 21 via the FP insulating film 40. In Figure 3, FP electrodes 31 and 32 are shown as FP electrodes 30, and in Figure 4, FP electrodes 31 and 33 are shown as FP electrodes 30. FP electrodes 31, 32, and 33 are examples of the first field plate electrode, second field plate electrode, and third field plate electrode in the claims, respectively.

[0034] The FP electrode 30 is electrically insulated from the semiconductor layer 2 by the FP insulating film 40 and is electrically connected to the source electrode 12. In the examples of Figures 3 and 4, the source electrode 12 protrudes downward from the upper surface 2b of the semiconductor layer 2 and has a portion that contacts the FP electrode 30. The FP electrode 30 is made of polysilicon containing, for example, p-type or n-type impurities.

[0035] In this embodiment, the FP electrode 30 is positioned adjacent to both the drift region 21 and the base region 23. That is, the upper end of the FP electrode 30 is higher than the lower end of the base region 23. However, the upper end of the FP electrode 30 may be lower than the lower end of the base region 23.

[0036] The FP insulating film 40 is provided in a columnar shape within the drift region 21, with the FP electrode 30 positioned inside. More specifically, the FP insulating film 41 is provided in a columnar shape within the drift region 21, with the FP electrode 31 positioned inside. The FP insulating film 42 is provided in a columnar shape within the drift region 21, with the FP electrode 32 positioned inside. The FP insulating film 43 is provided in a columnar shape within the drift region 21, with the FP electrode 33 positioned inside. The FP insulating films 41, 42, and 43 are examples of the first field plate insulating film, the second field plate insulating film, and the third field plate insulating film as defined in the claims.

[0037] As shown in Figure 1, the FP insulating film 40 comprises a first portion 40a and a second portion 40b. As shown in Figure 2, for example, the FP insulating film 41 comprises a first portion 41a and a second portion 41b. In Figure 3, the first portion 40a of the FP insulating film 40 is shown to be the first portion 41a of the FP insulating film 41 and the first portion 42a of the FP insulating film 42. In Figure 4, the second portion 40b of the FP insulating film 40 is shown to be the second portion 41b of the FP insulating film 41 and the second portion 43b of the FP insulating film 43.

[0038] The dielectric constant of the second portion 40b in the FP insulating film 40 is higher than that of the first portion 40a in the FP insulating film 40. For example, the dielectric constant of the second portion 41b in the FP insulating film 41 is higher than that of the first portion 41a in the FP insulating film 41. In this embodiment, the first portion 40a of the FP insulating film 40 is a silicon oxide film, and the second portion 40b of the FP insulating film 40 is made of a material with a higher dielectric constant than the silicon oxide film. The second portion 40b includes, for example, a silicon nitride film. In this case, for example, the relative dielectric constant of the first portion 41a is about 3.9, and the relative dielectric constant of the second portion 40b is about 7.0.

[0039] Furthermore, as shown in Figure 4, in this embodiment, the FP insulating film 40 includes a third portion 40c located below the second portion 40b and positioned above the drift region 21. For example, the FP insulating film 41 includes a third portion 41c located below the second portion 41b and positioned above the drift region 21. In Figure 4, the third portion 40c of the FP insulating film 40 is shown as the third portion 41c of the FP insulating film 41 and the third portion 43c of the FP insulating film 43. The third portion 40c is made of the same material as, for example, the first portion 40a. The third portion 40c is, for example, a silicon oxide film.

[0040] The gate insulating film 50 electrically insulates the gate electrode 13 from the semiconductor layer 2 and the source electrode 12. The gate insulating film 50 includes, for example, silicon oxide or silicon nitride.

[0041] The interlayer insulating film 60 is provided on top of the FP insulating film 40. The interlayer insulating film 60 contains, for example, silicon oxide or silicon nitride. The thickness of the interlayer insulating film 60 and the position of its lower end are not limited to the examples shown in Figures 3 and 4 and are arbitrary. The interlayer insulating film 60 may also be provided on top of the gate electrode 13.

[0042] Next, with reference to Figure 2, the planar structure of the semiconductor device 1 according to this embodiment will be described in more detail.

[0043] As shown in Figure 2, in this embodiment, the FP insulating film 40 is hexagonal in a plane perpendicular to the Z-axis, i.e., a plane containing the U-axis and V-axis (UV plane). For example, the FP insulating film 41 in the FP trench FT1 is hexagonal in the UV plane.

[0044] The FP trench FT2 is positioned to align with the FP trench FT1 along the U-axis direction, which is perpendicular to the Z-axis direction. That is, the FP electrode 32 is aligned with the FP electrode 31 along the U-axis direction. Also, the FP insulating film 42 is aligned with the FP insulating film 41 along the U-axis direction.

[0045] The FP trench FT3 is positioned parallel to the FP trench FT1 along the V-axis, which is perpendicular to the Z-axis and different from the U-axis. That is, the FP electrode 33 is aligned with the FP electrode 31 along the V-axis. Also, the FP insulating film 43 is aligned with the FP insulating film 41 along the V-axis.

[0046] Furthermore, FP trench FT2 is located closer to FP trench FT1 than FP trench FT3. That is, the distance d1 between FP electrode 31 and FP electrode 32 is smaller than the distance d2 between FP electrode 31 and FP electrode 33. Distances d1 and d2 are examples of the first and second distances in the claims, respectively.

[0047] In the example in Figure 2, distance d1 is defined as the distance between the center C of FP electrode 31 and the center C of FP electrode 32 in the UV plane. Distance d2 is defined as the distance between the center C of FP electrode 31 and the center C of FP electrode 33 in the UV plane. Note that the definitions of distance d1 and distance d2 are not limited to those described above. For example, distance d1 may be defined as the distance between the end of FP electrode 31 and the end of FP electrode 32 in the UV plane.

[0048] Furthermore, the first portion 41a of the FP insulating film 41 is located on the line connecting the FP electrode 31 and the FP electrode 32. The second portion 41b of the FP insulating film 41 is located on the line connecting the FP electrode 31 and the FP electrode 33. That is, the first portion 41a of the FP insulating film 41 is located at the edge of the FP insulating film 41 in the UV plane. The second portion 41b of the FP insulating film 41 is located at the corner of the FP insulating film 41 in the UV plane. Note that the planar shapes of the first portion 40a and the second portion 40b are not limited to the example shown in Figure 2, but are arbitrary. For example, the width of the first portion 40a may be larger or smaller than the example shown in Figure 2.

[0049] Furthermore, the positions of the first portion 41a and the second portion 41b of the FP insulating film 41 are related to the gate electrode 13 as follows. That is, the gate electrode 13 extends for at least a predetermined length along a direction perpendicular to the Z-axis. For example, in Figure 2, the gate electrode 13 between the FP insulating film 41 and the FP insulating film 42 extends for at least a predetermined length along a direction perpendicular to the U-axis. In this direction, there are positions P1 and P2 on the gate electrode 13 that are at different distances from the FP insulating film 41. More specifically, the distance between the FP electrode 31 and position P1 of the gate electrode 13 is smaller than the distance between the FP electrode 31 and position P2 of the gate electrode 13. The first portion 41a of the FP insulating film 41 is located on the line connecting the FP electrode 31 and position P1, and the second portion 41b of the FP insulating film 41 is located on the line connecting the FP electrode 31 and position P2. In the example in Figure 2, position P1 corresponds to the position in the gate electrode 13 between the FP insulating films 41 and 42 that is closest to the center C of the FP electrode 31. Furthermore, position P2 corresponds to the position furthest from the center C in the gate electrode 13 between the FP insulating films 41 and 42. In other words, for example, position P2 is located at the geometric centroid of the FP electrodes 31 and 32 and the FP electrode 30 shown below the FP electrode 32 in Figure 2. Position P1 is an example of a first position in the claims. Position P2 is an example of a second position in the claims.

[0050] As described above, the semiconductor device 1 according to this embodiment includes an FP insulating film 41 provided in a columnar shape within the drift region 21, with an FP electrode 31 disposed inside; an FP insulating film 42 provided in a columnar shape within the drift region 21, with an FP electrode 32 disposed inside, and aligned with the FP insulating film 41 along the U-axis direction perpendicular to the Z-axis direction from the lower surface 2a to the upper surface 2b of the semiconductor layer 2; and an FP insulating film 43 provided in a columnar shape within the drift region 21, with an FP electrode 33 disposed inside, and aligned with the FP insulating film 41 along the V-axis direction perpendicular to the Z-axis direction and different from the U-axis direction. The distance d1 between the FP electrode 31 and the FP electrode 32 is smaller than the distance d2 between the FP electrode 31 and the FP electrode 33. The FP insulating film 41 includes a first portion 41a located on the line connecting the FP electrode 31 and the FP electrode 32, and a second portion 42b located on the line connecting the FP electrode 31 and the FP electrode 33. The dielectric constant of the second portion 42b in the FP insulating film 41 is higher than the dielectric constant of the first portion 41a in the FP insulating film 41.

[0051] According to this embodiment, the breakdown voltage of the semiconductor device 1 can be improved. The effects and advantages of this embodiment will be described below.

[0052] Generally, in semiconductor devices equipped with dot-type FP electrodes, when a reverse bias is applied between the drain electrode 11 and the source electrode 12, the depletion layer extending from the FP insulating film 40 around the FP electrode 30 to the drift region 21 is formed first in the portion close to the FP electrode 30, while the arrival (depletion) of the depletion layer is delayed in the portion farther from the FP electrode 30. For example, at a certain point in time, the depletion layer from the FP electrode 31 (32) reaches the area below the Z-axis direction of position P1 shown in Figure 2. On the other hand, the depletion layer from the FP electrode 31 has not yet reached the area below the Z-axis direction of position P2. When there is such a difference in the arrival of the depletion layer, the electric field concentrates in the undepleted area, and the breakdown voltage of the semiconductor device 1 decreases.

[0053] On the other hand, according to the semiconductor device 1 of this embodiment, the dielectric constant of the second portion 40b in the FP insulating film 40 is higher than the dielectric constant of the first portion 40a in the FP insulating film 40. As a result, in the region of the drift region 21 that is in contact with the second portion 40b, the formation of the depletion layer is promoted more than in the region that is in contact with the first portion 40a. This makes it possible to suppress differences in the arrival of the depletion layer depending on the position within the drift region 21. Therefore, the breakdown voltage of the semiconductor device 1 can be improved.

[0054] Furthermore, the above effects can be obtained without reducing the impurity concentration in the drift region 21. Therefore, according to this embodiment, the breakdown voltage of the semiconductor device 1 can be improved without reducing the impurity concentration in the drift region 21. In other words, the trade-off between breakdown voltage and on-resistance in the semiconductor device 1 can be improved.

[0055] Furthermore, in this embodiment, the third portion 40c is provided below the second portion 40b, thereby improving the leakage characteristics of the semiconductor device 1.

[0056] In the example above, the second portion 40b was provided at all corners of the FP insulating film 40 in the UV plane. However, it is not limited to this, and the second portion 40b may be provided at at least one corner of the FP insulating film 40. In this case, the corner where the second portion 40b is not provided is made of the same material as the first portion 40a, for example.

[0057] <Method for manufacturing semiconductor device 1> Next, an example of a method for manufacturing the semiconductor device 1 according to this embodiment will be described with reference to Figures 5A to 5I. Figures 5A to 5C and 5E to 5I are cross-sectional views illustrating an example of the manufacturing process of the semiconductor device 1 according to the first embodiment, and are cross-sectional views along line AA in Figure 2. Figure 5D is a schematic plan view of the semiconductor device 1 according to the first embodiment in the manufacturing process shown in Figure 5C.

[0058] First, a semiconductor layer as shown in Figure 5A is prepared. This semiconductor layer comprises a semiconductor region 101 of the first conductivity type and an insulating region 103. The semiconductor region 101 corresponds to the aforementioned drift region 21. The insulating region 103 corresponds to the aforementioned FP insulating film 40. The insulating region 103 is, for example, a silicon oxide film. Within the semiconductor region 101, there are at least multiple insulating regions 103, each corresponding to the aforementioned FP insulating films 41, 42, and 43. The planar shape and positional relationship of the multiple insulating regions 103 are the same as those of the FP insulating films 41, 42, and 43. Although not shown, the aforementioned FP electrodes 30 are arranged inside each insulating region 103.

[0059] Next, as shown in Figure 5B, an insulating region 105 is formed by depositing an insulating material on the upper surface of the semiconductor layer using chemical vapor deposition (CVD), such as reduced-pressure CVD (LPCVD). The insulating material is, for example, silicon nitride, and the insulating region 105 is a silicon nitride film.

[0060] Next, as shown in Figure 5C, an opening 105a is formed in the insulating region 105 by photolithography and reactive ion etching (RIE), etc. As shown in Figure 5D, the opening 105a is formed so as to be located above the corner of the insulating region 103.

[0061] Next, as shown in Figure 5E, a trench T1 is formed in the insulating region 103 using an RIE or the like with the insulating region 105 as a mask (hard mask). In this embodiment, the trench T1 is formed by removing at least part of the insulating region 103 from the upper surface of the semiconductor layer. As a result, an insulating region 103a, which is a part of the insulating region 103, remains at the bottom of the trench T1. The insulating region 103a corresponds to the third portion 40c (for example, the third portion 41c) mentioned above.

[0062] Next, as shown in Figure 5F, the insulating region 105 is removed by wet etching or the like. Note that if the insulating region 105 is made of the same material as the insulating region 107 described later, this step may be omitted.

[0063] Next, as shown in Figure 5G, an insulating material is deposited on the upper surface of the semiconductor layer using LPCVD or the like. This fills the trench T1 and forms an insulating region 107 that covers the upper surface of the semiconductor layer. The insulating material is a material with a higher dielectric constant than the silicon oxide film, such as silicon nitride. The insulating region 107 is, for example, a silicon nitride film.

[0064] Next, as shown in Figure 5H, the portion of the insulating region 107 above the upper surface of the semiconductor layer is removed by wet etching or the like. More specifically, the portion of the insulating region 107 located above the semiconductor region 101, the portion located above the insulating region 103, and the portion protruding upward from the trench T1 are removed. As a result, the portion of the insulating region 107 that fills the trench T1 remains as the insulating region 109. The insulating region 109 corresponds to the second portion 40b (for example, the second portion 41b) mentioned above. Also, the portions of the insulating region 103 located on both sides of the insulating region 109 correspond to the first portion 40a (for example, the first portion 41a) mentioned above.

[0065] Next, as shown in Figure 5I, an insulating region 111 is formed by depositing an insulating material on the upper surface of the semiconductor layer using CVD or the like. The insulating material is, for example, silicon oxide, and the insulating region 111 is a silicon oxide film. The insulating region 111 corresponds to the interlayer insulating film 60 described above.

[0066] Subsequently, although not shown in the diagram, a gate electrode 13 and a gate insulating film 50 are formed on the upper surface of the semiconductor layer by RIE and CVD, etc. Also, a base region 23 is formed by ion implantation of p-type impurities on the upper surface of the semiconductor layer. Then, a source region 24 is formed by ion implantation of n-type impurities on the upper surface of the semiconductor layer. Then, a drain region 22 is formed by ion implantation of n-type impurities on the lower surface of the semiconductor layer. Finally, a drain electrode 11 is formed on the lower surface of the semiconductor layer and a source electrode 12 is formed on the upper surface of the semiconductor layer.

[0067] The semiconductor device 1 is manufactured through the above process.

[0068] In the manufacturing method of the semiconductor device 1 described above, a trench T1 is formed, and after filling the trench T1 with an insulating region 109, the base region 23 and source region 24 are formed. However, the method is not limited to this; the trench T1 may be formed after the base region 23 and source region 24 are formed, and then the trench T1 may be filled with an insulating region 109.

[0069] (Modification of the first embodiment) In the manufacturing method of the first embodiment described above, the portion of the insulating region 107 above the upper surface of the semiconductor layer was removed in the step shown in Figure 5H. However, this step is not limited to this and may be omitted. Below, a modified example of the manufacturing method of the first embodiment in which this step is omitted will be described, focusing on the differences from the first embodiment.

[0070] Figure 6 is a cross-sectional view of a semiconductor device 1A according to a modification of the first embodiment, along the U-axis direction of Figure 1. As shown in Figure 6, in this modification, the FP insulating film 40 further comprises a fourth portion 40Ad located on the first portion 40a. That is, the fourth portion 40Ad is provided between the first portion 40a and the interlayer insulating film 60. In Figure 6, the fourth portion 40Ad is shown as the fourth portion 41Ad of the FP insulating film 41 and the fourth portion 42Ad of the FP insulating film 42. The fourth portion 40Ad includes a silicon nitride film. Although not shown, the fourth portion 40Ad may also be provided on at least one of the source region 24 and the gate insulating film 50.

[0071] <Manufacturing method for semiconductor device 1A> Figure 7 is a cross-sectional view illustrating an example of the manufacturing process of a semiconductor device 1 according to a modified example of the first embodiment, and corresponds to a cross-sectional view along line AA in Figure 2.

[0072] As shown in Figure 7, in this modified example, after forming the insulating region 107, an insulating region 111 corresponding to the interlayer insulating film 60 is formed without removing a portion of the insulating region 107. Note that if the fourth portion 40Ad is not provided on the source region 24 and the gate insulating film 50, the portion of the insulating region 107 located on the semiconductor region 101 is removed before forming the insulating region 111.

[0073] The subsequent steps are the same as in the first embodiment.

[0074] According to the manufacturing method of the semiconductor device 1A in this modified example, it is possible to suppress the intrusion of moisture from the insulating region 111, which is an interlayer insulating film, into the semiconductor layer. Therefore, according to this modified example, the reliability of the semiconductor device 1A can be improved.

[0075] (Second Embodiment) In the first embodiment described above, a silicon oxide film is provided in the first portion 40a of the FP insulating film 40, and a material with a dielectric constant higher than that of the silicon oxide film is provided in the second portion 40b. On the other hand, in the second embodiment described below, a silicon oxide film is provided in the second portion 40b of the FP insulating film 40, and a material with a dielectric constant lower than that of the silicon oxide film is provided in the first portion 40a. The second embodiment will be described below, focusing on the differences from the first embodiment.

[0076] Figure 8 is a plan view of semiconductor device 1B according to the second embodiment. Figure 9 is an enlarged view of Figure 8, showing an enlarged view of the area around FP trenches FT1, FT2, and FT3. As shown in Figures 8 and 9, in this embodiment, the second portion 40Bb of the FP insulating film 40 is a silicon oxide film, and the first portion 40Ba of the FP insulating film 40 is made of a material with a lower dielectric constant than the silicon oxide film. The first portion 40Ba includes, for example, a spin-on-glass film (SOG film). The material of the SOG film is silica glass, alkylsiloxane polymer, alkylsilsesquioxane polymer, hydrogenated silsesquioxane polymer, hydrogenated alkylsilsesquioxane polymer, etc. In this case, for example, the relative dielectric constant of the first portion 41Ba is about 2.9, and the relative dielectric constant of the second portion 40Bb is about 3.9.

[0077] Figure 10 is a cross-sectional view of the semiconductor device 1B according to the second embodiment along the U-axis direction of Figure 8. Figure 11 is a cross-sectional view of the semiconductor device 1B according to the second embodiment along the V-axis direction of Figure 8. As shown in Figure 10, this embodiment includes a fifth portion 40Bc located below the first portion 40Ba and positioned above the drift region 21. In Figure 10, the fifth portion 41Bc of the FP insulating film 41 and the fifth portion 42Bc of the FP insulating film 42 are shown as the fifth portion 40Bc of the FP insulating film 40. The fifth portion 40Bc is made of the same material as, for example, the second portion 40Bb. The fifth portion 40Bc is, for example, a silicon oxide film.

[0078] In this embodiment, contrary to the first embodiment, the formation of the depletion layer is suppressed in the region of the drift region 21 that is in contact with the first portion 40Ba, more so than in the region that is in contact with the second portion 40Bb. As a result, similar to the first embodiment, differences in the arrival of the depletion layer depending on the position within the drift region 21 can be suppressed. Therefore, the breakdown voltage of the semiconductor device 1B can be improved.

[0079] Furthermore, in this embodiment, the provision of a fifth portion 40Bc below the first portion 41Ba improves the leakage characteristics of the semiconductor device 1B.

[0080] In the example above, the first portion 40Ba was provided at all corners of the FP insulating film 40 in the UV plane. However, it is not limited to this, and the first portion 40Ba may be provided at at least one edge of the FP insulating film 40. In this case, the corners where the first portion 40Ba is not provided are made of the same material as, for example, the second portion 40Bb.

[0081] Furthermore, this embodiment may be combined with the first embodiment. For example, in the UV plane, a first portion made of a material with a dielectric constant lower than that of the silicon oxide film may be provided at the edge of the FP insulating film 40, a second portion made of a material with a dielectric constant higher than that of the silicon oxide film may be provided at the corner of the FP insulating film 40, and a portion made of the silicon oxide film may be provided between the first portion and the second portion.

[0082] <Manufacturing method for semiconductor device 1B> Next, an example of a manufacturing method for the semiconductor device 1B according to this embodiment will be described with reference to Figures 12A to 12F. Figures 12A and 12C to 12F are cross-sectional views illustrating an example of the manufacturing process for the semiconductor device 1B according to the second embodiment, and are cross-sectional views along line BB in Figure 9. Figure 12B is a schematic plan view of the semiconductor device 1B according to the second embodiment in the manufacturing process shown in Figure 12A.

[0083] First, a semiconductor layer comprising a semiconductor region 101 of a first conductivity type and an insulating region 103 is prepared, similar to the manufacturing method of the first embodiment. Then, an insulating region 105 is formed by depositing an insulating material on the upper surface of the semiconductor layer using LPCVD or the like.

[0084] Next, as shown in Figure 12A, an opening 105b is formed in the insulating region 105 by photolithography and RIE, etc. As shown in Figure 12B, the opening 105b is formed so as to be located on the edge of the insulating region 103.

[0085] Next, as shown in Figure 12C, a trench T2 is formed in the insulating region 103 using an RIE or the like with the insulating region 105 as a mask. In this embodiment, the trench T2 is formed such that an insulating region 103b, which is a part of the insulating region 103, remains at the bottom of the trench T2. The insulating region 103b corresponds to the fifth portion 40Bc (for example, the fifth portion 41Bc) mentioned above.

[0086] Next, as shown in Figure 12D, the insulating region 105 is removed by wet etching or the like.

[0087] Next, as shown in Figure 12E, the trench T2 is filled with a material with a dielectric constant lower than that of the silicon oxide film. For example, an insulating region to fill the trench T2 is formed by using a method such as spin-on-glass. Then, the portion of the insulating region above the top surface of the semiconductor layer is removed by wet etching or the like. This forms an insulating region 113 to fill the trench T2. The insulating region 113 corresponds to the first portion 40Ba (for example, the first portion 41Ba) mentioned above. In addition, the portions of the insulating region 103 located on both sides of the insulating region 113 correspond to the second portion 40Bb (for example, the second portion 41Bb) mentioned above.

[0088] Next, as shown in Figure 12F, an insulating region 111 is formed by depositing an insulating material using CVD or the like. The subsequent steps are the same as in the first embodiment.

[0089] The semiconductor device 1B is manufactured through the above process.

[0090] (Third embodiment) In the second embodiment described above, the first portion 40Ba of the FP insulating film 40 is provided with a material having a dielectric constant lower than that of the silicon oxide film. However, the first portion of the FP insulating film may be a void. The void has a dielectric constant lower than that of the silicon oxide film. Below, the third embodiment, in which the first portion is a void, will be described, focusing on the differences from the second embodiment.

[0091] Figure 13 is a cross-sectional view of the semiconductor device 1C according to the third embodiment, along the U-axis direction of Figure 8. As shown in Figure 13, in this embodiment, the first portion 40Ca of the FP insulating film 40 is a void. In Figure 13, the first portion 41Ca of the FP insulating film 41 and the first portion 42Ca of the FP insulating film 42 are shown as the first portion 40Ca of the FP insulating film 40.

[0092] Furthermore, in this embodiment, the FP insulating film 40 includes a sixth portion 40Cd surrounding the first portion 40Ca. In Figure 13, the sixth portion 41Cd of the FP insulating film 41 and the sixth portion 42Cd of the FP insulating film 42 are shown as the sixth portion 40Cd of the FP insulating film 40. The sixth portion 40Cd is made of the same material as the interlayer insulating film 60, for example. Specifically, the sixth portion 40Cd is, for example, a silicon oxide film. Note that the sixth portion 40Cd may be made of a material with a lower dielectric constant than the silicon oxide film.

[0093] According to this embodiment, similar to the first and second embodiments, it is possible to suppress differences in the arrival of the depletion layer depending on the position within the drift region 21, thereby improving the breakdown voltage of the semiconductor device 1C.

[0094] <Manufacturing method for semiconductor device 1C> Next, an example of a method for manufacturing the semiconductor device 1C according to this embodiment will be described with reference to Figure 14. Figure 14 is a cross-sectional view illustrating an example of the manufacturing process for the semiconductor device 1C according to the third embodiment, and corresponds to a cross-sectional view along line BB in Figure 9.

[0095] As shown in Figure 14, in this embodiment, after forming a trench T2, when depositing an insulating material using CVD or the like, an insulating region 111A is formed such that a void 115 is formed within the trench T2. The insulating material is, for example, silicon oxide, and the insulating region 111A is a silicon oxide film. The insulating region 111A corresponds to the aforementioned sixth portion 40Cd (e.g., sixth portion 41Cd) and the interlayer insulating film 60. More specifically, the portion of the insulating region 111A sandwiched between insulating regions 103 corresponds to the sixth portion 40Cd, and the portion located above the insulating region 103 corresponds to the interlayer insulating film 60. The void 115 corresponds to the aforementioned first portion 40Ca (e.g., first portion 41Ca). The subsequent steps are the same as in the second embodiment.

[0096] The semiconductor device 1C is manufactured through the above process.

[0097] In the first to third embodiments described above, the FP insulating film 40 (for example, the FP insulating film 41) was hexagonal in the UV plane. However, the shape of the FP insulating film 40 in the UV plane is not limited to a hexagon, as long as the shape changes the distance between the FP electrode 30 and the gate electrode 13. Below, we will describe five other modifications of the embodiment in which the shape of the FP insulating film 40 in the UV plane is changed. In all of these modifications, it is possible to suppress differences in the arrival of the depletion layer depending on the position within the drift region 21, and to improve the breakdown voltage of the semiconductor device.

[0098] (Another variation of the embodiment 1) Figure 15 is a plan view of a semiconductor device 1D according to another modification 1 of the embodiment. This modification corresponds to the case where the first embodiment described above is applied to a rectangular FP insulating film 40D. The following description will focus on the differences between this modification and the first embodiment.

[0099] As shown in Figure 15, in this modified example, the FP insulating film 40D (e.g., FP insulating film 41D) is rectangular in the UV plane. Each FP insulating film 40D is provided with a rectangular FP electrode 30D (e.g., FP electrode 31D) inside.

[0100] In this modified example, the gate electrode 13D and the gate insulating film 50D have a stripe-like shape. That is, the gate electrode 13D and the gate insulating film 50D extend for at least a predetermined length along a direction perpendicular to the Z-axis.

[0101] Furthermore, in this modified example, the first portion 40Da (for example, the first portion 41Da) of the FP insulating film 40D is located at the edge of the FP insulating film 40D in the UV plane. The second portion 40Db (for example, the second portion 41Db) of the FP insulating film 40D is located at the corner of the FP insulating film 40D in the UV plane.

[0102] Furthermore, in this modified example, the positions of the first portion 41Da and the second portion 41Db of the FP insulating film 41D are also related to the gate electrode 13D as follows. For example, in Figure 15, the gate electrode 13D between the FP insulating films 41D and 42D extends for at least a predetermined length along a direction perpendicular to the U-axis. The distance between the FP electrode 31D and the position P1 of the gate electrode 13D is smaller than the distance between the FP electrode 31D and the position P2 of the gate electrode 13D.

[0103] According to this modified example, the configuration of the first embodiment can also be applied to a rectangular FP insulating film 40D. Note that the portion of the first portion 40Da that sandwiches the FP electrode 30D along the extending direction of the gate electrode 13D (for example, the first portion 41Da located to the left and right of the FP electrode 31D in Figure 15) may be replaced with the second portion 40Db.

[0104] (Another variation of the embodiment 2) Figure 16 is a plan view of semiconductor device 1E according to another modification 2 of the embodiment. This modification corresponds to the case where the second embodiment is applied to a rectangular FP insulating film. That is, this modification corresponds to the case where the configuration of the FP insulating film in the second embodiment is applied to another modification 1 of the embodiment. The following description will focus on the differences between this modification and another modification 1 of the embodiment.

[0105] As shown in Figure 16, in this modified example, the first portion 40Ea (e.g., the first portion 41Ea) of the FP insulating film 40E (e.g., the FP insulating film 41E) is located at the edge of the FP insulating film 40E in the UV plane. The second portion 40Eb (e.g., the second portion 41Eb) of the FP insulating film 40E is located at the corner of the FP insulating film 40E in the same plane.

[0106] According to this modified example, the configuration of the second embodiment can also be applied to a rectangular FP insulating film 40E.

[0107] (Another variation of the embodiment 3) Figure 17 is a plan view of the semiconductor device 1F according to another modification 3 of the embodiment. This modification corresponds to applying another modification 1 of the embodiment to a circular FP insulating film 40F. The following description will focus on the differences between this modification and another modification 1 of the embodiment.

[0108] As shown in Figure 16, in this modified example, the FP insulating film 40F (e.g., FP insulating film 41F) is circular in the UV plane. The FP insulating film 40F is provided with a circular FP electrode 30F (e.g., FP electrode 31F) inside.

[0109] In this modified example, the first portion 40Fa and the second portion 40Fb of the FP insulating film 40F (for example, the first portion 41Fa and the second portion 41Fb of the FP insulating film 41F) are alternately arranged along the circumferential direction of the FP insulating film 40F in the UV plane. However, for example, the first portion 41Fa is located on the line connecting the FP electrode 31F and the FP electrode 32F, and the second portion 41Fb is located on the line connecting the FP electrode 31F and the FP electrode 33F.

[0110] According to this modified example, the configuration of the first embodiment can also be applied to a circular FP insulating film 40F. Note that the portion of the first portion 40Fa that sandwiches the FP electrode 30F along the extending direction of the gate electrode 13F (for example, the first portion 41Fa located to the left and right of the FP electrode 31F in Figure 17) may be replaced with a second portion 40Fb. Alternatively, this modified example may be applied to the configuration of the second embodiment.

[0111] (Another variation of the embodiment 4) Figure 18 is a plan view of a semiconductor device 1G according to another modification 4 of the embodiment. This modification corresponds to the case in another modification 1 of the embodiment in which a rectangular FP insulating film 40D is offset along the extending direction of the gate electrode 13D. In this modification as well as in other modification 1 of the embodiment, the FP insulating film 40G (for example, FP insulating film 41G) comprises a first portion 40Ga and a second portion 40Gb (for example, a first portion 41Ga and a second portion 41Gb).

[0112] According to this modified example, the configuration of the first embodiment can also be applied to FP insulating films 40G that are positioned at an offset. This modified example may also be applied to the configuration of the second embodiment, or to a circular FP insulating film.

[0113] (Another variation of the embodiment 5) Figure 19 is a plan view of the semiconductor device 1H according to another modification 5 of the embodiment. This modification corresponds to the case in another modification 4 of the embodiment in which a mesh-like gate electrode is provided. The following description will focus on the differences between this modification and another modification 4 of the embodiment.

[0114] In this modified example, the gate insulating film 50H is arranged to surround the FP insulating film 40H (for example, the FP insulating film 41H). Furthermore, a mesh-like gate electrode 13H, which is coupled to itself, is provided around the gate insulating film 50H.

[0115] According to this modified example, the configuration of the first embodiment can also be applied to a semiconductor device 1H having a gate electrode 13H arranged in a square mesh pattern. This modified example may also be applied to the configuration of the second embodiment. Alternatively, a circular FP insulating film may be provided inside the gate electrode 13H arranged in a square mesh pattern.

[0116] (Other variations) In the embodiments and modifications described above, the FP trench FTs all had the same configuration. However, at least one FP trench FT may have a different configuration from the other FP trench FTs. For example, the FP insulating films 41 and 42 in FP trenches FT1 and FT2 may have the same configuration as in the first embodiment, while the FP insulating film 43 in FP trench FT3 may have a first portion 43a and a second portion 43b made of the same material.

[0117] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0118] 1 Semiconductor device 11 Drain electrode 12 Source electrodes 13 gates 2 Semiconductor layers 21 Drift Region 22 Drain region 23 Base area 24 Source Area 30,31,32,33 FP electrode 40, 41, 42, 43 FP insulating film 50 Gate Insulator 60 Interlayer insulating film 40a,41a,42a,43a 1st part 40b,41b,42b,43b 2nd part d1,d2 distance P1,P2 position

Claims

1. A semiconductor layer comprising a first main surface and a second main surface, The first electrode provided on the first main surface, The second electrode provided on the second main surface, A first semiconductor region of a first conductivity type is provided within the semiconductor layer and electrically connected to the first electrode, A second semiconductor region of a second conductivity type is provided within the semiconductor layer and located above the first semiconductor region, A third semiconductor region of a first conductivity type is provided within the semiconductor layer and located above the second semiconductor region, A gate electrode provided within the second semiconductor region via a gate insulating film, A first field plate insulating film is provided in a columnar shape within the first semiconductor region, and a first field plate electrode is disposed inside it, A columnar structure is provided within the first semiconductor region, a second field plate electrode is positioned inside it, and a second field plate insulating film is aligned with the first field plate insulating film along a second direction perpendicular to the first direction from the first main surface toward the second main surface, A columnar structure is provided within the first semiconductor region, a third field plate electrode is positioned inside it, and a third field plate insulating film is aligned with the first field plate insulating film along a third direction that is perpendicular to the first direction and different from the second direction, Equipped with, The first distance between the first field plate electrode and the second field plate electrode is smaller than the second distance between the first field plate electrode and the third field plate electrode. The first field plate insulating film comprises a first portion located on the line connecting the first field plate electrode and the second field plate electrode, and a second portion located on the line connecting the first field plate electrode and the third field plate electrode. The dielectric constant of the second portion of the first field plate insulating film is higher than the dielectric constant of the first portion of the first field plate insulating film. Semiconductor equipment.

2. The first portion of the first field plate insulating film is a silicon oxide film, The semiconductor device according to claim 1, wherein the second portion of the first field plate insulating film is made of a material with a dielectric constant higher than that of a silicon oxide film.

3. The semiconductor device according to claim 2, wherein the second portion of the first field plate insulating film includes a silicon nitride film.

4. The semiconductor device according to claim 2, wherein the first field plate insulating film further comprises a third portion which is a silicon oxide film, located below the second portion of the first field plate insulating film and positioned above the first semiconductor region.

5. The semiconductor device according to claim 2, wherein the first field plate insulating film further comprises a fourth portion located on the first portion and including a silicon nitride film.

6. The second portion of the first field plate insulating film is a silicon oxide film, The semiconductor device according to claim 1, wherein the first portion of the first field plate insulating film is made of a material with a dielectric constant lower than that of a silicon oxide film.

7. The semiconductor device according to claim 6, wherein the first portion of the first field plate insulating film includes a spin-on-glass film.

8. The semiconductor device according to claim 6, wherein the first field plate insulating film further comprises a fifth portion which is a silicon oxide film, located below the first portion of the first field plate insulating film and positioned on the first semiconductor region.

9. The second portion of the first field plate insulating film is a silicon oxide film, The semiconductor device according to claim 1, wherein the first portion of the first field plate insulating film is a void.

10. The first field plate insulating film is hexagonal in a plane perpendicular to the first direction, The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane, The second portion of the first field plate insulating film is located at the corner of the first field plate insulating film in the plane. A semiconductor device according to any one of claims 1 to 9.

11. The first field plate insulating film is rectangular in a plane perpendicular to the first direction, The first portion of the first field plate insulating film is located at the edge of the first field plate insulating film in the plane, The second portion of the first field plate insulating film is located at the corner of the first field plate insulating film in the plane. A semiconductor device according to any one of claims 1 to 9.

12. The first field plate insulating film is circular in a plane perpendicular to the first direction, The semiconductor device according to any one of claims 1 to 9, wherein the first portion and the second portion of the first field plate insulating film are alternately arranged in the plane along the circumferential direction of the first field plate insulating film.

13. A semiconductor layer comprising a first main surface and a second main surface, The first electrode provided on the first main surface, The second electrode provided on the second main surface, A first semiconductor region of a first conductivity type is provided within the semiconductor layer and electrically connected to the first electrode, A second semiconductor region of a second conductivity type is provided within the semiconductor layer and located above the first semiconductor region, A third semiconductor region of a first conductivity type is provided within the semiconductor layer and located above the second semiconductor region, A gate electrode is provided within the second semiconductor region via a gate insulating film and extends along a direction perpendicular to the first direction from the first main surface toward the second main surface, A first field plate insulating film is provided in a columnar shape within the first semiconductor region, and a first field plate electrode is disposed inside it, Equipped with, The distance between the first field plate electrode and the first position of the gate electrode is smaller than the distance between the first field plate electrode and the second position of the gate electrode. The first field plate insulating film comprises a first portion located on a line connecting the first field plate electrode and the first position, and a second portion located on a line connecting the first field plate electrode and the second position. The dielectric constant of the second portion of the first field plate insulating film is higher than the dielectric constant of the first portion of the first field plate insulating film. Semiconductor equipment.

14. A semiconductor layer comprising a first main surface and a second main surface, comprising: a first semiconductor region having a first conductivity type; a first field plate insulating film provided columnar within the first semiconductor region with a first field plate electrode disposed inside; a second field plate insulating film provided columnar within the first semiconductor region with a second field plate electrode disposed inside, and aligned with the first field plate insulating film along a second direction perpendicular to a first direction toward the second main surface; and a third field plate insulating film provided columnar within the first semiconductor region with a third field plate electrode disposed inside, and aligned with the first field plate insulating film along a third direction perpendicular to the first direction and different from the second direction, wherein the first distance between the first field plate electrode and the second field plate electrode is smaller than the second distance between the first field plate electrode and the third field plate electrode. In the portion of the first field plate insulating film located on the line connecting the first field plate electrode and the third field plate electrode, a trench is formed by removing at least part of the first field plate insulating film from the second main surface. The trench is filled with a material that has a higher dielectric constant than the silicon oxide film. A method for manufacturing a semiconductor device.

15. A semiconductor layer comprising a first main surface and a second main surface, comprising: a first semiconductor region having a first conductivity type; a first field plate insulating film provided columnar within the first semiconductor region with a first field plate electrode disposed inside; a second field plate insulating film provided columnar within the first semiconductor region with a second field plate electrode disposed inside, and aligned with the first field plate insulating film along a second direction perpendicular to a first direction toward the second main surface; and a third field plate insulating film provided columnar within the first semiconductor region with a third field plate electrode disposed inside, and aligned with the first field plate insulating film along a third direction perpendicular to the first direction and different from the second direction, wherein the first distance between the first field plate electrode and the second field plate electrode is smaller than the second distance between the first field plate electrode and the third field plate electrode. In the portion of the first field plate insulating film located on the line connecting the first field plate electrode and the second field plate electrode, a trench is formed by removing at least part of the first field plate insulating film from the second main surface. The trench is filled with a material that has a lower dielectric constant than the silicon oxide film, or Insulating material is deposited in the trench so that a void is formed. A method for manufacturing a semiconductor device.

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