Semiconductor photodetector and method for manufacturing a semiconductor photodetector

Abstract

The present invention provides a semiconductor photodetector with an optical filter that exhibits low dark current, and a method for manufacturing the semiconductor photodetector. [Solution] The semiconductor photodetector according to this disclosure comprises a substrate, a semiconductor laminate having a light-receiving portion, and an upper electrode, wherein the upper electrode has a frame-shaped electrode and a pad electrode connected to a part of the frame-shaped electrode, and in a top view, the frame-shaped electrode is arranged to surround the light-receiving portion of the semiconductor laminate, and the photodetector has an optical filter that covers the entire surface of the semiconductor laminate and the frame-shaped electrode, excluding the external connection surface of the pad electrode, and the resistivity of the optical filter is 3.0 × 10 12 It is greater than Ωμm.

Description

[Technical Field]

[0001] This invention relates to a semiconductor photodetector and a method for manufacturing a semiconductor photodetector. [Background technology]

[0002] Conventionally, semiconductor photodetectors have been used in various applications such as communications and sensing. Multilayer film technology has been developed to allow for the selection of the light-receiving wavelength.

[0003] For example, Patent Document 1 discloses a photodetector for optical communication, and Patent Document 1 discloses a technique for forming a filter (a multilayer film such as SiO2 / SiN / Al2O3) on the upper surface of a chip in order to selectively receive light in the 1,300 nm band and the 1,550 nm band, respectively. The same document also proposes electrically isolating the semiconductor stacked portion at the boundary of adjacent filters by etching.

[0004] Furthermore, Patent Document 2 describes a technology for a photodetector in which the ultraviolet region is cut off by a multilayer film filter. In this document, on the incident surface of the semiconductor chip, an optical filter of dielectric multilayer film is formed across the entire upper surface, spanning the pn junction. Furthermore, Patent Document 3 proposes a photodetector in which wavelengths other than a specific range are reflected by a multilayer film of Si and SiO2. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 11-54785 [Patent Document 2] Japanese Patent Publication No. 2004-119678 [Patent Document 3] Japanese Patent Publication No. 2002-33503 [Overview of the project] [Problems that the invention aims to solve]

[0006] In recent years, as a sensing technology for acquiring information on objects such as people, sensors using an infrared light-emitting element with a specific wavelength and a light-receiving element have been widely developed. In such sensor applications, a light-receiving element with an optical filter for blocking information other than the specific wavelength has been demanded.

[0007] In order to increase the blocking effect of wavelengths other than the specific wavelength, it is necessary to provide an optical filter without a gap on the main surface side where light is received. Therefore, when the inventors of the present invention form an optical filter that blocks wavelengths other than the specific wavelength on the entire surface of the main surface side of the light-receiving element except on the electrode pad, it has been found that the leakage current (i.e., dark current) tends to increase significantly. Therefore, an object of the present invention is to provide a semiconductor light-receiving element having an optical filter and having a small dark current, and a method for manufacturing the semiconductor light-receiving element.

Means for Solving the Problems

[0008] The inventors of the present invention have intensively studied ways to solve the above problems. As described above, when an optical filter that blocks wavelengths outside the specific wavelength range is formed on the entire upper surface except for the pad electrode, the leakage current tends to increase significantly. The inventors of the present invention consider that the cause is that the leakage current occurs from the upper surface electrode through the optical filter and along the end face of the element, and as a result of further intensive study of the optical filter and its manufacturing method, it has been found that the problem can be solved by adjusting the resistivity of the optical filter. That is, the gist configuration of the present invention is as follows.

[0009] (1) A substrate, A semiconductor laminate having a light-receiving portion on the substrate, An upper surface electrode on the semiconductor laminate, A light-receiving element comprising: The upper surface electrode has a frame-shaped electrode and a pad electrode connected to a part of the frame-shaped electrode, In a top view, the frame-shaped electrode is arranged so as to be separated from the outer periphery of the semiconductor laminate, The light-receiving element has an optical filter that covers the entire surface of the semiconductor laminate and the frame-shaped electrode, excluding the external connection surface of the pad electrode. The resistivity of the optical filter is 3.0 × 10⁻⁶. 12 It is greater than or equal to Ωμm. Semiconductor photodetector.

[0010] (2) The optical filter includes a laminate of a Si layer and an SiO2 layer. The semiconductor photodetector described in (1) above.

[0011] (3) The resistivity of the SiO2 layer is 3.0 × 10 12 It is greater than Ωμm The semiconductor photodetector described in (2) above.

[0012] (4) The resistivity of the optical filter is 7.0 × 10 12 It is greater than or equal to Ωμm. The semiconductor photodetector described in (1) or (2) above.

[0013] (5) The light-receiving peak wavelength of the light-receiving unit is 800 nm or more and 2500 nm or less. A semiconductor photodetector as described in any one of the above items (1) to (3).

[0014] (6) The substrate includes an InP growth substrate or a support substrate via a reflective metal layer. A semiconductor photodetector as described in any one of the above items (1) to (3).

[0015] (7) A step of forming a semiconductor laminate having a light-receiving portion on a substrate, An electrode formation step in which, in a top view, a frame-shaped electrode is formed so as to be spaced apart from the outer periphery of the semiconductor laminate, A step of forming a pad electrode that connects to a part of the frame-shaped electrode, A step of forming an optical filter that covers the entire surface of the semiconductor laminate and the frame-shaped electrode, excluding the external connection surface of the pad electrode, A method for manufacturing a light-receiving element having, In the process of forming the optical filter, the resistivity of the optical filter is 3.0 × 10 12 A method for manufacturing a semiconductor photodetector, which is formed to have a thickness of Ωμm or greater.

[0016] (8) The optical filter includes a laminate of a Si layer and an SiO2 layer, A semiconductor manufacturing method for the photodetector described in (7) above.

[0017] (9) The Si layer of the optical filter is formed by sputtering, and the SiO2 layer is formed by reactive sputtering, and the oxygen flow rate is 100 sccm or more and 300 sccm or less. A method for manufacturing a semiconductor photodetector as described in (8) above.

[0018] (10) A protective film is further formed on the optical filter by plasma CVD. The method for manufacturing a semiconductor photodetector as described in (7) above. [Effects of the Invention]

[0019] According to the present invention, it is possible to provide a semiconductor photodetector that has an optical filter while having a low dark current, and a method for manufacturing a semiconductor photodetector. [Brief explanation of the drawing]

[0020] [Figure 1] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. [Figure 2A] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 1. [Figure 2B] This is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 1. Here, the cross-sectional view in Figure 2A is a schematic cross-sectional view when the semiconductor photodetector Figure 2B is cut along the dotted line. [Figure 3A] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 2A. [Figure 3B] Figure 3A is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 2B. Here, the cross-sectional view in Figure 3A is a schematic cross-sectional view when the semiconductor photodetector Figure 3B is cut along the dotted line. [Figure 4A] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 3A. [Figure 4B] Figure 3B is a top view illustrating part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Here, the cross-sectional view in Figure 4A is a schematic cross-sectional view when the semiconductor photodetector in Figure 4B is cut along the dotted line. [Figure 5A] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 4A. [Figure 5B] Figure 4B is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Here, the cross-sectional view in Figure 5A is a schematic cross-sectional view when the semiconductor photodetector Figure 5B is cut along the dotted line. [Figure 6A] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 5A. [Figure 6B] Figure 5B is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Here, the cross-sectional view in Figure 5B is a schematic cross-sectional view obtained when the semiconductor photodetector Figure 5A is cut along the dotted line. [Figure 7A] This is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention, following Figure 6A. [Figure 7B] Figure 7B is a top view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. Here, the cross-sectional view in Figure 7B is a schematic cross-sectional view obtained when the semiconductor photodetector Figure 7A is cut along the dotted line. [Figure 8] Figure 7 is a schematic cross-sectional view illustrating a part of the manufacturing process of a semiconductor photodetector according to one embodiment of the present invention. [Figure 9A]It is a top view showing a method for measuring the resistivity of an optical filter of a fabricated semiconductor light-receiving element by the two-terminal method. [Figure 9B] It is a side view of the measurement method in FIG. 9A. [Figure 10] It is a schematic cross-sectional view for explaining a semiconductor light-receiving element according to another embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0021] Prior to the situation of the embodiments according to the present invention, the following points will be explained in advance.

[0022] In this specification, when simply denoted as "InGaAs" without specifying the elemental composition ratio, the composition ratio of the total of group III elements In (indium) and Ga (gallium) and group V element As (arsenic) is 1:1, and the ratio of In and Ga, which are group III elements, means an arbitrary compound, and when expressed as In x Ga (1-x) GaAs, it is preferably 0 < x < 1. "InGaAs" may contain Al of 5% or less (molar concentration, the same hereinafter) with respect to the total of In and Ga. It may contain P (phosphorus) and Sb (antimony) within 5% with respect to As. Also, in the case of simply denoted as "InP", the ratio of the composition ratio of group III elements and group V elements can be measured by photoluminescence measurement, X-ray diffraction measurement, etc.

[0023] Also, in this specification, a layer that functions as a p-type electrically is referred to as a p-type semiconductor layer (sometimes referred to as a "p-type layer"), and a layer that functions as an n-type electrically is referred to as an n-type semiconductor (referred to as an "n-type layer"). On the other hand, when specific impurities such as Si, Zn, and S are not intentionally added, it is treated as "i-type" or "undoped" in this specification.

[0024] In this specification, the resistivity of an optical filter is measured using a two-terminal method. The measurement method used in this specification is described in detail below. Figure 9A shows a top view of the measurement method using the two-terminal method, and Figure 9B shows a side view thereof. First, an optical filter 90 is formed on an insulating quartz glass substrate (made of synthetic quartz, 400 μm thick, not shown) in the same manner as the method of lamination on a semiconductor laminate described later. Then, the quartz glass substrate is scribed and cut into strips with a width L together with the optical filter 90. After that, an Au wire 5 (20 μm in diameter) is brought into contact with the sides of the quartz glass substrate at both ends of the width L, and Ag paste 6 is applied to the entire surface including the sides of the quartz glass substrate and the sides of the optical filter 90 so as to enclose the Au wire 5. The paste is then heat-treated at 70°C for 2 hours to cure, and a sample for resistivity measurement is obtained with two electrodes spaced L apart. Here, the cross-sectional area S of the optical filter 90 in contact with the electrode (Ag paste 6 in Figure 9) is calculated from the length of the strip of the optical filter 90 (e.g., 1000 μm) and the thickness of the optical filter 90. Then, as shown in Figure 9, an insulating glass plate 3 and an external connection terminal 7 are placed on the glass epoxy substrate 2, and the Au wire 5 is bonded to the glass plate 3 using an insulating adhesive 4, thereby suspending the strip-shaped resistivity measurement sample in mid-air using the Au wire 5. The Au wire 5 is connected to the external connection terminal 7, and a Source Measure Unit (SMU) is connected to the external connection terminal 7 to pass current and measure the VI curve. The resistance R of the optical filter 90 is calculated from its slope, and the resistance R (Ω), width L (μm), and cross-sectional area S (μm) are obtained. 2 The resistivity ρ = R × S / L (Ω·μm) is calculated from the value of ). The width L can be, for example, 200 μm. The method for measuring the resistivity of the optical filter 90 after protective film formation is the same.

[0025] In this specification, the light-receiving wavelength of a semiconductor photodetector is determined by spectral sensitivity spectroscopy. In the examples described later, a spectral sensitivity spectroscopy device (model CARY7000) manufactured by Agilent Technologies was used.

[0026] The embodiments of the present invention will be described below with reference to the drawings. In each drawing, for the sake of clarity, the aspect ratios of the substrate and each layer are exaggerated from the actual ratios. Also, the correspondence between each schematic cross-sectional view and the top view does not always coincide due to dimensional constraints, and the ratios are changed in cases where it becomes difficult to distinguish them.

[0027] (Manufacturing method for semiconductor photodetectors) The method for manufacturing a semiconductor photodetector according to the present invention includes at least the steps of forming a semiconductor laminate, forming an electrode frame-shaped electrode, forming a pad electrode, forming an optical filter, and individualizing the components. Referring to Figures 1 to 8, the method for manufacturing the semiconductor photodetector 1 according to an embodiment of the present invention, including optional steps, includes a first step (semiconductor laminate formation step), a second step (contact region formation step), a third step (diffusion prevention layer formation step), a fourth step (Zn diffusion step), a fifth step (dielectric layer formation step), a sixth step (frame-shaped electrode and pad electrode formation step), Figure 7 (optical filter formation step), Figure 8 (backside electrode formation step), and individualizing the components (not shown). Details of each step will be described later. In addition, in Figures 2 to 7, Figure 2A, Figure 2B, etc., are shown as follows: Figure 2B is a top view of the semiconductor photodetector under fabrication, and Figure 2A is a cross-sectional view taken at a cross section perpendicular to the dotted line in Figure 2B. Hereafter, when the figures 2 through 7 are referred to simply by their numbers, as in Figure 2, it will refer to both Figure 2A and Figure 2B.

[0028] In the first step (the step of forming a semiconductor laminate), multiple compound semiconductor layers, each containing at least a light-receiving layer 20, are stacked on the substrate 10 (Figure 1). In the second step, a predetermined pattern is formed on the contact layer 40, which will be described later (Figure 2). In the third step, a diffusion prevention layer 50 is formed to create an opening pattern for the Zn diffusion region, which will be described later (Figure 3). In the fourth step, the diffusion prevention layer 50 is used as a mask to diffuse p-type impurities from the surface side of the window layer 30 and the contact layer 40. The contact layer 40 becomes a p-type contact layer 61, and the interface between the region where p-type impurities have diffused in the semiconductor layer (p-type region 62) and the p-type impurity non-diffusing region in the light-receiving layer 20 becomes the light-receiving portion 63 (Figure 4). In the fifth step, a dielectric layer 70 is formed over the entire surface, and a pattern is formed to expose the p-type contact layer 61 (Figure 5). In the sixth step, a frame-shaped electrode 81 is formed on the p-type contact layer 61 so as to be spaced apart from the outer periphery of the semiconductor laminate 11, and a pad electrode 82 is formed to connect to a part of the frame-shaped electrode 81 (Figure 6). In the seventh step, an optical filter 90 is formed to cover the entire surface of the semiconductor laminate and the frame-shaped electrode 81, excluding the external connection surface of the pad electrode 82 (Figure 7). In the eighth step, a back electrode is formed on the back surface of the substrate 10 for current conduction (Figure 8). The ninth step, although not shown, is a fragmentation step. Steps 1 through 8 are performed on a substrate where numerous elements that have not been fragmented into individual elements are arranged, but Figures 1 to 8 show a representative area of ​​one element on the substrate.

[0029] <1st process> The first step, as described above, is the process of stacking multiple compound semiconductor layers, each containing a light-receiving layer 20, on a substrate 10 (Figure 1). The substrate 10 is preferably an InP growth substrate. For the sake of explanation, the following embodiment will use an n-type InP growth substrate 10. The n-type InP growth substrate 10 can be one that is generally available, and its thickness should be sufficient to physically support the semiconductor layers described later.

[0030] In the first step, a light-receiving layer 20, a window layer 30, and a contact layer 40 may be formed in this order on a substrate 10 for growing n-type InP. The light-receiving layer 20 is preferably an InGaAs layer. The light-receiving layer 20 may be undoped or n-type, but the average n-type impurity concentration determined by SIMS analysis is preferably 2.5×10 14 / cm 3 or more and 1.0×10 15 / cm 3 or less, and more preferably doped so as to be 3.0×10 14 / cm 3 or more and 9.5×10 14 / cm 3 or less. The n-type impurity is preferably at least one selected from Si, Ge, Sn, Pb, S, Se, and Te, and among them, Si or Ge is more preferable. The film thickness of the light-receiving layer 20 is preferably 1.0 μm or more and 5.0 μm or less, and more preferably 2.0 μm or more and 4.0 μm or less. The window layer 30 can be an n-type InP layer, and the contact layer 40 can be an undoped InGaAs layer. The film thickness of the window layer 30 is preferably 500 nm or more and 2.0 μm or less. The film thickness of the contact layer 40 is preferably 50 nm or more and 200 nm or less, and more preferably 70 nm or more and 150 nm or less. A buffer layer may be provided between the substrate 10 for growing n-type InP and the light-receiving layer 20 to eliminate lattice mismatch. The light-receiving layer 20, the window layer 30, the contact layer 40, and any other layers are collectively referred to as a semiconductor laminate 11, and the total film thickness of the substrate 10 and the semiconductor laminate 11 is preferably 500 μm or less, and more preferably 400 μm or less. In addition to the layers mentioned above, a first buffer layer, a second buffer layer, a first contact layer, etc. may be formed.

[0031] Here, each layer of the semiconductor described above can be formed by epitaxial growth, for example, by known thin-film growth methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering. For example, by using trimethylindium (TMIn) as the In source, trimethylgallium (TMGa) as the Ga source, and arsine (AsH3) as the As source in a predetermined mixing ratio, and growing these raw material gases in the vapor phase with a carrier gas, each layer can be formed to a desired thickness depending on the growth time. If each layer is to be dopanted into a p-type or n-type, a dopant source gas may be used as desired.

[0032] <Second process> The second step, as described above, is the step of forming a predetermined pattern on the contact layer 40 (Figure 2). By forming a resist pattern on the surface of the contact layer 40, etching the openings, and peeling off the resist, a predetermined pattern can be formed on the contact layer 40. When the contact layer 40 is an InGaAs layer, although not limited to this, for example, H2SO4:H2O2:H2O=1:1:7 can be used as the etching solution. Figure 2B is a top view of Figure 2, but the contact layer 40 does not necessarily have to be closed as a frame, and although it is rectangular except for the openings in Figure 2B, it may be circular or the like. The width of the contact layer 40 is preferably 5 nm to 20 nm, and more preferably 8 nm to 15 nm (see reference numeral 40 in Figure 2B). If it is narrower than this range, sufficient current will not flow to the light-receiving part described later, and if it is wider than this range, the amount of light reaching the light-receiving part will be small. In addition, the size of the inner circumference of the contact layer 40 can be adjusted as appropriate depending on the application. For each application, it is preferable to design it so that sufficient current flows to the light-receiving part described later.

[0033] <3rd process> The third step, as described above, is the step of forming the diffusion prevention layer 50. That is, the diffusion prevention layer 50 is deposited on the surface of the window layer 30, which includes the contact layer 40 on the upper surface of Figure 2. The diffusion prevention layer 50 may be SiO2, SiON, etc., but it is preferably Si3N4. The thickness of the diffusion prevention layer 50 is preferably the same as the thickness of the contact layer 40. The thickness of the diffusion prevention layer 50 is preferably 50 nm to 200 nm, and more preferably 70 nm to 150 nm. The diffusion prevention layer 50 can be deposited by, for example, plasma CVD (Chemical Vapor Deposition). After that, a resist pattern is formed on the diffusion prevention layer 50, the openings are etched, and the resist is peeled off to form a diffusion prevention layer 50 with a predetermined pattern. The etching solution for Si3N4 is BHF (ultra-high purity buffered hydrofluoric acid). It is preferable to form the diffusion prevention layer 50 on the outside of the contact layer 40. The formed diffusion-preventing layer 50 can be used as a mask during the diffusion of p-type impurities in the fourth step.

[0034] <4th process> The fourth step, as described above, is a step in which p-type impurities are diffused from the contact layer 40 and window layer 30 to the light-receiving layer 20, using the mask opening not covered by the diffusion-preventing layer 50 as the entry point for diffusion. For example, Zn can be used as the p-type impurity. Since Zn is not easily diffused into the diffusion-preventing layer 50 formed in the third step, it can be diffused using the MOCVD method from the mask opening not covered by the diffusion-preventing layer 50 (window layer 30 and contact layer 40 in Figure 3B). In terms of the diffusion distance in the depth direction, it is preferable to adjust the conditions so that Zn diffuses to a depth of 0.1 μm to 0.5 μm from the interface between the window layer 30 and the light-receiving layer 20 towards the light-receiving layer 20. By diffusing Zn, the contact layer 40 becomes a p-type contact layer 61, and a portion of the window layer 30 and the light-receiving layer 20 becomes p-type. The interface between the region where the p-type impurities have diffused in the semiconductor layer (p-type region 62) and the p-type impurity non-diffusing region in the light-receiving layer 20 is made into a light-receiving section 63 (Figure 4A). This allows for the formation of a semiconductor laminate 11 having a light-receiving portion 63 on an n-type InP growth substrate 10. The p-type contact layer 61, the p-type region 62, and the light-receiving portion 63 together form a Zn diffusion region 60. Here, the size of the inner circumference of the Zn diffusion region, excluding the pad electrode portion 82 described later, can be set appropriately according to the application. Lateral diffusion of Zn after entering through the opening is possible, but for the sake of explanation, when viewed from above (Figure 4B), the p-type region 62 (light-receiving portion 63) will be described as being approximately the same region as the mask opening of the diffusion prevention layer 50 used as a mask during p-type impurity diffusion.

[0035] <5th process> The fifth step, as described above, is the step of forming the dielectric layer 70. That is, the dielectric layer 70 is deposited on the surface including the diffusion prevention layer 50, the p-type region 62, and the p-type contact layer 61 on the upper surface of Figure 4. The dielectric layer 70 is preferably the same Si3N4 as the diffusion prevention layer 50, but it may also be SiO2 or SiON, etc. The thickness of the dielectric layer 70 may be the same as the thickness of the diffusion prevention layer 50, but it is preferable that it be thicker than the diffusion prevention layer 50. The dielectric layer 70 can be deposited, for example, by the plasma CVD (Chemical Vapor Deposition) method. After that, a resist pattern is formed on the dielectric layer 70, the openings are etched, and the resist is peeled off to form a dielectric layer 70 with a predetermined pattern. The etching solution for Si3N4 is BHF. When the dielectric layer 70 with a predetermined pattern is formed and the p-type contact layer 61 is exposed, the width of the opening of the p-type contact layer 61 is preferably 3 nm or more and 10 nm or less, and more preferably 5 nm or more and 8 nm or less (see reference numeral 61 in Figure 5). Furthermore, it is preferable that the p-type contact layer 61 is located in the center of the width of the contact layer 40 formed in the second step (Figures 5A and 5B). It is also preferable that the Si3N4 on the outer periphery extends to the edge of the semiconductor layer. In this embodiment, the dielectric layer 70 is formed while the diffusion prevention layer 50 remains, but the diffusion prevention layer 50 may be removed after the fourth step before forming the dielectric layer 70.

[0036] <6th process> The sixth step, as described above, is the step of forming the frame-shaped electrode 81 and the pad electrode 82. When there is a p-type region 63 on the main surface side that receives light as shown in Figure 6, the frame-shaped electrode 81 is formed on the p-type contact layer 61 and the pad electrode 82 is formed to connect to a part of the dielectric layer 70. Here, the frame-shaped electrode 81 is an electrode that is on the main surface side that receives light from the light-receiving part 63 and electrically connects the light-receiving part 63 and the pad electrode 82. When the light-receiving element 1 is viewed from above from the optical filter side, there may be a part that overlaps with the light-receiving part 63, or the light-receiving part 63 may be completely enclosed. Since the frame-shaped electrode 81 itself, which is on the main surface side that receives light from the light-receiving part 63, may cast a shadow and reduce the amount of light that reaches the light-receiving part 63, it is preferable to place it near the outer circumference of the light-receiving part 63. In addition, in order to prevent leakage current that travels along the end face of the element, the frame-shaped electrode 81 is formed so as to be spaced apart from the outer circumference of the semiconductor laminate 11. The shortest distance (referred to as the separation distance) between the outer circumference of the frame electrode 81 and the outer circumference of the semiconductor laminate 11 on the surface where the frame electrode 81 is formed is preferably 25 μm or more and 100 μm or less, and more preferably 30 μm or more and 70 μm or less. Similar to the frame electrode 81, it is preferable that the pad electrode 82 be formed to be spaced apart from the outer circumference of the semiconductor laminate 11. The shape of the frame electrode 81 depends on the shape of the contact layer 40 formed earlier, and the outer and inner shapes can be any shape, such as rectangular or circular. The pad electrode 82 is formed to connect to a part of the frame electrode 81 (Figure 6B). The frame electrode 81 and the pad electrode 82 may be formed by vapor deposition or sputtering, but it is preferable to form them using EB metal vapor deposition (Figure 6). A predetermined resist pattern (electrode pattern) is formed on the dielectric layer 70 and the p-type contact layer 61, and the dielectric layer 70 at the openings is etched. A metal layer for conductivity is formed by vapor deposition, and the resist is swollen to remove metal other than the electrode pattern, thereby forming a frame-shaped electrode 81 and a pad electrode 82. The frame-shaped electrode 81 and the pad electrode 82 can be formed from, for example, Ti, Pt, Au, etc. It is preferable that the frame-shaped electrode 81 and the pad electrode 82 are of the same height. The film thickness (or total film thickness) of the frame-shaped electrode 81 and the pad electrode 82 is not particularly limited. The formed frame-shaped electrode 81 and the pad electrode 82 may be subjected to alloy treatment.In the top view of Figure 6, the width of the frame electrode 81 and the diameter of the pad electrode 82 can be adjusted as appropriate depending on the application. The frame electrode 81 and the pad electrode 82 together are referred to as the top electrode 80.

[0037] <7th process> As described above, the seventh step is to form an optical filter 90 so as to cover the entire surface of the semiconductor laminate 11 and the frame-shaped electrode 81, excluding the external connection surface of the pad electrode 82 (Figure 7A). In the seventh step of forming the optical filter 90, the resistivity of the optical filter 90 is 3.0 × 10⁻⁶. 12 The pad electrode is formed to have a thickness of Ωμm or greater. A portion of the surface of the pad electrode 82 is not covered by the optical filter 90 and is required to be exposed to allow electrical wiring to the outside. Therefore, the surface of the pad electrode 82 exposed by the opening of the optical filter 90 is called the external connection surface of the pad electrode 82. It is preferable to form a dielectric multilayer film on the upper surface of the element fabricated up to Figure 6 by sputtering a Si layer and by reactive sputtering an SiO2 layer, with an oxygen flow rate of 100 sccm to 300 sccm. This makes it possible to increase the resistivity of the optical filter to the range of the present invention. It is more preferable to form it with an oxygen flow rate of 130 sccm to 300 sccm, and even more preferable to form it with an oxygen flow rate of 150 sccm to 300 sccm. The optical filter 90 preferably includes, for example, a laminate of a Si layer and an SiO2 layer as a high refractive index / low refractive index laminate of the dielectric multilayer film. A dielectric multilayer film may also be formed from a laminate of high refractive index, medium refractive index, and low refractive index using layers of different materials from the Si layer and SiO2 layer. The resistivity of the optical filter 90 mentioned above is 3.8 × 10⁻⁶. 12 It is more preferable that the size be Ωμm or larger, and 5.0 × 10 12 It is even more preferable that the size be Ωμm or larger, and 6.0 × 10 12 It is even more preferable that the size be Ωμm or larger, and 7.0 × 10 12 It is most preferable that the resistivity be Ωμm or greater. There is no upper limit to the resistivity of the optical filter 90, but for example, 9.3 × 10⁻⁶ 13The resistivity can be set to Ωμm or less. By changing the deposition rate, which depends on the power input to the sputtering target, and the gas flow rate (Ar, O2, H, etc.) used in the sputtering method, it is possible to adjust the resistivity range within a desired range. The Si layer or SiO2 layer may be formed by a deposition method such as ion beam-assisted deposition if it is possible to adjust it to obtain the high resistivity mentioned above. Subsequently, an optical filter 90 having a predetermined aperture can be formed by a lift-off method in which a resist pattern is placed in advance before deposition of the optical filter 90, and the resist is removed along with a part of the optical filter on the resist after deposition. Alternatively, an optical filter 90 having a predetermined aperture can be formed by forming a resist pattern on the optical filter 90 after deposition, etching the pad electrode 82 portion, and peeling off the resist. The aperture diameter of the optical filter 90 is arbitrary as it depends on the method of connection to the outside of the pad electrode 82, but it is preferably 120 μm or less (Figure 7B). It is preferable to further form a protective film made of SiO2 or Si3N4 on the optical filter 90 using plasma CVD. The thickness of the protective film is preferably 300 nm to 500 nm, and more preferably 350 nm to 450 nm.

[0038] <8th process> The eighth step, as described above, is the step of forming a back electrode 100 on the back surface of the substrate 10 for electrical conduction (Figure 8). The back surface of the substrate 10 may be ground before forming the back electrode 100, and the thickness of the substrate 10 after grinding is preferably 80 μm or more and 300 μm or less, and more preferably 200 μm or less. In addition, the overall thickness of the element including the substrate 10 and the semiconductor laminate 11 (thickness remaining after grinding) is preferably 100 μm or more and 350 μm or less, and more preferably 150 μm or more and 280 μm or less. After grinding the substrate 10, the back surface of the substrate 10 is cleaned, and the back electrode 100 can be formed by metal deposition or sputtering. For example, the back electrode 100 can be an alloy containing Au. The film thickness (total film thickness) of the back electrode 100 is not limited, but is preferably, for example, 500 nm or more and 1000 nm or less.

[0039] <9th process> The ninth step, as mentioned above, is the individualization step, although it is not shown in the diagram. The semiconductor photodetector 1 fabricated in Figure 8 is individualized into chips using a dicing device such as a laser dicer. Individualization may be performed by cutting from the optical filter to the substrate as shown in Figure 8, or by cutting partway and then using scribing or breaking in combination. Furthermore, if a mesa formation step is added between steps 5 and 8, and the semiconductor layer including the photodetector layer is partially removed along the planned cutting line in the individualization step by dry etching or the like, then in the individualization step, only the remaining part including the substrate needs to be cut.

[0040] According to the above embodiment, in the process of forming an optical filter, the resistivity of the optical filter is set to 3.0 × 10 12 Because the density is set to Ωμm or greater, it is possible to manufacture a photodetector with a low dark current while still having an optical filter. The embodiments of the manufacturing method according to the present invention are not limited to the above embodiments, and for example, the following modifications may be applied, or these may be combined.

[0041] (Variation 1) As a modification 1 of the first embodiment described above, a different type of light-receiving part is given. In the above embodiment, the light-receiving part 63 is a PIN junction or PN junction by Zn diffusion, but the light-receiving part 63 may be formed by doping during epitaxial growth instead of by the Zn diffusion method. Alternatively, the amount of doping may be adjusted to form an APD (avalanche photodiode) type. Furthermore, although the above embodiment describes an InGaAs-based light-receiving element using an n-type InP growth substrate 10 as an example, the dark current that can be suppressed in the present invention is considered to be the current in the path from the top electrode 80 through the optical filter 90 along the side of the element to the back electrode 100. In other words, since it is not due to the current flowing inside the element, the effects of the invention may be achieved regardless of the type of substrate 10 and semiconductor laminate 11. Depending on the type of substrate 10 and the light-receiving center wavelength, each layer constituting the semiconductor laminate 11 may be appropriately selected from a III-V semiconductor layer consisting of one or more elements selected from the group III elements Al, Ga, and In, and one or more elements selected from the group V elements N, As, P, and Sb.

[0042] (Modification 2) As a second modification of the above embodiment, a diffusion prevention layer 50 and dielectric layer 70 with different ranges are provided. In the above embodiment, the diffusion prevention layer 50 and dielectric layer 70 are formed up to the edge of the semiconductor photodetector 1, but these diffusion prevention layer 50 and dielectric layer 70 do not have to be formed up to the edge of the semiconductor photodetector 1. They may be formed as a mesa, and the diffusion prevention layer 50 and dielectric layer 70 may not be formed at the edge of the semiconductor photodetector 1, and instead an optical filter 90 may be formed.

[0043] (Variation 3) As described in our Japanese Patent Application No. 2024-073142, after forming the dielectric layer 70 in the fifth step described above, the process may also include a step of forming a bonding layer on the p-type electrode 16 and the dielectric layer 70, and bonding the support substrate via the bonding layer. Examples of the support substrate include a Si substrate, a Ge substrate, a compound semiconductor substrate, a metal substrate (Cu-Mo, Mo, etc.), or a ceramic substrate (AlN sintered body, etc.). In this case, since the InP growth substrate is etched off, the frame electrode, pad electrode, and optical filter are formed on the side from which the InP growth substrate was removed. Even in this case, in the semiconductor photodetector 1 shown in Figure 10, the resistivity of the optical filter 90 is 3.0 × 10⁻⁶. 12 Because the density is set to Ωμm or greater, it is possible to manufacture a photodetector with a small dark current while still having an optical filter 90. As shown in Figure 10, if there is an n-type window layer 13 instead of a p-type region 62 on the main surface side of the light-receiving part 63, a frame-shaped electrode 81 can be formed on the n-type contact layer 12.

[0044] (Semiconductor photodetector) Next, the semiconductor photodetector 1 obtained through the above-described steps of forming at least the semiconductor laminate 11, forming the frame-shaped electrode 81, forming the pad electrode 82, forming the optical filter 90, and individualizing the semiconductor photodetector 1 will be described. As shown in Figure 8, the semiconductor photodetector 1 comprises a substrate 10, a semiconductor laminate 11 having a light-receiving portion 63 of the substrate 10, and an upper electrode 80 on the semiconductor laminate 11. The upper electrode 80 has a pad electrode 82 that connects to a part of the frame-shaped electrode 81 and the frame-shaped electrode 82, and in a top view, the frame-shaped electrode 81 is arranged to be spaced apart from the outer circumference of the semiconductor laminate. The semiconductor photodetector 1 has an optical filter 90 that covers the entire surface of the semiconductor laminate 11 and the frame-shaped electrode 81, excluding the external connection surface of the pad electrode 82, and the resistivity of the optical filter 90 is 3.8 × 10⁻⁶. 12 It is greater than Ωμm.

[0045] The optical filter 90 of the semiconductor photodetector 1 is preferably a dielectric multilayer film, and more preferably a laminate of high refractive index / low refractive index layers. In this embodiment, it is preferable to include a laminate of a Si layer as the high refractive index layer and an SiO2 layer as the low refractive index layer. A laminate of high refractive index, medium refractive index, and low refractive index layers may also be included by using layers of materials other than the Si layer and SiO2 layer. Layers containing materials other than the Si layer and SiO2 layer may also be included. Here, the resistivity of the low refractive index layer used in the optical filter 90 is 3.0 × 10⁻⁶. 12 Preferably, the size is Ωμm or larger, and 3.8 × 10 12 It is more preferable that the size be Ωμm or larger, and 4.5 × 10 12 It is even more preferable that the resistivity is Ωμm or greater. Furthermore, the overall resistivity of the optical filter 90 is 3.0 × 10⁻⁶. 12 Formed to be Ωμm or larger, 3.8 × 10 12 It is more preferable that the size be Ωμm or larger, and 5.0 × 10 12 It is even more preferable that the size be Ωμm or larger, and 6.0 × 10 12 It is even more preferable that the size be Ωμm or larger, and 7.0 × 10 12 It is most preferable that the particle size be Ωμm or larger.

[0046] The semiconductor photodetector 1 preferably has a photodetector peak wavelength (the wavelength at which the intensity in the photosensitivity spectrum is maximum) of 800 nm to 2500 nm, more preferably 850 nm to 2000 nm, and even more preferably 900 nm to 1700 nm. The photodetector layer 20 is preferably an InGaAs layer. The full width at half maximum of the peak in the photosensitivity spectrum is preferably, for example, 50 nm to 200 nm.

[0047] The semiconductor photodetector 1 described above can reduce dark current while still having an optical filter 90.

[0048] Furthermore, in addition to the embodiment in which the substrate 10 of the semiconductor photodetector 1 is an InP growth substrate, it is also preferable to use a support substrate with a reflective metal layer, as described in Japanese Patent Application No. 2024-073142. As shown in Figure 10, when using a support substrate with a reflective metal layer 45, it is not necessary to consider lattice bonding with the semiconductor laminate 11 as the support substrate, thus widening the range of usable support substrates. In particular, by using a Si substrate, the substrate thickness can be significantly reduced because it is less prone to cracking than an InP substrate, it has excellent heat dissipation properties and is also suitable for combination mounting with various semiconductor devices. [Examples]

[0049] The present invention will be described in more detail below using examples, but the present invention is not limited in any way to the following examples. Reference numerals are shown in Figures 1 to 8.

[0050] 3-inch n-type InP growth substrate 10 (thickness: 350 μm, S-doped, carrier density: 2 × 10) 8 / cm 3 ) Using the MOCVD method, an undoped InP buffer layer (film thickness 0.5 μm) and a tracely Si-doped InP layer were formed. 0.53 Ga 0.47 As photodetector layer 20 (film thickness: 3.0 μm, average Si concentration 9 × 10⁻¹⁶ by SIMS analysis) 14 / cm 3 (Carrier density too low to measure), n-type InP window layer 30 (film thickness: 1.0 μm, Si doped, carrier density: 8 × 10) 15 / cm 3 ), and undoped In 0.53 Ga 0.47 As contact layers 40 (film thickness: 0.1 μm) were sequentially deposited to form a semiconductor laminate 11. This process is shown in Figure 1.

[0051] A pattern as shown in Figure 2 was formed on the undoped InGaAs contact layer 40. For this pattern formation, a resist pattern was created, and the openings (etched areas) were etched. A solution of H2SO4:H2O2:H2O = 1:1:7 was used as the etching solution for the InGaAs. Next, it was allowed to stand for 30 seconds, washed with ultrapure water, and dried. Afterward, the resist was removed by washing. As shown in Figure 2b, the InGaAs contact layer 40 was not a complete frame shape when viewed from above, but rather an open frame shape for the pad electrode 82, which will be described later. The width of the InGaAs contact layer 40 was 11 μm. Furthermore, when the InGaAs contact 40 was considered a closed rectangle, the inner circumference size of the rectangle was 396 μm × 396 μm, and the outer circumference size was 418 μm × 418 μm.

[0052] Next, a diffusion-blocking layer 50 (thickness: 100 nm) made of Si3N4 was deposited on the n-type InP window layer 30, including the undoped InGaAs contact layer 40 on which the above pattern was formed, using plasma CVD. A resist pattern was formed on the deposited Si3N4 diffusion-blocking layer 50, and the openings were etched. BHF solution was used as the etching solution for the Si3N4 diffusion-blocking layer 50, and it was allowed to stand for 3 minutes and 30 seconds, washed with ultrapure water, and dried. After that, the resist was removed by washing. In this way, a diffusion-blocking layer 50 as shown in Figure 3 was formed.

[0053] By supplying a Zn source gas while heating using the MOCVD method, Zn was diffused in the depth direction of the n-type InP window layer 30 and the undoped InGaAs contact layer 40. Zn was diffused from the interface between the undoped InGaAs contact layer 40 and the n-type InP window layer 30 and the undoped InGaAs photodetector layer 20 to the undoped InGaAs photodetector layer 20, up to a region of 300 nm. DEZn (diethylzinc) was used as the Zn source. Since Zn diffusion can form a p-type region, the InGaAs contact layer 40 after Zn diffusion becomes a p-type InGaAs contact layer 61, the portion of the n-type InP window layer 30 and the undoped InGaAs photodetector layer 20 where Zn has diffused and become p-type is a p-type region 62, and the interface with the p-type region 62 within the undoped InGaAs photodetector layer 20 is the photodetector portion 63. The average Zn concentration in the thickness direction of the p-type region 62 in the n-type InP window layer 30 is 5.0 × 10⁻¹⁴. 18 / cm 3 Furthermore, the size of the Zn diffusion region 60, excluding the area near the pad electrode 82, was 422 μm × 422 μm.

[0054] A dielectric layer 70 (thickness: 177 nm) made of Si3N4 was deposited by plasma CVD. A resist pattern was formed on the deposited Si3N4 dielectric layer 70, and the openings were etched. BHF solution was used as the etching solution for the Si3N4 dielectric layer 70, and it was allowed to stand for 6 minutes, washed with ultrapure water, and dried. After that, the resist was removed by washing. In this way, a dielectric layer 70 as shown in Figure 5 was formed. The width of the p-type contact layer 61 was 7 nm. The p-type contact layer 61 was located in the center of the undoped contact layer 40 formed in Figure 2. In Figure 5, the Si3N4 dielectric layer 70 covers the area except for the p-type contact layer 61 portion exposed on the surface (Figure 5b).

[0055] A frame-shaped electrode 81 and a pad electrode 82, as shown in Figure 6, were formed on the surface of Figure 5. For electrode pattern formation, a resist pattern was first formed, followed by etching of the electrode formation area. Ti (film thickness: 30 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 1000 nm) were deposited by EB metal deposition. Next, excess metal and resist were removed by lift-off to form the electrode pattern shown in Figure 6. The width of the frame-shaped electrode 81 was 20 μm, and the distance from the outer periphery of the semiconductor laminate 11 was 40 μm. The diameter of the pad electrode 82 was 105 μm. The size of the area surrounded by the inner circumference of the frame-shaped electrode 81, excluding the area of ​​the pad electrode 82, was 390 μm × 390 μm. Similarly, the size of the outer periphery of the frame-shaped electrode 81, excluding the area of ​​the pad electrode 82, was 430 μm × 430 μm. The frame-shaped electrode 81 and the pad electrode 82 were combined to form the top electrode 80.

[0056] An optical filter 90 was formed to cover the entire surface of the Si3N4 dielectric layer 70 and the frame-shaped electrode 81, except for the opening for the pad electrode 82 to connect to the outside. For the optical filter 90, first a resist pattern was formed in the region that would become the external connection surface of the pad electrode 82, and then the dielectric multilayer film for forming the optical filter 90 was formed by sputtering. The specific structure and deposition conditions of the examples and comparative examples of the optical filter 90 will be described later. Next, the excess dielectric multilayer film and resist on the external connection surface of the pad electrode 82 were removed by lift-off, and an optical filter 90 having an opening as shown in Figure 7 was formed. The opening diameter was 85 μm.

[0057] The back surface of the growth substrate 10 was ground to achieve an overall thickness of 150 μm. Furthermore, as shown in Figure 8, a back surface electrode 100 containing Au was formed on the back surface of the growth substrate 10.

[0058] Finally, the fabricated semiconductor photodetector 1 was separated into individual chips using a laser dicer.

[0059] Table 1 shows the layer structure of the optical filter 90 for Examples 1-3 and Comparative Examples 1-2. Table 2 shows the layer structure of the optical filter 90 for Comparative Example 3. Table 3 shows the materials and total film thickness of the high refractive index layer and the materials and total film thickness of the low refractive index layer, respectively.

[0060] In Examples 1 and 2 and Comparative Examples 1 and 2, a Si layer (amorphous silicon layer) was used as the high refractive index layer, and an SiO2 layer was used as the low refractive index layer. In the sputtering apparatus, Si was used as the target, the TS distance was set to 110 mm, Ar gas was flowed at 300 sccm, the pressure was 0.6 Pa, and the discharge power was 9 W. As shown in Table 3, the oxygen flow rate conditions for forming the SiO2 layer differed in Examples 1 and 2 and Comparative Examples 1 and 2. The film formation conditions for the high refractive index layer were all the same. Comparative Example 3 used a Si layer as the high refractive index layer, and a TiO2 layer formed by replacing the target with Ti was used as the low refractive index layer. For comparison between low refractive index layers, the film thickness was the same in all examples and comparative examples. In Example 3, SiO2 was formed on the last SiO2 (23rd layer) of Example 1 by plasma CVD with a film thickness of 390 nm, and this was used as a protective film. In Example 4, silicon nitride (Si3N4) was formed on the last SiO2 (23rd layer) of Example 1 by plasma CVD with a film thickness of 390 nm, and this was used as a protective film.

[0061] [Table 1]

[0062] [Table 2]

[0063] [Table 3]

[0064] Table 4 shows the dark current, resistivity of the optical filter 90, resistivity of the high refractive index layer, and resistivity of the low refractive index layer when 5V was applied to Examples 1-4 and Comparative Examples 1-2. For reference, the results when no optical filter was formed are also shown. In the table, in Method 1, the quartz glass substrate (resistivity 1.4 × 10⁻¹⁰) 14 An optical filter 90 (including a protective film in Examples 3 and 4) was deposited on a Ωμm (400μm thickness) substrate, cut into small pieces measuring L200μm x 1000μm, and electrodes using Ag paste were formed as described above to create samples for resistivity measurement. Volume resistivity was measured using the two-terminal method by connecting Au wires as shown in Figures 9A and 9B. The measurement temperature was 25°C, and measurements were performed using a Keithley Source Measure Unit (SMU). In Method 2, volume resistivity was measured using the two-terminal method in the same manner as in Method 1, except that a single layer of a high refractive index layer or a single layer of a low refractive index layer with a thickness of 500 nm was deposited on a quartz glass substrate.

[0065] [Table 4]

[0066] From the above results, it was confirmed that a semiconductor photodetector having an optical filter fabricated to satisfy the resistivity conditions of the present invention can reduce the chip dark current compared to the comparative example. From these results, the resistivity was 3.0 × 10⁻⁶. 12 It is believed that the generation of dark current through the optical filter can be suppressed by forming an optical filter with a density of Ωμm or greater. [Explanation of symbols]

[0067] 1. Semiconductor photodetector 2. Glass epoxy substrate 3 glass plate 4. Adhesive 5 Au wires 6 Ag Paste 7 External connection terminals 10 circuit boards 11. Semiconductor Stack 12 n-type contact layer 13 n-type window layer 16 p-type electrode 20 Light-receiving layer 30 window layers 40 Contact Layers 45 Reflective metal layer 50 Diffusion prevention layer 60 Zn diffusion region 61 p-type contact layer 62 p-type region 63 Light receiving section 70 Dielectric layer 71 Second Dielectric Layer 80 Top electrode 81 Frame electrode 82 Pad electrodes 90 Optical Filters 100 Backside electrode

Claims

1. circuit board and A semiconductor laminate having a light-receiving portion on the substrate, The upper electrode on the semiconductor laminate, A light-receiving element equipped with, The upper electrode has a frame-shaped electrode and a pad electrode connected to a part of the frame-shaped electrode. In a top view, the frame-shaped electrode is positioned so as to be spaced apart from the outer periphery of the semiconductor laminate. The light-receiving element has an optical filter that covers the entire surface of the semiconductor laminate and the frame-shaped electrode, excluding the external connection surface of the pad electrode. The resistivity of the optical filter is 3.0 × 10⁻⁶. １２ It is greater than or equal to Ωμm. Semiconductor photodetector.

2. The light-receiving element according to claim 1, wherein the optical filter comprises a Si layer and SiO ２ A semiconductor photodetector including a stacked structure of layers.

3. The light-receiving element according to claim 2, wherein the SiO ２ The resistivity of the layer is 3.0 × 10⁻⁶ １２ A semiconductor photodetector with a thickness of Ωμm or greater.

4. A light-receiving element according to claim 1 or 2, wherein the resistivity of the optical filter is 7.0 × 10 １２ A semiconductor photodetector with a thickness of Ωμm or greater.

5. A semiconductor photodetector according to any one of claims 1 to 3, wherein the peak wavelength of the light-receiving portion is 800 nm or more and 2500 nm or less.

6. A semiconductor photodetector according to any one of claims 1 to 3, wherein the substrate includes an InP growth substrate or a support substrate via a reflective metal layer.

7. A process of forming a semiconductor laminate having a light-receiving portion on a substrate, An electrode formation step in which, in a top view, a frame-shaped electrode is formed so as to be spaced apart from the outer periphery of the semiconductor laminate, A step of forming a pad electrode that connects to a part of the frame-shaped electrode, A step of forming an optical filter that covers the entire surface of the semiconductor laminate and the frame-shaped electrode, excluding the external connection surface of the pad electrode, A method for manufacturing a light-receiving element having, In the process of forming the optical filter, the resistivity of the optical filter is 3.0 × 10 １２ A method for manufacturing a semiconductor photodetector, which is formed to have a thickness of Ωμm or greater.

8. A method for manufacturing a light-receiving element according to claim 7, wherein the optical filter comprises a Si layer and SiO ２ A method for manufacturing a semiconductor photodetector, including a laminated structure of layers.

9. A method for manufacturing a light-receiving element according to claim 8, wherein the Si layer of the optical filter is produced by sputtering, and the SiO ２ A method for manufacturing a semiconductor photodetector, wherein the layer is formed by reactive sputtering and the oxygen flow rate is 100 sccm or more and 300 sccm or less.

10. A method for manufacturing a photodetector according to claim 7 or 8, wherein a protective film is further formed on the optical filter by a p-CVD method, the method for manufacturing a semiconductor photodetector.

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