Superjunction type MOSFET
The superjunction MOSFET with a PIN diode structure addresses radiation resistance issues by capturing holes through quantum tunneling, improving device reliability and efficiency in high-radiation environments.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- POTENS SEMICON
- Filing Date
- 2025-05-01
- Publication Date
- 2026-06-30
Smart Images
Figure 2026108502000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a super junction type MOSFET that embeds a PIN diode by ion implantation to improve radiation resistance.
Background Art
[0002] With the rise of space technology and the progress of nuclear energy technology, preventing damage caused by radiation and charged particles to semiconductor devices has become an increasingly important research topic year by year (see Figure 1).
Summary of the Invention
Problems to be Solved by the Invention
[0003] However, in the conventional technology described above, when a MOSFET was exposed to a high-intensity radiation environment R, the semiconductor structure underwent ionization, generating electron / hole pairs (e-h). These electron / hole pairs were easily trapped in defect structures within the device. These defect structures include the interface between the semiconductor and the dielectric layer, the dielectric layer itself, or grain boundaries in polycrystalline structures. Referring to Figure 2, when an n-channel MOSFET is connected to a voltage and conducts, negatively charged electrons (e) drift towards the high potential external voltage at the drain located at the bottom (moving in the opposite direction to the electric field), while positively charged holes (h) drift towards the low voltage at the gate or source located at the top (moving along the direction of the electric field). In this case, since the drift rate of holes (h) is much slower than that of electrons (e), the gate could potentially generate a corresponding induced electric charge (IEC). As induced charge IECs accumulate continuously, the device can become permanently open (or closed), leading to equipment failure. This is called the cumulative dose or total dose effect (TID) due to prolonged exposure. The single event effect (SEE), resulting from short-term exposure, refers to the phenomenon where a single high-energy particle (usually a heavy ion or proton) hits the oxide layer or semiconductor of an electronic device, causing ionization of atoms in a certain region, generating a large amount of charge that is transmitted within the device and also trapped by defect structures.
[0004] In high-radiation environments, semiconductor devices can lose their effectiveness, leading to problems such as radioactive leaks and the failure of aerospace systems. Therefore, determining the degree of degradation of devices due to radiation energy damage and their radiation resistance has been particularly important. In response to this situation, in recent years, the effects of radiation damage have been reduced by strengthening the radiation hardening (Rad-Hard) of many semiconductor electronic devices that are susceptible to radiation damage. For example, cavities are created within semiconductor devices using special processes, or deep boron layers (DBLs) are embedded to capture holes created by radiation irradiation, preventing damage caused by the capture of defect structures. However, the former process (cavities) had the problem of low yield when mass-produced using wafer bonding. The radiation hardening effect of the latter (DBLs) was not as significant as that of the former. Furthermore, the conventional technologies presented above not only have a certain degree of difficulty in their processes, but also have the problem that there is room for improvement in the effectiveness of their radiation resistance. Therefore, when mass-producing semiconductor devices, the problem that needs to be solved is how to effectively enhance radiation resistance and improve TID and SEE.
[0005] Therefore, the inventors believed that the above-mentioned shortcomings could be improved, and after diligent research, arrived at the present invention, which effectively improves the above-mentioned problems through a rational design.
[0006] This invention has been made in view of the above circumstances, and one of its objectives is to solve the problems described above. Specifically, the main objective of this invention is to provide a superjunction type MOSFET that effectively enhances radiation resistance. [Means for solving the problem]
[0007] To achieve the above objective, the superjunction type MOSFET having a PIN (or NIP) structure according to the present invention employs the following means. The superjunction type MOSFET having a PIN (or NIP) structure according to the present invention comprises a substrate, an N-type drift layer, a plurality of P-type columnar regions, a plurality of gate regions, and a plurality of PIN diodes. The present invention mainly involves forming PIN diodes having N-type and P-type semiconductors highly doped by ion implantation within the N-type drift layer, thereby eliminating the low-yield wafer bonding process. Furthermore, by forming a thin I-type junction surface between the N-type and P-type semiconductors through high-concentration doping, it achieves a suitable quantum tunneling effect, more easily capturing holes generated by radiation irradiation, and improving the problem of enhanced radiation resistance. In addition, the PIN diodes have different radiation resistance enhancement effects and conductor resistance (RDS(on)) based on the position where the N-type drift layer is embedded, meeting various user needs.
[0008] The following information will become clear from the description in the specification and drawings described later. [Brief explanation of the drawing]
[0009] [Figure 1] This is a schematic diagram illustrating a conventional MOSFET and radiation. [Figure 2] This is a schematic diagram of a conventional MOSFET irradiated with radiation. [Figure 3] This is a schematic diagram showing a superjunction type MOSFET according to the present invention. [Figure 4] This is a schematic diagram (1) showing a superjunction type MOSFET according to one embodiment of the present invention. [Figure 5] This is a schematic diagram showing an embodiment of a superjunction type MOSFET according to the present invention. [Figure 6] This is experimental data figure (1) showing the superjunction type MOSFET according to the present invention. [Figure 7] This is experimental data diagram (2) showing the superjunction type MOSFET according to the present invention. [Figure 8]This is a schematic diagram (2) showing a superjunction type MOSFET according to one embodiment of the present invention. [Figure 9] This is a schematic diagram (3) showing a superjunction type MOSFET according to one embodiment of the present invention. [Figure 10] This is a schematic diagram (1) showing a SiC material according to one embodiment of the present invention. [Figure 11] This is a schematic diagram (2) showing a SiC material according to one embodiment of the present invention. [Figure 12] This is a schematic diagram (1) showing a P-channel type according to one embodiment of the present invention. [Figure 13] This is a schematic diagram (2) showing a P-channel type according to one embodiment of the present invention. [Modes for carrying out the invention]
[0010] Embodiments of the present invention will be described in detail below. However, the present invention is not limited thereto, and various modifications are possible within the scope described. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of the present invention.
[0011] First, embodiments of the present invention will be described in detail with reference to Figures 3 to 13.
[0012] In the example shown in Figure 3, the present invention uses a superjunction type MOSFET 1, and the structure in which multiple vertical PN junction surfaces are arranged maintains breakdown voltage while simultaneously reducing the conductor resistance RDS(on) and gate charge amount Qg, improving the problem that when the breakdown voltage of a planar MOSFET increases, the thickness of the drift layer increases, which increases the conductor resistance. The present invention comprises a substrate 101 that is highly doped with an N-type conductive medium and used to conduct as a drain, an N-type drift layer 102 implanted on the substrate 101 by ion implantation using a low-concentration doped N-type conductive medium, and a plurality of P-type columnar regions 103 that are implanted on the substrate 101 and within the N-type drift layer 102 by ion implantation using a low-concentration doped P-type conductive medium after a lithography process is performed on the N-type drift layer 102, wherein each P-type columnar region 103 is The present invention comprises a plurality of P-type columnar regions 103 that are parallel to each other with respect to an N-type drift layer 102 and have a plurality of PN junction surfaces formed thereon; a plurality of P-type well regions 104 implanted on each of the P-type columnar regions 103 so as to be formed by the P-type conductive medium; a plurality of N-type source regions 105 implanted on each of the P-type well regions 104 so as to be formed by the N-type conductive medium; a plurality of gate regions 106 implanted on the N-type drift layer 102 so as to be formed by the N-type conductive medium and located between the P-type well regions 104; a plurality of dielectric layers 107 formed on each of the gate regions 106 by techniques such as chemical vapor deposition (CVD); and a plurality of gate layers 108 formed on each of the dielectric layers 107, the material of which is, for example, polycrystalline silicon, but the present invention is not limited thereto. Furthermore, multiple type I regions 109 are embedded in the N-type drift layer 102, and at least one doping ion is implanted in each of the type I regions 109.The doping ion is, for example, an argon ion (Ar), and since it has many quantum states in the type I region 109, when the superjunction type MOSFET 1 is irradiated with radiation, the quantum states in the type I region 109 can absorb the holes h generated by the radiation. By using the type I region 109, it is possible to prevent holes h from being trapped at defective structural locations in the transistor, thereby reducing the problem of device damage due to the accumulation of gate-induced charge.
[0013] In the example shown in Figure 4, the I-type region 109 may be replaced with a PIN diode 110, which is embedded in the N-type drift layer 102 and comprises a P-type semiconductor 1101 and an N-type semiconductor 1102. The P-type semiconductor 1101 is embedded in the N-type drift layer 102 by an ion implantation method, and the N-type semiconductor 1102 is implanted on top of the P-type semiconductor 1101. The I-type junction surface 1103 is formed by the contact between each P-type semiconductor 1101 and each N-type semiconductor 1102. When a forward voltage is applied to the PIN diode 110, electrons pass from the N-type semiconductor 1102 through the I-type junction surface 1103 to the P-type semiconductor 1101 via the quantum tunneling effect and capture holes generated by radiation irradiation. When the doping concentrations of the P-type semiconductor 1101 and the N-type semiconductor 1102 are high, there are more quantum states between the I-type junction surface 1103 of the P-type semiconductor 1101 and the N-type semiconductor 1102, and consequently, the number of charge carriers (electrons or holes) entering the conduction band also increases, meaning that more electrons tunnel into the P-type semiconductor 1101. Furthermore, the I-type junction surface 1103 is formed using a doping material alone by an ion implantation method. The doping material may be, for example, at least one argon ion (Ar), and by implanting at least one argon ion between the P-type semiconductor 1101 and the N-type semiconductor 1102, the quantum states in the I-type junction surface 1103 are further increased.
[0014] Also, as the doping concentrations of the P-type semiconductor 1101 and the N-type semiconductor 1102 increase, the thickness of the I-type junction surface 1103 formed to contact them becomes thinner. The thicknesses of the N-type drift layer 102, the P-type columnar region 103, the P-type semiconductor 1101, and the N-type semiconductor 1102 are all adjusted based on the breakdown voltage required for the super junction type MOSFET 1. The P-type conductive medium is, for example, boron ions (Boron, B), indium ions (Indium, In), or gallium ions (Gallium, Ga), and the N-type conductive medium is, for example, phosphorus ions (Phosphorus, P), arsenic ions (Arsenic, As), or antimony ions (Antimony, Sb). However, the present invention is not limited to this. The N-type conductive medium (labeled "N" in the drawings) and the P-type conductive medium (labeled "P" in the drawings) have opposite electric properties to each other, and the concentration of the conductive medium is indicated by the symbol "+" (plus in mathematical symbols) or "-" (minus in mathematical symbols). "+" indicates a relatively high concentration, "-" indicates a relatively low concentration, and when there is no symbol such as "+" or "-", it indicates that the relative concentration is between the two.
[0015] Subsequently, in the example of FIG. 5, when the present invention is irradiated with radiation, the excited electrons e drift toward the substrate 101 to which the drain D is electrically connected along the direction opposite to the electric field direction, and the generated holes h drift toward the gate layer 108 to which the gate G is electrically connected along the forward direction of the electric field direction. The holes h are attracted by the electrons of the I-type junction surface 1103 by the PIN diode 110 and are captured to fill them. Therefore, the PIN diode 110 is used to absorb the holes h generated by receiving radiation, effectively preventing the situation where the holes h are captured at the defective structure parts of the transistor, and reducing the problem of element damage caused by the accumulation of gate-induced charges.
[0016] Referring to FIGS. 6 and 5 together, the present invention has doping concentrations (1E15 cm -3 , 1E16 cm -3 , 1E17 cm -3 , 1E18 cm-3 、 1E19 cm -3 ) Based on the difference, implant to form the PIN diode 110. When the doping concentrations of the P-type semiconductor 1101 and the N-type semiconductor 1102 are 1E19 cm -3 , the induced electric field generated when the gate G receives radiation is effectively reduced. When the doping concentration of the PIN diode 110 is 1E19 cm -3 , the in-position and out-of-position quantum state energy levels generated by the I-type junction surface 1103 can absorb electrons that tunnel between the P-type semiconductor 1101 and the N-type semiconductor 1102. Due to the effect of synchronizing the quantum states by overlapping, the hole h absorption effect is significantly increased, and the quantity of holes h absorbed is more than five times that in the case of the doping concentration 1E15 cm -3 . Also, in the example of FIG. 7, the conductor resistance (RDS(on)) of the present invention shows different performance results when the current is high or low compared to a transistor in which the PIN diode 110 is not embedded. In a general transistor without the embedded PIN diode 110, the conductor resistance is higher at high current (140 A) than at low current (22 A), and the power loss at high current increases. However, in the super junction type MOSFET1 of the present invention, the conductor resistance is lower at high current (140 A) than at low current (22 A), indicating that the power loss of the element at high current is small, and the energy conversion efficiency is increased.
[0017] Referring to Figures 8 and 4 together, the present invention shows that the radiation resistance enhancement effect differs depending on the height at which the PIN diode 110 is implanted. When the PIN diode 110 is implanted above the N-type drift layer 102 (Figure 4), and the gate region 106 is implanted on the N-type semiconductor 1102 of the PIN diode 110, the holes drift toward the gate layer 108 after the circuit becomes conductive. When the PIN diode 110 is located above the N-type drift layer 102, the hole trapping effect is best, and the conductor resistance becomes relatively high. When the PIN diode 110 is implanted in the middle of the N-type drift layer 102 (see Figure 8), the hole trapping effect of the PIN diode 110 is not as high as when it is implanted above the N-type drift layer 102, and its conductor resistance is also relatively low. In the example shown in Figure 9, when the PIN diode 110 is implanted at the bottom of the N-type drift layer 102 and the P-type semiconductor 1101 is implanted so as to be formed on the substrate 101, the hole capture effect of the PIN diode 110 is the lowest among the three, its conductor resistance is also the lowest, and power loss is minimized. Users can implant the PIN diode 110 in the appropriate location according to their needs, effectively capturing holes generated by radiation irradiation and simultaneously effectively suppressing power loss.
[0018] Next, in the example shown in Figure 10, according to the present invention, the SiC material may be present, and the present invention may form the SiC substrate 201 with the SiC material, and conduction is provided as a drain by a highly doped N-type conductive medium. The SiC-N-type drift layer 202 is implanted on the SiC substrate 201 by an ion implantation method using a low-concentration doped N-type conductive medium. Multiple P-type columnar regions 103 are implanted on the SiC substrate 201 and within the SiC-N-type drift layer 202 by an ion implantation method using a low-concentration doped P-type conductive medium after a lithography process has been performed on the SiC-N-type drift layer 202, so that each P-type columnar region 103 and the SiC-N-type drift layer 202 are parallel to each other, and multiple PN junction surfaces are formed. Multiple P-type well regions 104 are implanted on each of the P-type columnar regions 103 by the P-type conductive medium. Multiple N-type source regions 105 are implanted within each P-type well region 104 by a highly doped N-type conductive medium. Multiple SiC gate regions 203 are implanted on the SiC-N-type drift layer 202 by an N-type conductive medium and are located between each P-type well region 104. Multiple dielectric layers 107 are formed on each SiC gate region 203 by techniques such as chemical vapor deposition (CVD). Multiple gate layers 108 are formed on each dielectric layer 107, and their material may be, for example, polycrystalline silicon, but the present invention is not limited thereto.Multiple type I regions 109 are embedded in the SiC-N type drift layer 202, and at least one doping ion is implanted in each type I region 109. The doping ion is, for example, an argon (Ar) ion, and since the type I region 109 has many quantum states, when the superjunction type MOSFET 1 is irradiated with radiation, the quantum states in the type I region 109 can absorb the holes h generated by the radiation. By using the type I region 109, the situation in which holes h are trapped at defective structural locations in the transistor is effectively prevented, and the problem of device damage due to the accumulation of gate-induced charge is reduced.
[0019] Next, in the example of Figure 11, the aforementioned I-type region 109 may be replaced by a PIN diode 110, which is embedded in the SiC-N-type drift layer 202 and comprises a P-type semiconductor 1101 and an N-type semiconductor 1102. The P-type semiconductor 1101 is embedded so as to be formed in the SiC-N-type drift layer 202 by an ion implantation method, and the N-type semiconductor 1102 is implanted so as to be formed on top of the P-type semiconductor 1101, and an I-type junction surface 1103 is formed by the contact between each P-type semiconductor 1101 and each N-type semiconductor 1102. When a forward voltage is applied to the PIN diode 110, electrons pass from the N-type semiconductor 1102 through the I-type junction surface 1103 to the P-type semiconductor 1101 by the quantum tunneling effect, and capture holes generated by radiation irradiation. As the doping concentrations of the P-type semiconductor 1101 and the N-type semiconductor 1102 increase, more quantum states are present between the I-type junction surface 1103 of the P-type semiconductor 1101 and the N-type semiconductor 1102, and the number of charge carriers (electrons or holes) that subsequently enter the conduction band increases, meaning that more electrons tunnel into the P-type semiconductor 1101. Furthermore, the I-type junction surface 1103 is formed using an ion implantation method with the doping material used alone. The doping material may be, for example, at least one argon ion (Ar), and by implanting at least one argon ion between the P-type semiconductor 1101 and the N-type semiconductor 1102, the quantum states of the I-type junction surface 1103 are increased. In addition, as the doping concentrations of the P-type semiconductor 1101 and the N-type semiconductor 1102 increase, the thickness of the I-type junction surface 1103, which is formed to make contact, becomes thinner. The thicknesses of the SiC-N type drift layer 202, the P type columnar region 103, the P type semiconductor 1101, and the N type semiconductor 1102 are all adjusted based on the required withstand voltage for the superjunction type MOSFET 1.The P-type conductive medium may be, for example, boron ions (B), indium ions (In), or gallium ions (Ga), and the N-type conductive medium may be, for example, phosphate ions (P), arsenic ions (As), or antimony ions (Sb), and the present invention is not limited to these. The N-type conductive medium (indicated as "N" in the drawings) and the P-type conductive medium (indicated as "P" in the drawings) have opposite properties. The concentration of the conductive medium is indicated by a "+" (mathematical plus) or "-" (mathematical minus) symbol, where "+" indicates a high relative concentration, "-" indicates a low relative concentration, and the absence of a "+" or "-" symbol indicates a relative concentration between the two.
[0020] Next, the PIN diode 110 of the present invention produces differences in radiation resistance enhancement effects by being implanted at different height positions. When the PIN diode 110 is implanted above the SiC-N type drift layer 202, and the SiC gate region 203 is implanted on the N type semiconductor 1102 of the PIN diode 110, the hole capture effect is best when the PIN diode 110 is positioned above the SiC-N type drift layer 202, as the holes drift toward the gate layer 108 after the circuit becomes conductive, and its conductor resistance is also relatively high. When the PIN diode 110 is implanted in the middle of the SiC-N type drift layer 202, the hole capture effect of the PIN diode 110 is not as high as when it is implanted above the SiC-N type drift layer 202, and its conductor resistance is also relatively low. When the PIN diode 110 is implanted at the bottom of the SiC-N type drift layer 202, and the P type semiconductor 1101 is implanted so as to be formed on the SiC substrate 201, the hole capture effect of the PIN diode 110 is the lowest among the three, its conductor resistance is also the lowest, and power loss is minimized. Users can implant the PIN diode 110 in the appropriate location according to their needs, effectively capturing holes generated by radiation irradiation and simultaneously effectively suppressing power loss.
[0021] In the example shown in Figure 12, the aforementioned superjunction type MOSFETs are described as examples exhibiting the characteristics of N-Channel MOSFETs, but these can also be replaced with P-Channel MOSFETs. The present invention includes a substrate 301 that conducts as a drain by a highly doped P-type conductive medium. The material of the substrate 301 is, for example, Si, SiC, etc., but the present invention is not limited thereto. The material of the P-type drift layer 302 is, for example, Si, SiC, etc., but the present invention is not limited thereto, and is implanted on the substrate 101 by ion implantation using a low-concentration doped P-type conductive medium. Multiple N-type columnar regions 303 are implanted in the substrate 301 and the P-type drift layer 302 by ion implantation using a low-concentration doped N-type conductive medium after a lithography process has been performed on the P-type drift layer 302, so that each N-type columnar region 303 and the P-type drift layer 302 are parallel to each other, and multiple PN junction surfaces are formed. Multiple N-type well regions 304 are implanted in the N-type conductive medium so that they are formed on each of the N-type columnar regions 303. Multiple P-type source regions 305 are implanted in the N-type well region 304 so that they are formed on each of the N-type well regions 304 using a high-concentration doped P-type conductive medium. The material of the multiple gate regions 306 is, for example, Si, SiC, etc., but the present invention is not limited thereto, and they are implanted in the P-type drift layer 302 so that they are formed on each of the P-type drift layers 302 using a P-type conductive medium and are located between each of the N-type well regions 304. Multiple dielectric layers 307 are formed on each gate region 306 by techniques such as chemical vapor deposition (CVD). Multiple gate layers 308 are formed on each dielectric layer 307, and their material is, for example, polycrystalline silicon, but the present invention is not limited thereto. In addition, multiple type I regions 309 are embedded in the type P drift layer 302, and at least one doping ion is implanted in each type I region 309.The doping ion is, for example, an argon ion (Ar), and has many quantum states within the type I region 309. When the superjunction type MOSFET 1 is irradiated with radiation, the quantum states in the type I region 309 can absorb the holes h generated by the radiation. Therefore, by using the type I region 309, it is possible to effectively prevent holes h from being trapped at defective structural locations in the transistor, thereby reducing the problem of device damage due to the accumulation of gate-induced charge.
[0022] In the example shown in Figure 13, the I-type region 309 described above may be replaced with an NIP diode 310, which is embedded in the P-type drift layer 302 and comprises an N-type semiconductor 3101 and a P-type semiconductor 3102. The N-type semiconductor 3101 is embedded so as to be formed in the P-type drift layer 302 by an ion implantation method, and the P-type semiconductor 3102 is implanted so as to be formed on top of the N-type semiconductor 3101, and an I-type junction surface 3103 is formed by the contact between each N-type semiconductor 3101 and each P-type semiconductor 3102. When a forward voltage is applied to the NIP diode 310, electrons pass from the P-type semiconductor 3102 through the I-type junction surface 3103 to the N-type semiconductor 3101 by the quantum tunneling effect and capture holes h generated by radiation irradiation. As the doping concentrations of the N-type semiconductor 3101 and the P-type semiconductor 3102 increase, more quantum states are present between the I-type junction surface 3103 of the N-type semiconductor 3101 and the P-type semiconductor 3102, and the number of charge carriers (electrons or holes) that subsequently enter the conduction band increases, meaning that more electrons tunnel into the N-type semiconductor 3101. Furthermore, the I-type junction surface 3103 can be formed using an ion implantation method with the doping material alone. The doping material is, for example, at least one argon ion (Ar), and at least one argon ion is implanted between the N-type semiconductor 3101 and the P-type semiconductor 3102, increasing the quantum states of the I-type junction surface 3103. Note that as the doping concentrations of the N-type semiconductor 3101 and the P-type semiconductor 3102 increase, the thickness of the I-type junction surface 3103 formed to make contact becomes thinner. The thicknesses of the P-type drift layer 302, the N-type columnar region 303, the N-type semiconductor 3101, and the P-type semiconductor 3102 are all adjusted based on the required voltage withstand voltage for the superjunction type MOSFET 1.The P-type conductive medium is, for example, a boron ion (B), an indium ion (In), or a gallium ion (Ga), and the N-type conductive medium is, for example, a phosphorus ion (P), an arsenic ion (As), or an antimony ion (Sb), but the present invention is not limited to these. The N-type conductive medium (indicated as "N" in the drawings) and the P-type conductive medium (indicated as "P" in the drawings) have opposite electrical properties, and the concentration of the conductive medium is indicated by the "+" or "-" symbol. "+" indicates a relatively high concentration, "-" indicates a relatively low concentration, and the absence of a symbol such as "+" or "-" indicates that the relative concentration is between the two.
[0023] Furthermore, by implanting the NIP diode 310 of the present invention at different height positions, differences in the radiation resistance enhancement effect can be produced. When the NIP diode 310 is implanted above the P-type drift layer 302 and the gate region 303 is implanted on the P-type semiconductor 3102 of the NIP diode 310, the hole capture effect is best when the NIP diode 310 is located above the P-type drift layer 302, and its conductor resistance becomes relatively high. When the NIP diode 310 is implanted in the middle of the P-type drift layer 302, the hole capture effect of the NIP diode 310 is not as high as when it is implanted above the P-type drift layer 302, and its conductor resistance becomes relatively low. When the NIP diode 310 is implanted at the bottom of the P-type drift layer 302, and the N-type semiconductor 3101 is implanted so as to be formed on the substrate 301, the hole capture effect of the NIP diode 310 is the lowest among the three, its conductor resistance is also the lowest, and power loss is minimized. Users can implant the NIP diode 310 in the appropriate location according to their needs, effectively capturing holes generated by radiation while effectively reducing power loss.
[0024] As described above, the present invention mainly involves embedding a PIN diode in an N-type drift layer using an ion implantation method, increasing the doping concentrations of both the P-type and N-type semiconductors in the PIN diode, and forming an I-type junction surface by bringing them into contact. By effectively capturing holes generated by radiation irradiation through the quantum tunneling effect, not only can the device process be simplified, but radiation resistance can be further effectively enhanced while mass-producing semiconductor devices, improving the TID and SEE conditions. Therefore, the objective of providing a superjunction type MOSFET with effectively enhanced radiation resistance is reliably achieved by implementing the present invention.
[0025] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. [Explanation of Symbols]
[0026] 1. Superjunction type MOSFET 101 circuit board 301 circuit board 102 N-type drift layer 302 P-type drift layer 103 P-type columnar region 303 N-type columnar region 104 P-type well area 304 N-type well region 105 N-type source area 305 P-type source area 106 Gate Region 306 Gate Region 107 Dielectric layer 307 Dielectric layer 108 Gate Layer 308 Gate Layer 109 Type I region 309 Type I region 110 PIN diode 310 NIP diodes 1101 P-type semiconductor 3101 N-type semiconductor 1102 N-type semiconductor 3102 P-type semiconductor 1103 I type joint surface 3103 I type joint surface 201 SiC substrate R radiation 202 SiC-N type drift layer H Hall 203 SiC gate region e electronic G Gate IEC induced charge D Drain S Sauce
Claims
1. A substrate doped with a high concentration of N-type conductive medium, An N-type drift layer stretched to form on the substrate with the N-type conductive medium doped at a low concentration, Multiple P-type columnar regions are stretched to be formed within the N-type drift layer by a P-type conductive medium doped to a low concentration, A plurality of P-type well regions are implanted on each of the P-type columnar regions, respectively, using the P-type conductive medium, Multiple N-type source regions are implanted within each of the P-type well regions so as to be formed by the N-type conductive medium which is highly doped, Multiple gate regions are implanted on the N-type drift layer using the N-type conductive medium and are located between each of the P-type well regions, A plurality of dielectric layers are formed on each of the gate regions, A plurality of gate layers are formed on each of the dielectric layers, A superjunction type MOSFET characterized by comprising a plurality of I-type regions, each embedded in the N-type drift layer and having at least one doping ion implanted in each region.
2. The superjunction type MOSFET according to claim 1, characterized in that the doping ion in the type I region is an argon ion.
3. The superjunction type MOSFET according to claim 1, characterized in that the material of the substrate, the N-type drift layer, and the plurality of gate regions is Si or SiC.
4. A substrate doped with a high concentration of N-type conductive medium, An N-type drift layer stretched to form on the substrate with the N-type conductive medium doped at a low concentration, Multiple P-type columnar regions are stretched to be formed within the N-type drift layer by a P-type conductive medium doped to a low concentration, A plurality of P-type well regions are implanted on each of the P-type columnar regions, respectively, using the P-type conductive medium, Multiple N-type source regions are implanted within each of the P-type well regions so as to be formed by the N-type conductive medium which is highly doped, Multiple gate regions are implanted on the N-type drift layer using the N-type conductive medium and are located between each of the P-type well regions, A plurality of dielectric layers are formed on each of the gate regions, A plurality of gate layers are formed on each of the dielectric layers, A superjunction type MOSFET characterized by comprising a plurality of PIN diodes, each embedded in the N-type drift layer, wherein each PIN diode includes a P-type semiconductor and an N-type semiconductor, the N-type semiconductor being implanted so as to be formed on top of the P-type semiconductor, and an I-type junction surface being formed by the contact between the P-type semiconductor and the N-type semiconductor.
5. Each of the aforementioned P-type semiconductors is 1E19cm² -3 The P-type conductive medium doped to the above concentration is implanted and molded, and each of the N-type semiconductors is 1E19cm -3 The superjunction type MOSFET according to claim 4, characterized in that it is formed by implanting the N-type conductive medium doped to the above concentration.
6. The superjunction type MOSFET according to claim 4, characterized in that the material of the substrate, the N-type drift layer, and the plurality of gate regions is Si or SiC.
7. The superjunction type MOSFET according to claim 4, characterized in that the P-type conductive medium is boron ions, indium ions, or gallium ions, and the N-type conductive medium is one of phosphorus ions, arsenic ions, or antimony ions.
8. The superjunction type MOSFET according to claim 4, characterized in that at least one of the PIN diodes is embedded in the N-type drift layer, and the position in which the PIN diode is embedded is located in the middle of the N-type drift layer.
9. The superjunction type MOSFET according to claim 4, characterized in that at least one of the PIN diodes is embedded in the N-type drift layer, and the gate region is implanted on the N-type semiconductor of the PIN diode.
10. The superjunction type MOSFET according to claim 4, characterized in that at least one of the PIN diodes is embedded in the N-type drift layer and the P-type semiconductor is implanted so as to be formed on the substrate.
11. The superjunction type MOSFET according to claim 4, characterized in that the I-type junction surface is formed by an ion implantation method using a doping substance alone.
12. The superjunction type MOSFET according to claim 11, characterized in that the doping substance is at least one argon ion.
13. A substrate doped with a high concentration of P-type conductive medium, A P-type drift layer stretched to form on the substrate using the P-type conductive medium doped at a low concentration, Multiple N-type columnar regions are stretched to be formed within the P-type drift layer by an N-type conductive medium doped to a low concentration, Multiple N-type well regions are implanted on each of the N-type columnar regions so as to be formed by the N-type conductive medium, Multiple P-type source regions are implanted within each of the N-type well regions so as to be formed by the P-type conductive medium which is highly doped, Multiple gate regions are implanted on the P-type drift layer using the P-type conductive medium and are located between each of the N-type well regions, A plurality of dielectric layers are formed on each of the gate regions, A plurality of gate layers are formed on each of the dielectric layers, A superjunction type MOSFET characterized by comprising a plurality of I-type regions, each embedded in the P-type drift layer and having at least one doping ion implanted in each region.
14. The superjunction type MOSFET according to claim 13, characterized in that the doping ion in the type I region is an argon ion.
15. The superjunction type MOSFET according to claim 13, characterized in that the material of the substrate, the P-type drift layer, and the plurality of gate regions is Si or SiC.
16. A substrate doped with a high concentration of P-type conductive medium, A P-type drift layer stretched to form on the substrate using the P-type conductive medium doped at a low concentration, Multiple N-type columnar regions are stretched to be formed within the P-type drift layer by an N-type conductive medium doped to a low concentration, Multiple N-type well regions are implanted on each of the N-type columnar regions so as to be formed by the N-type conductive medium, Multiple P-type source regions are implanted within each of the N-type well regions so as to be formed by the P-type conductive medium which is highly doped, Multiple gate regions are implanted on the P-type drift layer using the P-type conductive medium and are located between each of the N-type well regions, A plurality of dielectric layers are formed on each of the gate regions, A plurality of gate layers are formed on each of the dielectric layers, A superjunction type MOSFET comprising a plurality of NIP diodes, each embedded in the P-type drift layer, wherein the NIP diodes include an N-type semiconductor and a P-type semiconductor, the P-type semiconductor being implanted so as to be formed on top of the N-type semiconductor, and an I-type junction surface being formed by the contact between the N-type semiconductor and the P-type semiconductor.
17. The superjunction type MOSFET according to claim 16, characterized in that the material of the substrate, the P-type drift layer, and the plurality of gate regions is Si or SiC.
18. The superjunction type MOSFET according to claim 16, characterized in that the P-type conductive medium is boron ions, indium ions, or gallium ions, and the N-type conductive medium is one of phosphorus ions, arsenic ions, or antimony ions.
19. The superjunction type MOSFET according to claim 16, characterized in that at least one NIP diode is embedded in the P-type drift layer, and the position in which the NIP diode is embedded is located in the middle of the P-type drift layer.
20. The superjunction type MOSFET according to claim 16, characterized in that at least one NIP diode is embedded in the P-type drift layer and the gate region is implanted on the P-type semiconductor of the NIP diode.
21. The superjunction type MOSFET according to claim 16, characterized in that at least one NIP diode is embedded in the P-type drift layer and the N-type semiconductor is implanted so as to be formed on the substrate.
22. The superjunction type MOSFET according to claim 16, characterized in that the I-type junction surface is formed by an ion implantation method using a doping substance alone.
23. The superjunction type MOSFET according to claim 22, characterized in that the doping substance is at least one argon ion.