Through-glass via structure including organic seed material layer for integrated circuit device package

Abstract

The present invention provides a glass substrate having through-glass vias (TGVs) that exhibit low warping and high manufacturing yield. [Solution] The package structure 1401 includes wiring structures 780A and 780B built up on top of surfaces 241 and 242, respectively. The wiring structure comprises one or more levels of redistribution layer (RDL) metallization features 782 embedded within one or more layers of dielectric material 781. The RDL metallization features contain one or more metals and preferably have the finest metallization line / space feature pitch (e.g., <3 μm lines and spaces) that can be directly patterned thanks to the flatness of the glass 210, electrically bridging two or more IC dies together. The wiring structure comprises metallization features that interconnect the multiple IC dies to a coaxial inductor structure or other TGV structure of the substrate core 601.

Description

[Background technology]

[0001] In electronics manufacturing, IC packaging is a stage in semiconductor device manufacturing, in which an IC, which is monolithically manufactured on a chip (or die), is assembled into a "package." This protects the IC chip from physical damage and allows it to communicate with other packaged IC chips and / or package substrates, i.e., enlarged host components such as printed circuit boards. Multiple chips can be assembled together, for example, in a multi-die package (MCP).

[0002] As an alternative to organic resin-based cores, more rigid package substrate cores, such as those made of bulk glass, have been considered as alternatives with lower warping and higher flatness. However, glass substrates have significantly lower CTEs compared to conventional organic copper-clad core or coreless substrates. When conductive features such as through-glass vias (TGVs) are formed within a glass substrate, the glass can be exposed to high stresses associated with the embedded conductive features. These high stresses can potentially lead to mechanical failure and reduce the yield of IC device packages. These problems are particularly pronounced, for example, when embedding coaxial inductor structures within TGVs, because it necessitates the additional need to form magnetic material within the TGVs. [Brief explanation of the drawing]

[0003] The subject matter described herein is presented as an example and is not intended to be an limitation in the accompanying drawings. For the sake of brevity and clarity of explanation, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where appropriate, reference numerals are repeated throughout the drawings to indicate corresponding or similar elements. The drawings are as follows:

[0004] [Figure 1] The flowchart shows a method for electroplating metal into through-glass vias (TGVs) by first lining the through-holes with an organic seed material layer, according to several embodiments.

[0005] [Figure 2] The diagram shows a cross-sectional view of an IC device package structure that, according to several embodiments, progresses to include a TGV opening and an inorganic seed material layer when one or more operations in the method shown in Figure 1 are performed. [Figure 3-1] Figure 3A shows a cross-sectional view of an IC device package structure that, according to several embodiments, progresses to include a TGV opening and an inorganic seed material layer when one or more operations in the method shown in Figure 1 are performed.

[0006] [Figure 3-2] Figure 3B shows a cross-sectional view of an IC device package, in which an inorganic seed material layer is complemented by an organic seed material layer within the TGV opening when one or more operations in the method shown in Figure 1 are performed, according to several embodiments.

[0007] [Figure 4] The images show cross-sectional views of IC device packages after electroplating one or more metals into TGV openings lined with organic seed material layers, according to several embodiments.

[0008] [Figure 5] This is a flowchart of a method for forming an IC device package structure including a coaxial inductor by depositing both inorganic and organic seed material layers on a glass substrate and electroplating magnetic and non-magnetic metals within through-glass vias (TGVs), according to several embodiments.

[0009] [Figure 6]A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments. [Figure 7] A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments. [Figure 8] A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments. [Figure 9] A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments. [Figure 10] A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments. [Figure 11] A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments. [Figure 12] A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments. [Figure 13] A cross-sectional view of an IC device package structure that evolves to include a coaxial inductor structure embedded within a glass substrate when one or more operations in the method shown in FIG. 5 are performed, according to some embodiments.

[0010] [Figure 14] The diagram shows a cross-sectional view of an IC device package structure that, in some embodiments, evolves to include multiple IC dies interconnected by an electrical wiring structure built up on the side of a glass core, including a through-glass coaxial inductor structure, when one or more operations in the method shown in Figure 5 are performed. [Figure 15] The diagram shows a cross-sectional view of an IC device package structure that, in some embodiments, evolves to include multiple IC dies interconnected by an electrical wiring structure built up on the side of a glass core, including a through-glass coaxial inductor structure, when one or more operations in the method shown in Figure 5 are performed.

[0011] [Figure 16] Figure 15 shows a system that includes an IC device package structure, which is attached to a host component with solder features, according to several embodiments.

[0012] [Figure 17] This document describes a mobile computing platform and a data server machine using a device package structure with a through-glass coaxial inductor structure, according to several embodiments.

[0013] [Figure 18] This is a functional block diagram of an electronic computing device according to several embodiments. [Modes for carrying out the invention]

[0014] Embodiments will be described with reference to the attached figures. Specific configurations and arrangements are illustrated and discussed in detail, but this is for illustrative purposes only. Those skilled in the art will understand that other configurations and arrangements are possible without departing from the spirit and scope of this specification. Those skilled in the art will also see that the techniques and / or arrangements described herein can be used in a variety of other systems and applications not described in detail herein.

[0015] In the following detailed description, reference will be made to the accompanying drawings, which form part of this specification and illustrate exemplary embodiments. Furthermore, it should be understood that even if other embodiments are utilized, or structural and / or logical modifications are made, this will not deviate from the scope of the claimed subject matter. It should also be noted that directions and criteria such as top, bottom, upper, and lower may be used simply to facilitate the description of features in the drawings. Therefore, the following detailed description should not be taken as restrictive, and the scope of the claimed subject matter is defined solely by the attached claims and their equivalents.

[0016] Numerous details are provided in the following description. However, it will be apparent to those skilled in the art that embodiments may be carried out without these specific details. In some cases, well-known methods and devices are shown in block diagram form rather than in detail, in order to avoid obscuring the embodiments. Throughout this specification, any reference to “embodiment,” “one embodiment,” or “several embodiments” means that a particular feature, structure, function, or characteristic described in relation to that embodiment is included in at least one embodiment. Thus, the phrases “in an embodiment,” “in one embodiment,” or “in several embodiments” appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, functions, or characteristics may be combined in any preferred manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment in any case, provided that the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0017] As used herein and in the appended claims, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context otherwise explicitly indicates. Where used herein, the term “and / or” should also be understood to refer to and encompass any and all possible combinations of one or more of the items listed relating to this specification.

[0018] The terms “joined” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between multiple components. These terms are not intended to be synonymous with each other. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with one another. “Joined” may be used to indicate that two or more elements are in direct or indirect (with other intervening elements between them) physical or electrical contact with one another, and / or that two or more elements cooperate or interact with one another (e.g., as causally related).

[0019] As used herein, the terms “over,” “under,” “between,” and “on” refer to the relative position of one component or material to another component or material where such a physical relationship is noteworthy. For example, in the context of materials, one material or layer that is above or below another may be in direct contact with it, or may have one or more intervening materials or layers. Furthermore, one material that is between two materials or layers may be in direct contact with both materials / layers, or may have one or more intervening materials / layers. In contrast, a first material or layer that is “on” a second material or layer is in direct contact with that second material / layer. Similar distinctions are made in the context of component assemblies.

[0020] Throughout this description, and where used in the claims, a list of items connected by the terms “at least one of” or “one or more of” may mean any combination of the listed words. For example, the phrase “at least one of A, B, or C” may mean A, B, C; A and B, A and C; B and C; or A, B and C.

[0021] Unless otherwise explicitly stated in the specific context of use, the term “primarily” means more than 50% or more than half. For example, a composition that is primarily the first component means that more than half of its composition is the first component (e.g., <50 atomic%). The term “primarily” means the most abundant or largest portion. For example, a composition that is primarily the first component means that its composition contains more of the first component than any other component. A composition that is primarily the first and second components means that its composition contains more of the first and second components than any other component. The term “substantially” means that only accidental variation exists. For example, a composition that is substantially the first component means that its composition may contain <1% of any other component. A composition that is substantially the first and second components means that its composition may contain <1% of any other component that replaces either the first or second component.

[0022] Integrated circuit (IC) device package structures comprising a glass matrix with embedded metallized portions such as through-glass vias (TGVs) are described herein. An electrical wiring structure comprising a redistribution layer (RDL) metallized portion may be built up on at least one side of the glass and electrically coupled to the metallized portion embedded in the glass. An IC die may be further assembled to the wiring structure. In exemplary embodiments, the metallized portion embedded in the glass is electroplated above an organic seed material layer, which may be absent from metallized portions extending above the front or back surface of the glass, which may be complemented by an inorganic seed material layer.

[0023] As further described below, the organic seed material has sufficient conductivity to support the electroplating of one or more metals on the sidewalls of the opening or recess in the glass. The organic seed material has a low modulus of elasticity (e.g., Young's modulus) and, advantageously, can deform to absorb (i.e., buffer) stress between the glass and the electroplated metal. The organic seed material may further have relatively low electrical conductivity, which may advantageously reduce electrical parasitic components during the operation of the inductor structure, including magnetic metals electroplated on the organic seed material within the opening or recess in the glass. Electrodeposition dependent on the organic seed material may be complemented and / or enhanced, for example, with inorganic seed material formed on the glass surface beyond the opening or recess. Inorganic seed material may improve the electroplating efficiency and enhance the plating rate on the back and / or front surfaces of the glass compared to within the opening in the glass.

[0024] Various manufacturing methods may be employed to form an IC device package structure having one or more of the features described herein. Figure 1 shows a flowchart of Method 101 for forming organic and inorganic seed material layers on a glass matrix and electroplating one or more metals on top of the seed material layers. Method 101 begins at Input 110, where a workpiece including the thickness of glass is received. The workpiece may be prepared upstream of Method 101 and may be in the form of a large panel, a wafer, or similar. In addition to glass, the workpiece received at Input 110 may have one or more surfaces covering a material on which an electrical wiring structure may be formed.

[0025] Figure 2 is a cross-sectional view of an exemplary substrate core 201 including glass 210. IC device package structures may be advantageously fabricated on glass 210 because the control of the flatness and / or thickness of the glass matrix may be superior to that of an initial substrate based on an organic material (e.g., epoxy), and the cost may be significantly lower than that of a single-crystal material (e.g., silicon). Glass 210 may also be more rigid than conventional core materials such as copper-clad laminate (CCL). Glass 210 is a solid bulk material layer that may be pre-formed into any shape in plan view (e.g., xy plane), e.g., a rectangle, suitable for a packaging workpiece. Glass 210 has a thickness T0 that may vary depending on the mounting configuration, for example, to remain thin enough to allow the formation of through-vias at the smallest possible pitch, while limiting warping, e.g., due to the surface flatness of glass 210. In exemplary embodiments, the thickness T0 is advantageously 50 μm to 2000 μm. Organic adhesives and / or other organic materials may be absent from the glass 210. The glass 210 is advantageously a bulk material of substantially homogeneous composition, in contrast to composite materials that may simply contain glass fillers (particles) and / or glass fibers within a binder (e.g., epoxy). While the glass 210 is substantially amorphous in some embodiments, it may also have other forms or microstructures, such as polycrystalline (e.g., nanocrystalline). Thus, the glass 210 may be a rectangular volume distinguished from, for example, a “prepreg,” which typically contains glass fibers with a diameter in the range of 5–20 μm embedded in a resin-based organic material, such as epoxy.

[0026] Glass 210 may contain materials including silicon and oxygen. The glass 210 preferably consists mainly of silicon and oxygen. In some embodiments, the glass 210 contains at least 23 percent silicon and at least 26 percent oxygen by weight (i.e., weight %). The glass 210 may further contain one or more additives, such as aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, or zinc. In the glass 210, the weight percentage of silicon is at least 0.5% (e.g., from about 0.5% to 50%) and may be from about 1% to 48%. For example, if the glass 210 is specifically fused silica, the weight percentage of silicon may be about 47%. In some embodiments where the glass 210 contains at least 23 wt% Si, the glass 210 contains at least 26 wt% O. The additives within the glass 210 may form suboxides (A2O), monoxide (AO), dioxide (AO2), trioxide (ABO3), and mixtures thereof. For example, the glass 210 is AlO x (e.g., Al2O3), BO x (e.g., B2O3), MgO x (e.g., MgO), CaO x (e.g., CaO), SrO x (e.g., SrO), BaO x (e.g., BaO), SnO x (e.g., SnO2), NaO x (e.g., Na2O), KO x (e.g., K2O), PO x (e.g., P2O3) ZrO x (e.g., ZrO2), LiO x (e.g., Li2O), TiO x [[ID=)26]](e.g., TiO2), or ZnO x (e.g., ZnO2). In some specific examples, the glass 210 further contains at least 5 wt% Al. Thus, depending on the chemical composition, the glass 210 may be referred to as, for example, silica, fused silica, aluminosilicate, soda lime glass, soda lime silica, borosilicate glass, lead borate glass, borosilicate, or aluminoborosilicate.

[0027] As further shown in Figure 2, one or more material layers 225 may cover either or both of the front glass surface 241 or the back glass surface 242, so that the glass 210 is a bulk or core layer of the multilayer substrate. In some embodiments, the material layer 225 is an inorganic material. In some examples, the inorganic material is a metal seed layer having sufficient conductivity at some predetermined material layer thickness to support the electroplating process. In some embodiments, the metal seed layer is mainly copper (Cu), and may be pure Cu with substantially only trace amounts (e.g., <1 wt%) of impurities. The metal seed layer may also be of varying composition and / or a laminate of two or more sublayers. For example, the metal seed layer may contain approximately 50 nm of mainly Ti in contact with the glass 210, and approximately 100 nm of mainly Cu above the Ti. In other embodiments, the material layer 225 is silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ) are alternative inorganic dielectric materials. In other embodiments, the material layer 225 may be a silicon layer (polycrystalline or monocrystalline). In yet another embodiment, the material layer 225 may instead be an organic material layer, such as a polymer dielectric material. Thus, the glass 210 is advantageously substantially free of organic materials (e.g., adhesives), while the IC die package workpiece may further contain organic materials within the substrate laminate containing the glass 210.

[0028] Returning to Figure 1, method 101 continues at block 120, where features (e.g., recesses and / or through-holes) are formed within the glass matrix. The features may be manufactured by any process known to be suitable for bulk glass. In some embodiments, block 120 includes laser ablation, a glass etching process (laser-assisted or otherwise), or any other technique known to be suitable for forming features (e.g., holes) with a desired diameter and feature pitch, penetrating the thickness of the glass received in input 110. In some embodiments, the features are defined in block 120 by photolithography in a mask material, and then the glass is etched according to the mask features. In embodiments where the workpiece includes one or more coating layers above the glass matrix, the features formed within the glass matrix may also be formed within the coating layers by either the same process used to pattern the glass, or a separate process.

[0029] Figure 3A shows an exemplary embodiment illustrating a substantially symmetrical double-sided opening formation process that results in an opening 320 having a tapered (e.g., x-dimensional) transverse width W that is maximized at each of the glass surfaces 241 and 242, while being substantially symmetrical with respect to the vertical z-axis (shown by a dashed line). The opening 320 has a minimum transverse width W that is half the thickness T0, i.e., near the centerline plane of the glass 210. The maximum width W may vary depending on the implementation. However, in some examples, the maximum width W is 100 μm or less, and favorably, 50 μm or less. Thus, the aspect ratio (T0: maximum width W) of the opening 320 may also vary, but the exemplary aspect ratio range is 10 to 20:1.

[0030] In some embodiments where the glass 210 has a thickness T0 of at least 500 μm, the opening 320 has a minimum lateral pitch P of 200 μm or less, and advantageously, 100 μm or less. The symmetrical taper shown in Figure 3A illustrates a double-sided through-hole forming process, but a single-sided asymmetric through-hole embodiment is also possible. Although Figure 3 shows a through-hole, blind holes or recesses that do not completely pass through the thickness T0 may also be manufactured within one or both of the glass surfaces 241 or 242. The opening 320 (or blind hole) may have any shape in the plan view (xy) plane, e.g., substantially circular, rectangular, or any other polygon. The plan view shape of the through-hole, i.e., the blind hole, may also vary over the thickness T0.

[0031] As further shown in Figure 3A, the opening 320 extends through the covering material layer 225 on the front and back surfaces. Therefore, after patterning the through-hole, the material layer 225 is present on the glass surface 241 or glass surface 242, but absent from the glass sidewall surface within the opening 320.

[0032] Returning to Figure 1, Method 101 continues in block 130, where one or more conductive material layers are formed above the glass matrix. These material layers are intended to facilitate the electroplating of one or more metals into the holes or recesses in block 150, and are therefore referred to as (plating) seed material layers. In block 130, an organic seed material layer is formed at least above the sidewall surface of the opening or recess in the glass matrix. In some embodiments, the organic seed material layer is formed or retained only above the sidewall surface. In other embodiments, the organic seed material layer is formed and retained above the sidewall surface of the opening in the glass, in addition to above the front and / or back surface of the glass matrix.

[0033] In embodiments where the front and back surfaces of the glass matrix are not already covered with an inorganic seed material layer, an inorganic seed material may be formed on the front and / or back surfaces of the glass in block 135. The inorganic seed material layer may complement the organic seed material layer formed on the sidewalls of the feature in block 130 to, for example, reduce the total electrical resistance of the composite seed layer or otherwise improve the electroplating performance in block 150. Block 135 is shown with a dashed line to emphasize that the addition of inorganic seed material on the front and / or back surfaces of the glass is optional. For example, if the glass matrix is ​​already covered with an inorganic seed material, block 135 does not need to be implemented. In another example where the organic seed material is deposited above the sidewalls and above the front and / or back surfaces of the glass matrix, block 135 does not need to be implemented if the electrical resistance of the organic seed material is low enough to allow the plating in block 150 to perform adequately.

[0034] The organic seed material layer may be formed in block 130 according to any technique suitable for forming the material on the sidewalls of the patterned features within the glass matrix. In some embodiments, the polymer precursor fluid is applied by processes such as slit coating, spin coating, spray coating, dip coating, or inkjet printing. In other embodiments, self-assembly techniques (e.g., those driven by surface charge) may be employed to form the organic material layer. The polymer precursor may be dried and / or cured to evaporate the solvent from the fluid and form an organic polymer seed material having desirable mechanical properties. In some examples, curing may include heating the workpiece at a temperature of 200C to 500C for 10 minutes or longer.

[0035] Figure 3B shows an exemplary embodiment in which an organic seed material layer 325 is formed above the substrate core 201. As shown, the organic material layer 325 is located above the front glass surface 241, the back glass surface 242, and the sidewall glass surface 321 within the opening 320. Because the organic seed material is located above the surface coating material layer 225, in embodiments where the coating material layer 225 is an inorganic seed layer (e.g., Cu), a multilayer inorganic / organic material laminate is present above the front and back glass surfaces 241, 242, while a single layer of organic material is present on the sidewall 321.

[0036] In exemplary embodiments, the organic seed material layer 325 is a conductive polymer. The conductivity of the organic seed material layer 325 may vary with implementation, but in some embodiments, the material conductivity is at least 100 S / cm and may be 1000 S / cm or higher. However, in some advantageous embodiments where the coating material layer 225 is a Cu seed layer, the organic seed material layer 325 has a conductivity lower than that of the coating material layer 225. Embodiments of the organic seed material layer 325 having lower conductivity may improve the performance of certain devices, such as coaxial inductor structures. Thus, the conductivity of the organic seed material layer 325 may be optimized between plating performance and the operating performance of the resulting device structure. In some cases, the conductivity of the organic seed material 325 may be measured directly, but references to conductivity herein are also applicable to bulk materials having substantially the same chemical composition and microstructure as the organic seed material 325. Therefore, even if the conductivity of the organic seed material layer 325 cannot be directly measured in situ, a material of substantially the same composition and microstructure may be formed to a somewhat larger thickness that is more suitable for electrical measurement. Unless otherwise proven, the conductivity of such a bulk thickness is presumed to be approximately the same as that of a thin film of substantially the same composition and microstructure.

[0037] In some further embodiments, the organic seed material layer 325 is made of a material having an elastic modulus lower than 110 GPa. The inventors have found that materials with an elastic modulus significantly above this threshold (e.g., 120 GPa) may not be able to absorb sufficient internal stress, and less flexible materials may delaminate when deposited in pores or depressions in glass. Therefore, some embodiments of the organic seed material layer 325 may have an elastic modulus of less than 100 GPa, and more preferably less than 90 GPa. The references to the elastic modulus herein are also applicable to bulk materials having substantially the same chemical composition and microstructure as the thin film. Thus, even if the elastic modulus of the organic seed material layer 325 is not directly measurable, a material having substantially the same composition and microstructure may be formed to a somewhat larger thickness that is more suitable for modulus measurement. Unless otherwise proven, it is presumed that the modulus associated with such a bulk thickness will be substantially the same as that of a thin film of substantially the same composition and microstructure.

[0038] In further embodiments, the organic seed material layer 325 is made of a material having a relatively low (linear) coefficient of thermal expansion (e.g., <20 ppm / K), which is consistent with the CTE of silica glass (e.g., 4–9 ppm / K). In some exemplary embodiments, the organic seed material layer 325 may have a CTE in the range of 3–20 ppm / K, more specifically in the range of 5–12 ppm / K. In some cases, the CTE of the organic seed material layer 325 may be measured directly, but the mention of CTE is also applicable to bulk materials having substantially the same chemical composition and microstructure as the organic seed material layer 325. Therefore, even if the CTE of the organic seed material layer 325 is not directly measurable, a material having substantially the same composition and microstructure may be formed to a larger thickness that is more suitable for CTE measurement. Unless otherwise proven, it is assumed that the CTE associated with such a bulk thickness will be in close agreement with that of a thin film having substantially the same composition and microstructure.

[0039] The composition of the organic seed material layer 325 may vary depending on the deposition technique and may be determined, for example, by one or more of the following methods: FTIR, Raman spectroscopy, AFM, AFM-IR, TEM, XPS, or X-EDS. Generally, the organic seed material layer 325 may contain at least one of the following: a trifluoromethyl group, a carbonyl group, a sulfonyl group, or an ester group, all of which may be detected, for example, by FTIR or XPS.

[0040] In some embodiments, the organic seed material layer 325 has a chemical composition known to be suitable as a conductive material in organic light-emitting diodes (OLEDs) or polymer light-emitting diodes (PLEDs). Generally, such organic polymers mainly consist of carbon chains and may further consist of heterocyclic structures containing, for example, oxygen and / or sulfur. In some examples, the organic seed material layer 325 contains counterions such as dioxypoly(3,4-ethylenedioxythiophene) (PDOT) and poly(styrenesulfonic acid) (PSS). PDOT:PSS π-conjugated polymers are known to have a wide range of conductivity depending on the thickness of the organic seed material layer 325. In other embodiments, the organic seed material layer 325 comprises 3,4-ethylenedioxythiophene (EDOT), thieno[3,4-c]pyrrole-4,6-dione (TPD)-based conjugated monomer, polypyrrole (PPy), polypyrrole-polystyrene sulfonic acid (PPy:PSS), polyaniline (PANI), or the like.

[0041] As further shown in Figure 3B, the organic seed material layer 325 has a sidewall layer thickness T1 perpendicular to the sidewall 321. The sidewall layer thickness T1 may vary with implementation, but in exemplary embodiments, the minimum sidewall layer thickness T1 is at least 500 nm. In some advantageous embodiments, the thickness T1 is 0.5 μm to 5 μm. A greater thickness of the organic material layer 325 is advantageous for absorbing stress, for example, by introducing strain along the thickness T1. A greater thickness of the organic material layer 325 may also improve plating efficiency. However, the thickness T1 may be limited in order to keep the conductivity of the organic seed material layer 325 below some predetermined threshold.

[0042] In the exemplary embodiment shown in Figure 3B, the organic seed material layer 325 is in direct contact with the glass 210. However, in alternative embodiments, one or more intervening material layers may be present between the glass 210 and the organic seed material layer 325. For example, as further described below, the organic seed material layer 325 may be in contact with an intervening liner material layer that can improve the adhesion of the organic seed material layer 325 and / or perform some other function.

[0043] In block 150 (Figure 1), one or more metals are electroplated onto the workpiece, with both an organic seed material layer 325 along the sidewall of the glass 210 and an inorganic seed material layer 225 above the front / back surface of the glass 210. The electroplating may follow any method known to be suitable for lining and / or substantially filling recesses or openings in the IC die package substrate. The electroplating may be selective and limited, for example, by one or more plating masks, or a non-selective (overall) metal deposition process may be performed. In some embodiments, one or more filler metals (e.g., mainly copper) may be electroplated onto the surface of the seed material layer. The rate of metal deposition may vary between the inorganic seed material layer 225 and the organic seed material layer 325. For example, if the inorganic seed material layer 225 has a higher conductivity than the organic seed material layer 325, the electrodeposition rate near the organic seed material layer 325 (i.e., in the opening or pore) may be lower than above the inorganic seed material layer 225. Electroplated metals may have significantly higher elastic moduli and / or CTEs than the organic seed material layer 325. For example, a filled metallized portion consisting mainly of Cu can be expected to have an elastic moduli of approximately 130 GPa and a CTE of 16-17 ppm / K.

[0044] Figure 4 shows an example in which a filler metal 430 is plated onto an organic seed material layer 325 within an opening 320. In this example, the excess metal plated onto surfaces 241 and / or 242 is completely removed through a planarization process. Alternatively, the workpiece shown in Figure 4 may also be obtained through a chemical metal etching process, with or without incorporating mechanical polishing. This metal removal process also removes the inorganic seed material layer 225, thereby exposing the glass 210 and leaving only the conductive TGV structure extending between the front glass surface 241 and the back glass surface 242. Notably, the organic seed material layer 325 remains as a permanent feature of the TGV structure.

[0045] Returning to Figure 1, Method 101 ends at Output 160, where the package is completed, for example, the workpiece is completed as a package substrate, which may further be assembled with an IC die. This embodiment is not limited thereto, and any known IC die package substrate process, such as redistribution layer (RDL) metallization build-up, may be performed at Output 160. Any die mounting process may further be performed at Output 160.

[0046] Figure 5 is a flowchart of Method 501 for forming an IC device package structure including an embedded coaxial inductor by depositing both inorganic and organic seed material layers on a glass substrate and electroplating both magnetic and non-magnetic metals within the TGV structure. Thus, Method 501 is a subset of embodiments of Method 101. Figures 6–13 show cross-sectional views of IC device package structures according to several exemplary embodiments, progressing to include an embedded coaxial inductor structure within a glass substrate when the operation of Method 501 (Figure 5) is performed.

[0047] Referring first to Figure 5, Method 501 begins at input 110, where a workpiece containing glass is received. The received workpiece may have any of the workpiece characteristics and / or attributes described above in the context of Method 101 (Figure 1). Method 501 (Figure 5) continues at block 120, where a through-hole or recess is formed in block 120. The through-hole or recess may be formed, for example, according to any of the techniques described above in the context of Method 101 (Figure 1). Figure 6 shows an exemplary embodiment in which the substrate core 601 includes an opening 320 that penetrates the glass 210. In contrast to the substrate core 201 (Figure 3A), the substrate core 601 lacks inorganic seed material on the front and back surfaces 241, 242. The substrate core 601 may have any of the other attributes described above in the context of Figure 3A.

[0048] Returning to Figure 5, Method 501 may optionally include the deposition of one or more liner materials in block 525 (shown by a dashed line to emphasize the optional nature of block 525). In some embodiments, an inorganic liner material is deposited in block 525. The inorganic liner material may be, for example, a dielectric or intermetallic compound with high electrical resistivity. The inorganic liner may function, for example, as an adhesive layer. In other embodiments, an organic liner material is deposited in block 525. In contrast to an organic seed material, the organic liner material formed in block 525 is one with high electrical resistivity (i.e., an electrical insulator or nonconductor).

[0049] In an advantageous embodiment, the deposition of the liner material employs a “dry” process that can form a thin film of the material on the sidewalls of features having a high aspect ratio (e.g., greater than 10:1). In the case of an embodiment of an inorganic material, block 525 may include deposition processes that offer high film thickness uniformity, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), but physical vapor deposition (PVD) techniques, which offer less uniformity, may also be employed. In the case of an embodiment of an organic material, block 525 may also include vapor deposition techniques. In one example, an initiated chemical vapor deposition (iCVD) process deposits a polymer material on the sidewalls of an opening, for example, into direct contact with a previously deposited inorganic material. Generally, in iCVD techniques, monomers are deposited on the workpiece surface, and non-thermally activated initiator radicals activate the monomers, thereby initiating a polymerization reaction on the surface. Such techniques offer an opportunity to directly graft polymers onto previously deposited inorganic materials. Furthermore, it is possible to leave dangling bonds on the surface of organic materials, thereby providing bonding sites for subsequent material layers and enhancing adhesion with the organic material.

[0050] Figure 7 shows an example in which a liner material layer 720 is deposited on a substrate core 601. In this example, the liner material layer 720 is deposited on the glass surfaces 241 and 242, as well as above the side wall 321 of the opening 320. The liner material layer 720 is in direct contact with the glass 210.

[0051] In some inorganic embodiments, the liner material layer 720 advantageously contains only trace amounts of carbon, if any, less than 1.0 wt%. In further embodiments, the liner material layer 720 contains nitrogen. Nitrogen-containing functional groups (e.g., nitrides) can have particularly good adhesion to the glass surface, thereby reducing the risk of the liner delaminating from the glass 210. Nitride functional groups may also promote good adhesion to organic material layers deposited later. In some embodiments, the liner material layer 720 further contains silicon, advantageously silicon nitride (SiN x ) may be, one example being the stoichiometric composition Si3N4. In some embodiments, the liner material layer 720 contains oxygen, which is present in combinations of both silicon and nitrogen (e.g., SiO2 x N y ), or in the absence of nitrogen (e.g., SiO x ) may be any of the above, and here an example is the stoichiometric composition SiO2. Optionally, the liner material layer 720 may also contain one or more metals. Exemplary metals include Ti (e.g., TiN) x , TiO x , TiO x N y ,TiSi x ,TiSi x O y N z ), Ta (for example, TaN x TaO x TaO x N y , TaSi x , TaSi x O y N z ), or W (for example, WN x WO x WOx N y , WSi x , WSi x O y N z ) comprising one or more of the above. Other metals (e.g., Al, Sn, Sc, In, or Au), and their nitrides, oxides, silicides, or silicates are also possible.

[0052] In some organic embodiments, the liner material layer 720 is a polymer material having a significantly higher carbon content than in the inorganic embodiments. In some embodiments, the liner material layer 720 is an organic polymer, but with a different composition than that of the conductive organic seed material. The composition of the organic polymer may vary, but some examples include polytetrafluoroethylene (PTFE), poly(glycidyl methacrylate) (PGMA), poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), or poly(1H,1H,2H,2H-perfluorodecyl acrylate) (pPFDA). Such materials may be deposited by iCVD using an initiator such as tert-butyl peroxide (TBPO) in the case of PGMA, or perfluorobutanesulfonyl fluoride (PBSF) in the case of PTFE.

[0053] Returning to Figure 5, Method 501 continues at block 130, where an organic seed material layer is formed in a hole or recess in the glass. Block 130 may include any of the steps described above in the context of Method 101 (Figure 1) and may form any of the above-described organic seed material layers. In the example illustrated in Figure 8, the substrate core 601 here includes an organic seed material layer 325. In this example, the organic seed material layer 325 is deposited on the glass surfaces 241, 242, as well as above the side wall 321 of the opening 320. In embodiments including a liner material layer 720, the organic seed material layer 325 is in direct contact with the liner material layer 720. In embodiments lacking a liner material layer 720, the organic seed material layer 325 may instead be in direct contact with the glass 210. The seed material layer 325 may have any of the above-described chemical compositions and, similarly, any of the above-described attributes or characteristics.

[0054] As further shown in Figure 9, the organic seed material layer 325 may be selectively removed from the front glass surface 241 and / or the back glass surface 242. Alternatively, the organic seed material layer 325 may be selectively formed only within the opening 320 to achieve the same structure as shown in Figure 9. Selective removal may be, for example, through a surface planarization process. Such a process may also remove the liner material layer beneath either, thereby exposing the glass 210. In an alternative embodiment, an etching solution or solvent of the organic seed material layer 325 may be applied to the front surface 241 and / or the back surface 242 to similarly expose the underlying liner material layer 720 or glass 210 while retaining the organic seed material layer 325 within the opening 320. In yet another embodiment, the organic seed material layer 325 is retained above the front surface 241 and / or the back surface 242.

[0055] Returning to Figure 5, method 501 continues in block 135, where an inorganic seed material is formed on the front and / or back surface of the package substrate workpiece. In embodiments where the surface of the substrate core is not covered with seed material, the organic seed material formed in block 130 (Figure 5) may be supplemented with inorganic seed material through the implementation of any of the methods or techniques described above for block 135. In the example shown in Figure 10, the substrate core 601 further includes an inorganic seed material layer 225 in direct contact with the glass 210. Alternatively, if the organic seed material 325 is held on surfaces 241, 242, the inorganic seed material layer 225 may be in direct contact with the organic seed material 325. In any embodiment, the inorganic seed material layer 225 may have any of the chemical compositions described above, one example being primarily Cu.

[0056] As shown in Figure 10, the inorganic seed material layer 225 may be selectively formed above the surfaces 241, 242 by a non-conformal (directional) deposition process, such as PVD. Parameters of the PVD process, such as power and pressure, may be controlled to limit the accumulation of the inorganic seed material layer 225 within the opening 320. For example, the thickness of the inorganic seed material layer 225 may decrease from some nominal thickness perpendicular to the front surface 241 to zero along the sidewall 321 beyond the threshold aspect ratio of the opening 320. In some exemplary embodiments, the inorganic seed material layer 225 is absent from the sidewall 321 at a distance not greater than 750 nm from the front surface 241. When the inorganic seed material layer 225 is absent, the conductivity of the material along the sidewall 321 may be advantageously lower than in the region where the inorganic seed material layer 225 is present.

[0057] With the workpiece covered with a combination of organic and inorganic seed material layers, the fabrication of the coaxial magnetic inductor structure may continue by electroplating, for example, through one or more plating masks. Returning to Figure 5, method 501 continues by forming a masked electroplated area of ​​magnetic metal in block 550, and then forming a masked electroplated area of ​​non-magnetic filler metal in block 555. The electroplating process carried out in block 550 may be by any technique known to be suitable for magnetic metals. The electroplating process carried out in block 555 may similarly follow any technique known to be suitable for filler metals to form a coaxial structure containing a non-magnetic metal surrounded by an annular portion of magnetic metal.

[0058] In an example further shown in Figure 11, the substrate core 601 includes a plating mask 1110 above the front glass surface 241 and above the back glass surface 242. The openings in the plating mask 1110 surround the opening 320. The magnetic metal 1125 is plated onto the unmasked portions of the organic seed material layer 325 and the unmasked portions of the inorganic material layer 225. Thus, within the opening 320, the magnetic metal 1125 forms a liner above the organic seed material layer 325. One or more openings 320 that do not contain the magnetic metal 1125 may be protected by a portion of the plating mask 1110.

[0059] The magnetic metal 1125 may be of any composition known to be compatible with electroplating. The magnetic metal 1125 may, advantageously, have a high permeability, for example, in the range of 5 to 20. Suitable metals include alloys containing any of iron, nickel, cobalt, platinum, palladium, manganese, molybdenum, copper, vanadium, indium, aluminum, barium, strontium, and / or zinc. In some exemplary embodiments, the magnetic metal 1125 is an iron-cobalt (Fe-Co) alloy that can be readily electroplated. Within the opening 320, the magnetic metal 1125 is, advantageously, a continuous film with a layer thickness perpendicular to the sidewall 321, which may be in the range of 100 to 500 nm.

[0060] As further shown in Figure 12, the plating mask 1110 is removed from the substrate core 601 and replaced with another plating mask 1210, which defines larger openings above the front and back surfaces 241 and 242, which also surround the opening 320 that penetrates the glass 210. In the example shown, the filler metal 430 may be characterized as a filler metal portion 430A embedded in the glass 210, i.e., an axial filament, and a filler metal portion 430B above the front and back surfaces of the glass 210. As shown in the enlarged view of Figure 12, the filler metal portion 430A is in direct contact with the magnetic material layer 1125. In contrast, the filler metal portion 430B is in direct contact with the inorganic seed material layer 225 in a region beyond the outer edge of the magnetic material layer 1125 by a non-zero distance (e.g., beyond the side wall 321). In the case of any TGV structure that did not receive the magnetic metal 1125, the filling metal portion 430A may be in direct contact with the organic seed material layer 325.

[0061] The filling metal portions 430A / 430B may be of any metal composition known to be suitable as a conductor embedded within the surrounding magnetic core metal. The filling metal may have any of the compositions described elsewhere in this specification. For example, the filling metal may be primarily Cu (e.g., substantially pure Cu). In embodiments where the inorganic seed material layer 225 and the filling metal portions 430A / 430B have substantially the same composition (e.g., both are primarily Cu), the connection surface between the two may be clearly visible in TEM images, thereby revealing that the inorganic seed material layer 225 has a different microstructure from that of the filling metal portion 430B. For example, the seed material layer 225 may have a smaller grain size (e.g., grain size of 5-20 nm) than the filling metal portion 430B (e.g., grain size of >25 nm).

[0062] After electroplating, all plating mask material and underlying seed material may be removed from the workpiece. In the example shown in Figure 13, the plating mask 1210 is removed, and the inorganic seed material layer 225 is removed, for example, by wet chemical etching. The coaxial inductor structure, comprising the filling metal portion 430A surrounded by the magnetic metal 1125, remains embedded within the TGV extending through the glass 210. The organic seed material layer 325 is retained as a permanent feature of the coaxial inductor structure. In advantageous embodiments where the organic seed material layer 325 has relatively low conductivity, the coaxial inductor structure may exhibit lower parasitic components (e.g., those related to eddy currents) during device operation. Thus, the organic seed material layer 325 may enable the electroforming of a coaxial inductor structure that exhibits superior performance compared to those formed with conventional (inorganic) seed material. Furthermore, because stress may be better absorbed by the organic seed material layer 325, the coaxial inductor structure may exhibit improved stability.

[0063] Returning to Figure 5, Method 501 continues with the build-up of an electrical wiring structure in block 560, which is electrically coupled to a TGV formed within the substrate core. The wiring structure build-up may be performed on one or more surfaces of the glass before assembling with one or more IC dies. The electrical wiring structure may be electrically coupled to a coaxial inductor structure and may include, for example, one or more levels of metallized features embedded in any suitable dielectric material. The electrical wiring structure may interconnect one or more IC dies and / or couple one or more of the IC dies to various types of TGVs (e.g., magnetic and / or non-magnetic). Before or after forming the wiring structure, the workpiece may be fixed to a handle or carrier having any suitable composition and any suitable thickness, for embodiments herein are not limited in this respect.

[0064] In Figure 14, the package structure 1401 includes a wiring structure 780A built up on top of surface 241. Similarly, another wiring structure 780B may be built up on top of surface 242. The wiring structure 780B is shown with dashed lines to emphasize that the buildup on both sides is optional. The wiring structure 780A (780B) comprises one or more levels of RDL metallization features 782 embedded within one or more layers of dielectric material 781. The RDL metallization features 782 may contain one or more metals, one example being primarily copper. At least some of the RDL metallization features 782 preferably electrically bridge two or more IC dies together with the finest metallization line / space feature pitch (e.g., <3 μm lines and spaces) that can be directly patterned thanks to the flatness of the glass 210. The wiring structure 780 may include a metallization feature 782 that interconnects multiple IC dies to a coaxial inductor structure (or other TGV structure) on the substrate core 601. In some examples where the inductor structure includes an organic seed material layer, such an organic seed material layer is absent from the metallization feature 782.

[0065] Depending on the embodiment, the dielectric material 781 may be, for example, a mold compound, a spin-on material, or a dry film laminate material. The dielectric material 781 may be introduced into the mold in a wet / uncured state and then dried / cured. Alternatively, the dielectric material 781 may be introduced as a semi-cured dry film and fully cured after its application over the glass 210. The composition of the dielectric material 781 may vary depending on the mounting configuration. In some advantageous embodiments, the dielectric material 781 is an organic dielectric, such as an epoxy resin, phenolic glass, or a resin film such as the GX series film (ABF) commercially available from Ajinomoto Fine-Techno Co., Inc. The dielectric material 781 may include an epoxy resin (e.g., an acrylate of novolac, such as epoxyphenol novolac (EPN) or epoxy cresol novolac (ECN)). In some specific examples, the dielectric material 781 is, for example, a bisphenol A type epoxy resin containing epichlorohydrin. In other examples, the dielectric material 781 includes an aliphatic epoxy resin.

[0066] Returning to Figure 5, method 101 may continue in block 570, where at least one IC die is optionally assembled into a workpiece, more specifically an electrical wiring structure. Each IC die assembled in block 570 may include any electrical circuit configuration, one example being a logic circuit configuration with logic gates. The IC dies assembled in block 570 may also include any photonic circuit configuration suitable for detecting, emitting, or processing (e.g., filtering, multiplexing, and demultiplexing) optical signals.

[0067] In the example shown in Figure 15, IC dies 891-894 are assembled as the first die of a co-packaged multi-die IC device package structure 1501, on the interconnection surface within the uppermost metallized level of the wiring structure 780A. IC dies 891-894 may be directly bonded to the wiring structure 780A. Alternatively, IC dies 891-894 may be electrically coupled through an intervening electrical interconnect (not shown), which may include, for example, solder of any preferred composition. In the example shown, IC dies 891-893 are each mounted by flip-chips, and the integrated circuit configuration within each die is located proximal to the front surface 241. However, IC die 894 has a through-die via 899, and the integrated circuit configuration is distal to the package substrate surface 241.

[0068] Each of the IC dies 891-894 may be a fully functional ASIC, or a chiplet or tile with more limited functionality that complements the functionality of one or more other IC dies that are part of the same multi-die device. The chiplet or tile may be, for example, a radio wave circuit, a microprocessor core, an electronic memory circuit, a floating-point gate array (FPGA), a power management and / or power supply circuit, or may include a MEMS device. In some examples, one or more of the IC dies 891-894 include one or more active repeater circuit configurations to improve the multi-die interconnect (e.g., a network-on-chip architecture). In other examples, one or more of the IC dies 891-894 include a clock generator circuit configuration or a temperature sensing circuit configuration. In other examples, one or more of the IC dies 891-894 include a logic circuit configuration that, together with the other IC dies 891-894, implements a multi-chiplet aggregated logic circuit configuration (e.g., a mesh network-on-chip architecture). In some specific examples, at least one of the IC dies 891 to 894 includes a microprocessor core circuit configuration, for example, one or more shift registers.

[0069] IC dies 891-894 advantageously include field-effect transistors (FETs) having a device pitch of 80 nm or less. The FETs may be of any architecture (e.g., planar, unplanar, single-gate, multi-gate, multilayer nanosheet, etc.). In some embodiments, the FET terminals have a feature pitch smaller than 30 nm. Additionally, or instead, IC dies 891-894 may include active devices other than FETs. For example, IC dies 891-894 may include electronic memory structures such as magnetic tunnel junctions (MTJs), capacitors, or similar.

[0070] IC dies 891-894 may include one or more IC die metallization levels embedded within the insulator. The IC die metallization features may have any composition with sufficient conductivity, but in exemplary embodiments, the IC die metallization features are primarily copper (Cu). In other examples, the metallization features are primarily other than Cu, for example, primarily Ru, or primarily W, but are not limited to these. The best of the metallization features within IC dies 891-894 may have a feature pitch in the range of, for example, 100 nm to several microns.

[0071] Returning to Figure 5, Method 501 may terminate at Output 580, where the assembled device package structure may optionally be further mounted to a suitable host component. Similar to the die mounting block 570, Output 580 is indicated by a dashed line to emphasize that it is optional and may be performed later in Method 501. Figure 16 shows an exemplary system 1601, including one device package structure 1501 mounted to a host component 1605 by an interconnect 1611, according to several embodiments. In exemplary embodiments, the interconnect 1611 is a solder (e.g., SAC) microbump, but other interconnect features are also possible. In some embodiments, the host component 1605 is primarily silicon. The host component 1605 may also include one or more alternative materials known to be suitable as interposers or package substrates (e.g., epoxy matrix, cored or coreless copper-clad laminate, FR4, etc.). The host component 1605 may also include a printed circuit board (PCB). The host component 1605 may include one or more metallized redistribution levels (not shown) embedded within the dielectric material. The host component 1605 may also include one or more IC dies embedded within it.

[0072] The host component 1605 may include interconnects 1620, indicated by dashed lines. Each of the interconnects 1620 may have any solder (balls, bumps, etc.) suitable for a given host board architecture (e.g., surface mount FR4). One or more heat spreaders and / or heat sinks 1650 may be further coupled to the device package structure 1501, as indicated by dashed lines, which may be advantageous, for example, if the IC dies 891-894 have one or more CPU cores or other circuit configurations with similar power density. Any package dielectric, such as a molding material, may surround the sidewalls of the IC dies 891-894.

[0073] Figure 17 shows a mobile computing platform 1705 and a data server machine 1706 using an IC device package with a TGV including an organic seed material layer, for example, as described elsewhere in this specification for a coaxial inductor structure. The server machine 1706 may be any commercial server, for example, comprising any number of high-performance computing platforms arranged in a rack and networked together for electronic data processing, which in an exemplary embodiment includes system 1601, for example, as described elsewhere in this specification. The mobile computing platform 1705 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, or the like, respectively. For example, the mobile computing platform 1705 may be a tablet, smartphone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), an integrated system 1710, and a battery 1715.

[0074] As further shown in Figure 17, system 1601 may be coupled to one or more Power Management Integrated Circuits (PMICs) or RF Integrated Circuits (RFICs), including a broadband RF (radio) transmitter and / or receiver. The PMIC may perform battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to battery 1715 and an output that provides current to other functional modules. As further shown, in exemplary embodiments, the RFIC has an output coupled to an antenna (not shown) to implement any of a number of radio standards or protocols, including, but not limited to, Wi-Fi® (IEEE 802.11 family), WiMAX® (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM®, GPRS, CDMA, TDMA, DECT, Bluetooth®, their derivatives, and any other radio protocols designated as 3G, 4G, and later.

[0075] Figure 18 is a block diagram of a cryogenically cooled computing device 1800 according to several embodiments. For example, one or more components of the computing device 1800 may include any of the devices or structures discussed elsewhere in this specification. Although numerous components are shown in Figure 18 as being included in the computing device 1800, one or more of these components may be omitted or duplicated if suitable for the application. In some embodiments, some or all of the components included in the computing device 1800 may be mounted on one or more printed circuit boards (e.g., motherboards). In some embodiments, various components may be manufactured on a single system-on-a-chip (SoC) die. Additionally, in various embodiments, the computing device 1800 may not include one or more of the components shown in Figure 18, but the computing device 1800 may include interface circuit configurations for coupling with one or more components. For example, computing device 1800 does not have to include display device 1803, but may include a display device interface circuit configuration (e.g., connector and driver circuit configuration) to which display device 1803 can be coupled.

[0076] The computing device 1800 may include processing devices 1801 (e.g., one or more processing devices). As used herein, the term processing device or processor refers to a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1801 may include memory 1821, communication devices 1822, refrigeration / active cooling devices 1823, battery / power regulation devices 1824, logic 1825, interconnects 1826, thermal regulation devices 1827, and hardware security devices 1828.

[0077] The processing device 1801 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0078] The processing device 1801 may include a memory 1802, which itself may include one or more memory devices, such as volatile memory (e.g., Dynamic Random-Access Memory (DRAM)), non-volatile memory (e.g., Read-Only Memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, a memory 1821 includes a memory that shares a memory die with the processing device 1801. This memory may be used as a cache memory and may include embedded Dynamic Random-Access Memory (eDRAM) or Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM).

[0079] The computing device 1800 may include a thermal conditioning / refrigeration device 1806. The thermal conditioning / refrigeration device 1806 may maintain the processing device 1801 (and / or other component computing devices 1800) at a predetermined low temperature during operation. This predetermined low temperature may be any of the temperatures discussed elsewhere in this specification.

[0080] In some embodiments, the computing device 1800 may include a communication chip 1807 (e.g., one or more communication chips). For example, the communication chip 1807 may be configured to manage wireless communication for data transfer to and from the computing device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium.

[0081] The communication chip 1807 may implement any wireless standard or protocol, including, but not limited to, Electrical and Electronics Engineer (IEEE) standards, including Wi-Fi® (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and Long-Term Evolution (LTE) projects with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultramobile Broadband (UMB) project (also known as “3GPP® 2”)). The communication chip 1807 may operate in accordance with the Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1807 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN).The communication chip 1807 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and their derivatives, and any other radio protocols designated as 3G, 4G, 5G, and later. The computing device 1800 may include an antenna 1813 for facilitating and / or receiving other radio communications (such as AM or FM radio transmissions).

[0082] The computing device 1800 may include a battery / power circuit configuration 1808. The battery / power circuit configuration 1808 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit configurations for the coupling component of the computing device 1800 to an energy source separate from the computing device 1800 (e.g., AC line power).

[0083] The computing device 1800 may include a display device 1803 (or a corresponding interface circuit configuration as discussed above). The display device 1803 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0084] The computing device 1800 may include an audio output device 1804 (or a corresponding interface circuit configuration as discussed above). The audio output device 1804 may include any device that generates an audible indicator, such as a speaker, headset, or earbuds.

[0085] The computing device 1800 may include an audio input device 1810 (or a corresponding interface circuit configuration as discussed above). The audio input device 1810 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output).

[0086] The computing device 1800 may include a Global Positioning System (GPS) device 1809 (or a corresponding interface circuit configuration as discussed above). The GPS device 1809 may communicate with a satellite-based system and receive the location of the computing device 1800, as is known in the art.

[0087] The computing device 1800 may include another output device 1805 (or a corresponding interface circuit configuration as discussed above). Examples include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0088] The computing device 1800 may include another input device 1811 (or a corresponding interface circuit configuration as discussed above). Examples may include an accelerometer, gyroscope, compass, image acquisition device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, Quick Response (QR) code reader, any sensor, or Radio Frequency Identification (RFID) reader.

[0089] The computing device 1800 may include a security interface device 1812. The security interface device 1812 may include any device that provides security measures to the computing device 1800, such as intrusion detection, biometric authentication, security encoding or decoding, access list management, malware detection, or spyware detection.

[0090] The computing device 1800 or a subset of its components may have any suitable form factor, for example, a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, Personal Digital Assistant (PDA®), ultramobile personal computer, etc.), a desktop computing device, a server, or other network-connected computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device.

[0091] While certain features described herein have been explained with reference to various implementations, this explanation is not intended to be constrained. Therefore, various modifications of the implementation examples described herein and other implementation examples, though obvious to those skilled in the art to whom this disclosure relates, are considered to be within the spirit and scope of this disclosure.

[0092] This disclosure is not limited to the embodiments described herein and may be implemented with modifications and alterations without departing from the scope of the appended claims. For example, the embodiments described above may include certain combinations of features further provided below.

[0093] In a first embodiment, the apparatus comprises a substrate having glass having a thickness between a first side surface and a second side surface. The apparatus comprises an opening extending through the thickness of the glass and one or more metals within the opening. At least one of the metals is Cu. The apparatus comprises a conductive material layer within the opening, between the metal and the side walls of the glass, the conductive material layer having carbon and sulfur.

[0094] In the second embodiment, with respect to any of the first embodiments, the conductive material layer is absent on at least one of the first side surface or the second side surface.

[0095] In the third embodiment, with respect to any of the second embodiments, at least one of the one or more metals extends beyond the periphery of the opening by a non-zero distance above the first side surface or the second side surface.

[0096] In the fourth embodiment, in any of the first to third embodiments, the metal comprises a layer of magnetic alloy in direct contact with the conductive material layer, and a filler metal surrounded by the layer of magnetic alloy. The filler metal mainly consists of Cu and is physically separated from the conductive material layer by the layer of magnetic alloy.

[0097] In the fifth embodiment, with respect to any of the fourth embodiments, the conductive material layer is absent on at least one of the first side surface or the second side surface, and the filler metal extends beyond the outer edge of the magnetic alloy layer by a non-zero distance above the first side surface or the second side surface.

[0098] In the sixth embodiment, in any of the fourth to fifth embodiments, the magnetic alloy comprises Co and Fe.

[0099] In the seventh embodiment, in any of the first to sixth embodiments, the conductive material layer has a layer thickness of at least 100 nm.

[0100] In the eighth embodiment, in any of the seventh embodiments, the conductive material layer has a layer thickness of 0.5 to 5 μm.

[0101] In the ninth embodiment, in any of the seventh to eighth embodiments, the conductive material layer has an electrical conductivity of at least 100 S / cm.

[0102] In the tenth embodiment, in any of the ninth embodiments, the conductive material layer comprises poly(3,4-ethylenedioxythiophene) and poly(styrenesulfonic acid).

[0103] In the eleventh embodiment, in any of the first to tenth embodiments, the apparatus further comprises a liner located within the opening and between the conductive material layer and the side wall of the glass. The liner has an inorganic material layer.

[0104] In the twelfth embodiment, with respect to any of the eleventh embodiment, the inorganic material layer comprises nitrogen and at least one of copper, titanium, silicon, or oxygen.

[0105] In a thirteenth embodiment, the system comprises a plurality of integrated circuit (IC) dies electrically coupled to a first metallized feature on a first side of a substrate including glass. The system includes through-holes extending through the thickness of the glass between the first side surface and the second side surface of the glass. The system includes a coaxial metal inductor structure located within the through-hole. The coaxial metal inductor structure has a metal filament having Cu and extending through the thickness of the glass, and an annular layer of magnetic metal alloy covering the filament. The system includes a polymer layer lining the through-hole between the magnetic metal alloy and the glass.

[0106] In the 14th embodiment, in any of the 13th embodiments, the polymer layer is in contact with the magnetic metal alloy, the polymer layer has a thickness of at least 200 nm, and the polymer layer is absent from the first side surface and the second side surface.

[0107] In the 15th embodiment, in any of the 14th embodiments, the polymer layer comprises poly(3,4-ethylenedioxythiophene) and poly(styrenesulfonic acid).

[0108] In the sixteenth embodiment, in any of the fourteenth to fifteenth embodiments, the system further comprises an electrical wiring structure located on the first side of the glass, the wiring structure having the first metallized feature and dielectric material. The coaxial metal inductor structure extends from the wiring structure to the second side of the glass. The wiring structure electrically couples the coaxial metal inductor structure to at least one of the IC dies.

[0109] In the 17th embodiment, the method comprises the steps of receiving a workpiece containing glass, forming a hole through the thickness of the glass, depositing a polymer seed layer above the sidewall of the hole, and electroplating a metallized portion within the hole by conducting an electric current through the polymer seed layer.

[0110] In the 18th embodiment, with respect to any of the 17th embodiment, the step of electroplating the metallized portion includes the steps of plating a magnetic metal layer into the holes so as to contact the polymer seed layer, and plating a non-magnetic metal into the holes so as to contact the magnetic metal layer.

[0111] In the 19th embodiment, with respect to any of the 18th embodiments, the step of depositing the polymer seed layer comprises the steps of coating the workpiece with a fluid precursor and curing the precursor into the polymer seed layer having an electrical conductivity of at least 100 S / cm.

[0112] In the 20th embodiment, with respect to any of the 19th embodiment, the method further comprises the step of depositing an inorganic seed layer containing a metal on the surface of the glass, which is electrically coupled to the polymer seed layer. The step of electroplating the metallized portion into the pores comprises the step of conducting the current through the inorganic seed layer and the polymer seed layer.

[0113] However, the embodiments described above are not limited to this, and in various implementations, the embodiments may include applying only a subset of such features, applying different orders of such features, applying different combinations of such features, and / or applying additional features other than those explicitly enumerated. The scope of this disclosure should therefore be determined by referring to the appended claims together with the entire scope of equivalents to which such claims are entitled. [Other possible items] [Item 1] A substrate having glass with a thickness between the first side surface and the second side surface; An opening extending through the aforementioned thickness of the glass; One or more metals within the opening, wherein at least one of the metals is Cu; and A conductive material layer in the opening between the glass and the metal and side wall, wherein the conductive material layer comprises carbon and sulfur. A device or apparatus to equip. [Item 2] The apparatus according to item 1, wherein the conductive material layer is absent on at least one of the first side surface or the second side surface. [Item 3] The apparatus according to item 2, wherein at least one of the one or more metals extends beyond the periphery of the opening by a non-zero distance above the first side surface or the second side surface. [Item 4] The aforementioned metal is A layer of magnetic alloy in direct contact with the conductive material layer; and A filling metal surrounded by a layer of magnetic alloy, which mainly contains Cu and is physically separated from the conductive material layer by the layer of magnetic alloy. The apparatus described in item 1, having the following features. [Item 5] The conductive material layer is absent from at least one of the first side surface or the second side surface; The filling metal extends beyond the outer edge of the magnetic alloy layer by a non-zero distance above the first side surface or the second side surface. The device described in item 4. [Item 6] The apparatus according to item 4, wherein the magnetic alloy comprises Co and Fe. [Item 7] The apparatus according to item 1, wherein the conductive material layer has a layer thickness of at least 100 nm. [Item 8] The apparatus according to item 7, wherein the conductive material layer has a layer thickness of 0.5 to 5 μm. [Item 9] The apparatus according to item 7, wherein the conductive material layer has an electrical conductivity of at least 100 S / cm. [Item 10] The apparatus according to item 9, wherein the conductive material layer comprises poly(3,4-ethylenedioxythiophene) and poly(styrenesulfonic acid). [Item 11] The apparatus according to item 1, further comprising a liner located within the opening and between the conductive material layer and the side wall of the glass, wherein the liner has an inorganic material layer. [Item 12] The apparatus according to item 11, wherein the inorganic material layer comprises nitrogen and at least one of copper, titanium, silicon, or oxygen. [Item 13] Multiple integrated circuit (IC) dies electrically coupled to a first metallized feature on a first side of a substrate containing glass; A through-hole extending between the first and second side surfaces of the glass, penetrating the thickness of the glass; A coaxial metal inductor structure located within the aforementioned through hole, A metal filament having Cu and extending through the thickness of the glass; and An annular layer of magnetic metal alloy covering the filament; A coaxial metal inductor structure having; and A polymer layer lining the through-hole between the magnetic metal alloy and the glass, wherein the polymer layer is mainly carbon and further contains sulfur. A system that includes these features. [Item 14] The polymer layer is in contact with the magnetic metal alloy; The polymer layer has a thickness of at least 200 nm; The polymer layer is absent from the first side surface and the second side surface. The system described in item 13. [Item 15] The system according to item 14, wherein the polymer layer comprises poly(3,4-ethylenedioxythiophene) and poly(styrenesulfonic acid). [Item 16] The system according to item 15, further comprising an electrical wiring structure located on the first side of the glass, the wiring structure having the first metallized feature and dielectric material, the coaxial metal inductor structure extending from the wiring structure to the second side of the glass, and the wiring structure electrically coupling the coaxial metal inductor structure to at least one of the IC dies. [Item 17] The stage where the workpiece, including the glass, is received; A step of forming a hole that penetrates the thickness of the glass; A step of depositing a polymer seed layer above the side wall of the hole, wherein the polymer seed layer contains sulfur; and The step of electroplating the metallized portion into the pores by conducting an electric current through the polymer seed layer. A method that includes [a certain feature]. [Item 18] The step of electroplating the metallized portion is as follows: A step of plating a magnetic metal layer into the pores so that it comes into contact with the polymer seed layer; and A step of plating a non-magnetic metal into the hole so that it comes into contact with the magnetic metal layer. The method described in item 17, which has the following characteristics. [Item 19] The step of depositing the polymer seed layer is: The step of coating the workpiece with a fluid precursor; and A step of curing the precursor into the polymer seed layer having an electrical conductivity of at least 100 S / cm; The method described in item 18, which has the following characteristics. [Item 20] The method further comprises the step of depositing an inorganic seed layer containing a metal on the surface of the glass, which is electrically bonded to the polymer seed layer; The step of electroplating the metallized portion into the hole includes the step of conducting the current through the inorganic seed layer and the polymer seed layer. The method described in item 19.

Claims

1. A microelectronic device package substrate having glass with thickness between the first side surface and the second side surface; An opening extending through the aforementioned thickness of the glass; One or more metals within the opening, wherein at least one of the metals is Cu; and A conductive material layer in the opening between the glass, the metal and the side wall, wherein the conductive material layer comprises carbon and sulfur. A device or apparatus to equip.

2. The apparatus according to claim 1, wherein the conductive material layer is absent on at least one of the first side surface or the second side surface.

3. The apparatus according to claim 2, wherein at least one of the one or more metals extends beyond the periphery of the opening by a non-zero distance above the first side surface or the second side surface.

4. The aforementioned metal is A layer of magnetic alloy in direct contact with the conductive material layer; and A filling metal surrounded by the magnetic alloy layer, which mainly contains Cu and is physically separated from the conductive material layer by the magnetic alloy layer. The apparatus according to claim 1, having the following features.

5. The conductive material layer is absent from at least one of the first side surface or the second side surface; The filling metal extends beyond the outer edge of the magnetic alloy layer by a non-zero distance above the first side surface or the second side surface. The apparatus according to claim 4.

6. The apparatus according to claim 4, wherein the magnetic alloy comprises Co and Fe.

7. The apparatus according to claim 1, wherein the conductive material layer has a layer thickness of at least 100 nm.

8. The apparatus according to claim 7, wherein the conductive material layer has a layer thickness of 0.5 to 5 μm.

9. The apparatus according to claim 7, wherein the conductive material layer has an electrical conductivity of at least 100 S / cm.

10. The apparatus according to claim 9, wherein the conductive material layer comprises poly(3,4-ethylenedioxythiophene) and poly(styrenesulfonic acid).

11. The apparatus according to any one of claims 1 to 10, further comprising a liner located within the opening and between the conductive material layer and the side wall of the glass, wherein the liner has an inorganic material layer.

12. The apparatus according to claim 11, wherein the inorganic material layer comprises nitrogen and at least one of copper, titanium, silicon, or oxygen.

13. Multiple integrated circuit (IC) dies electrically coupled to a first metallized feature on a first side of a package substrate containing glass; A through hole extending through the thickness of the glass and between the first side surface and the second side surface of the glass; A coaxial metal inductor structure located within the aforementioned through hole, A metal filament having Cu and extending through the thickness of the glass; and An annular layer of magnetic metal alloy covering the filament; A coaxial metal inductor structure having; and A polymer layer lining the through-hole between the magnetic metal alloy and the glass, wherein the polymer layer contains carbon and sulfur. A system equipped with these features.

14. The polymer layer is in contact with the magnetic metal alloy; The polymer layer has a thickness of at least 200 nm; The polymer layer is absent from the first side surface and the second side surface. The system according to claim 13.

15. The system according to claim 14, wherein the polymer layer comprises poly(3,4-ethylenedioxythiophene) and poly(styrenesulfonic acid).

16. The system according to claim 13, further comprising an electrical wiring structure located on the first side of the glass, the electrical wiring structure having the first metallized feature and a dielectric material, the coaxial metal inductor structure extending from the electrical wiring structure to the second side of the glass, and the electrical wiring structure electrically coupling the coaxial metal inductor structure to at least one of the IC dies.

17. The system according to claim 13, further comprising a liner in the through hole and between the polymer layer and the glass, wherein the liner comprises an inorganic material layer.

18. The system according to claim 17, wherein the inorganic material layer comprises nitrogen and at least one of copper, titanium, silicon, or oxygen.

19. The system according to any one of claims 13 to 18, wherein the polymer layer is absent on at least one of the first side or the second side of the glass.

20. The stage where you receive the workpiece, including the glass; A step of forming a hole that penetrates the thickness of the glass; A step of depositing a polymer seed layer above the side wall of the hole, wherein the polymer seed layer contains sulfur; A step of electroplating the metallized portion into the pores by conducting an electric current through the polymer seed layer; and The step of forming an interconnection feature on at least one side of the glass, wherein the interconnection feature connects one or more IC dies to the metallized portion in the hole. A method that includes [a certain feature].

21. The step of electroplating the metallized portion is as follows: A step of plating a magnetic metal layer into the pores so that it comes into contact with the polymer seed layer; and A step of plating a non-magnetic metal into the hole so that it comes into contact with the magnetic metal layer. The method according to claim 20, comprising:

22. The step of depositing the polymer seed layer is: The step of coating the workpiece with a fluid precursor; and A step of curing the fluid precursor into the polymer seed layer having an electrical conductivity of at least 100 S / cm; The method according to claim 20, comprising:

23. The method further comprises the step of depositing an inorganic seed layer containing a metal on the surface of the glass that is in contact with the polymer seed layer. The step of electroplating the metallized portion into the hole includes the step of conducting the current through both the inorganic seed layer and the polymer seed layer. The method according to claim 20.

24. The method according to claim 20, further comprising depositing an inorganic liner on the sidewalls of the pores before depositing the polymer seed layer, wherein the inorganic liner comprises nitrogen and at least one of copper, titanium, silicon, or oxygen.

25. The method according to any one of claims 20 to 24, further comprising attaching a plurality of IC dies to the interconnection feature.

Images