Manufacturing method for SOI substrates

Abstract

To reduce defects caused at the wafer bonding interface. [Solution] A method for manufacturing an SOI substrate according to an embodiment of the present invention includes the steps of: forming a stopper layer 111, a semiconductor layer 112, an embedded insulating film 113 and a first bonding insulating layer 114 using SiCN on a sacrificial wafer 110; forming a second bonding insulating layer 124 using SiCN on a reference wafer 120; forming Si-OH bonds in the first and second bonding insulating layers 114 and 124 by O2 plasma treatment and scrubbing of the first and second bonding insulating layers 114 and 124; forming a bonding structure by bonding the sacrificial wafer 110 and the reference wafer 120 so that the first and second bonding insulating layers 114 and 124 are in contact; and annealing the bonding structure.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a SOI substrate, and more particularly, to a method for manufacturing a SOI substrate for improving the bonding strength of a wafer bonding interface.

Background Art

[0002] Direct wafer bonding is a technique that can directly bond two wafers having completely flat surfaces without using an adhesive (such as paste or glue). Such a type of bonding is a technical step commonly used in the manufacture of SOI (Silicon on Insulator) substrates.

[0003] Bonding techniques for joining two wafers (or substrates) without an adhesive cause various defects. For example, defects such as voids generated at the bonding interface, edge voids in the thin film layer of the final structure (i.e., the SOI substrate), and low bonding energy between the bonding interfaces may occur. Such defects may adversely affect the characteristics of semiconductor devices manufactured using the SOI substrate.

[0004] Therefore, when manufacturing a SOI substrate, techniques for suppressing the generation of edge voids in the wafer, suppressing the generation of voids between the bonding interfaces of a group of wafers, and strengthening the bonding strength of the bonding interface are required.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present invention provide a method for manufacturing a SOI substrate that can reduce voids formed at a wafer bonding interface.

[0006] Embodiments of the present invention provide a method for manufacturing a SOI substrate that can improve the bonding strength of a wafer bonding interface.

Means for Solving the Problems

[0007] A method for manufacturing an SOI substrate according to an embodiment of the present invention includes the steps of: forming a first bonding insulating layer on a sacrificial wafer, comprising a stopper layer, a semiconductor layer, an embedded insulating film, and SiCN; forming a second bonding insulating layer on a reference wafer, comprising SiCN; forming Si-OH bonds in the first bonding insulating layer and the second bonding insulating layer by O2 plasma treatment and scrubbing of the first bonding insulating layer and the second bonding insulating layer; forming a bonding structure by bonding the sacrificial wafer and the reference wafer so that the first bonding insulating layer and the second bonding insulating layer are in contact; and annealing the bonding structure. [Effects of the Invention]

[0008] According to embodiments of the present invention, by using SiCN as the wafer bonding insulating layer, when high-temperature annealing is performed after bonding, H2 gas released from the sacrificial wafer (outgassing) can be effectively adsorbed, thereby suppressing the generation of voids at the interface between multiple bonding insulating layers.

[0009] Furthermore, according to embodiments of the present invention, by cleaving Si-C bonds with O2 plasma treatment of SiCN, forming Si-OH bonds by scrubbing, inducing van der Waals hydrogen bonds (Si-OH---OH-Si) between multiple bonding insulating layers, and converting van der Waals hydrogen bonds (Si-OH---OH-Si) to Si-O-Si covalent bonds by annealing, the bonding strength can be strengthened by reducing the bond length and interface gap between multiple bonding insulating layers.

[0010] Furthermore, according to embodiments of the present invention, by injecting helium gas during a set time and then bonding the sacrificial wafer and the reference wafer at room temperature, the generation of wafer edge voids due to the Joule-Thomson effect can be prevented. [Brief explanation of the drawing]

[0011] [Figure 1] This is a sequence diagram showing a method for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 2] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 3] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 4] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 6] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 7] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 9] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view showing a process for manufacturing an SOI substrate according to an embodiment of the present invention. [Modes for carrying out the invention]

[0012] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the examples described below in detail, along with the accompanying drawings. However, the present invention is not limited to the examples disclosed below and can be embodied in a variety of different forms. These examples are provided, however, to ensure that the disclosure of the present invention is complete and that a person with ordinary skill in the art to which the invention belongs can accurately recognize the category of the invention, and the present invention is defined only by the category of the claims. In the figures, the size and relative size of layers and areas may be exaggerated for clarity of explanation. Throughout the specification, the same reference numerals refer to the same components.

[0013] Figure 1 is a sequence diagram showing a method for manufacturing an SOI substrate according to an embodiment of the present invention, and Figures 2 to 10 are cross-sectional view steps showing a method for manufacturing an SOI substrate according to an embodiment of the present invention.

[0014] Referring to Figures 1 and 2, the first processing of the sacrificial wafer 110 can be performed (S10). For example, the first processing may be referred to as the first cleaning step or the first washing step. The sacrificial wafer 110 may include at least one material selected from Si, Ge, SiC, Group IV-IV, Group III-V, or Group II-VI semiconductor compounds, and piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.).

[0015] In the embodiment, the first treatment may include the steps of applying SC1 (NH4OH:H2O2:H2O) to the sacrificial wafer 110 to form an oxide film 110a containing impurities on the surface of the sacrificial wafer 110, and removing the formed oxide film. For example, the H2O2 of SC1 forms an oxide film 110a containing impurities on the surface of the sacrificial wafer 110, and the etching power of NH4OH removes the oxide film 110a containing impurities from the surface of the sacrificial wafer 110 (not shown). This allows for the primary removal of impurities present on the surface of the sacrificial wafer 110.

[0016] At this time, as shown in FIG. 2, impurities in the sacrificial wafer 110 can be removed by the first process, but the chemical oxide film 110b (see FIG. 3) formed by H2O2 in SC1 may remain.

[0017] Referring to FIGS. 1 and 3, a high-temperature H2 heat treatment (H2 Bake) can be performed on the sacrificial wafer 110 (S20). Thereby, the chemical oxide film 110b on the surface of the sacrificial wafer 110 can be removed (not shown). In particular, by effectively removing impurities in the bevel region of the sacrificial wafer 110 by H2 Bake, the generation of dislocation defects due to lattice mismatch can be reduced.

[0018] Referring to FIGS. 1 and 4, a stopper layer 111 and a semiconductor layer 112 can be sequentially formed on the sacrificial wafer 110 using an epitaxial growth method (S30). In an embodiment, the stopper layer 111 and the semiconductor layer 112 can be formed in-situ by an epitaxial growth method.

[0019] The stopper layer 111 can prevent the semiconductor layer 112 from flowing out when the sacrificial wafer 110 is removed in a subsequent process. For this purpose, the stopper layer 111 can be formed using a material having an etching selectivity different from that of the sacrificial wafer 110 and the semiconductor layer 112. Also, the stopper layer 111 can be formed using a material having a small physical property difference from the semiconductor layer 112. In an embodiment, the stopper layer 111 can be a single-crystalline silicon germanium (SiGe) layer, and the semiconductor layer 112 can be a single-crystalline silicon (Si) layer.

[0020] Referring to FIGS. 1 and 5, a buried oxide (BOX) 113 can be formed on the semiconductor layer 112 (S40). For example, the buried oxide film 113 can include a silicon oxide (SiO2) layer, but is not limited thereto.

[0021] Referring to Figures 1 and 6, a first bonding insulating layer 114 and a second bonding insulating layer 124 can be formed on the sacrificial wafer 110 and the reference wafer 120, respectively (S50). In this embodiment, the first bonding insulating layer 114 can be formed in contact with the embedded insulating film 113 of the sacrificial wafer 110, and the second bonding insulating layer 124 can be formed in contact with the surface of the reference wafer 120. The reference wafer 120 may include at least one material selected from Si, Ge, SiC, Group IV-IV, Group III-V, or Group II-VI semiconductor compounds, and piezoelectric materials (e.g., LiNbO3, LiTaO3, etc.).

[0022] For example, forming a first bonding insulating layer 114 on the embedded insulating film 113 of the sacrificial wafer 110, or forming a second bonding insulating layer 124 on the reference wafer 120, can be performed alternately in the same chamber, simultaneously in the same chamber, or simultaneously in different chambers.

[0023] In the examples, the first bonding insulating layer 114 and the second bonding insulating layer 124 may include a silicon carbonitride (SiCN) layer. For example, the first bonding insulating layer 114 and the second bonding insulating layer 124 can each be formed by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method, stabilized by injecting tetramethylsilane (TMS) gas, nitrogen gas, and helium gas, and then subjected to plasma treatment.

[0024] For example, the carbon (C) concentration in the first and second bonding insulating layers 114 and 124 may be 36% or higher, but is not limited to this. The higher the carbon (C) concentration in the first and second bonding insulating layers 114 and 124, the more silicon dangling bonds (Si dangling bonds) formed during the O2 plasma treatment described later will be. As a result, the H2 gas stored in the sacrificial wafer 110 during the H2 Bake process and released (outgassed) during the annealing process will be more effectively adsorbed, thereby suppressing the generation of voids.

[0025] Referring to Figures 1 and 7, O2 plasma treatment can be performed on the first bonding insulating layer 114 and the second bonding insulating layer 124 (S60). For example, after injecting O2 gas into the process chamber, it can be stabilized for a certain period of time (e.g., 30 seconds), and then the first bonding insulating layer 114 and the second bonding insulating layer 124 can be plasma-treated for a time set to 50-400W of HF power (e.g., 10 seconds).

[0026] In this way, by performing O2 plasma treatment on the SiCN of the first and second bonding insulating layers 114 and 124 to remove C from the Si-C bond, the first and second bonding insulating layers 114D and 124D, which have been transformed into silicon dangling bonds (Si dangling bonds), can be formed, as shown in Figure 7.

[0027] Referring to Figures 1 and 8, scrubbing can be performed on the sacrificial wafer 110 and the reference wafer 120 (S70). For example, after performing O2 plasma treatment, particles originating from previous processes may be present on the sacrificial wafer 110 and the reference wafer 120. To remove such particles, the sacrificial wafer 110 and the reference wafer 120 can be subjected to a rinsing process using ultrapure water (DIW) and a drying process using an N2 dryer, respectively, for a certain period of time (e.g., 30 seconds) using a scrubber.

[0028] At this time, the OH group of H2O provided by ultrapure water (DIW) is adsorbed onto the silicon dangling bond of the first and second bonding insulating layers 114D and 124D (see Figure 7), thereby forming the first and second bonding insulating layers 114H and 124H having Si-OH bonds, as shown in Figure 8.

[0029] Referring to Figures 1 and 9, the sacrificial wafer 110 can be bonded onto the reference wafer 120 in the reverse direction (S80).

[0030] For example, the sacrificial wafer 110 is fixed to an upper chuck (not shown) in the reverse direction, and the reference wafer 120 is fixed to a lower chuck (not shown). In this case, the sacrificial wafer 110 and the reference wafer 120 are fixed to the upper and lower chucks, respectively, by vacuum suction.

[0031] In this embodiment, with the sacrificial wafer 110 and the reference wafer 120 fixed to the upper and lower chucks, respectively, helium gas can be injected into the process chamber for a set time (e.g., 35 seconds or more). After the set time has elapsed, the vacuum in the upper chuck to which the sacrificial wafer 110 is fixed is released, separating the sacrificial wafer 110 from the upper chuck, causing it to fall onto the reference wafer 120 and be bonded.

[0032] In this way, by injecting helium gas with a negative Joule-Thomson coefficient for a set time before bonding the sacrificial wafer 110 and the reference wafer 120, the generation of edge voids due to the Joule-Thomson effect can be suppressed.

[0033] Furthermore, as described above, by bonding the sacrificial wafer 110 and the reference wafer 120 such that the first and second bonding insulating layers 114H and 124H, which have Si-OH bonds, are in contact with each other, the first bonding insulating layer 114H and the second bonding insulating layer 124H are bonded together by van der Waals hydrogen bonds (Si-OH---OH-Si) between the Si-OH bonds of the first bonding insulating layer 114H and the Si-OH bonds of the second bonding insulating layer 124H. As a result, a bonding structure can be formed on the reference wafer 120 in which the second bonding insulating layer 124H, the first bonding insulating layer 114H, the embedded insulating film 113, the semiconductor layer 112, the stopper layer 111, and the sacrificial wafer 110 are sequentially arranged, bonded by van der Waals hydrogen bonds (Si-OH---OH-Si).

[0034] Referring to Figures 1 and 10, annealing can be performed on the bonding structure (S90). For example, annealing can be performed at 430°C, but is not limited to this. In the example, by performing annealing at a high temperature, H2O is removed from the van der Waals hydrogen bonds (Si-OH---OH-Si) between the first bonding insulating layer 114H and the second bonding insulating layer 124H, forming Si-O-Si covalent bonds and reducing the bond length. As a result, as shown in Figure 10, the interface gap between the first and second bonding insulating layers 114B and 124B is reduced, thereby strengthening the bond strength.

[0035] Furthermore, in step S20 described above, a high-temperature H2 heat treatment was performed to remove the chemical oxide film on the surface of the sacrificial wafer 110. At this time, while the chemical oxide film is removed, H2 gas is stored within the sacrificial wafer 110. When high-temperature annealing is performed, the H2 gas stored within the sacrificial wafer 110 may be released (outgassed) to bonding interfaces with relatively weak bonding strength (for example, the weak bonding force portion of the joint surface between the first bonding insulating layer and the second bonding insulating layer), potentially forming voids. However, in this embodiment, the released H2 is effectively adsorbed by the N of the SiCN used as the bonding insulating layer, thus preventing the formation of voids at the interface between the bonding insulating layers 114B and 124B.

[0036] As described above, in this embodiment, a bonding insulating layer is formed on each of the sacrificial wafer 110 and the reference wafer 120 using SiCN. Silicon dangling bonds are formed by O2 plasma treatment of the SiCN, and OH is adsorbed onto the silicon dangling bonds during the scrubbing process to form a bonding insulating layer having Si-OH bonds. Such a bonding insulating layer having Si-OH bonds is bonded by van der Waals hydrogen bonds (Si-OH---OH-Si), and during annealing, H2O is detached from the van der Waals hydrogen bonds (Si-OH---OH-Si), forming Si-O-Si covalent bonds. In this way, the bond length is reduced and the interface gap between bonding insulating layers is reduced, thereby strengthening the bonding strength between the bonding insulating layers. In this embodiment, after annealing is completed, the bonding strength between the bonding insulating layers is 1.8 J / m 2 The above are possible, but not limited to them.

[0037] Although not shown in the diagram, once annealing to the bonding structure is complete, the sacrificial wafer 110 and stopper layer 111 can be sequentially removed to complete the manufacturing of the SOI substrate.

[0038] For example, before bonding, a portion of the edge of the sacrificial wafer 110, which is placed at the top of the bonding structure, can be removed by wafer trimming. After bonding and annealing, the sacrificial wafer 110 can be removed by a polishing process to have a set thickness (or height). Thereafter, the remaining sacrificial wafer and stopper layer 111 can be removed sequentially.

[0039] The remaining sacrificial wafer can be removed by wet cleaning and dry cleaning methods. For example, the remaining sacrificial wafer can be removed by a drying process using an IPA dryer after performing a DHF (Dilute HF) pre-treatment cleaning process and a wet alkali (Diluted NH4OH, TMAH:(CH3)4N(OH), KOH, etc.) post-treatment cleaning process in succession. The stopper layer 111 can also be removed by wet cleaning and dry cleaning methods. For example, the stopper layer 111 can be removed by a wet alkali (Diluted NH4OH, TMAH:(CH3)4N(OH), KOH, etc.) cleaning process and a dry cleaning method using a fluorine compound.

[0040] As described above, by sequentially removing the remaining sacrificial wafer and stopper layer 111, the manufacturing of the SOI substrate, which includes the reference wafer 120, the second bonding insulating layer 124 sequentially laminated on the reference wafer 120, the first bonding insulating layer 114, the embedded insulating film 113, and the semiconductor layer 112, can be completed.

[0041] Although the present invention has been described in detail above with reference to preferred embodiments, the present invention is not limited to the above embodiments, and can be modified in various ways by persons with ordinary skill in the art within the scope of the technical idea of ​​the present invention. [Explanation of Symbols]

[0042] 110 Sacrificial wafers 111 Stopper layer 112 Semiconductor layer 113 Embedded insulating film 114 First bonding insulating layer 120 Reference wafers 124 Second bonding insulating layer

Claims

1. The steps include forming a stopper layer, a semiconductor layer, an embedded insulating film, and a first bonding insulating layer using SiCN on a sacrificial wafer, The steps include forming a second bonding insulating layer using SiCN on a reference wafer, O to the first bonding insulating layer and the second bonding insulating layer ２ The steps include forming Si-OH bonds in the first bonding insulating layer and the second bonding insulating layer by plasma treatment and scrubbing, The steps include forming a bonding structure by bonding the sacrificial wafer and the reference wafer so that the first bonding insulating layer and the second bonding insulating layer are in contact, A method for manufacturing an SOI substrate, comprising the step of annealing the bonding structure.

2. A method for manufacturing an SOI substrate according to claim 1, further comprising the step of performing a cleaning process on the sacrificial wafer.

3. The cleaning process described above is: The sacrificial wafer contains SC1(NH ４ OH: H ２ O ２ : H ２ The steps include applying O) to form an oxide film containing impurities on the surface of the sacrificial wafer, and removing the formed oxide film, High temperature H for the sacrificial wafer ２ A method for manufacturing an SOI substrate according to claim 2, comprising the step of removing a chemical oxide film formed on the surface of the sacrificial wafer by heat treatment.

4. The method for manufacturing an SOI substrate according to claim 1, wherein the stopper layer and the semiconductor layer are each formed on the sacrificial wafer by an epitaxial growth method.

5. The stopper layer contains single-crystal silicon germanium (SiGe), The method for manufacturing an SOI substrate according to claim 1, wherein the semiconductor layer includes single-crystal silicon (Si).

6. The step of forming Si-OH bonds in the first bonding insulating layer and the second bonding insulating layer is: The aforementioned O ２ The steps include: transforming the Si-C bonds in the first bonding insulating layer and the second bonding insulating layer into silicon dangling bonds by plasma treatment; H provided by the aforementioned scrub ２ A method for manufacturing an SOI substrate according to claim 1, comprising the step of using O to adsorb OH onto the silicon dangling bond.

7. The step of forming the bonding structure is: The steps include fixing the sacrificial wafer in the upper chuck in the reverse direction, The steps include fixing the reference wafer to the lower chuck, The process involves injecting He gas into the bonding chamber for a set period of time, A method for manufacturing an SOI substrate according to claim 1, comprising the step of separating the sacrificial wafer from the upper chuck so that the sacrificial wafer is bonded onto the reference wafer when the set time has elapsed.

8. The above-mentioned O ２ The plasma treatment is carried out by injecting O gas into the process chamber, stabilizing it for a certain period of time, and then applying 50 to 400 W of HF power for a set time. The method for manufacturing an SOI substrate according to claim 1 ２ ​

9. The first and second bonding insulating layers using SiCN are, Formed by the PECVD (Plasma Enhanced Chemical Vapor Deposition) method, A method for producing an SOI substrate according to claim 1, comprising stabilizing the substrate by injecting tetramethylsilane (TMS) gas, nitrogen gas, and helium gas, and then performing plasma treatment.

10. The method for manufacturing an SOI substrate according to claim 1, wherein the carbon (C) concentration in the SiCN is 36% or more.

11. A method for manufacturing an SOI substrate according to claim 1, further comprising the step of sequentially removing the sacrificial wafer and the stopper layer from the bonding structure after the step of annealing the bonding structure.

12. The method for manufacturing an SOI substrate according to claim 11, wherein the sacrificial wafer and the stopper layer are removed by a wet cleaning method and a dry cleaning method, respectively.

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