Package Laminate

Abstract

We provide a package laminate. [Solution] An embodiment of the present invention provides a package laminate 100 comprising a carrier board 110, a plurality of conductive pillars 120, a semiconductor element 150, a plurality of electronic elements 130, and a first encapsulant 140. An electronic element placement area 111b and a conductive pillar placement area 111c are defined on the surface of the carrier board 110, with the conductive pillar placement area 111c located between the electronic element placement area 111b and the surface edge 111a. The plurality of conductive pillars 120 are installed only in the conductive pillar placement area 111c and are used to electrically connect the carrier board 110 and the semiconductor element 150. The first encapsulant 140 is located between the carrier board 110 and the semiconductor element 150 and is used to support the semiconductor element 150 and to seal the plurality of conductive pillars 120 and the plurality of electronic elements 130.

Description

Technical Field

[0001] The present invention relates to a package laminate, and more particularly to a package laminate that increases electrical functions.

Summary of the Invention

Problems to be Solved by the Invention

[0002] Due to the increasing demand for increased electrical functions and thinner and smaller sizes of electronic products, there is an urgent need to reduce the size of the package structure. For this reason, installing a plurality of electronic elements with different electrical functions on a carrier board with limited usable space has become a problem that must be solved in conventional package structure technology.

[0003] The present invention has been made through the intensive research of the inventor in view of the above problems, and its purpose is to enable the installation of electronic elements in the space between the carrier board and the semiconductor element so that the electrical function of the package laminate is improved based on the demand for electrical characteristics.

Means for Solving the Problems

[0004] To achieve the above objective, a package laminate according to one aspect of the present invention comprises a carrier board, a plurality of conductive pillars, a semiconductor element, a plurality of electronic elements, and a first encapsulant. The first surface of the carrier board has a plurality of edges, and an electronic element placement region and a conductive pillar placement region are defined on the surface, with the conductive pillar placement region located only between one edge and the electronic element placement region. The plurality of conductive pillars are installed only in the conductive pillar placement region, each having a first end, and each of the first ends of each conductive pillar is electrically connected to the carrier board. The second surface of the semiconductor element faces the first surface, and a first junction region and a second junction region are defined. The second end of each conductive pillar is bonded to the first junction region so as to be electrically connected to the semiconductor element. The second junction region is located above the electronic element placement region, and a space is formed between the second junction region and the electronic element placement region, with the plurality of electronic elements installed in the electronic element placement region where the plurality of conductive pillars are not installed, and also located in the space. The first encapsulant is placed between the carrier board and the semiconductor element, covers the plurality of conductive pillars and the plurality of electronic elements located in the space, and is used to support the second junction region that is not bonded to the plurality of conductive pillars. [Effects of the Invention]

[0005] As the present invention is configured as described above, it produces the following effects. The conductive pillar placement region of the carrier board is located only between one edge and the electronic element placement region, and multiple conductive pillars are placed only in the conductive pillar placement region so that a space is formed between the electronic element placement region of the carrier board and the second junction region of the semiconductor element. The electrical functionality of the package stack is improved by allowing multiple electronic elements to be placed in the space based on the requirements of the electrical properties.

[0006] The following information will become clear from the description in the specification and drawings described later. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing a carrier board according to one embodiment of the present invention. [Figure 2A] This is a plan view showing a carrier board according to one embodiment of the present invention. [Figure 2B] This is a plan view showing a carrier board according to one embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view showing conductive pillars and electronic components attached to a carrier board. [Figure 4A] This is a schematic plan view showing conductive pillars and electronic components mounted on a carrier board. [Figure 4B] This is a schematic plan view showing conductive pillars and electronic components mounted on a carrier board. [Figure 5A] This is a schematic cross-sectional view showing a first sealing material according to one embodiment of the present invention sealing a conductive pillar and an electronic element. [Figure 5B] This is a schematic cross-sectional view showing a first sealing material according to one embodiment of the present invention sealing a conductive pillar and an electronic element. [Figure 6] This is a schematic cross-sectional view showing a semiconductor element according to one embodiment of the present invention bonded to a conductive pillar. [Figure 7A] This is a schematic cross-sectional view showing a package laminate according to one embodiment of the present invention. [Figure 7B] This is a schematic cross-sectional view showing a package laminate according to one embodiment of the present invention. [Figure 8A] This is a schematic cross-sectional view showing a package laminate according to one embodiment of the present invention. [Figure 8B] This is a schematic cross-sectional view showing a package laminate according to one embodiment of the present invention. [Figure 9A] This is a schematic cross-sectional view showing a package laminate according to one embodiment of the present invention. [Figure 9B] This is a schematic cross-sectional view showing a package laminate according to one embodiment of the present invention. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described in detail below. However, the present invention is not limited thereto, and various modifications are possible within the scope described. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of the present invention.

[0009] First, an example of a specific embodiment of the package laminate of the present invention will be described with reference to the drawings.

[0010] The package laminate 100 of the present invention comprises a carrier board 110, a plurality of conductive pillars 120, a plurality of electronic elements 130, a first encapsulant 140, and a semiconductor element 150 (see Figure 6). In one embodiment, the package laminate 100 further includes a second encapsulant 160 and a heat dissipation layer 170 (see Figures 8A and 8B). In another embodiment, the package laminate 100 further comprises a second encapsulant 160 and an electromagnetic shield 180 (see Figures 9A and 9B).

[0011] In this case, as shown in Figures 1, 2A, 2B, and 6, the first surface 111 of the carrier board 110 has a plurality of edges 111a, and the first surface 111 has at least one electronic element placement area 111b and a conductive pillar placement area 111c defined, the conductive pillar placement area 111c being located only between one edge 111a and the electronic element placement area 111b. The plurality of conductive pillars 120 are installed only in the conductive pillar placement area 111c, the first end 121 of each conductive pillar 120 is electrically connected to the carrier board 110, and the plurality of conductive pillars 120 are arranged in the conductive pillar placement area 111c along one direction. Multiple conductive pillars 120 are arranged in the conductive pillar arrangement region 111c along direction Y (see Figure 4A), and multiple conductive pillars 120 are arranged in the conductive pillar arrangement region 111c along another direction X (see Figure 4B).

[0012] As shown in Figure 6, the second surface 151 of the semiconductor element 150 is oriented toward the first surface 111 of the carrier board 110, and a first junction region 151a and a second junction region 151b are defined on the second surface 151. The second end 122 of each conductive pillar 120 is bonded to the first junction region 151a so as to be electrically connected to the semiconductor element 150. In this embodiment, the first junction region 151a is adjacent to the edge 151c of the second surface 151, located between the second junction region 151b and the edge 151c, and located above the conductive pillar arrangement region 111c. The second junction region 151b is located above the electronic element arrangement region 111b, and a space S is formed between the second junction region 151b and the electronic element arrangement region 111b.

[0013] As shown in Figure 6, the multiple electronic elements 130 are installed in the electronic element placement region 111b and are located in space S. The first encapsulant 140 is filled between the carrier board 110 and the semiconductor element 150, and the multiple conductive pillars 120 and the multiple electronic elements 130 located in space S are covered by the first encapsulant 140. The first encapsulant 140 is used to support the second junction region 151b that is not joined to the multiple conductive pillars 120.

[0014] Figures 1 to 9B are schematic diagrams showing a method for manufacturing a package laminate 100 according to one embodiment of the present invention. In the example of Figure 1, first, a carrier A is provided, which may be selected from a wafer, a circuit board, or a glass substrate, and the carrier A may be mounted on adhesive tape (not shown) to carry out subsequent processes. The carrier A comprises a plurality of interconnected carrier boards 110, each carrier board 110 having a first surface 111 with a plurality of edges 111a, and the first surface 111 has defined electronic element placement areas 111b and conductive pillar placement areas 111c. The conductive pillar placement area 111c is located only between one edge 111a and the electronic element placement area 111b (see Figure 2A or Figure 2B).

[0015] In this case, as shown in FIGS. 3, 4A, and 4B, a plurality of conductive pillars 120 are installed in the conductive pillar arrangement region 111c, and a plurality of electronic elements 130 are installed in the electronic element arrangement region 111b. Each conductive pillar 120 is electrically connected to the carrier board 110 via the first end portion 121. The material of the plurality of conductive pillars 120 may be copper, but the present invention is not limited thereto. The plurality of electronic elements 130 are electrically connected to the carrier board 110. As the plurality of electronic elements 130, chips, filters, passive elements, etc. may be selected, and different electronic elements may be installed based on the requirements of electrical characteristics.

[0016] The plurality of conductive pillars 120 are arranged in the conductive pillar arrangement region 111c along one direction. As shown in FIG. 4A, the plurality of conductive pillars 120 are arranged in the conductive pillar arrangement region 111c along the direction Y, and as shown in FIG. 4B, the plurality of conductive pillars 120 are arranged in the conductive pillar arrangement region 111c along the direction X. Based on the requirements of electrical characteristics, a plurality of electronic elements 130 may be installed in the electronic element arrangement region 111b where the plurality of conductive pillars 120 are not installed.

[0017] As shown in FIG. 5A, the plurality of conductive pillars 120 and the plurality of electronic elements 130 are sealed by the first sealing material 140, and the second end portion 122 of each conductive pillar 120 is covered by the first sealing material 140. Next, the first sealing material 140 is ground so that the second end portion 122 is exposed. As shown in FIG. 5B, in another embodiment, the plurality of conductive pillars 120 and the plurality of electronic elements 130 are sealed by the first sealing material 140, but the second end portion 122 is not covered by the first sealing material 140.

[0018] As shown in Figure 6, the semiconductor element 150 is provided, and the semiconductor element 150 is bonded to the second end 122 of each conductive pillar 120, and a first junction region 151a and a second junction region 151b are defined on the second surface 151 of the semiconductor element 150. The second surface 151 of the semiconductor element 150 is oriented toward the first surface 111 of the carrier board 110, and the second end 122 of each conductive pillar 120 is bonded to the first junction region 151a so as to be electrically connected to the plurality of conductive pillars 120 and the semiconductor element 150. A space S is formed between the second junction region 151b and the electronic element placement region 111b, and the space S is used to install the plurality of electronic elements 130 and the first encapsulant 140. The second junction region 151b that is not bonded to the plurality of conductive pillars 120 may be supported, except that the plurality of conductive pillars 120 and the plurality of electronic elements 130 are covered by the first encapsulant 140.

[0019] As shown in Figure 7A, the semiconductor element 150 is sealed by the second encapsulant 160. In this embodiment, the other surface 152 of the semiconductor element 150 is covered by the second encapsulant 160, and then a heat dissipation layer 170 used for heat dissipation is formed on the second encapsulant 160. Finally, a cutting process is performed to separate the multiple package stacks 100 (see Figure 8A).

[0020] As shown in Figure 7B, the semiconductor element 150 is sealed by the second encapsulant 160, and the surface 152 of the semiconductor element 150 is covered. In this embodiment, the second encapsulant 160 may be ground down so that the surface 152 is exposed, and then the heat dissipation layer 170 is placed on the surface 152 of the semiconductor element 150. Finally, a cutting process is performed to separate the multiple package stacks 100 (see Figure 8B).

[0021] As shown in Figure 9A, in another embodiment, after the semiconductor element 150 is sealed with the second encapsulant 160, a cutting process is first performed to separate the multiple package stacks 100, and then an electromagnetic shield 180 is formed on each package stack 100. The electromagnetic shield 180 covers the side walls 141 of the second encapsulant 160 and the first encapsulant 140 and is electrically connected to the carrier board 110.

[0022] As shown in Figure 9B, after the semiconductor element 150 is sealed with the second encapsulant 160, the second encapsulant 160 may be ground so that the surface 152 is exposed. Next, a cutting process is performed to separate the multiple package stacks 100, and then an electromagnetic shield 180 is formed on each package stack 100. In this embodiment, the electromagnetic shield 180 covers the second encapsulant 160, the surface 152 of the semiconductor element 150, and the side wall 141 of the first encapsulant 140, and is electrically connected to the carrier board 110.

[0023] The conductive pillar placement region 111c of the carrier board 110 is located only between one edge 111a and the electronic element placement region 111b, and the multiple conductive pillars 120 are installed only in the conductive pillar placement region 111c. This increases the area of ​​the electronic element placement region 111b of the carrier board 110, and a space S is formed between the electronic element placement region 111b of the carrier board 110 and the second junction region 151b of the semiconductor element 150. Multiple electronic elements 130 may be installed in the space S based on the demands of electrical characteristics in order to improve the electrical function of the package laminate 100.

[0024] The present invention is not limited to the embodiments described above, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0025] 100-package stack 110 Carrier Board 111 Page 1 111a Edge 111b Electronic device placement area 111c Conductive pillar placement area 120 conductive pillars 121 First end 122 Second end 130 Electronic Elements 140 First sealing material 141 Side wall 150 semiconductor devices 151 2nd page 151a 1st joint area 151b 2nd junction area 151c Edge 152 Surface 160 Second sealing material 170 Heat dissipation layer 180 Electromagnetic Shielding A Career S space X direction Y direction

Claims

1. A carrier board having a first surface having multiple edges and defining an electronic element placement area and a conductive pillar placement area, wherein the conductive pillar placement area is located only between one of the edges and the electronic element placement area, A plurality of conductive pillars are installed only in the conductive pillar arrangement region, each having a first end, and each first end being electrically connected to the carrier board. A semiconductor element having a second surface facing the first surface and on which a first junction region and a second junction region are defined, wherein the second end of each conductive pillar is joined to the first junction region so as to be electrically connected to the semiconductor element, the second junction region is located above the electronic element arrangement region, and a space is formed between the second junction region and the electronic element arrangement region. Multiple conductive pillars are installed in the electronic element placement region where none are installed, and multiple electronic elements are located in the space, A package laminate characterized by comprising: a first sealing material installed between the carrier board and the semiconductor element, covering the plurality of conductive pillars and the plurality of electronic elements located in the space, and supporting the second bonding region not bonded to the plurality of conductive pillars.

2. The package laminate according to claim 1, characterized in that the plurality of conductive pillars are arranged in the conductive pillar arrangement region along one direction.

3. The package laminate according to claim 1 or 2, further comprising a second sealing material and a heat dissipation layer, wherein the semiconductor element is sealed by the second sealing material, and the heat dissipation layer is formed on the second sealing material.

4. The package laminate according to claim 3, characterized in that the surface of the semiconductor element is exposed from the second sealing material, and the heat dissipation layer is formed on the surface of the semiconductor element.

5. The package laminate according to claim 1 or 2, further comprising a second encapsulant and an electromagnetic shield, wherein the semiconductor element is sealed by the second encapsulant, the side walls of the second encapsulant and the first encapsulant are covered by the electromagnetic shield, and the electromagnetic shield is electrically connected to the carrier board.

6. The package laminate according to claim 5, characterized in that the surface of the semiconductor element is exposed from the second sealing material, and the surface of the semiconductor element is covered by the electromagnetic shield.

7. The package laminate according to claim 1, characterized in that the first bonding region is adjacent to the edge of the second surface, located between the second bonding region and the edge, and located above the conductive pillar arrangement region.

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