Structural improvements to semiconductor memory package units
The integration of a redistribution layer with a dielectric layer and conductive wires addresses the challenges of dense wiring in semiconductor memory package units, enhancing design flexibility and reliability while reducing costs.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- WALTON ADVANCED ENG INC
- Filing Date
- 2025-12-17
- Publication Date
- 2026-06-30
AI Technical Summary
Conventional semiconductor memory package units face issues with dense wiring layouts that complicate design, increase manufacturing costs, and reduce product reliability and yield rates due to uncertain soldering.
Incorporating a redistribution layer (RDL) with a dielectric layer and conductive wires between the die and insulating layer, allowing for flexible wiring layouts and connections to the outside through rearranged conductive wires.
The RDL process enhances design flexibility, reduces manufacturing costs, and improves soldering success and product reliability by avoiding excessive wire density.
Smart Images
Figure 2026108597000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor memory package unit, and particularly relates to a structural improvement for adding at least one redistribution layer (RDL) on a die package of the semiconductor memory package unit.
Background Art
[0002] FIGS. 8 to 11 are schematic views of each part of a well-known standardized structure in a conventional semiconductor memory package unit 1a. What is included in the semiconductor memory package unit 1a is The assembly consists of one die package 10a, a plurality of first connectors 40a, and one substrate 50a. The die package 10a contains one die 11a and one insulating layer 30a. The die 11a has one first surface 12a, and on the first surface 12a, a plurality of die pads 13a. The insulating layer 30a is located on the die 11a and is formed to cover the die 11a. The insulating layer 30a has one first surface 31a and a plurality of first openings 32a, and a copper column 321a can be installed in each of the first openings 32a, which each of the die pads 13a of the die 11a uses to make an electrical connection with the outside. A portion of each first connector 40a is provided within each of the first openings 32a of the insulating layer 30a, and each first connector 40a forms an electrical connection with each of the die pads 13a of the die 11a via each of the copper columns 321a. The substrate 50a is located on the first surface 31a and each of the first connectors 40a of the insulating layer 30a, and it has one first surface 51a and one opposing second surface 52a, the first surface 51a having one first protective layer 53a and the second surface 52a having one second protective layer 54a. On the first protective layer 53a, there are a plurality of second openings 55a, each of which has a first wiring 56a, each of which is used for electrical connection to the outside. Each of which has an first wiring 56a is electrically connected to the outside via a second connector 60a (e.g., a solder ball). On the second protective layer 54a, there are a plurality of third openings 57a, each of which has a second wiring 58a. A portion of each first connector 40a is provided within each third opening 57a, and each first connector 40a forms an electrical connection with each second wiring 58. Between each first wiring 56a and each second wiring 58a, there is a conductive pillar 59a, and each conductive pillar 59a forms an electrical connection with each first wiring 56a and each second wiring 58a. To clearly illustrate the structural relationships between the components, each die pad 13a, each first opening 32a, each copper pillar 321a, each first connector 40a, each second opening 55a, each first wiring 56a, each third opening 57a, each second wiring 58a, and each conductive pillar 59a shown in Figure 8 are each shown as one or one example.
[0003] The thicknesses of the standardized structure of the conventional semiconductor memory package unit 1a shown in Figure 8 are as follows: the thickness of each copper pillar 321a is 50 μm, the thickness of each first connector 40a is 20 μm, the thickness of the first protective layer 53a is 30 μm, the thickness of each second wiring 58a is 25 μm, the thickness of each conductive pillar 59a is 75 μm, the thickness of the substrate 50a is 75 μm, the thickness of each first wiring 56a is 25 μm, and the thickness of the solder ball connector formed on each first wiring 56a for external connection is 350 μm.
[0004] Figure 9 shows a top view (chip side up) of the die package 10a, where the chip size is 9963um × 7498um, the smallest die pad 13a on the die 11a has a minimum pad size of 50um × 60um, and the minimum spacing between each die pad 13 is 30um.
[0005] Figure 10 shows a top view (SBT Top View) of the substrate 50a. The layout area (POD) is 11000um × 9000um, the minimum spacing between each second wiring 58a on the second surface 52a is 30um, the minimum line width of each second wiring 58a is 30um, the laser size is 200um, and the laser pad size is 100um.
[0006] Figure 11 shows a bottom view (SBT Bottom View) of the substrate 50a. The minimum spacing between each first wiring 56a on the first surface 51a of the substrate 50a is 30um, the minimum line width of each first wiring 56a is 30um, the number of solder balls to be installed is 78, the size of the solder balls forming electrical connections with each first wiring 56a is 500um, and the minimum ball pitch between each solder ball is 800um.
[0007] As can be seen above, the standardized structure of conventional semiconductor memory package units 1a has the following drawbacks and problems: As shown in Figure 9, the wiring layout on the die package 10a is excessively dense, making design difficult; as shown in Figure 10, the wiring layout on the substrate 50a that forms an electrical connection with the die package 10a is also relatively dense; and as shown in Figure 11, the same problem occurs on the second surface 52a that makes an electrical connection to the outside of the substrate 50a, resulting in a relative increase in the manufacturing cost of the substrate (e.g., printed circuit board). In addition, excessively dense wiring not only makes design difficult and increases manufacturing costs, but also leads to problems such as a relative decrease in product reliability and yield rate due to uncertain soldering. [Prior art documents] [Patent Documents]
[0008] [Patent Document 1] Japanese Patent Publication No. 2000-138262 [Overview of the project] [Problems that the invention aims to solve]
[0009] The main objective of the present invention is to provide an improved structure for a semiconductor memory package unit. The semiconductor memory package unit includes one die package, a plurality of first connectors, and one substrate. The die package includes one redistribution layer (RDL), which has one dielectric layer and a plurality of conductive wires, each of which forms an electrical connection with a plurality of die pads on the die in the die package. By utilizing the RDL process to improve the layout design space for each external conductive wire on the die package, and further forming the semiconductor memory package unit by molding, the spacing between each wire is increased, effectively solving the shortcomings and problems caused by the standardized structure of conventional semiconductor memory package units. [Means for solving the problem]
[0010] To solve the above-mentioned objectives, the present invention provides an improvement in the structure of a semiconductor memory package unit. The semiconductor memory package unit includes one die package, a plurality of first connectors, and one substrate. The die package includes one die and one insulating layer, the die having one first surface and a plurality of die pads on the first surface. The insulating layer is located on and covers the die. The insulating layer has one first surface and a plurality of first openings, each of which is used to electrically connect each die pad of the die to the outside.
[0011] A portion of each of the first connectors is provided within each of the first openings in the insulating layer, and each of the first connectors further forms an electrical connection with each of the die pads of the die.
[0012] The substrate is located on the first surface of the insulating layer and on each of the first connectors. The substrate has one first surface and one opposing second surface, the first surface of the substrate has one first protective layer, and the second surface of the substrate has one second protective layer. On the first protective layer, there are a plurality of second openings, each of which has one first wiring, and each first wiring is used to make an electrical connection with the outside. On the second protective layer, there are a plurality of third openings, each of which has one second wiring. A portion of each of the first connectors is provided in each of the third openings, and each of the first connectors further forms an electrical connection with each of the second wirings. There is a conductive pillar between each of the first wirings and each of the second wirings, and each conductive pillar forms an electrical connection with each of the first wirings and each of the second wirings.
[0013] The semiconductor memory package unit further has a redistribution layer formed using a redistribution layer (RDL) process. The redistribution layer is provided between the die and the insulating layer and is covered by the insulating layer. The RDL has a dielectric layer and a plurality of conductive wires. The dielectric layer has a first surface, which is positioned on the first surface of the die. The dielectric layer has a plurality of recesses, each of which can expose each die pad of the die to the outside. Each of the conductive wires is provided within each recess, and each conductive wire forms an electrical connection with each die pad. Each of the conductive wires is made of a metallic material.
[0014] The die of the semiconductor memory package unit is electrically connected to the outside via, in order, each die pad, each conductive wiring, each first connector, each second wiring, each conductive pillar, and each first wiring.
[0015] In one best embodiment of the present invention, each conductive wire exposed to the outside through each first opening is soldered to the outside using a solder ball. Simultaneously with soldering, the solder ball forms each first connector within each first opening and each third opening.
[0016] In one best embodiment of the present invention, the first wiring of each second opening on the substrate is soldered to the outside using a solder ball. After soldering, the solder ball forms a second connector on the first wiring of each second opening.
[0017] In one best embodiment of the present invention, the thickness of each die pad is 2 μm, the thickness of the dielectric layer is 10 μm, the thickness of each conductive wiring is 10 μm, the thickness of each first connector is 50 μm, the thickness of the substrate is 135 μm, the thickness of the first protective layer is 30 μm, the thickness of the second protective layer is 30 μm, the thickness of the first wiring is 25 μm, the thickness of the second wiring is 25 μm, the thickness of each conductive pillar is 75 μm, and the thickness of each second connector is 350 μm.
[0018] In one best embodiment of the present invention, each of the conductive wirings is made of silver (Ag). Each of the first wirings, each of the second wirings, and each of the conductive pillars are made of copper (Cu).
[0019] In one best embodiment of the present invention, the semiconductor memory package unit is further mounted on a printed circuit board (PCB).
[0020] In one best embodiment of the present invention, the memory types of the semiconductor memory package unit include dynamic random-access memory (DRAM), static random-access memory (SRAM), and synchronous dynamic random-access memory (SDRAM). [Effects of the Invention]
[0021] This invention allows for greater diversification of the layout design between the external connections of each conductive wire by forming each die pad using an RDL process and making electrical connections to the outside through rearranged conductive wires. Furthermore, because the wiring layout space on the die package is relatively flexible and easy to design, the wiring layout on the substrate that forms electrical connections with the die package is also relatively flexible and easy to design, which is advantageous in reducing manufacturing costs on the manufacturing side. Moreover, because the wiring layout on the die package is relatively flexible and avoids excessive density between wires, it is advantageous in ensuring the success of the soldering process and improving product reliability and yield rate. [Brief explanation of the drawing]
[0022] [Figure 1] This is a side cross-sectional view of the semiconductor memory package unit of the present invention. [Figure 2] This is a side cross-sectional view showing the connection between the die package and the substrate of the present invention. [Figure 3] The figure is a side cross-sectional view of the semiconductor memory package unit of the present invention where solder balls are installed. [Figure 4] The figure is a top plan view of the first surface of the insulating layer of the die package of the present invention. [Figure 5] The figure is a partial enlarged view of FIG. 4. [Figure 6] The figure is a top plan view of the second surface of the substrate of the present invention. [Figure 7] The figure is a partially enlarged portion of FIG. 6. [Figure 8] The figure is a side cross-section of a conventional semiconductor memory package unit. [Figure 9] The figure is a top plan view of the first surface of the insulating layer of a conventional die package. [Figure 10] The figure is a top plan view of the second surface of a conventional substrate. [Figure 11] The figure is a top plan view of the first surface of a conventional substrate.
Embodiments for Carrying Out the Invention
[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure, the same or corresponding parts are denoted by the same reference numerals, and in the description of the present embodiment, the description of the same or corresponding parts will be appropriately omitted or simplified.
Examples
[0024] FIG. 1 shows an improvement in the structure of the semiconductor memory package unit provided by the present invention. The semiconductor memory package unit 1 includes one die package 10, a plurality of first connectors 40, and one substrate. The die package 10 is combined with the substrate 50 through each of the first connectors 40 to constitute the semiconductor memory package unit 1.
[0025] [[ID=4...]] Referring to Figure 1, the die package 10 includes one die 11, one redistribution layer (RDL) 20, and one insulating layer 30. The die 11 has one first surface 12, and on this first surface 12, there are a plurality of die pads 13. The RDL 20 is formed using an RDL process, and is provided between the die 11 and the insulating layer 30, and is covered by the insulating layer 30. The RDL 20 has one dielectric layer 21 and a plurality of conductive wirings 22. The dielectric layer 21 has one first surface 211, and this first surface 211 of the dielectric layer 21 is positioned correspondingly on the first surface 12 of the die 11. The dielectric layer 21 has a plurality of recesses 212, each of which allows each of the die pads 13 of the die 11 to be exposed to the outside. Each conductive wire 22 is provided within each recess 212, and each conductive wire 22 forms an electrical connection with each die pad 13. Each conductive wire 22 is made of a metallic material. The insulating layer 30 is located on and covers the die 11. The insulating layer 30 has one first surface 31 and a plurality of first openings 32, each of which is used to electrically connect each die pad 13 of the die 11 to the outside.
[0026] Referring to Figure 1, a portion of each first connector 40 is provided within each first opening 32 of the insulating layer 30, and each first connector 40 further forms an electrical connection with each die pad 13 of the die 11.
[0027] Referring to Figure 1, the substrate 50 is located on the first surface 31 of the insulating layer 30 and on each of the first connectors 40. The substrate 50 has one first surface 51 and one opposing second surface 52, the first surface 51 of the substrate 50 has one first protective layer 53, and the second surface 52 of the substrate 50 has one second protective layer 54. On the first protective layer 53, there are a plurality of second openings 55, each of which has one first wiring 56, and each first wiring is used to make an electrical connection to the outside. On the second protective layer 54, there are a plurality of third openings 57, each of which has one second wiring 58. A portion of each of the first connectors 40 is located within each of the third openings 57, and each of the first connectors 40 further forms an electrical connection with each of the second wirings 58. There is a conductive pillar 59 between each of the first wiring 56 and each of the second wiring 58, and each conductive pillar 59 forms an electrical connection with each of the first wiring 56 and each of the second wiring.
[0028] Referring to Figure 1, the die 11 of the semiconductor memory package unit 1 is electrically connected to the outside via, in order, the die pad 13, the conductive wiring 22, the first connector 40, the second wiring 58, the conductive pillar 59, and the first wiring 56.
[0029] To simplify the content of the diagram and to more clearly explain the structural relationships between each component, each die pad 13, each first opening 32, each first connector 40, each second opening 55, each first wiring 56, each third opening 57, each second wiring 58, and each conductive pillar 59 shown in Figure 1 are shown as one or one example, but this does not limit the present invention.
[0030] Referring to Figure 2, each conductive wire 22 exposed to the outside through each first opening 32 is soldered to the outside using a solder ball 41. Also, as shown in Figure 1, the solder ball 41 simultaneously forms each first connector 40 within each first opening 32 and each third opening 57.
[0031] Referring to Figure 3, the first wiring 56 of each second opening 55 of the substrate 50 is soldered to the outside using solder balls 61. Also, as shown in Figure 1, after soldering, the solder balls 61 form a second connector 60 on each first wiring 56 of the second opening 55. The thickness of each of the second connectors 60 is 350 μm, as shown in Figure 1.
[0032] The thickness of each component on the semiconductor memory package unit 1 is as follows, but is not limited thereto. As shown in Figure 3, the thickness of each die pad 13 is 2 μm; as shown in Figure 2, the thickness of the dielectric layer 21 is 10 μm; as shown in Figure 2, the thickness of the conductive wiring 22 is 10 μm; as shown in Figure 3, the thickness of each first connector 40 is 50 μm; as shown in Figure 2, the thickness of the substrate 50 is 135 μm; as shown in Figure 3, the thickness of the first protective layer 53 is 30 μm; as shown in Figure 3, the thickness of the second protective layer 54 is 30 μm; as shown in Figure 2, the thickness of the first wiring 56 is 25 μm; as shown in Figure 2, the thickness of the second wiring 58 is 25 μm; and as shown in Figure 2, the thickness of each conductive pillar 59 is 75 μm.
[0033] Referring to Figure 1, each conductive wire 22 is made of silver (Ag). Each of the first wires 56, each of the second wires 58, and each of the conductive pillars 59 are made of copper (Cu).
[0034] Referring to Figure 1, the semiconductor memory package unit 1 is further mounted on a printed circuit board 2 (PCB).
[0035] Referring to Figure 1, the memory types of the semiconductor memory package unit 1 include dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM).
[0036] Referring to Figure 4, the die size of the die package 10 is 9963um × 7498um, the minimum dimensions of the external connection portion (so-called solder pad) of each conductive wiring 22 are 60um × 149.8um, the minimum spacing (die pad to die pad) between the external connection portions (so-called solder pads) of each conductive wiring 22 is 20um, the minimum line width of each conductive wiring 22 is 40um, the die alignment parameter (L2F-DIE Align.) is 5um, the size of the solder balls that form an electrical connection with each conductive wiring 22 is 170um, the number of solder balls to be installed is 90, and the minimum spacing (min. ball pitch) between each solder ball is 300um.
[0037] Referring to Figure 5, the layout area (POD) of the substrate 50 is 11000um × 9000um, the minimum spacing between each of the second wirings 58 on the upper surface of the second surface 52 is 70um, the minimum line width of each of the second wirings 58 is 70um, the laser size is 127um, and the laser pad size is 250um.
[0038] According to current semiconductor memory package unit manufacturing practices, the manufacturing cost of some components (e.g., printed circuit boards) in the existing standardized structure of conventional semiconductor memory package units is approximately $0.60. The manufacturing cost of some related components (e.g., the RDL20 and PCB2) corresponding to the semiconductor memory package unit 1 of the present invention is estimated by the applicant to be approximately $0.30. Thus, although the production of the RDL20 is increased in the present invention, it is approximately half the price in comparison.
[0039] The method for manufacturing the semiconductor memory package unit 1 includes the following steps:
[0040] Step S1: Provide a die 11 as shown in Figure 1. The die 11 has a first surface 12 and a plurality of die pads 13 on the first surface 12.
[0041] Step S2: As shown in Figure 1, an RDL 20 is provided on the first surface 11 of the die 11 using the RDL process. The RDL 20 has one dielectric layer 21 and a plurality of conductive wirings 22. The dielectric layer 21 has one first surface 211, which is positioned on the first surface 12 of the die 11. The dielectric layer 21 has a plurality of recesses 212, each of which allows each of the die pads 13 of the die 11 to be exposed to the outside. Each of the conductive wirings 22 is provided within each recess 212, and each of the conductive wirings 22 forms an electrical connection with each of the die pads 13.
[0042] Step S3: An insulating layer 30 is placed on the die 11 and the RDL 20, the insulating layer 30 covering both the die 11 and the RDL 20, thereby forming a die package 10. The insulating layer 30 has one first surface 31 and a plurality of first openings 32, each of which is used to electrically connect each die pad 13 of the die 11 to the outside.
[0043] Step S4: Provide a substrate 50 as shown in Figure 1. The substrate 50 has a first surface 51 and an opposing second surface 52, the first surface 51 of the substrate 50 has a first protective layer 53, and the second surface 52 of the substrate 50 has a second protective layer 54. On the first protective layer 53, there are a plurality of second openings 55, each of which has a first wiring 56, and each of which is used to make an electrical connection to the outside. On the second protective layer 54, there are a plurality of third openings 57, each of which has a second wiring 58. There is a conductive pillar 59 between each of the first wirings 56 and each of the second wirings 58, and each of the conductive pillars 59 forms an electrical connection with each of the first wirings 56 and each of the second wirings.
[0044] Step S5: As shown in Figure 2, the die package 10 and the substrate 50 are integrated by forming an electrical connection using a plurality of solder balls 40a. As shown in Figure 1, after soldering, each solder ball 40a forms a plurality of first connectors 49 between the die package 10 and the substrate 50, thereby constituting a single semiconductor memory package unit 1. A portion of each first connector 40 is provided within each first opening 32 of the insulating layer 30, and each first connector 40 forms an electrical connection with each die pad 13 of the die 11. A portion of each first connector 40 is provided within each third opening 57, and each first connector 40 further forms an electrical connection with each second wiring 58. The die 11 of the semiconductor memory package unit 1 is electrically connected to the outside via each die pad 13, each conductive wiring 22, each first connector 40, each second wiring 58, each conductive pillar 59, and each first wiring 56, in order.
[0045] As can be seen from step S2 above, the RDL20 is formed by horizontally stretching it onto the surface of the die 11 using the RDL process. Since the RDL20 is a process that is easy to implement precisely, the process can be simplified, and while the RDL20 undergoes electrical stretching and interconnection in the XY plane, the completed semiconductor memory package unit 1 can maintain or achieve a certain degree of specific effects in terms of weight reduction, thinning, and miniaturization.
[0046] The semiconductor memory package unit 1 of the present invention has the following advantages when compared to a conventional semiconductor memory package unit:
[0047] (1) Each die pad 13 of the present invention is formed using an RDL process, and by making an electrical connection to the outside with each of the rearranged conductive wires 22, the layout design between the connection points (so-called solder pads) of each conductive wire 22 to the outside can be further diversified.
[0048] (2) Because the wiring layout space on the die package 10 is relatively flexible and easy to design, the wiring layout on the substrate 50 that forms an electrical connection with the die package 10 is also relatively flexible and easy to design, which is advantageous in reducing manufacturing costs on the manufacturing side.
[0049] (3) The wiring layout on the die package 10 is relatively flexible and avoids excessive density between wires, which is advantageous in ensuring the success of the soldering process and improving product reliability and yield rate. [Explanation of symbols]
[0050] 1. Semiconductor memory package unit 10 die packages 11 Dies 12 1st surface 13 Die Pad 20 Redistribution layer 21 Dielectric layer 211 1st surface 212 recesses 22 Conductive Wiring 30 Insulating layer 31 1st surface 32 First opening 40 First connection 41 Solder ball 50 circuit boards 51 1st surface 52 2nd surface 53 1st protective layer 54 Second protective layer 55 Second opening 56 1st wiring 57 Third opening 58 2nd wiring 59 Conductive Pillar 60 Second connection 61 Solder ball 1a Semiconductor memory package unit 10a die package 11a Die 12a 1st surface 13a die pad 30a insulating layer 31a 1st surface 32a 1st opening 321a Copper Pillar 40a First connector 50a substrate 51a 1st surface 52a 2nd surface 53a 1st protective layer 54a 2nd protective layer 55a 2nd opening 56a First wiring 57a 3rd opening 58a Second wiring 59a Conductive Pillar 60a Second connector 2 Printed circuit boards
Claims
1. It includes one die package, multiple first connectors and one substrate, The die package includes one die and one insulating layer, the die having one first surface and having a plurality of die pads on the first surface, the insulating layer is located on and covers the die, the insulating layer has one first surface and a plurality of first openings, each of which is used to electrically connect each of the die pads of the die to the outside, a portion of each of the first connectors is provided within each of the first openings of the insulating layer, and each of the first connectors further forms an electrical connection with each of the die pads of the die, the substrate is located on the first surface of the insulating layer and each of the first connectors, the substrate has one first surface and one opposing second The substrate has a surface, the first surface of the substrate has a first protective layer, the second surface of the substrate has a second protective layer, the first protective layer has a plurality of second openings, each of which has a first wiring, each of which is used to make an electrical connection to the outside, the second protective layer has a plurality of third openings, each of which has a second wiring, a part of each of the first connectors is provided in each of the third openings, each of the first connectors further forms an electrical connection with each of the second wirings, there is a conductive pillar between each of the first wirings and each of the second wirings, each of which has an electrical connection with each of the first wirings and each of the second wirings, and its features are, The semiconductor memory package unit further has a Reduction Layer (RDL) formed using a Reduction Layer (RDL) process, the RDL is provided between the die and the insulating layer and is covered by the insulating layer, and the RDL has one dielectric layer and multiple conductive wirings. The dielectric layer has one first surface, the first surface of the dielectric layer is positioned correspondingly on the first surface of the die, the dielectric layer has a plurality of recesses, each of which allows each of the die pads of the die to be exposed to the outside. Each of the conductive wires is provided within each recess, each conductive wire forms an electrical connection with each die pad, and each conductive wire is made of a metallic material. Structural improvement of a semiconductor memory package unit, characterized in that the die of the semiconductor memory package unit is electrically connected to the outside via, in order, each die pad, each conductive wiring, each first connector, each second wiring, each conductive pillar, and each first wiring.
2. The structural improvement of the semiconductor memory package unit according to claim 1, characterized in that each conductive wiring exposed to the outside from each of the first openings is soldered to the outside using a solder ball, and the solder ball simultaneously forms each of the first connectors in each of the first openings and each of the third openings.
3. The structural improvement of the semiconductor memory package unit according to claim 1, characterized in that the first wiring of each second opening of the substrate is soldered to the outside using a solder ball, and the solder ball simultaneously forms a second connector on each first wiring of the second opening.
4. The structural improvement of the semiconductor memory package unit according to claim 1, characterized in that the thickness of each die pad is 2 μm, the thickness of the dielectric layer is 10 μm, the thickness of each conductive wiring is 10 μm, the thickness of each first connector is 50 μm, the thickness of the substrate is 135 μm, the thickness of the first protective layer is 30 μm, the thickness of the second protective layer is 30 μm, the thickness of the first wiring is 25 μm, the thickness of the second wiring is 25 μm, the thickness of each conductive pillar is 75 μm, and the thickness of each second connector is 350 μm.
5. The structural improvement of the semiconductor memory package unit according to claim 1, characterized in that each of the conductive wirings is made of silver (Ag), and each of the first wirings, each of the second wirings, and each of the conductive pillars are made of copper (Cu).
6. The improved structure of the semiconductor memory package unit according to claim 1, characterized in that the semiconductor memory package unit is further mounted on a printed circuit board (PCB).
7. The structural improvement of the semiconductor memory package unit according to claim 1, characterized in that the memory type of the semiconductor memory package unit includes DRAM, SRAM, and SDRAM.