Designed substrate structures for power and RF applications

Abstract

This invention provides a substrate structure designed to be CTE-matched to a gallium nitride-based epitaxial layer suitable for use in optical, electronic, and optoelectronic applications, as well as a method for manufacturing the same. [Solution] The substrate 100 includes a support structure having a polycrystalline ceramic core 110, a first adhesive layer 112 bonded to the polycrystalline ceramic core 110, a conductive layer 114 bonded to the first adhesive layer 112, a second adhesive layer 116 bonded to the conductive layer 114, and a barrier layer 118 bonded to the second adhesive layer 116; further includes a bonding layer 120 bonded to the support structure; a substantially single-crystal layer 122 bonded to the bonding layer 120, comprising at least one of silicon carbide, sapphire, or gallium nitride; and an epitaxial semiconductor layer 130 bonded to the substantially single-crystal layer 122.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 350,084, entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS," filed on 14 June 2016, and to U.S. Provisional Patent Application No. 62 / 350,077, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE," filed on 14 June 2016, the disclosures thereof incorporated herein by reference in their entirety for all purposes.

[0002]

[0002] The following two U.S. patent applications were filed concurrently with this application, and the disclosures of these two applications are incorporated herein by reference in their entirety for all purposes.

[0003]

[0003] Application No. 15 / 621,335, titled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS", filed on June 13, 2017 (Agent reference number 098825-1049529-001110US).

[0004]

[0004] Application No. 15 / 621,338, titled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE", filed on June 13, 2017 (Agent reference number 098825-1049532-001610US). [Background technology]

[0005]

[0005] Light-emitting diode (LED) structures are typically grown epitaxially on a sapphire substrate. Currently, many products use LED devices, including lighting, computer monitors, and other display devices.

[0006]

[0006] The growth of gallium nitride-based LED structures on a sapphire substrate is a heteroepitaxial growth process because the substrate and the epitaxial layer are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown material may exhibit various adverse effects, including reduced uniformity and decreased metrics related to the electronic / optical properties of the epitaxial layer. Therefore, improved methods and systems related to the epitaxial growth process and substrate structure are needed in this field. [Overview of the project]

[0007]

[0007] The present invention relates to generally designed substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. As just one example, the present invention relates to methods and systems that provide substrate structures suitable for epitaxial growth, the structures characterized by a coefficient of thermal expansion (CTE) substantially compatible with the epitaxial layer grown thereon. The methods and techniques can be applied to a variety of semiconductor processing operations.

[0008]

[0008] According to one embodiment of the present invention, a substrate is provided. The substrate includes a support structure comprising a polycrystalline ceramic core, a first adhesive layer bonded to the polycrystalline ceramic core, a conductive layer bonded to the first adhesive layer, a second adhesive layer bonded to the conductive layer, and a barrier layer bonded to the second adhesive layer. The substrate also comprises a silicon oxide layer bonded to the support structure and a silicon oxide layer It includes a substantially single-crystal silicon layer bonded to a silicon layer, and an epitaxial III-V layer bonded to the substantially single-crystal silicon layer.

[0009]

[0009] According to another embodiment of the present invention, a method for manufacturing a substrate is provided. This method includes forming a support structure by preparing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesive shell, encapsulating the first adhesive shell in a conductive shell, encapsulating the conductive shell in a second adhesive shell, and encapsulating the second adhesive shell in a barrier shell. This method also includes bonding a bonding layer to the support structure, bonding a substantially single-crystal silicon layer to the bonding layer, forming an epitaxial silicon layer on the substantially single-crystal silicon layer by epitaxial growth, and forming an epitaxial III-V layer on the epitaxial silicon layer by epitaxial growth.

[0010]

[0010] According to a particular embodiment of the present invention, a designed substrate structure is provided. The designed substrate structure includes a support structure, a bonding layer bonded to the support structure, a substantially single-crystal silicon layer bonded to the bonding layer, and an epitaxial single-crystal silicon layer bonded to the substantially single-crystal silicon layer. The support structure includes a polycrystalline ceramic core, a first adhesive layer bonded to the polycrystalline ceramic core, a conductive layer bonded to the first adhesive layer, a second adhesive layer bonded to the conductive layer, and a barrier shell bonded to the second adhesive layer.

[0011]

[0011] Many advantages are achieved by the present invention compared to the prior art. For example, embodiments of the present invention provide a substrate structure designed to be CTE-matched to a gallium nitride-based epitaxial layer suitable for use in optical, electronic, and optoelectronic applications. An encapsulation layer, used as a component of the designed substrate structure, prevents the diffusion of impurities present in the central portion of the substrate from reaching the semiconductor processing environment in which the designed substrate is used. Key properties related to the substrate material, including thermal expansion coefficient, lattice mismatch, thermal stability, and shape control, are uniquely designed for improved (e.g., optimized) matching with the gallium nitride-based epitaxial layer and device layer, as well as with various device architectures and performance targets. Process integration is simplified because the substrate material layers are integrated together in a conventional semiconductor manufacturing process. These and other embodiments of the present invention, along with many of their advantages and features, will be described in more detail below in reference to the text and accompanying drawings. [Brief explanation of the drawing]

[0012] [Figure 1] This is a simplified schematic diagram showing a substrate structure designed according to one embodiment of the present invention. [Figure 2A] This is a SIMS profile showing the species concentration as a function of depth for a structure designed according to one embodiment of the present invention. [Figure 2B] This is a SIMS profile showing the species concentration as a function of depth for the designed structure after annealing according to an embodiment of the present invention. [Figure 2C] This is a SIMS profile showing the seed concentration as a function of depth for a designed structure having an annealed silicon nitride layer according to an embodiment of the present invention. [Figure 3] This is a simplified schematic diagram showing a substrate structure designed according to another embodiment of the present invention. [Figure 4] This is a simplified schematic diagram showing a substrate structure designed according to yet another embodiment of the present invention. [Figure 5]A simplified flowchart showing a method of manufacturing a designed substrate according to an embodiment of the present invention. [Figure 6] A simplified schematic diagram showing an epitaxial / designed substrate structure for RF and power applications according to an embodiment of the present invention. [Figure 7] A simplified schematic diagram showing a group III-V epitaxial layer on a designed substrate structure according to an embodiment of the present invention. [Figure 8] A simplified flowchart showing a method of manufacturing a designed substrate according to another embodiment of the present invention. **Embodiments for Carrying Out the Invention**

[0013]

[0022] Embodiments of the present invention relate to designed substrate structures. More specifically, the present invention relates to methods and systems suitable for use in an epitaxial growth process. As a mere example, the present invention is applicable to methods and systems for providing a substrate structure suitable for epitaxial growth, the structure of which is characterized by a coefficient of thermal expansion (CTE) that substantially matches that of the epitaxial layer growing thereon. The methods and techniques can be applied to various semiconductor processing operations.

[0014]

[0023] FIG. 1 is a simplified schematic diagram showing a designed substrate structure according to an embodiment of the present invention. The designed substrate 100 shown in FIG. 1 is suitable for various electronic and optical applications. The designed substrate includes a core 110 that can have a coefficient of thermal expansion (CTE) that substantially matches that of the epitaxial material to be grown on the designed substrate 100. The epitaxial material 130 is shown as an optional feature since it is not necessary as an element of the designed substrate but is typically grown on the designed substrate.

[0015]

[0024] In applications involving the growth of gallium nitride (GaN)-based materials (epitaxial layers including GaN-based layers), the core 110 can be made of polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN) containing a bonding material such as yttrium oxide. Other materials including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), etc. can be used for the core 110.

[0016]

[0025] The thickness of the core can be about 100 to 1500 μm, for example, 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which can be referred to as a shell or encapsulating shell. In one embodiment, the first adhesive layer 112 includes a tetraethyl orthosilicate (TEOS) layer with a thickness of about 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used in the adhesive layer in some embodiments, other materials (e.g., ceramics, especially polycrystalline ceramics) that provide adhesion between the subsequently deposited layer and the underlying layer or material can also be used according to embodiments of the present invention. For example, SiO2 or other silicon oxides (Si x O y ) adhere well to ceramic materials and provide a surface suitable for subsequent deposition of conductive materials, for example. In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a completely encapsulated core and can be formed using an LPCVD process. The first adhesive layer 112 provides a surface on which subsequent layers are adhered to form an element of the substrate structure designed.

[0017]

[0026] In addition to the use of LPCVD processes, furnace processes, etc., for forming the first encapsulation adhesive layer, other semiconductor processes, including CVD processes or similar deposition processes, can be utilized according to embodiments of the present invention. For example, a deposition process can be used to coat a portion of the core, the core can be flipped over, and the deposition process can be repeated to coat additional portions of the core. Thus, in some embodiments, LPCVD technology is used to provide a fully encapsulated structure, but other film deposition technologies can be used depending on the specific application.

[0018]

[0027] A conductive layer 114 is formed so as to surround the adhesive layer 112. In one embodiment, since polysilicon has poor adhesion to ceramic materials, the conductive layer 114 is a shell of polysilicon (i.e., polycrystalline silicon) formed so as to surround the first adhesive layer 112. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer may be approximately 500 to 5,000 Å, for example, 2,500 Å. In some embodiments, the polysilicon layer can be formed as a shell so as to completely surround the first adhesive layer 112 (e.g., the TEOS layer), thereby forming a completely encapsulated first adhesive layer, and can also be formed using an LPCVD process. In other embodiments, as will be described later, the conductive material can be formed in part of the adhesive layer, for example, in the lower half of the substrate structure. In some embodiments, the conductive material can be formed as a completely encapsulated layer and subsequently removed on one side of the substrate structure.

[0019]

[0028] In one embodiment, the conductive layer 114 can be a polysilicon layer doped to provide a highly conductive material, for example, a polysilicon layer doped with boron to provide a p-type polysilicon layer. In some embodiments, to provide high conductivity, the doping with boron is 1 × 10⁻⁶. 19 cm -3 From 1 x 10 20 cm -3 This is the level of other dopants at different dopant concentrations (e.g., 1 × 10⁻⁶).16 cm -3 to 5×10 18 cm -3 Using a dopant concentration (such as phosphorus, arsenic, bismuth, etc.) in the range of, it is possible to provide either an n-type or p-type semiconductor material suitable for use in a conductive layer. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0020]

[0029] The presence of the conductive layer 114 is useful when electrostatically chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 114 enables rapid de-chucking after processing in a semiconductor processing tool. Thus, embodiments of the present invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0021]

[0030] A second adhesive layer 116 (e.g., a TEOS layer having a thickness of about 1,000 Å) is formed to surround the conductive layer 114. In some embodiments, the second adhesive layer 116 completely surrounds the conductive layer 114 to form a complete encapsulation structure and can be formed using an LPCVD process, a CVD process, or any other suitable deposition process including the deposition of spin-on dielectrics.

[0022]

[0031] A barrier layer 118, such as a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118 with a thickness of approximately 2,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 116 to form a complete encapsulation structure, and can also be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc., can be used as barrier layers. In some embodiments, the barrier layer 118 includes several sublayers constructed to form the barrier layer. Therefore, the term barrier layer is intended to encompass one or more materials laminated in a composite manner, rather than meaning a single layer or single material. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0023]

[0032] In some embodiments, a barrier layer 118, such as a silicon nitride layer, prevents elements present within the core 110, such as yttrium oxide (i.e., yttria), oxygen, metallic impurities, and other trace elements, from diffusing and / or releasing gases into the semiconductor processing chamber environment in which the designed substrate can be present, for example, during a high-temperature (e.g., 1,000°C) epitaxial growth process. Using the encapsulation layers described herein, ceramic materials containing polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0024]

[0033] Figure 2A is a secondary ion mass spectrometry (SIMS) profile showing the species concentration as a function of depth for a structure designed according to one embodiment of the present invention. The structure did not include barrier layer 118. Referring to Figure 2A, several species present in the ceramic core (e.g., yttrium, calcium, and aluminum) are reduced to negligible concentrations in the designed layer 120 / 122. The concentrations of calcium, yttrium, and aluminum are reduced by 3, 4, and 6 orders of magnitude, respectively.

[0025]

[0034] Figure 2B is a SIMS profile showing the seed concentration as a function of depth for a barrier-free designed structure after annealing according to an embodiment of the present invention. As described above, during semiconductor processing operations, the designed substrate structures provided by embodiments of the present invention may be exposed to high temperatures (approximately 1100°C) for several hours, for example, during the epitaxial growth of a GaN-based layer.

[0026]

[0035] For the profile shown in Figure 2B, the designed substrate structure was annealed at 1100°C for 4 hours. As shown in Figure 2B, calcium, yttrium, and aluminum, which were originally present in the deposition sample at low concentrations, diffused into the designed layer and reached similar concentrations to the other elements.

[0027]

[0036] Figure 2C is a SIMS profile showing the species concentration as a function of depth for a designed structure with a barrier layer after annealing, according to one embodiment of the present invention. Integrating a diffusion barrier layer 118 (e.g., a silicon nitride layer) into the designed substrate structure prevents the diffusion of calcium, yttrium, and aluminum into the designed layer during the annealing process, which would occur in the absence of the diffusion barrier layer. As shown in Figure 2C, the calcium, yttrium, and aluminum present in the ceramic core remain at low concentrations in the designed layer after annealing. Therefore, the use of the barrier layer 118 (e.g., a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier, thereby preventing them from being released into the environment surrounding the designed substrate. Similarly, any other impurities present in the bulk ceramic material are also contained by the barrier layer.

[0028]

[0037] Typically, the ceramic material used to form the core 110 is fired at temperatures in the range of 1,800°C. This process is expected to remove a considerable amount of impurities present in the ceramic material. These impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttria as a sintering agent. Subsequently, during the epitaxial growth process, which takes place at much lower temperatures in the range of 800°C to 1100°C, it would be expected that the subsequent diffusion of these impurities would be minimal. However, contrary to conventional expectations, the inventors have found that significant diffusion of elements can occur through the layers of the designed substrate even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. Therefore, embodiments of the present invention integrate a barrier layer 118 (e.g., a silicon nitride layer) to prevent out-diffusion of background elements into epitaxial layers such as layers 120 / 122 designed from polycrystalline ceramic material (e.g., AlN) and any GaN layer 130. The silicon nitride layer 118, which encloses the underlying layer and material, provides the desired barrier layer function.

[0029]

[0038] As shown in Figure 2B, elements originally present in the core 110, including yttrium, diffuse into and through the first TEOS layer 112, the polysilicon layer 114, and the second TEOS layer 116. However, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing their release into the environment surrounding the designed substrate, as shown in Figure 2C.

[0030]

[0039] Referring again to Figure 1, the bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118, for example, on the upper surface of the barrier layer, and is then used during bonding of the substantially single-crystal silicon layer 122. In some embodiments, the bonding layer 120 may have a thickness of about 1.5 μm.

[0031]

[0040] The substantially single-crystal layer 122 is suitable for use as a growth layer during the epitaxial growth process for forming the epitaxial material 130. In some embodiments, the epitaxial material 130 includes a GaN layer with a thickness of 2 μm to 10 μm, which can be used as one of several layers utilized in optoelectronic devices, RF devices, power devices, etc. In one embodiment, the substantially single-crystal layer 122 includes a substantially single-crystal silicon layer attached to the silicon oxide layer 118 using a layer transfer process.

[0032]

[0041] Figure 3 is a simplified schematic diagram showing a designed substrate structure according to one embodiment of the present invention. The designed substrate 300 shown in Figure 3 is suitable for a variety of electronic and optical applications. The designed substrate includes a core 110 which can have a coefficient of thermal expansion (CTE) substantially matching that of the epitaxial material 130 grown on the designed substrate 300. The epitaxial material 130 is not required as an element of the designed substrate structure, but is shown as an optional choice because it is typically grown on the designed substrate structure.

[0033]

[0042] In applications involving the growth of gallium nitride (GaN)-based materials (epitaxial layers including GaN-based layers), the core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core may be approximately 100 to 1500 μm, for example, 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which can be called a shell or encapsulation shell. In this embodiment, the first adhesive layer 112 completely encapsulates the core, although this is not required by the present invention, as will be discussed in more detail with respect to Figure 4.

[0034]

[0043] In one embodiment, the first adhesive layer 112 includes a tetraethyl orthosilicate (TEOS) layer with a thickness of approximately 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. While TEOS is used for the adhesive layer in some embodiments, other materials that provide adhesion between the subsequently deposited layer and the layer or material beneath it can also be used according to embodiments of the present invention. For example, SiO2, SiON, etc., adhere well to ceramic materials and provide a surface suitable for subsequent deposition of conductive materials, for example. In some embodiments, the first adhesive layer 112 completely surrounds the core 110, forming a fully encapsulated core, which can be formed using an LPCVD process. The adhesive layer provides a surface upon which subsequent layers are bonded to form elements of the designed substrate structure.

[0035]

[0044] In addition to using LPCVD processes, furnace processes, etc., for forming the encapsulation adhesive layer, other semiconductor processes can be utilized according to embodiments of the present invention. For example, a deposition process such as CVD or PECVD can be used to coat a portion of the core, the core can be turned over, and the deposition process can be repeated to coat additional portions of the core.

[0036]

[0045] A conductive layer 314 is formed on at least a portion of the first adhesive layer 112. In one embodiment, the conductive layer 314 includes polysilicon (i.e., polycrystalline silicon) formed by a deposition process on the lower part (e.g., the lower half or back surface) of the core / adhesive layer structure. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer may be on the order of several thousand angstroms, for example, 3,000 Å. In some embodiments, the polysilicon layer can be formed using an LPCVD process.

[0037]

[0046] In one embodiment, the conductive layer 314 can be a polysilicon layer doped to provide a highly conductive material; for example, the conductive layer 314 can be doped with boron to provide a p-type polysilicon layer. In some embodiments, to provide high conductivity, Boron doping is approximately 1 × 10⁻⁶ 19 cm -3 From 1 x 10 20 cm -3 This is within the range of levels. The presence of a conductive layer is useful when electrostatically chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC). The conductive layer 314 allows for rapid de-chucking after processing. Thus, embodiments of the present invention provide a substrate structure that can be processed in the same manner as used with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0038]

[0047] A second adhesive layer 316 (e.g., a second TEOS layer) is formed to surround the conductive layer 314 (e.g., a polysilicon layer). The thickness of the second adhesive layer 316 is approximately 1,000 Å. In some embodiments, the second adhesive layer 316 completely surrounds the conductive layer 314 and the first adhesive layer 112 to form a complete encapsulation structure, and can also be formed using an LPCVD process. In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314, ending at a position indicated by a plane 317 which can be aligned with the upper surface of the conductive layer 314. In this example, the upper surface of the conductive layer 314 will be in contact with a portion of the barrier layer 118. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0039]

[0048] A barrier layer 118 (for example, a silicon nitride layer) is formed to surround the second adhesive layer 316. In some embodiments, the thickness of the barrier layer 118 is approximately 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 316 to form a complete encapsulation structure, and can also be formed using an LPCVD process.

[0040]

[0049] In some embodiments, the use of a silicon nitride barrier layer prevents elements present within the core 110, such as yttrium oxide (i.e., yttria), oxygen, metallic impurities, and other trace elements, from diffusing and / or releasing gases into the semiconductor processing chamber environment in which the designed substrate may be present, for example, during high-temperature (e.g., 1,000°C) epitaxial growth processes. Using the encapsulation layers described herein, ceramic materials containing polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0041]

[0050] Figure 4 is a simplified schematic diagram showing a substrate structure designed according to another embodiment of the present invention. In the embodiment shown in Figure 4, the first adhesive layer 412 is formed on at least a portion of the core 110, but the core 110 is not encapsulated. In this embodiment, the first adhesive layer 412 is formed on the underside (back side of the core 110) of the core 110 to enhance adhesion of the conductive layer 414 that is subsequently formed, as will be described in more detail below. Although the adhesive layer 412 is shown only on the underside of the core 110 in Figure 4, it will be understood that the deposition of adhesive layer material on other parts of the core does not adversely affect the performance of the designed substrate structure, and such material can be present in various embodiments. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0042]

[0051] The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is substantially aligned with the first adhesive layer 412. While the conductive layer 414 is shown extending along the bottom or back surface of the first adhesive layer 412 and extending upward along a portion of the side surface, extension along a vertical plane is not required by the present invention. Therefore, embodiments can utilize deposition on one side of the substrate structure, masking of one side of the substrate structure, etc. The conductive layer 414 can be formed on one side of the first adhesive layer 412, for example, a portion of the bottom / back surface. The conductive layer 414 provides electrical conductivity to one side of the designed substrate structure, which can be advantageous in RF and high-power applications. The conductive layer may include doped polysilicon, as described with respect to conductive layer 114 in Figure 1.

[0043]

[0052] A portion of the core 110, a portion of the first adhesive layer 412, and the conductive layer 414 are covered with a second adhesive layer 416 to enhance the adhesion of the barrier layer 418 to the underlying material. The barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layer, as described above.

[0044]

[0053] In addition to semiconductor conductive layers, in other embodiments, the conductive layer 414 is a metal layer, such as 500 Å titanium.

[0045]

[0054] Referring again to Figure 4, depending on the embodiment, one or more layers can be removed. For example, layers 412 and 414 can be removed, leaving only a single adhesive shell 416 and barrier layer 418. In another embodiment, only layer 414 can be removed. In this embodiment, layer 412 can also balance the stress caused by layer 120 deposited on top of layer 418 and the bending of the wafer. A substrate structure configuration having an insulating layer on the upper surface of the core 110 (for example, having only an insulating layer between the core 110 and layer 120) benefits power / RF applications where a highly insulating substrate is desired.

[0046]

[0055] In another embodiment, the barrier layer 418 may directly enclose the core 110, followed by a conductive layer 414 and then an adhesive layer 416. In this embodiment, layer 120 can be deposited directly onto the adhesive layer 416 from the top surface. In yet another embodiment, the adhesive layer 416 may be deposited onto the core 110, followed by the barrier layer 418, then the conductive layer 414, and then another adhesive layer 412.

[0047]

[0056] While several embodiments have been discussed in terms of layers, the term "layer" should be understood to include several sublayers constructed to form the layer of interest. Thus, the term "layer" is intended to encompass one or more materials laminated in a composite manner to form the desired structure, rather than meaning a single layer consisting of a single material. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0048]

[0057] Figure 5 is a simplified flowchart showing a method for manufacturing a substrate designed according to an embodiment of the present invention. This method can be used to manufacture a substrate with CTE matching to one or more epitaxial layers grown on the substrate. Method 500 includes forming a support structure by preparing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesive layer (e.g., a tetraethyl orthosilicate (TEOS) shell) that forms a shell (512), and encapsulating the first adhesive layer in a conductive shell (514) (e.g., a polysilicon shell). The first adhesive layer can be formed as a single layer of TEOS. The conductive shell can be formed as a single layer of polysilicon.

[0049]

[0058] This method also includes encapsulating a conductive shell in a second adhesive layer (516) (e.g., a second TEOS shell) and encapsulating the second adhesive layer in a barrier layer shell (518). The second adhesive layer can be formed as a single layer of TEOS. The barrier layer shell can be formed as a single layer of silicon nitride.

[0050]

[0059] Once the support structure is formed by processes 510-518, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (520) and bonding a substantial single crystal layer, e.g., a substantial single crystal silicon layer, to the silicon oxide layer (522). According to embodiments of the present invention, other substantial single crystal layers, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc., can be used. Bonding the bonding layer may include depositing a bonding material and a subsequent planarization process as described herein. In embodiments described later, a substantial single crystal layer (e.g., substantial single crystal silicon) Bonding a layer to a bonding layer utilizes a layer transfer process, where the layer is a single-crystal silicon layer transferred from a silicon wafer.

[0051]

[0060] Referring to Figure 1, the bonding layer 120 can be formed by depositing a thick (e.g., 4 μm thick) oxide layer, followed by a chemical mechanical polishing (CMP) process to thin the oxide to approximately 1.5 μm. The thick initial oxide may be present after the fabrication of the polycrystalline core and helps fill voids and surface features present on the support structure, which may remain present when the encapsulation layer shown in Figure 1 is formed. The CMP process provides a substantially flat surface free of voids, particles, or other features, which can then be used during the wafer transport process to bond a substantially single-crystal layer 122 (e.g., a substantially single-crystal silicon layer) to the bonding layer 120. The bonding layer 120 does not need to be characterized by an atomically flat surface, but should provide a substantially flat surface that facilitates bonding of a substantially single-crystal layer (e.g., a substantially single-crystal silicon layer) with the desired reliability.

[0052]

[0061] A substantially single-crystal silicon layer 122 can be bonded to a bonding layer 120 using a layer transfer process. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is injected to form a cleavage plane. After wafer bonding, the silicon substrate can be removed along with a portion of the single-crystal silicon layer beneath the cleavage plane, resulting in the exfoliated single-crystal silicon layer 122 shown in Figure 1. The thickness of the substantially single-crystal layer 122 can be varied to suit the specifications of various applications. Furthermore, the crystal orientation of the substantially single-crystal layer 122 can be varied to suit the specifications of the application. In addition, the doping level and profile in the substantially single-crystal layer 122 can be varied to suit the specifications of a particular application.

[0053]

[0062] The method shown in Figure 5 may also include smoothing the substantial single-crystal layer (524). In some embodiments, the thickness and surface roughness of the substantial single-crystal layer 122 can be modified for high-quality epitaxial growth. Different apparatus applications may have slightly different specifications regarding the thickness and surface smoothness of the substantial single-crystal layer 122. The cleavage process exfoliates the substantial single-crystal layer 122 from the bulk single-crystal silicon wafer at the peak of the implanted ion profile. After cleavage, the substantial single-crystal layer 122 can be adjusted or modified in several embodiments before being used as a growth surface for epitaxial growth of other materials such as gallium nitride.

[0054]

[0063] Firstly, the transferred substantial single-crystal layer 122 may contain a small amount of residual hydrogen and may have some crystal damage due to the implantation. Therefore, it may be beneficial to remove the thin portion of the transferred substantial single-crystal layer 122 in which the crystal lattice is damaged. In some embodiments, the implantation depth can be adjusted to be greater than the desired final thickness of the substantial single-crystal layer 122. The additional thickness allows for the removal of the damaged thin portion of the transferred substantial single-crystal layer, leaving an undamaged portion of the desired final thickness.

[0055]

[0064] Secondly, it may be desirable to adjust the overall thickness of the substantial single-crystal layer 122. Generally, the substantial single-crystal layer 122 is desirable to be thick enough to provide a high-quality lattice template for the subsequent growth of one or more epitaxial layers, but thin enough for a high degree of fit. The substantial single-crystal layer 122 can be said to be "well-fitted" when it is relatively thin, so that its physical properties are not too constrained and it can mimic the physical properties of the surrounding material with a tendency to generate fewer crystal defects. The fit of the substantial single-crystal layer 122 may be inversely proportional to its thickness. The higher the fit, the lower the defect density of the epitaxial layer grown on the template, and the more thick the epitaxial layer can be grown. In some embodiments, the thickness of the substantial single-crystal layer 122 can be increased by epitaxially growing silicon on the exfoliated silicon layer. Cut.

[0056]

[0065] Thirdly, improving the smoothness of the substantial single-crystal layer 122 may be beneficial. The smoothness of the layer may be related to the total hydrogen dose, the presence of any co-injected species, and the annealing conditions used to form the hydrogen-based cleavage plane. As will be discussed later, the initial roughness resulting from the layer transfer (i.e., the cleavage process) can be mitigated by thermal oxidation and oxide exfoliation.

[0057]

[0066] In some embodiments, the removal of the damaged layer and adjustment of the final thickness of the substantially single-crystal layer 122 can be achieved by thermal oxidation of the top of the exfoliated silicon layer, followed by exfoliation of the oxide layer with hydrofluoric acid (HF). For example, a exfoliated silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to form a silicon dioxide layer with a thickness of approximately 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer may be approximately 53 nm. During thermal oxidation, the injected hydrogen can move toward the surface. Therefore, the subsequent exfoliation of the oxide layer can remove some damage. Also, thermal oxidation is typically carried out at temperatures of 1000°C or higher. High temperatures can also repair lattice damage.

[0058]

[0067] The silicon oxide layer formed on top of the substantial single-crystal layer during thermal oxidation can be exfoliated using HF acid etching. The etching selectivity between silicon oxide and silicon (SiO2:Si) by HF acid can be adjusted by controlling the temperature and concentration of the HF solution, as well as the stoichiometry and density of the silicon oxide. Etching selectivity refers to the etching rate of one material compared to another. The selectivity of the HF solution can range from about 10:1 to about 100:1 for (SiO2:Si). High etching selectivity can reduce surface roughness from the initial surface roughness by similar factors. However, the resulting surface roughness of the substantial single-crystal layer 122 may still be greater than desired. For example, a bulk Si(111) surface can have a root mean square (RMS) surface roughness of less than 0.1 nm, as determined by a 2 μm × 2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the desired surface roughness for epitaxially growing gallium nitride material on Si(111) may be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm on a 30 μm × 30 μm AFM scan area.

[0059]

[0068] If the surface roughness of the substantial single-crystal layer 122 after thermal oxidation and oxide layer delamination exceeds the desired surface roughness, additional surface smoothing can be performed. There are several methods for smoothing a silicon surface. These methods may include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., chemical mechanical polishing, i.e., CMP). These methods may involve preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, resulting in a smoother surface.

[0060]

[0069] It should be understood that the specific steps shown in Figure 5 provide a specific method for manufacturing a substrate designed according to one embodiment of the present invention. Other embodiments may also perform other sets of steps. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, the individual steps shown in Figure 5 may include several sub-steps that can be performed in various orders as appropriate for the individual steps. Additionally, additional steps may be added or removed depending on the specific application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0061]

[0070] Figure 6 is a simplified schematic diagram showing an epitaxial / designed substrate structure for RF and power applications according to one embodiment of the present invention. In some LED applications, the designed substrate structure provides a growth substrate that enables the growth of a high-quality GaN layer, and the designed substrate The board structure is subsequently removed. However, for RF and power equipment applications, the designed substrate structure forms part of the finished equipment, and consequently, the electrical, thermal, and other properties of the designed substrate structure or its elements are important for the specific application.

[0062]

[0071] Referring to Figure 1, the single-crystal silicon layer 122 is typically a delamination layer separated from a silicon donor wafer using injection and delamination techniques. Typical injections are hydrogen and boron. For power and RF equipment applications, the electrical properties of the layers and materials in the designed substrate structure are important. For example, some equipment architectures are 10 3Leakage through the substrate and interface layers is reduced or eliminated by utilizing a highly insulating silicon layer with resistance exceeding Ωcm. Other applications utilize designs that include a conductive silicon layer of a predetermined thickness (e.g., 1 μm) to connect the device's power source to other elements. Therefore, in these applications, it is desirable to control the dimensions and properties of the single-crystal silicon layer. In designs where injection and exfoliation techniques are used during layer transfer, residual injected atoms, such as hydrogen or boron, are present in the silicon layer, thereby altering its electrical properties. Furthermore, it can be difficult to control the thickness, conductivity, and other properties of thin silicon layers by adjusting the injection amount, surface roughness, and cleavage plane position accuracy, which can affect conductivity and the full width at half maximum (FWHM) of the injection profile, as well as the injection depth, which can affect the layer thickness.

[0063]

[0072] According to embodiments of the present invention, desired properties of a single-crystal silicon layer suitable for a specific device design are achieved by utilizing silicon epitaxy on a designed substrate structure.

[0064]

[0073] Referring to Figure 6, the epitaxial / designed substrate structure 600 includes a designed substrate structure 610 and a silicon epitaxial layer 620 formed thereon. The designed substrate structure 610 may be similar to the designed substrate structures shown in Figures 1, 3, and 4. Typically, the substantial single-crystal silicon layer 122 is about 0.5 μm thick after layer transfer. Using surface preparation processes, some processes can reduce the thickness of the single-crystal silicon layer 122 to about 0.3 μm. To increase the thickness of the single-crystal silicon layer to about 1 μm for use in forming reliable ohmic contacts, an epitaxial single-crystal silicon layer 620 is grown on the substantial single-crystal silicon layer 122 formed by the layer transfer process, for example, using an epitaxial process. The epitaxial single-crystal silicon layer 620 can be grown using various epitaxial growth processes, including CVD, ALD, and MBE. The thickness of the epitaxial single-crystal silicon layer 620 can range from approximately 0.1 μm to approximately 20 μm, for example, between 0.1 μm and 10 μm.

[0065]

[0074] Figure 7 is a simplified schematic diagram showing a III-V epitaxial layer on a substrate structure designed according to one embodiment of the present invention. The structure shown in Figure 7 can be called a double epitaxial structure, as will be described below. As shown in Figure 7, the designed substrate structure 710, which includes an epitaxial single-crystal silicon layer 620, has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN).

[0066]

[0075] The desired thickness of the III-V epitaxial layer 720 can vary substantially depending on the desired function. In some embodiments, the thickness of the III-V epitaxial layer 720 can vary between 0.5 μm and 100 μm, for example, to a thickness greater than 5 μm. The resulting breakdown voltage of an apparatus fabricated on the III-V epitaxial layer 720 can vary depending on the thickness of the III-V epitaxial layer 720. Some embodiments provide breakdown voltages of at least 100 V, 300 V, 600 V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

[0067]

[0076] A pair of vias 724 are formed to provide conductivity between portions of the III-V epitaxial layer 720, which may contain multiple sublayers, and in this example, pass from the top surface of the III-V epitaxial layer 720 to the epitaxial single-crystal silicon layer 620. The vias 724 can be aligned with insulating layers (not shown) so that they are insulated from the III-V epitaxial layer 720. As an example, these vias can be used to connect electrodes of a diode or transistor to the underlying silicon layer by providing ohmic contact through the vias, thereby easing the charge that accumulates in the device.

[0068]

[0077] When a III-V epitaxial layer is grown on a single-crystal silicon layer 122, it is difficult to complete via etching within the single-crystal silicon layer 122, for example, etching down to 5 μm of GaN and reliably completing the etching at a 0.3 μm silicon layer across the entire wafer, thus making it difficult to form such ohmic contacts via vias. Embodiments of the present invention make it possible to provide a single-crystal silicon layer with a thickness of several microns, which is difficult to achieve using injection and exfoliation processes because high injection energy is required to achieve large injection depths. Instead, the thick silicon layer enables applications such as the illustrated via, which allows for various device designs.

[0069]

[0078] In addition to increasing the thickness of the silicon "layer" by epitaxially growing a single-crystal silicon layer 620 on a single-crystal silicon layer 122, other adjustments, including modifications to conductivity, crystallinity, etc., can be made to the original properties of the single-crystal silicon layer 122. For example, if a silicon layer of about 10 μm is desired before the additional epitaxial growth of the III-V layer or other material, such a thick layer can be grown according to embodiments of the present invention.

[0070]

[0079] Since the injection process can affect the properties of the single-crystal silicon layer 122, for example, residual boron / hydrogen atoms can affect the electrical properties of silicon, embodiments of the present invention remove a portion of the single-crystal silicon layer 122 before epitaxial growth of the single-crystal silicon layer 620. For example, the single-crystal silicon layer 122 can be thinned to form a layer with a thickness of 0.1 μm or less, thereby removing most or all of the residual boron / hydrogen atoms. The subsequent growth of the single-crystal silicon layer 620 is used to provide a single-crystal material having electrical and / or other properties substantially independent of the corresponding properties of the layer formed using the layer transfer process.

[0071]

[0080] In addition to increasing the thickness of the single-crystal silicon material bonded to the designed substrate structure, the electrical properties, including conductivity, of the epitaxial single-crystal silicon layer 620 may differ from those of the single-crystal silicon layer 122. Doping of the growing epitaxial single-crystal silicon layer 620 can produce p-type silicon by doping with boron and n-type silicon by doping with phosphorus. Growing undoped silicon can provide high-resistance silicon for use in devices with insulating regions. Insulating layers may be particularly useful in RF devices.

[0072]

[0081] The lattice constant of the epitaxial single-crystal silicon layer 620 can be adjusted during growth to differ from the lattice constant of the single-crystal silicon layer 122, thereby producing a strained epitaxial material. In addition to silicon, other elements can be epitaxially grown to provide layers containing strained layers, silicon-germanium layers, and the like. For example, buffer layers can be grown on the single-crystal silicon layer 122, on the epitaxial single-crystal silicon layer 620, or between layers to enhance subsequent epitaxial growth. These buffer layers may include strained III-V layers, silicon-germanium strained layers, and the like. Furthermore, the buffer layers and other epitaxial layers can be varied in terms of mole fraction, dopants, polarity, etc. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0073]

[0082] In some embodiments, strain present in the single-crystal silicon layer 122 or the epitaxial single-crystal silicon layer 620 can be relieved during the growth of subsequent epitaxial layers, including the III-V epitaxial layer.

[0074]

[0083] Figure 8 is a simplified flowchart illustrating a method for manufacturing a substrate designed according to another embodiment of the present invention. This method includes forming a support structure by providing a polycrystalline ceramic core (810) and forming a first adhesive layer bonded to at least a portion of the polycrystalline ceramic core (812). The first adhesive layer may include a tetraethyl orthosilicate (TEOS) layer. The method also includes forming a conductive layer bonded to the first adhesive layer (814). The conductive layer may be a polysilicon layer. The first adhesive layer may be formed as a single layer of TEOS. The conductive layer may be formed as a single layer of polysilicon.

[0075]

[0084] The method also includes forming a second adhesive layer bonded to at least a portion of the conductive layer (816) and forming a barrier shell (818). The second adhesive layer may be formed as a single layer of TEOS. The barrier shell may be formed as a single layer of silicon nitride or as a series of sublayers forming the barrier shell.

[0076]

[0085] Once the support structure is formed by processes 810-818, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (820) and bonding a substantially single-crystal silicon layer or a substantially single-crystal layer to the silicon oxide layer (822). Bonding the bonding layer may include depositing a bonding material and a subsequent planarization process as described herein.

[0077]

[0086] A substantially single-crystal silicon layer 122 can be bonded to a bonding layer 120 using a layer transfer process. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is injected to form a cleavage plane. After wafer bonding, the silicon substrate can be removed along with a portion of the single-crystal silicon layer beneath the cleavage plane, resulting in the exfoliated single-crystal silicon layer 122 shown in Figure 1. The thickness of the substantially single-crystal silicon layer 122 can be varied to suit the specifications of various applications. Furthermore, the crystal orientation of the substantially single-crystal layer 122 can be varied to suit the specifications of the application. In addition, the doping level and profile in the substantially single-crystal layer 122 can be varied to suit the specifications of a particular application. In some embodiments, the substantially single-crystal silicon layer 122 can be smoothed as described above.

[0078]

[0087] The method shown in Figure 8 also includes forming an epitaxial silicon layer on a substantially single-crystal silicon layer (824) by epitaxial growth, and forming an epitaxial III-V layer on an epitaxial silicon layer (826) by epitaxial growth. In some embodiments, the epitaxial III-V layer may contain gallium nitride (GaN).

[0079]

[0088] It should be understood that the specific steps shown in Figure 8 provide a specific method for manufacturing a substrate designed according to another embodiment of the present invention. Other embodiments may also perform a different set of steps. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, the individual steps shown in Figure 8 may include several sub-steps that can be performed in various orders as appropriate for the individual steps. Additionally, additional steps may be added or removed depending on the specific application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0080]

[0089] Furthermore, the examples and embodiments described herein are for illustrative purposes only, and it will be understood that various modifications or changes in light thereof will be suggested to those skilled in the art and will be included in the spirit and scope of this application and the appended claims.

Claims

1. A support structure, Polycrystalline ceramic core and A first adhesive layer bonded to the polycrystalline ceramic core, A conductive layer bonded to the first adhesive layer, A second adhesive layer bonded to the conductive layer, A barrier layer bonded to the second adhesive layer and A support structure including, A bonding layer coupled to the aforementioned support structure, A substantially single crystal layer comprising at least one of silicon carbide, sapphire, or gallium nitride, bonded to the bonding layer, An epitaxial semiconductor layer bonded to the substantially single crystal layer and A substrate containing a substrate.

2. The substrate according to claim 1, wherein the polycrystalline ceramic core contains aluminum nitride.

3. The substrate according to claim 1, wherein the bonding layer contains silicon oxide.

4. The substrate according to claim 1, wherein the epitaxial semiconductor layer includes an epitaxial III-V layer.

5. The substrate according to claim 4, wherein the epitaxial III-V layer includes an epitaxial gallium nitride layer having a thickness of about 5 μm or more.

6. The substrate according to claim 4, further comprising a plurality of vias penetrating from the epitaxial III-V layer to the epitaxial semiconductor layer.

7. The substrate according to claim 1, wherein the epitaxial semiconductor layer includes an epitaxial single-crystal silicon layer, and the substrate further includes an epitaxial III-V layer bonded to the epitaxial single-crystal silicon layer.

8. The first adhesive layer encloses the polycrystalline ceramic core, The conductive layer encloses the first adhesive layer, The substrate according to claim 1, wherein the second adhesive layer encapsulates the conductive layer.

9. The substrate according to claim 1, wherein an epitaxial silicon layer is formed on the substantially single crystal layer.

10. The first adhesive layer includes a first tetraethyl orthosilicate (TEOS) layer that encloses the polycrystalline ceramic core. The conductive layer includes a polysilicon layer that encloses the first TEOS layer. The second adhesive layer includes a second TEOS layer that encapsulates the polysilicon layer. The substrate according to claim 1, wherein the barrier layer includes a silicon nitride layer that encapsulates the second TEOS layer.

11. A method for manufacturing a substrate, wherein the method is We provide polycrystalline ceramic cores. A first adhesive layer is formed bonded to the polycrystalline ceramic core. A conductive layer is formed bonded to the first adhesive layer. A second adhesive layer is formed bonded to the conductive layer. A support structure is formed by forming a barrier layer bonded to the second adhesive layer, Forming a bonding layer connected to the aforementioned support structure, Bonding a substantial single crystal layer to the bonding layer, wherein the substantial single crystal layer contains at least one of silicon carbide, sapphire, or gallium nitride. To form one or more epitaxial III-V layers bonded to the substantially single-crystal layer, Methods that include...

12. The first adhesive layer encloses the polycrystalline ceramic core, The conductive layer encloses the first adhesive layer, The second adhesive layer encloses the conductive layer, The method according to claim 11, wherein the barrier layer encapsulates the second adhesive layer.

13. The method according to claim 11, further comprising forming an epitaxial silicon layer on the substantially single crystal layer.

14. The method according to claim 11, wherein the polycrystalline ceramic core contains aluminum nitride, and the one or more epitaxial III-V layers contain an epitaxial gallium nitride layer having a thickness of about 5 μm or more.

15. The method according to claim 14, wherein the one or more epitaxial III-V layers further comprise an epitaxial aluminum nitride layer, an epitaxial aluminum gallium nitride layer, or a combination thereof.

16. The method according to claim 11, further comprising forming a strained epitaxial silicon layer bonded to the substantially single crystal layer before forming the one or more epitaxial III-V layers, wherein the one or more epitaxial III-V layers are bonded to the strained epitaxial silicon layer.

17. The method according to claim 11, further comprising forming a plurality of vias penetrating from one or more epitaxial III-V layers to the substantially single-crystal layer.

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