Thin-film transistor

Abstract

The present invention provides thin-film transistors (TFTs) with low off-leak current and positive threshold voltage (e.g., turn-on voltage). [Solution] A TFT 100A including a channel layer stack 104A with layers having different mobilities transports a larger total current through both the low-mobility and high-mobility channel layers and / or the high-mobility channel layer due to the higher carrier density in the high-mobility channel layer, thereby increasing the response speed of the TFT. The TFT further includes a gate structure 121A placed on top of the channel layer stack, the gate structure includes one or more gate electrodes 108, and the TFT is a top-gate (TG), double-gate (DG), or bottom-gate (BG) TFT. The channel layer stack includes multiple layers having different mobilities. Layers having different mobilities bring various advantages to the TFT. The high-mobility layer increases the response speed of the TFT.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to devices in general, and more specifically to thin-film transistors. [Background technology]

[0002]

[0002] A thin-film transistor (TFT) is a type of metal-oxide-semiconductor field-effect transistor (MOSFET) made by depositing a thin film of an active semiconductor layer, a dielectric layer, and metal contacts on a support substrate. One application of TFTs is liquid crystal displays (LCDs), so the substrate is typically glass.

[0003]

[0003] TFTs have attracted considerable interest in display applications due to their high resolution, low power consumption, and fast operation in LCD and organic light-emitting diode (OLED) displays. TFTs are embedded in the display panel. Data line and gate line voltage signals from the display module of the display system are sent to the TFTs in the pixel circuit and / or gate driver circuit of the peripheral display panel area, switching the TFTs on and off to control the displayed image. Image distortion is reduced by improving the response of the TFTs with higher mobility and / or by reducing crosstalk between pixels. Most display products, including LCD televisions (TVs) and monitors, include TFTs in the panel. Many of the latest high-resolution, high-quality electronic visual display devices use active matrix-based displays with a large number of TFTs. One of the beneficial aspects of TFT technology is the use of a separate TFT for each pixel on the display. Each TFT acts as a switch or current source for the pixel circuit or gate driver circuit by controlling voltage and current via data and gate signal lines to improve control of the displayed image. Higher on-current from high-mobility TFTs enables faster refresh rates and better image quality by minimizing distortion in data and gate signal voltages.

[0004]

[0004] One drawback of TFTs in the current art is that the on-current may become unacceptably low due to low channel mobility, which may limit the response speed of the TFT, especially in the case of high-resolution and / or large-screen displays. To allow for a sufficient on-current for fast response, it is often desirable to use a high-mobility channel in the TFT. However, high-mobility TFTs typically have an unacceptably large off-leakage current and a negative threshold voltage (such as turn-on voltage) compared to low-mobility TFTs due to their highly conductive channel characteristics. In the case of a positive threshold voltage for the TFT, the carrier concentration in the semiconductor channel at the interface between the gate insulator and the semiconductor channel may be reduced, thereby reducing the mobility. Therefore, it can be difficult to achieve both high mobility and a positive threshold voltage in a TFT. Finally, TFTs in the current art may have an unacceptably large off-leakage current and a negative threshold voltage due to a high carrier concentration in the channel semiconductor, which can increase the power consumption of the display panel and cause malfunction of the display panel.

[0005]

[0005] Therefore, what is needed in the current art is an improved channel mobility for TFTs with a low off-leakage current and a positive threshold voltage (e.g., turn-on voltage).

SUMMARY OF THE INVENTION

[0006]

[0006] Embodiments herein include a thin-film transistor including a channel layer stack having layers with different mobilities. The thin-film transistor (TFT) disclosed herein transports a larger total current through both the low-mobility and high-mobility channel layers and / or through the high-mobility channel layer due to a higher carrier density in the high-mobility channel layer, thereby increasing the response speed of the TFT since the on-current of the TFT is larger.

[0007]

[0007] In one embodiment, a device is provided. The device includes a substrate, a multilayer semiconductor channel of a first thin film transistor (TFT) disposed on the substrate, a first gate insulator layer disposed on the multilayer semiconductor channel, a first gate electrode disposed on the first gate insulator layer, an interlayer dielectric (ILD) layer disposed on the first gate electrode, a first source electrode contacting the multilayer semiconductor channel, and a first drain electrode contacting the multilayer semiconductor channel. The multilayer semiconductor channel includes one or more stacks of two layers having alternating electron mobilities. The two layers include a first layer having a first electron mobility of less than about 20 cm 2 / Vs and a second layer contacting the first layer. The second layer has a second electron mobility greater than about 20 cm 2 / V·s. The first TFT has an electron mobility of from about 35 cm 2 / V·s to about 70 cm 2 / Vs. The first layer is in contact with the first gate insulator layer of the first TFT. The first source electrode is disposed within a first source electrode via of the ILD layer. The first drain electrode is disposed within a first drain electrode via of the ILD layer. The first TFT has a threshold voltage of from about -0.5V to about 2.5V.

[0008]

[0008] In another embodiment, a device is provided. The device includes a substrate, a multilayer semiconductor channel of a first thin film transistor (TFT) disposed on the substrate, a first gate insulator layer disposed on the multilayer semiconductor channel, a first gate electrode disposed on the first gate insulator layer, a first bottom gate electrode disposed on the substrate, an interlayer dielectric (ILD) layer disposed on the first gate electrode, a first source electrode contacting the multilayer semiconductor channel, and a first drain electrode contacting the multilayer semiconductor channel. The multilayer semiconductor channel includes one or more stacks of two layers having alternating electron mobilities. The two layers include a first layer having a first electron mobility of less than about 20 cm 2 / Vs and a second layer contacting the first layer. The second layer has a second electron mobility greater than about 20 cm 2 / V·s. The first TFT has an electron mobility of from about 35 cm2 from about 70 cm / V·s 2 has an electron mobility of / Vs. The first layer of the topmost stack of one or more stacks is in contact with the first gate insulator layer of the first TFT. The first source electrode is disposed within the first source electrode via of the ILD layer. The first drain electrode is disposed within the first drain electrode via of the ILD layer. The first TFT has a threshold voltage from about -0.5V to about 2.5V.

[0009]

[0009] In yet another embodiment, a device is provided. The device includes a substrate, an interlayer dielectric (ILD) layer disposed on the substrate, a first thin film transistor (TFT), and a second TFT. The first TFT includes a multilayer semiconductor channel disposed on the substrate, the multilayer semiconductor channel including one or more stacks of two layers having alternating electron mobilities, the two layers including a first layer having a first electron mobility of less than about 20 cm / Vs and a second layer contacting the first layer and having a second electron mobility greater than about 20 cm / V·s, a first bottom gate electrode disposed on the substrate, a first bottom insulator layer disposed on the first bottom gate electrode, a first source electrode electrically contacting the multilayer semiconductor channel, and a first drain electrode electrically contacting the multilayer semiconductor channel. The first TFT has a threshold voltage from about -0.5V to about 2.5V. 2 a first layer having a first electron mobility of less than about 20 cm / Vs, and a second layer contacting the first layer and having a second electron mobility greater than about 20 cm / V·s 2 a multilayer semiconductor channel, a first bottom gate electrode disposed on the substrate, a first bottom insulator layer disposed on the first bottom gate electrode, a first source electrode electrically contacting the multilayer semiconductor channel, and a first drain electrode electrically contacting the multilayer semiconductor channel. The first TFT has a threshold voltage from about -0.5V to about 2.5V. The second TFT includes a single layer semiconductor channel disposed on the substrate, the single layer semiconductor channel having an electron mobility of less than about 20 cm / Vs, a second bottom gate electrode disposed on the substrate, a second bottom insulator layer disposed on the second bottom gate electrode, a second source electrode electrically contacting the single layer semiconductor channel, and a second drain electrode electrically contacting the second semiconductor channel. The first TFT has an electron mobility from about 35 cm / V·s 2 to about 70 cm / Vs. The first TFT has a threshold voltage from about -0.5V to about 2.5V. The second TFT has a threshold voltage from about -0.5V to about 2.5V. 2 to about 70 cm / V·s 2 has an electron mobility of / Vs. The first TFT has a threshold voltage from about -0.5V to about 2.5V.

[0010]

[0010] In order to allow for a more detailed understanding of the above-mentioned features of the present disclosure, a more specific description of the present disclosure, which has been briefly summarized above, may be given by reference to some embodiments shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered to limit their scope, and other equally effective embodiments may be permitted. [Brief explanation of the drawing]

[0011] [Figure 1A] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 1B] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 1C] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 1D] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 2A] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 2B] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 2C] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 2D] Schematic side views of thin-film transistors according to several embodiments are shown. [Figure 3A] Schematic side views of the device according to several embodiments are shown. [Figure 3B] Schematic side views of the device according to several embodiments are shown. [Figure 3C] Schematic side views of the device according to several embodiments are shown. [Figure 3D] Schematic side views of the device according to several embodiments are shown. [Figure 3E] Schematic side views of the device according to several embodiments are shown. [Figure 3F] Schematic side views of the device according to several embodiments are shown. [Figure 3G] Schematic side views of the device according to several embodiments are shown. [Modes for carrying out the invention]

[0012]

[0014] For ease of understanding, the same reference numerals are used to indicate identical elements common to the figures where possible. Elements and features of one embodiment are intended to be usefully incorporated into other embodiments without further enumeration.

[0013]

[0015] Embodiments of this specification include thin-film transistors (TFTs) comprising a channel layer stack having layers with different mobilities. The TFTs disclosed herein transport a larger total current through both the low-mobility and high-mobility channel layers, and / or through the high-mobility channel layer, due to the higher carrier density in the high-mobility channel layer, thereby increasing the response speed of the TFT due to a larger on-current of the TFT. The TFT further includes a gate structure disposed on top of the channel layer stack. Since the gate structure includes one or more gate electrodes, the TFT is a top-gate (TG), double-gate (DG), or bottom-gate (BG) TFT. The channel layer stack comprises multiple layers having different mobilities. Layers with different mobilities provide various advantages to the TFT. High-mobility layers increase the response speed of the TFT. Low-mobility layers allow for a positive threshold voltage (turn-on voltage) and lower leakage current than the high-mobility layers of the same TFT. The combination of low-mobility and high-mobility layers, as described herein, results in a TFT with improved quality, such as improved mobility, lower off-leak current, and a positive threshold voltage (turn-on voltage). Furthermore, a channel layer stack has effective mobility due to the combination of layers within it. The embodiments disclosed herein may be useful for TFTs comprising a channel layer stack with layers having different mobilities, but are not limited thereto.

[0014]

[0016] Where used herein, the term “approximately” refers to a variation of + / - 10% from the stated value. It should be understood that such variation may be included in any value provided herein.

[0015]

[0017] Figures 1A to 1D and 2A to 2D show schematic cross-sectional views of TFTs according to several embodiments. Any of the TFTs described herein are configured to operate as conventional transistors in conventional circuits. Any of the TFTs described herein may be incorporated into a device.

[0016]

[0018] Figure 1A shows a schematic cross-sectional view of TFT100A according to one embodiment. TFT100A can be considered a top-gate (TG) TFT. As shown, TFT100A includes a substrate 101, a gate structure 121A, a channel layer stack (or referred to as a semiconductor channel) 104A, and an interlayer dielectric (ILD) layer 110, a source electrode 112, and a drain electrode 114.

[0017]

[0019] The substrate 101 may include any suitable material such as a silicon-based substrate, a semiconductor-based substrate, an insulating-based substrate, or a germanium-based substrate, and may generally include one or more common layers present in complementary metal-oxide-semiconductor (CMOS) device structures. The substrate 101 may include a transparent material such as rigid glass or flexible polyimide (PI), which may be useful when the TFT is used in LCD or OLED display applications such as televisions, tablets, laptops, mobile phones, or other displays.

[0018]

[0020] In some embodiments, a buffer layer 102 is placed on the substrate 101, and a channel layer stack 104A is placed on top of the buffer layer 102. The ILD layer 110 is placed on at least the channel layer stack 104A, the buffer layer 102, and the gate structure 121A. The source electrode 112 is placed in the source electrode via 116 of the ILD layer 110. The drain electrode 114 is placed in the drain electrode via 118 of the ILD layer 110.

[0019]

[0021] The gate structure 121A is located on top of the channel layer stack 104A. The gate structure 121A is configured to regulate the voltage within the channel layer stack 104A. As shown, the gate structure 121A includes an insulator layer (or referred to as the gate insulator layer) 106 and a gate electrode 108. The insulator layer 106 may contain silicon dioxide. The gate electrode 108 is configured to be connected to the gate line signal as a power source (not shown) for supplying voltage to the channel layer stack 104A. The gate electrode 108 is located on top of the insulator layer 106. The gate electrode 108 contains a conductive material.

[0020]

[0022] The buffer layer 102 may include insulating materials such as single silicon dioxide (SiOx), silicon nitride (SiNx), multilayer silicon nitride / silicon oxide (SiNx / SiOy), silicon oxynitride (SiON), other insulating materials, or combinations thereof. The ILD layer 110 may include insulating materials such as SiOx, SiNx, other insulating materials, or combinations thereof (including SiOy / SiNx). The insulator layer 106 may include insulating materials such as silicon, SiNx, other insulating materials, or combinations thereof. The gate electrode 108, source electrode 112, and drain electrode 114 each contain a conductive material such as alloy metals including molybdenum (Mo), chromium (Cr), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), and MoW; combinations of conductive materials including MoW, TiCu, MoCu, MoCuMo, TiCuTi, MoWCu, and MoWCuMoW; any conductive material including conductive metal oxides such as indium tin oxide (InSnO) [ITO] and indium zinc oxide (InZnO) [IZO]; or any combination thereof.

[0021]

[0023] The channel layer stack 104A is disposed on the substrate 101. The channel layer stack 104A includes one or more layers 105. In embodiments where the channel layer stack 104A includes multiple layers 105, the channel layer stack 104A may be called a multilayer channel layer stack (or multilayer semiconductor channel). In embodiments where the channel layer stack 104A includes one layer 105, the channel layer stack 104A may be called a single-layer channel layer stack (or single-layer semiconductor channel).

[0022]

[0024] Layer 105 includes any material that allows electrons and / or holes to be conducted, as will be shown in more detail below. One or more layers 105 may include two layers having alternating mobilities, such as a first layer 105A placed on top of the buffer layer 102 and a second layer 105B placed below the first layer. According to one embodiment, the first layer 105A has a greater mobility than the second layer 105B. According to one embodiment, the first layer 105A has a smaller mobility than the second layer 105B. A combination of multiple layers 105 can be approximately 1 cm 2 / Vs to approximately 70cm 2 / Vs, for example, about 25cm 2 / Vs is approximately 45cm 2 / Vs, for example, about 25cm 2 / Vs is approximately 35cm 2 / Vs, or approximately 35cm 2 / Vs is approximately 45cm 2 This results in a channel layer stack 104A with an effective mobility of / Vs.

[0023]

[0025] In embodiments where the first layer 105A has a higher mobility than the second layer 105B, the first layer 105A conducts most of the current through the channel layer stack 104A, thereby allowing the channel layer stack to conduct current effectively due to the high mobility of the first layer 105A. In these embodiments, the TFT may have a higher off-leak current and a negative threshold voltage due to the higher carrier density at the interface between the insulating layer 106 and the high-mobility channel (e.g., the second layer 105B). By suppressing the carrier density near the insulating layer 106, a lower off-leak current and a positive threshold voltage can be obtained, which may reduce the mobility of the channel layer stack 104A. Thus, there is a trade-off between mobility and threshold voltage / off-leak current. The combination of multiple layers 105 is approximately 20 cm². 2This results in a channel layer stack 104A with an effective mobility greater than / V·s. For example, the threshold voltage of TFT100A, where the width-to-length ratio (W / L = 40um / 10um) is approximately 4, is approximately -1.0V to approximately 1.0V, and the drain-source current is equal to the gate-source voltage (V GS ) is approximately -20V to approximately 20V, drain-source voltage (V DS The voltage is approximately 1V, and the current ranges from approximately 1E-12A to approximately 8E-5A. The mobility of the channel layer stack 104A is approximately 25cm. 2 / Vs is approximately 35cm 2 / Vs is the case.

[0024]

[0026] In embodiments where the first layer 105A has a lower mobility than the second layer 105B, the second layer 105B conducts most of the current through the channel layer stack 104A, thereby allowing the channel layer stack to effectively conduct current due to the high mobility of the second layer 105B. Furthermore, the lower mobility of the first layer 105A allows for reduced leakage current and a more positive threshold voltage (turn-on voltage) compared to a TFT with only high-mobility layers. Thus, higher effective mobility can be easily obtained along with lower off-leak current and a positive threshold voltage. The combination of multiple layers 105 is 20cm². 2 This results in a channel layer stack 104A having an effective mobility greater than / V·s. According to one embodiment, the first layer 105A is about 20 cm 2 Having a mobility of less than / V·s, the second layer 105B is approximately 20cm 2 It has a mobility greater than / V·s. For example, the threshold voltage of a TFT100A with a width (W) to length (L) ratio (W / L = 40um / 10um) of approximately 4 is approximately -0.5V to approximately 2.5V, and the drain-source current is equal to the gate-source voltage (V GS ) is approximately -20V to approximately 20V, drain-source voltage (V DS The voltage is approximately 1V, the current is approximately 1E-13A to approximately 1E-4A, and the mobility is approximately 35cm. 2 / Vs to approximately 70cm 2 / Vs is the case.

[0025]

[0027] Generally, all of the TFTs disclosed herein are approximately 35 cm². 2 / V·s to approximately 70cm 2 Electron mobility of / Vs, threshold voltage of approximately -0.5V to approximately 2.5V, and gate-source voltage of approximately -20V to approximately 20V (V GS ) has a drain-source current of approximately 1E-13A to approximately 1E-4A.

[0026]

[0028] Figure 1B shows a schematic cross-sectional view of TFT100B according to one embodiment. TFT100B is similar to TFT100A (Figure 1A), except that TFT100B includes channel layer stack 104B instead of channel layer stack 104A. TFT100B can be considered a TG TFT.

[0027]

[0029] As shown, the channel layer stack 104B includes multiple layers 105, including a first layer 105A, a second layer 105B, and a third layer 105C. The third layer 105C is located above the buffer layer 102 and below the second layer 105B. As shown in Figure 1B, the first layer 105A is in direct contact with the second layer 105B. In other embodiments, there are one or more additional layers located between the first layer 105A and the second layer 105B.

[0028]

[0030] The multiple layers 105, according to some embodiments, include an odd number of layers such as three layers 105A, 105B, and 105C shown in Figure 1B. According to one embodiment, the first layer 105A has lower mobility than the second layer 105B, the third layer 105C has lower mobility than the second layer 105B, the second layer 105B is located closer to the buffer layer 102 than the first layer 105A, and the third layer 105C is located closer to the buffer layer 102 than the second layer 105B. The first layer 105A can have the same, greater, or less mobility than the third layer 105C. According to one embodiment, each of layers 105A, 105B, and 105C contains indium (In). According to one embodiment, the first layer 105A and the third layer 105C are about 20 cm2 Having a mobility of less than / V·s, the second layer 105B is approximately 20cm 2 It has a mobility greater than / V·s.

[0029]

[0031] Due to band bending between the second layer 105B and the first layer 105A, and between the second layer 105B and the third layer 105C, electrons are restricted to the second layer 105B. Band bending is caused by differences in the band gap and / or upper valence band (VBM) between the first layer 105A and the second layer 105B, and / or between the second layer 105B and the third layer 105C. The increase in the number of electrons contained in the second layer 105B increases the free charge density of the second layer, and increases the current from the source electrode 112 to the drain electrode 114.

[0030]

[0032] While the TFTs 100A and 100B described herein each contain two layers 105A, 105B and three layers 105A, 105B, and 105C, respectively, it should be understood that the channel layer stacks 104A and 104B can contain any number of layers. For example, the channel layer stacks 104A and 104B may, in certain embodiments, contain four, five, six, or even more layers 105. The layers 105 are arranged alternately such that each layer has a different mobility than the adjacent layer. For example, the layers 105 alternate between relatively high mobility and relatively low mobility, as will be described in more detail below.

[0031]

[0033] According to one embodiment, the plurality of layers 105 include two high-mobility layers and three low-mobility layers, with the high-mobility layers positioned between adjacent low-mobility layers. Band bending between the low-mobility and high-mobility layers restricts electrons to the high-mobility layers. Increasing the number of electrons contained in the high-mobility layers increases the free charge density of the high-mobility layers, thereby increasing the current from the source electrode 112 to the drain electrode 114. Furthermore, using multiple high-mobility layers further increases the current from the source electrode 112 to the drain electrode 114.

[0032]

[0034] Figure 1C shows a schematic side view of TFT100C according to one embodiment. TFT100C is similar to TFT100A (Figure 1A), except that TFT100C includes gate structure 121B instead of gate structure 121A. TFT100C can be considered a double-gate (DG) TFT.

[0033]

[0035] The gate structure 121B is located above and below the channel layer stack 104A, as described in detail below. The gate structure 121B is configured to regulate the voltage within the channel layer stack 104A. As shown, the gate structure includes an insulator layer 106, a gate electrode 108, a bottom insulator layer 130, and a bottom gate electrode 131. Both the gate electrode 108 and the bottom gate electrode 131 are configured to be connected to one or more gate signal lines as power sources (not shown) for supplying voltage to the channel layer stack 104A. The same gate signal line or two different gate signal lines can be connected to the bottom gate electrode 131 and the gate electrode 108. The gate electrode 108 is located above the insulator layer 106. The bottom insulator layer 130 and the bottom gate electrode 131 are located above the buffer layer 102. The bottom insulator layer 130 may contain silicon dioxide. The bottom gate electrode 131 contains a conductive material. The gate structure 121B, which includes both the gate electrode 108 and the bottom gate electrode 131, enables a higher carrier density in the channel layer stack 104A, increasing mobility and the current flowing through it.

[0034]

[0036] As shown in Figure 1C, the length L of the bottom gate electrode 131 The length L of the gate electrode 106 It is almost the same as the above. In this embodiment, the length L of the bottom gate electrode 131 This increases the operating speed of the TFT100C and reduces parasitic capacitance.

[0035]

[0037] Figure 1D shows a schematic side view of TFT100D according to one embodiment. TFT100D has a bottom gate electrode length L 131The length L of the channel layer stack 104 It is similar to TFT100C (Figure 1C) except that it is almost the same. Therefore, the length L of the bottom gate electrode is 131 The length L of the gate electrode 106 It is longer than [this]. Increasing the length of the bottom gate electrode increases the parasitic capacitance compared to TFT100C shown in Figure 1C, which may reduce the operating speed of TFT100D. However, the increased length L of the bottom gate electrode 131 This can block unwanted light irradiation on the channel layer stack 104A.

[0036]

[0038] Figure 2A shows a schematic side view of TFT200A according to one embodiment. TFT200A is similar to TFT100C in Figure 1C, except that TFT200A includes a different gate structure 221A. Gate structure 221A includes a bottom gate electrode 131. The bottom gate electrode 131 is configured to be connected to the gate signal as a power source (not shown) for supplying voltage to the channel layer stack 104A. As shown in Figure 2A, the source electrode 212 and drain electrode 214 are placed directly on the channel layer stack 104A without using source electrode vias or drain electrode vias. TFT200A can be considered a bottom gate (BG) TFT.

[0037]

[0039] Figure 2B shows a schematic side view of TFT200B according to one embodiment. TFT200B is similar to TFT200A in Figure 2A, except that TFT200B includes a different gate structure 221B. Gate structure 221B further includes a top gate electrode 240. The bottom gate electrode 131 and the top gate electrode 240 are configured to be connected to one or more gate signal lines as a power source (not shown) for supplying voltage to the channel layer stack 104A. The same gate signal line or two different gate signal lines can be connected to the bottom gate electrode 131 and the top gate electrode 240. The top gate electrode 240 includes a conductive material. TFT200B can be considered a DG TFT.

[0038]

[0040] Figure 2C shows a schematic side view of TFT200C according to one embodiment. TFT200C is similar to TFT200A in Figure 2A, except that TFT200A includes a different gate structure 221C. The gate structure 221C includes a bottom gate electrode 131. As shown in Figure 2C, the source electrode 112 and drain electrode 114 are connected to the channel layer stack 104A by source electrode via 116 and drain electrode via 118. TFT200C can be considered a BG TFT. The bottom gate electrode 131 is configured to be connected to a gate signal line as a power source (not shown) for supplying voltage to the channel layer stack 104A.

[0039]

[0041] Figure 2D shows a schematic side view of a TFT200D according to one embodiment. The TFT200D is similar to the TFT200C in Figure 2A, except that the TFT200D includes a different gate structure 221D. The gate structure 221D further includes a bottom gate electrode 131 and a top gate electrode 240. As shown in Figure 2D, the source electrode 112 and drain electrode 114 are connected to the channel layer stack 104A by source electrode vias 116 and drain electrode vias 118. The TFT200D can be considered a DG TFT. The bottom gate electrode 131 and top gate electrode 240 are configured to be connected to one or more gate signal lines as a power source (not shown) to supply voltage to the channel layer stack 104A. The same gate signal line or two different gate signal lines can be connected to the bottom gate electrode 131 and top gate electrode 240.

[0040]

[0042] Figure 3A shows a schematic side view of device 300A according to one embodiment. As shown, device 300A includes a first TFT 301A and a second TFT 301B. As shown, the first TFT 301A includes a gate structure 321A. The first TFT 301A is similar to TFT 100A in Figure 1A. The channel layer stack 304B is similar to channel layer stack 104A. As shown, the second TFT 301B includes a gate structure 321B. The second TFT 301B is similar to TFT 100A in Figure 1A, but the second TFT 301B includes a channel layer stack 304B. As shown, the channel layer stack 304B includes a first layer 105A. In the second TFT301B, layer 105A from the channel layer stack 304B may be the same layer as, or a different layer from, the first layer 105A from the channel layer stack 104A in the first TFT301A.

[0041]

[0043] Figure 3B shows a schematic side view of device 300B according to one embodiment. As shown, device 300B includes a first TFT 301C and a second TFT 301D. As shown, the first TFT 301C includes a gate structure 321C. The first TFT 301C is similar to TFT 301A in Figure 3A. However, as shown, the second TFT 301D includes a gate structure 321D. The gate structures 321C and 321D further include bottom gate electrodes 131A and 131B, respectively.

[0042]

[0044] Figure 3C shows a schematic side view of device 300C according to one embodiment. As shown, device 300C includes a first TFT 301E and a second TFT 301F. As shown, the first TFT 301E includes a gate structure 321E. The first TFT 301E is similar to TFT 301A in Figure 3A. As shown, the second TFT 301F includes a gate structure 321F. The gate structures 321E and 321F further include a second insulating layer 306 disposed between the insulating layer 106 and the gate electrode 108. The second insulating layer 306 may include any of the materials disclosed above in the insulating layer 106.

[0043]

[0045] Figure 3D shows a schematic side view of device 300D according to one embodiment. As shown, device 300D includes a first TFT 301G and a second TFT 301H. As shown, the first TFT 301G includes a gate structure 321G. The first TFT 301G is similar to TFT 301A in Figure 3A, except that the first TFT 301G includes a channel layer stack 104C. As shown, the channel layer stack 104C further includes an insulating layer 106 located beneath the second layer 105B. As shown, the second TFT 301H includes a gate structure 321H. The gate structure 321H further includes a second insulating layer 306 located between the insulating layer 106 and the gate electrode 108.

[0044]

[0046] Figure 3E shows a schematic side view of device 300E according to one embodiment. As shown, device 300E includes a first TFT 301I and a second TFT 301J. As shown, the first TFT 301I includes a gate structure 221A. The first TFT 301I is similar to TFT 200A in Figure 2A. As shown, the second TFT 301J includes a gate structure 221A. The second TFT 301J is similar to TFT 200A in Figure 2A, except that TFT 301J includes a channel layer stack 304B (i.e., the channel layer stack 304B includes a first layer 105A). The first layer 105A of the channel layer stack 304B is a low-mobility layer (described below). The source electrodes 212A and 212B and the drain electrodes 214A and 214B are in electrical contact with the channel layer stacks 304A and 304B, respectively.

[0045]

[0047] In some embodiments, one or both of the TFTs 301I and 301J further include top gate electrodes (e.g., top gate electrode 240A and / or top gate electrode 240B) positioned on the ILD layer 110.

[0046]

[0048] Figure 3F shows a schematic side view of device 300F according to one embodiment. As shown, device 300F includes a first TFT 301K and a second TFT 301L. As shown, the first TFT 301K includes a gate structure 321C. The first TFT 301K is similar to TFT 301C in Figure 3B. As shown, the second TFT 301L includes a gate structure 321A. The second TFT 301L is similar to the second TFT 301B in Figure 3A. In some embodiments, the first TFT 301K includes a gate structure 321A instead of gate structure 321C, and the second TFT includes a gate structure 321C instead of gate structure 321A.

[0047]

[0049] In some embodiments, the first layer 105A from the channel layer stack 304A in the first TFT 301K is different from the first layer 105A from the channel layer stack 304B in the second TFT 301L. In some embodiments, the first layer 105A of the first TFT 301K is a high-mobility layer (described below), and the first layer 105A of the second TFT 301L is a low-mobility layer (described below). In some embodiments, the first layer 105A of the first TFT 301K is a low-mobility layer, and the first layer 105A of the second TFT 301L is a high-mobility layer.

[0048]

[0050] Figure 3G shows a schematic side view of device 300G according to one embodiment. As shown, device 300G includes a first TFT 301M and a second TFT 301N. As shown, the first TFT 301M includes a gate structure 221A. The first TFT 301M is similar to TFT 200A in Figure 2A. As shown, the second TFT 301N includes a gate structure 221A.

[0049]

[0051] In some embodiments, the first layer 105A from the channel layer stack 304A in the first TFT 301M is different from the first layer 105A from the channel layer stack 304B in the second TFT 301N. In some embodiments, the first layer 105A of the first TFT 301M is a high-mobility layer (described below), and the first layer 105A of the second TFT 301N is a low-mobility layer (described below). In some embodiments, the first layer 105A of the first TFT 301M is a low-mobility layer, and the first layer 105A of the second TFT 301N is a high-mobility layer. In some embodiments, one or both of the TFTs 301M and 301N include a top gate electrode (not shown) located on top of the ILD layer 110.

[0050]

[0052] While the TFTs disclosed herein are shown as including a specific channel layer stack (e.g., channel layer stack 104A) and / or (e.g., gate structure 121A), it should be understood that a TFT may instead include any channel layer stack and / or any gate structure disclosed herein. In other words, the channel layer stack of a TFT may include one, two, three, four, five, six, or more individual layers 105. The layers 105 are alternating such that each layer has a different mobility than the adjacent layer. For example, the layers 105 alternate between relatively high mobility and relatively low mobility, as will be described in more detail below. Furthermore, any channel layer stack may further include a first insulating layer 106 and / or a second insulating layer 306. Furthermore, any gate structure described herein may be included in any disclosed TFT, and therefore each TFT may be a TG, BG, or DG TFT.

[0051]

[0053] In any of the embodiments described above, the TFTs share a substrate 101. In some embodiments, the two-gate structure further includes a buffer layer 102, and the two TFTs share the buffer layer. It should be understood that any of the two-gate structures disclosed herein may include a buffer layer 102. The two TFTs in each two-gate structure are used as a pixel circuit in an LCD or OLED display, or in an in-panel gate driver (GIP) circuit. For example, each TFT in a two-gate structure can be used as a switching or driving TFT in an OLED pixel circuit.

[0052]

[0054] In one embodiment, which can be combined with other embodiments described herein, each of the layers 105 (e.g., layers 105A, 105B, and / or 105C) has a thickness of about 0.5 nm to about 50 nm. In another embodiment, which can be combined with other embodiments described herein, the mobility of each layer 105 is about 20 cm². 2 Larger than / V·s, or about 20cm2 It is either less than / V·s. For example, channel layer stack 104B contains alternating layers 105, each layer being approximately 20 cm². 2 Mobility greater than / V·s (referred to as the high-mobility layer in this specification) and approximately 20cm 2 It alternates between layers with mobilities smaller than / V·s (referred to as low-mobility layers in this specification). 20cm 2 The mobility of / V·s is an example, and it is understood that any high-mobility layer having a relatively higher mobility than the corresponding low-mobility layer is covered by the disclosure herein.

[0053]

[0055] In one embodiment, which can be combined with other embodiments described herein, the high-mobility layer and the low-mobility layer have substantially the same material composition. In another embodiment, which can be combined with other embodiments described herein, the high-mobility layer and the low-mobility layer have different material compositions.

[0054]

[0056] In one embodiment, which can be combined with other embodiments described herein, the high-mobility layer and / or low-mobility layer comprises indium (In), zinc (Zn), gallium (Ga), oxygen (O), tin (Sn), aluminum (Al), and / or hafnium (Hf). Examples of high-mobility layers include, but are not limited to, In-Ga-Zn-O, In-Ga-O, In-Zn-O, In-Ga-Sn-O, In-Zn-Sn-O, In-Ga-Zn-Sn-O, In-Sn-O, Hf-In-Zn-O, Ga-Zn-O, In-O, Al-Sn-Zn-O, Zn-O, Zn-Sn-O, Al-Zn-O, Al-Zn-Sn-O, Hf-Zn-O, Sn-O, and Al-Sn-Zn-In-O. Examples of low-mobility layers include, but are not limited to, In-Ga-Zn-O, Ga-O, In-Ga-O, Zn-Sn-O, In-Sn-O, Hf-In-Zn-O, Al-Sn-Zn-O, Zn-O, Al-In-Zn-Sn-O, and Al-Sn-Zn-O.

[0055]

[0057] In some embodiments, the materials for the high-mobility and low-mobility layers contain the same elements but have different material stoichiometry. For example, In-Ga-Zn-O is a multi-component amorphous oxide semiconductor (AOS) system that is commercially used in the mass production of LCD and OLED display products. In-Ga-Zn-O has a ratio of In-O, Ga-O, and Zn-O of 1:1:1 and is typically about 10 cm³. 2 The mobility value is / V·s, but by increasing the In composition and / or decreasing the Ga composition from the In-Ga-Zn-O AOS system, it can be increased to 10 cm 2 It is also possible to achieve mobilities greater than / V·s. Therefore, the mobility can be adjusted by changing the composition of the components in the AOS system. Zn-O or In-O without Ga in the AOS system allows for higher mobility (higher carrier concentration), but it can be difficult to obtain the amorphous phase. However, binary compositions such as Zn-In-O or Zn-Ga-O can form the amorphous phase because the composition of Zn-O and In-O changes. High mobility (>20cm²) 2 For / V·s)AOS, the carrier concentration can be increased by increasing the In composition and / or decreasing the Ga composition from the multi-component AOS system. Thus, in one embodiment, the low-mobility layer contains In-Ga-Zn-O, the high-mobility layer contains In-Ga-Zn-O, and the high-mobility layer has a higher In composition than the low-mobility layer. In another embodiment, the low-mobility layer contains In-Ga-Zn-O, the high-mobility layer contains In-Ga-Zn-O, and the high-mobility layer has a lower Ga composition than the low-mobility layer. In yet another embodiment, the low-mobility layer contains In-Ga-Zn-O, the high-mobility layer contains In-Ga-Zn-O, the high-mobility layer has a higher In composition than the low-mobility layer, and the high-mobility layer has a lower Ga composition than the low-mobility layer.

[0056]

[0058] It should be understood that the composition of In, Ga, Zn, and O can easily change the electron transport properties (e.g., mobility). For example, the electron transport properties (mobility, etc.) of an In2O3-Ga2O3-ZnO (In-Ga-Zn-O) thin film are determined by the composition of In2O3, Ga2O3, and ZnO by changing X, Y, and Z, where X is [(ZnO) X -(Ga2O3) 1-X Defined in mol%, Y is [(Ga2O3) Y -(In2O3) 1-Y Defined in mol%, where Z is (In2O3) Z -(ZnO) 1-Z It is defined as mol%. In the In-Ga-Zn-O system, the In atoms contained therein form electron pathways. 3+ It is generally understood that it acts as an ion, resulting in high electron mobility. Furthermore, the Zn atoms contained therein prefer tetrahedral coordination. 2+ It is understood that it acts as an ion, increasing the stability of the amorphous phase of In-Ga-Zn-O. Finally, the Ga atoms contained therein are Ga 3+ Ga suppresses carrier generation due to the high ion field strength of ions. 3+ It is understood to act as an ion. Ga 3+ Ions form stronger chemical bonds with oxygen atoms than with zinc and in atoms due to the formation of oxygen vacancies. Therefore, increasing the percentage of Ga leads to lower mobility and / or carrier concentration, and thus layers with a higher percentage of Ga have lower off-currents and a higher on / off current ratio.

[0057]

[0059] When X=Y=Z=0.5, In-Ga-Zn-O is approximately 9cm. 2Enables a mobility of / V·s. By reducing Ga and increasing In, higher mobility can be controlled. For example, when X = 1, Y = 0, Z = 1, the composition is In-O. When X = 1, Y = 0, Z = 0, the composition is Zn-O. However, In-O and Zn-O form a crystalline phase. When X = 1, Y = 0, 0 < Z < 1, the composition is In-Zn-O. Therefore, In-Zn-O has an amorphous phase and a mobility greater than about 20 cm 2 / V·s and can be a material for a high-mobility channel layer. In-Ga-Zn-O has an amorphous phase and a low mobility less than about 20 cm 2 / V·s and can be a material for a low-mobility channel layer.

[0058]

[0060] The AOS system can include In-Ga-Zn-O or other AOS including In-Zn-O, Zn-Sn-O, In-Ga-O, In-Zn-O, In-Ga-Sn-O, In-Zn-Sn-O, In-Ga-Zn-Sn-O, In-Sn-O, Hf-In-Zn-O, Ga-Zn-O, In-O, Al-Sn-Zn-O, Zn-O, Zn-Sn-O, Al-Zn-O, Al-Zn-Sn-O, Hf-Zn-O, Sn-O, Al-Sn-Zn-In-O, etc.

[0059]

[0061] As described above, a TFT is provided. The TFT includes a gate structure and a channel layer stack. The gate stack includes one or more gate structures, and thus the TFT is a TG, DG, or BG TFT. The channel layer stack includes a plurality of layers having different mobilities.

[0060]

[0062] The layers having different mobilities bring various advantages to the TFT. The high-mobility layer increases the response speed of the TFT. The low-mobility layer reduces the leakage current and enables a positive threshold voltage (turn-on voltage) in the TFT. The combination of the low-mobility layer and the high-mobility layer results in a TFT with improved qualities such as improved mobility, lower off-leakage current, and a positive threshold voltage (turn-on voltage), as described herein.

[0061]

[0063] While the foregoing is directed toward examples of the present disclosure, other further examples of the present disclosure may be devised without departing from its basic scope, the scope of which is determined by the following claims.

Claims

1. substrate, A multilayer semiconductor channel for a first thin-film transistor (TFT), wherein the multilayer semiconductor channel is disposed on the substrate, and the multilayer semiconductor channel includes one or more stacks of two layers having alternating electron mobilities, and the two layers are Approximately 20cm ２ A first layer having a first electron mobility less than / V·s, wherein the first layer of the uppermost stack of one or more stacks is in contact with the first gate insulator layer of the first TFT, and the first gate insulator layer is disposed on the multilayer semiconductor channel, and A second layer in contact with the first layer, wherein the second layer is approximately 20 cm ２ It has a second electron mobility greater than / V·s, and the first TFT is approximately 35 cm ２ / V.s to about 70cm ２ A second layer having an electron mobility of / V·s, Multilayer semiconductor channels, A first gate electrode disposed on the gate insulator layer, An interlayer dielectric (ILD) layer is disposed on the gate electrode, A first source electrode in contact with the semiconductor channel, the first source electrode disposed within the source electrode via of the ILD layer, and A first drain electrode in contact with the multilayer semiconductor channel, the first drain electrode disposed within the first drain electrode via of the ILD layer, A device comprising the first TFT having a threshold voltage of about -1.5V to about 2.5V.

2. A single-layer semiconductor channel of a second TFT disposed on the substrate, wherein the single-layer semiconductor channel is approximately 20 cm ２ A single-layer semiconductor channel having an electron mobility less than / V·s, wherein the layer of the single-layer semiconductor channel is in contact with the second gate insulator layer of the second TFT, and the second gate insulator layer is disposed on top of the single-layer semiconductor channel. A second gate electrode disposed on the second gate insulator layer, A second source electrode in contact with the single-layer semiconductor channel, the second source electrode disposed within the second source electrode via of the ILD layer, and A second drain electrode in contact with the single-layer semiconductor channel, the second drain electrode being disposed within the second drain electrode via of the ILD layer, The device according to claim 1, further comprising the second TFT having a threshold voltage of about -1.5V to about 2.5V.

3. The second TFT is A second bottom gate electrode disposed on the substrate, and A second bottom insulator layer is disposed on top of the second bottom gate electrode, The device according to claim 2, further comprising:

4. The first TFT is A first bottom gate, and disposed on the substrate, A first bottom insulator layer disposed on the first bottom gate electrode, The device according to claim 3, further comprising:

5. The first TFT is A first bottom gate, and disposed on the substrate, A first bottom insulator layer disposed on the first bottom gate electrode, The device according to claim 2, further comprising:

6. The device according to claim 1, wherein the multilayer semiconductor channel further includes one or more additional layers such that the total number of layers in the semiconductor channel is odd.

7. The device according to claim 1, wherein each of the two layers has a thickness of about 0.5 nm to about 50 nm.

8. substrate, A multilayer semiconductor channel of a first thin-film transistor (TFT) disposed on the substrate, wherein the multilayer semiconductor channel includes one or more stacks of two layers having alternating electron mobilities, and the two layers are Approximately 20cm ２ A first layer having a first electron mobility less than / V·s, wherein the first layer of the uppermost stack of one or more stacks is in contact with the first gate insulator layer of the first TFT, and the first gate insulator layer is disposed on the multilayer semiconductor channel, and A second layer in contact with the first layer, the second layer having a second electron mobility greater than about 20 cm ２ / V·s, and the first TFT having an electron mobility from about 35 cm ２ / V·s to about 70 cm ２ / V·s, the second layer Multilayer semiconductor channels, A first gate electrode disposed on the first gate insulator layer, A first bottom gate plate is placed on the substrate, A first bottom insulator layer disposed on the bottom gate electrode, An interlayer dielectric (ILD) layer disposed on the first gate electrode, A first source electrode in contact with the multilayer semiconductor channel, the first source electrode disposed within the first source electrode via of the ILD layer, and A first drain electrode in contact with the multilayer semiconductor channel, the first drain electrode disposed within the first drain electrode via of the ILD layer, A device comprising the first TFT having a threshold voltage of about -0.5V to about 2.5V.

9. A single-layer semiconductor channel of a second TFT disposed on the substrate, wherein the single-layer semiconductor channel is approximately 20 cm ２ A single-layer semiconductor channel having an electron mobility less than / V·s, wherein the single-layer semiconductor channel is in contact with the second gate insulator layer of the second TFT, and the second gate insulator layer is disposed on the single-layer semiconductor channel. A second gate electrode disposed on the second gate insulator layer, A second source electrode in contact with the single-layer semiconductor channel, the second source electrode disposed within the second source electrode via of the ILD layer, and A second drain electrode in contact with the single-layer semiconductor channel, the second drain electrode being disposed within the second drain electrode via of the ILD layer, The device according to claim 8, further comprising the second TFT having a threshold voltage of about -1.5V to about 2.5V.

10. A second bottom gate electrode disposed on the substrate, and A bottom insulator layer disposed on the second bottom gate electrode, The device according to claim 9, further comprising:

11. The device according to claim 8, wherein the multilayer semiconductor channel further includes one or more additional layers such that the total number of layers in the multilayer semiconductor channel is odd.

12. The device according to claim 8, wherein each of the aforementioned layers is a metal oxide-containing layer.

13. The device according to claim 12, wherein each of the layers comprises In-Zn-O, In-Sn-O, In-Zn-Sn-O, In-Ga-Zn-O, or any combination thereof.

14. The device according to claim 13, wherein the second layer has a lower atomic percentage of gallium (Ga) than the first layer.

15. substrate, An interlayer dielectric (ILD) layer is placed on the substrate. The first thin-film transistor (TFT) is, A multilayer semiconductor channel disposed on the substrate, wherein the multilayer semiconductor channel includes one or more stacks of two layers having alternating electron mobilities, and the two layers are Approximately 20cm ２ A first layer having a first electron mobility less than / V·s, wherein the first layer of the uppermost stack of the one or more stacks is in contact with the gate insulator layer of the TFT, and the gate insulator layer is located on the multilayer semiconductor channel, and A second layer in contact with the first layer, wherein the second layer is approximately 20 cm ２ It has a second electron mobility greater than / V·s, and the first TFT is approximately 35 cm ２ / V.s to about 70cm ２ A second layer having an electron mobility of / V·s, Multilayer semiconductor channels, A first bottom gate plate is placed on the substrate, A first bottom insulator layer disposed on the bottom gate electrode, The first source electrode, which is electrically in contact with the multilayer semiconductor channel, and A first drain electrode that is electrically in contact with the multilayer semiconductor channel, A first TFT having a threshold voltage of approximately -0.5V to approximately 2.5V, and The second TFT, A single-layer semiconductor channel disposed on the aforementioned substrate, approximately 20 cm ２ A single-layer semiconductor channel containing a layer having a first electron mobility smaller than / V·s, A second bottom gate electrode is placed on the aforementioned substrate, A second bottom insulator layer is disposed on top of the second bottom gate electrode, A second source electrode that is electrically in contact with the second semiconductor channel, and The second drain electrode is electrically in contact with the second semiconductor channel. A second TFT, which includes a threshold voltage of approximately -0.5V to approximately 2.5V, A device that includes this.

16. The first TFT is A first gate insulator layer disposed on the multilayer semiconductor channel, and A first gate electrode disposed on the first gate insulator layer, The device according to claim 15, further comprising:

17. The second TFT is A second gate insulator layer disposed on the single-layer semiconductor channel, and A second gate electrode disposed on the second gate insulator layer, The device according to claim 16, further comprising:

18. The device according to claim 15, wherein the bottom gate length of the first bottom gate electrode is longer than the gate length of the first gate electrode.

19. The device according to claim 15, wherein the first TFT further comprises a first top gate electrode disposed on the ILD layer.

20. The device according to claim 19, wherein the second TFT further comprises a second top gate electrode disposed on the ILD layer.

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