Semiconductor equipment

Abstract

To provide a transistor with good electrical characteristics. Or, to provide a transistor with stable electrical characteristics and a highly integrated semiconductor device. [Solution] In a semiconductor device, the transistor 100 includes a first insulator 103, an oxide semiconductor 104, a second insulator 105, a first conductor 106, a third insulator 108 formed on the side wall of the first conductor, a second conductor 109a and a third conductor 109b in contact with the upper surface of the oxide semiconductor, the side surface of the oxide semiconductor, and the side surface of the third insulator, a fourth insulator 110 in contact with the side surface of the second conductor and the side surface of the third conductor, and a fifth insulator 111 in contact with the upper surfaces of the fourth insulator, the second conductor and the third conductor, wherein the upper surface of the fourth insulator has a generally flat region, and the oxide semiconductor has a first region overlapping with the first conductor and a second region having lower resistance than the first region.

Description

[Technical Field]

[0001] One aspect of the present invention relates to transistors and semiconductor devices, and to methods for manufacturing them. ru.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. One aspect of the invention is a process, machine, manufacture, or composition. It concerns (of matter).

[0003] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of devices, including display devices (such as liquid crystal displays and light-emitting displays), lighting devices, and electro-optical devices. Energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices, etc., have semiconductor devices. There are cases where this occurs. [Background technology]

[0004] In recent years, transistors using oxide semiconductors have attracted attention. Oxide semiconductor films are... Because it can be formed using methods such as puttering, it can be used for transistors that make up large display devices. It can be used. In addition, transistors using oxide semiconductor films have high field effect transfer. Because it has a degree of precision, it is possible to realize a high-performance display device with an integrated drive circuit. Also, amorphous It is possible to modify and utilize some of the production equipment for transistors using silicon films. Therefore, there is also the advantage of being able to reduce capital investment.

[0005] Transistors using oxide semiconductors exhibit extremely low leakage current in the non-conductive state. It is known that the leakage current of an oxide semiconductor transistor is extremely high. Low-power CPUs and other technologies that take advantage of the characteristic of low power consumption have been disclosed (see Patent Document 1). . ) . [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2012-257187 [Overview of the project] [Problems that the invention aims to solve]

[0007] One of the challenges is to provide miniature transistors, or transistors with low parasitic capacitance. One of the objectives is to provide transistors. Alternatively, to provide transistors with high frequency characteristics. One of the objectives is to provide it. One of the objectives is to provide transistors with good electrical characteristics. One of the objectives is to provide a stable transistor, or a transistor with low power consumption. One of the objectives is to provide a transistor. Alternatively, to provide a transistor with good reliability. One of the objectives is to achieve this. Alternatively, one of the objectives is to provide a novel transistor. Alternatively, to provide a semiconductor device having at least one of these transistors. This will be one of the issues to address.

[0008] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title will become clear from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the drawings, claims, etc. [Means for solving the problem]

[0009] One aspect of the present invention comprises a first insulator, an oxide semiconductor on the first insulator, and an oxide semiconductor The upper second insulator, the first conductor on the second insulator, and the side adjacent to the first conductor A third insulator, the side surface of the oxide semiconductor, and a second conductive material in contact with the side surface of the third insulator. The body and the third conductor, and the side surface of the second conductor and the fourth in contact with the side surface of the third conductor An insulator and a fifth insulator in contact with the upper surfaces of the fourth insulator, the second conductor and the third conductor. A semiconductor device having the following: Here, the upper surface of the fourth insulator has a region that is generally flattened. The height of the upper ends of the second and third conductors is approximately equal to the height of the upper end of the fourth insulator. They closely match, the fourth insulator has excess oxygen, and the oxide semiconductor overlaps with the first conductor. It has a first region and a second region having lower resistance than the first region, and the first insulator and the second Insulator 5 has lower oxygen permeability than insulator 4.

[0010] In the above configuration, the third insulator is a side wall insulating layer, a side wall insulating film, or a side wall insulating film. It is sometimes called a wall. Also, in the above configuration, the semiconductor device is a transistor Preferably, the first conductor is the heat electrode of the transistor, and the second conductor The current body and the third conductor serve as the source electrode or drain electrode of the transistor, and the second The insulator is the gate insulator (also called the gate insulating film or gate insulating layer) of the transistor. It is preferable that it functions as (in some cases).

[0011] Furthermore, in the above configuration, the fourth insulator has an opening that reaches the first insulator, A fifth insulator is placed in the section, and the opening is an oxide semiconductor, a second insulator and a second It is preferable that the fifth insulator be arranged to surround the conductor on all four sides. Lower hydrogen permeability is preferable.

[0012] Furthermore, in the above configuration, at least one of the first insulator and the fifth insulator 1. Preferably, it has oxygen and aluminum. Also, in the above configuration, 2 The region may have a region that overlaps with the third insulator. Also, in the above configuration, the second The domains are tungsten, aluminum, titanium, magnesium, vanadium, and antimony. It may contain at least one of arsenic and sulfur.

[0013] Furthermore, in the above configuration, the semiconductor device has a sixth insulator, and the sixth insulator has a protrusion. It is preferable that the oxide semiconductor is formed in contact with the convex portion. The body consists of a first membrane, a second membrane in contact with the upper surface of the first membrane, and a third membrane in contact with the upper surface of the second membrane. Preferably, the second film has an electron affinity to the first film and the third film. Here, the electron affinity of the second film is such that the electron affinity of the first film and the third film is such that The electron affinity of the first film is greater than that of the second film, and the first conductor connects to the side of the second film through the second insulator. It has a region facing the surface, and the sum of the height of the protrusion and the thickness of the first film is equal to the thickness of the third film and the second insulating layer. It is preferable that it is greater than the sum of the thicknesses of the bodies. Also, the second conductor and the third conductor are It is preferable that it is in contact with either the upper surface of the second film or the upper surface of the third film.

[0014] Furthermore, in the above configuration, the fourth insulator has a third region that is mixed with the fifth insulator. This is also possible. Furthermore, the third region may have excess oxygen.

[0015] Alternatively, in one aspect of the present invention, a first insulator is formed on a substrate, and then on the first insulator An oxide semiconductor is formed on it, then a second insulator is formed on the oxide semiconductor, and then the A first conductor is formed on an insulator, and then the first element is added to the oxide semiconductor film. Subsequently, a third insulator is formed on the first conductor and the oxide semiconductor, and then the third A fourth insulator is formed on the side surface of the first electrode by etching the insulator, and then, A second conductor is formed on the first conductor and the fourth insulator, and then on the second conductor A fifth insulator is formed, and then the surface of the fifth insulator is flattened using a chemical mechanical polishing method. While both the first region of the second conductor and the second region of the fifth insulator are By removing the included region, a third conductor, a fourth conductor, and a sixth insulator are formed. Then, the first transistor is formed. Subsequently, the seventh insulator is formed on the sixth insulator. This is a method for fabricating a semiconductor device. Here, the first region and the second region are made of a first conductor and Overlapping, the height of the upper edges of the third and fourth conductors is equal to the height of the upper edge of the sixth insulator. They roughly coincide, with the first conductor functioning as the terminal electrode of the first transistor, and the third conductor The electromagnet and the fourth conductor are used as the source or drain electrode of the first transistor. The first and seventh insulators function, and have lower hydrogen permeability than the sixth insulator. At least one of insulator 1 and insulator 7 is aluminum oxide or nitride It contains silicon.

[0016] Here, in the above configuration, the fourth insulator is referred to as the sidewall insulating layer or sidewall insulating film. There is a combination. Also, in the above configuration, the first element is tungsten, aluminum, titanium Among ions, magnesium, vanadium, antimony, arsenic, and sulfur, at least one It may include any one of the following.

[0017] Alternatively, in one aspect of the present invention, a first insulator is formed on a substrate, and then on the first insulator An oxide semiconductor is formed on it, then a second insulator is formed on the oxide semiconductor, and then the A first conductor is deposited on the second insulator, and then a third insulator is deposited on the first conductor. Then, by removing a portion of the third insulator, a fourth insulator is formed, and then, A second conductor is formed by removing a portion of the first conductor, and then an oxide semiconductor is formed. The first element is added to the body, then the fifth insulator is formed on the fourth insulator, and then the By removing a portion of the insulator 5, a sixth insulator is formed on the side wall of the first conductor, After that, a third conductor is formed on the sixth insulator, and then a seventh insulator is formed on the third conductor. A film is formed, and the surface of the seventh insulator is planarized using a chemical mechanical polishing method, while the third conductor To remove the region that includes both the first region having and the second region having the seventh insulator. This forms a fourth conductor, a fifth conductor, and an eighth insulator, and the first transient A st is formed, and then a ninth insulator is placed on the sixth insulator, the fourth conductor and the fifth conductor. This is a method for fabricating a semiconductor device that forms a body. Here, the first region and the second region are the Overlapping with conductor 2, insulators 1 and 9 have higher hydrogen permeability than insulator 8. The properties are low, and at least one of the first insulator and the ninth insulator is oxygen and aluminum. It is preferable that it contains nium.

[0018] Here, in the above configuration, the sixth insulator is referred to as the sidewall insulating layer or sidewall insulating film. There is a combination. Also, in the above configuration, the first element is tungsten, aluminum, titanium Among ions, magnesium, vanadium, antimony, arsenic, and sulfur, at least one It may include any one of the following. [Effects of the Invention]

[0019] It can provide miniature transistors, or transistors with low parasitic capacitance. It can provide a transistor with high frequency characteristics. It can provide transistors with good electrical characteristics. Or, it can provide transistors with stable electrical characteristics. We can provide transistors that have low power consumption. It is possible to do so. Or, it is possible to provide a reliable transistor. Also, This can provide novel transistors. Or, fewer of these transistors A semiconductor device having at least one of these properties can be provided.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not need to have all of these effects. Other effects are described in the specification. This will become clear from the description in the drawings, claims, etc., and the specification, drawings, claims From descriptions such as these, it is possible to extract other effects. [Brief explanation of the drawing]

[0021] [Figure 1] A top view and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 2] A top view and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 3] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 4] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 5] A top view showing a semiconductor device according to one aspect of the present invention. [Figure 6] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 7] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 8] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 9] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 10] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 11] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 12] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 13] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 14] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 15] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 16] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 17] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 18] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 19] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 20] A top view and a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 21] A diagram illustrating the energy band structure. [Figure 22]A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 23] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 24] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 25] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 26] A figure showing an example of a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 27] High-resolution TEM image with Cs correction in cross-section of CAAC-OS, and schematic cross-sectional diagram of CAAC-OS. [Figure 28] High-resolution TEM image with Cs correction in the plane of CAAC-OS. [Figure 29] A diagram illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors. [Figure 30] A figure showing the electron diffraction pattern of CAAC-OS. [Figure 31] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 32] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 33] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 34] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 35] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 36] Circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 37] Circuit diagram of a semiconductor device according to one aspect of the present invention. [Figure 38] A block diagram showing an example of a CPU configuration. [Figure 39] A circuit diagram showing an example of a memory element. [Figure 40] A diagram illustrating an example of an imaging device. [Figure 41] A diagram illustrating an example of an imaging device. [Figure 42] A diagram illustrating an example of an imaging device. [Figure 43] A diagram illustrating an example of pixel configuration. [Figure 44] A diagram illustrating an example of pixel configuration. [Figure 45] A circuit diagram showing an example of an imaging device. [Figure 46] A cross-sectional view showing an example of the configuration of an imaging device. [Figure 47] A cross-sectional view showing an example of the configuration of an imaging device. [Figure 48] A block diagram and circuit diagram illustrating an example of a display device. [Figure 49] A block diagram illustrating an example of a display device. [Figure 50] A diagram illustrating an example of a display device. [Figure 51] A diagram illustrating an example of a display device. [Figure 52] A diagram illustrating an example of a display module. [Figure 53] A block diagram illustrating an example of an RF tag. [Figure 54] A diagram illustrating an example of RF tag usage. [Figure 55] A perspective view showing the cross-sectional structure of a package using a lead frame type interposer. [Figure 56] A diagram illustrating an example of an electronic device. [Figure 57] A top view showing an example of a film deposition apparatus. [Figure 58] A cross-sectional view showing an example of a film deposition apparatus. [Figure 59] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 60] A cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Modes for carrying out the invention]

[0022] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be modified in various ways. Those skilled in the art will readily understand what is possible. Therefore, the present invention is as shown in the following embodiments. The description is not limited to the contents of the above. Therefore, the same reference numeral is used in common across different drawings for parts that are the same or have similar functions. The explanation of this repetition may be omitted in some cases.

[0023] Furthermore, the position, size, and scope of each component shown in the drawings, etc., facilitate understanding of the invention. Therefore, the actual location, size, and range may not be represented. The invention is not necessarily limited to the position, size, scope, etc. disclosed in drawings or other documents. For example, in the actual manufacturing process, processes such as etching are used to remove layers and resist masks. Although this may be unintentionally reduced, it is sometimes omitted for the sake of easier understanding. .

[0024] Furthermore, in order to facilitate understanding of the invention, some components are omitted from the drawings. In some cases, this may be omitted. Also, some hidden lines and other details may be omitted.

[0025] In this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion of constituent elements. This is merely a label and does not indicate any order or ranking, such as process order or stacking order. Furthermore, even if an ordinal number is not attached to a term in this specification, etc., confusion of its constituent elements may occur. To avoid this, ordinal numbers may be added to the claims. Also, in this specification, etc. Even if a term is assigned an ordinal number in the text, if a different ordinal number is assigned in the claims... In some cases, this may be the case. Also, even if a term is given an ordinal number in this specification, etc., Ordinal numbers may be omitted in the scope of the request, etc.

[0026] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and This includes cases where the wiring is formed as an integrated unit.

[0027] In this specification, the terms "above" and "below" refer to the relative positions of the constituent elements, specifically when they are directly above or below. It is not limited to being directly below and in direct contact. For example, "electrical current on insulator A" If the expression is "electrode B," it is not necessary for electrode B to be directly in contact with insulator A. Cases that include other components between insulator A and electrode B are not excluded.

[0028] Furthermore, the source and drain functions may differ when using transistors with different polarities, In circuit operation, the direction of current changes, and depending on the operating conditions, they can be swapped. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. It shall be considered as such.

[0029] Furthermore, in this specification, etc., if it is explicitly stated that X and Y are connected, The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0030] Furthermore, in this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "has some electrical effect The term "of" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. Therefore, even when expressed as "electrically connected," in actual circuits, In some cases, there are no physical connections, and only wiring extends from the source.

[0031] Note that channel length refers to, for example, the length of the semiconductor (or transistor) in a top view of a transistor. When the inverter is ON, the part of the semiconductor through which current flows and the gate electrode overlap each other. In the region where a channel is formed, or the region where a channel is formed (also called the "channel-forming region") The source (source region or source electrode) and the drain (drain region or drain electrode) This refers to the distance between the poles. Note that in a single transistor, the channel length is the same across the entire region. They do not necessarily take the same value. That is, the channel length of a transistor is not fixed to one value. This may not always be the case. Therefore, in this specification, the channel length is defined as the region in which the channel is formed. This can be any one value, maximum value, minimum value, or mean value within the range.

[0032] Channel width refers to, for example, the width of a semiconductor (or transistor) when it is in the ON state. A region or channel is formed where the part through which current flows and the gate electrode overlap. This refers to the length of the portion of a region where the source and drain are facing each other. In transistors, the channel width is not necessarily the same across all regions. That is, The channel width of a single transistor may not be fixed to a single value. Therefore, In the detailed document, the channel width is any one value, the maximum value, in the region where the channel is formed. , or the minimum value or the average value.

[0033] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. Channel width (also called "effective channel width") and shown in the top view of the transistor. The channel width (also called the "apparent channel width") may differ from the actual channel width. For example, When the gate electrode covers the side of the semiconductor film, the effective channel width is the apparent channel width. The width can become larger, and its effects can become undeniable. For example, fine and fine electrical In transistors where the electrodes cover the sides of the semiconductor, the channel region formed on the upper surface of the semiconductor divides In some cases, the proportion of the channel region formed on the side surface of the semiconductor becomes larger. In this case, the effective channel width becomes larger than the apparent channel width.

[0034] In such cases, it can be difficult to estimate the effective channel width through actual measurements. For example, in order to estimate the effective channel width from the design value, the shape of the semiconductor is known. A certain assumption is necessary. Therefore, if the shape of the semiconductor is not precisely known, the effective It is difficult to accurately measure channel width.

[0035] Therefore, in this specification, the apparent channel width is referred to as the "enclosed channel width (SCW:S)". It is sometimes called "circular channel width". Also, this detail In the document, when simply referred to as channel width, it means enclosed channel width or apparent channel width. It may refer to the channel width. Or, in this specification, when it is simply referred to as channel width, It can refer to the effective channel width. Note that channel length, channel width, and effective channel Channel width, apparent channel width, enclosed channel width, etc., are determined by analyzing cross-sectional TEM images, etc. The value can be determined by these factors.

[0036] Furthermore, the field-effect mobility of the transistor and the current value per channel width are calculated to determine the value. In some cases, the calculation may be performed using the enclosed channel width. In that case, the effective channel The result may differ from the value obtained when calculating using the channel width.

[0037] Furthermore, semiconductor impurities refer to components other than the main components that make up the semiconductor, for example, concentrated Elements with a concentration of less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, lead to... The increasing Density of State (DOS) of semiconductors, and carrier migration. In some cases, the degree of quality may decrease, or the crystallinity may decrease. In the case of conductors, impurities that alter the properties of semiconductors include, for example, Group 1 elements and Group 2 elements. Other than the main components of Group 13, Group 14, Group 15 elements, and oxide semiconductors. These include transition metals, and in particular, for example, hydrogen (also found in water), lithium, and sodium. These include silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of oxide semiconductors, for example, hydrogen The presence of various impurities can lead to the formation of oxygen vacancies. Also, if the semiconductor is silicon... In this case, impurities that alter the properties of semiconductors include, for example, Group 1 elements other than oxygen and hydrogen. These include elements from Group 2, Group 13, Group 15, and so on.

[0038] Furthermore, in this specification, "parallel" means that two lines are at an angle of -10° or more and 10° or less. This refers to a state in which the positions are arranged. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "Approximately parallel" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" and "orthogonal" refer to two lines that are aligned at an angle of 80° to 100°. This refers to the state in which something is placed. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "abbreviated "Perpendicular" refers to a state where two straight lines are positioned at an angle between 60° and 120°.

[0039] In this specification, etc., the terms "identical," "same," and "equal" are used to refer to count values ​​and measured values. When using terms like "uniform" or "uniform" (including synonyms for these), use the terms that are explicitly stated. Excluding the above, the result should include a margin of error of plus or minus 20%.

[0040] Furthermore, in this specification, the etching process is performed after the photolithography process. In this case, unless otherwise specified, the resist mask formed in the photolithography process is It shall be removed after the etching process is complete.

[0041] Furthermore, in this specification, etc., the high power supply potential VDD (hereinafter simply referred to as "VDD" or "H potential") is used. (Also called "low power supply potential") indicates a power supply potential that is higher than the low power supply potential VSS. The VSS (hereinafter also simply referred to as "VSS" or "L potential") is the voltage relative to the high power supply potential VDD. It shows a power supply potential that is even lower. Also, use the ground potential as VDD or VSS. It is also possible. For example, if VDD is at ground potential, then VSS is at a lower potential than ground potential. If VSS is at ground potential, then VDD is at a higher potential than ground potential.

[0042] Furthermore, the words "membrane" and "layer" can be used interchangeably depending on the context or situation. Accordingly, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive layer". In some cases, the term can be changed to "film." Or, for example, "insulating film." In some cases, it may be possible to change the term to "insulating layer."

[0043] Furthermore, in this specification, if the crystal is trigonal or rhombohedral, it is listed as hexagonal. vinegar.

[0044] (Embodiment 1) In this embodiment, an example of the structure of a semiconductor device according to one aspect of the present invention will be described.

[0045] <Example Configuration> Figure 1(A) shows a top view of a semiconductor device according to one embodiment of the present invention. Figure 1(B) shows a top view of Figure 1(A). Figure 1(B) shows the cross-sections of the dashed lines L1-L2 and W1-W2. The semiconductor device shown comprises a substrate 101, an insulator 102 on the substrate 101, and an insulator 102 A transistor 100, an insulator 110 covering the transistor 100, and an insulating layer on the insulator 110. It has a rim 111 and

[0046] The transistor 100 has an oxide layer 104 on the insulator 103 and an insulating layer on the oxide layer 104. Body 105, conductor 106 on insulator 105, and insulator formed on the side wall of conductor 106 108 and the conductor 109a that is in contact with the side surface of the oxide layer 104 and the side surface of the insulator 108 The insulator 108 is adjacent to the side surface of the conductor 106. preferable.

[0047] Conductor 106 is the first gate electrode of transistor 100, and conductor 109a and The conductor 109b serves as the source electrode or drain electrode of the transistor 100, providing insulation. It is preferable that each of the bodies 105 functions as a gate insulator for the transistor 100. .

[0048] Here, the oxide layer 104 can be formed as a single layer or as multiple layers. For example, see Figure 1. As shown in (B), the oxide layer 104 consists of oxide layer 104a, oxide layer 104b, and acid It is preferable to form it with three layers of oxide layer 104c. The oxide layer 104b is the oxide layer 104a The oxide layer 104c is formed in contact with the oxide layer 104b.

[0049] The oxide layers 104a and 104c are closer to being insulators than the oxide layer 104b. Therefore, when a gate voltage is applied, oxide layer 104a, oxide layer 104b, oxide layer 10 Of the 4c ​​layers, channels are more likely to form in the oxide layer 104b. Therefore, in this specification, The oxide layer 104a and oxide layer 104c are sometimes referred to as insulators.

[0050] The transistor 100 shown in Figure 1(B) has an oxide layer 104a on the insulator 103 and an oxide layer 104a on the insulator 103. The oxide layer 104b in contact with the upper surface of the material layer 104a, and the oxide layer in contact with the upper surface of the oxide layer 104b It has a material layer 104c and an insulator 105 on the oxide layer 104c. The insulator 108 is It has a region that is in contact with the upper surface of the insulator 105. Also, the lower surface of the insulator 108 is connected to the conductor 106. It roughly coincides with the lower surface of the conductor 109a and conductor 109b. It has a region in contact with the upper surface of b.

[0051] Furthermore, in the oxide layer 104, the transistor 100 has a region that overlaps with the insulator 108, In the region overlapping with conductors 109a and 109b, there is a different component from the main component of the oxide layer 104. It contains metallic element 131. Metallic element 131 is present in the insulator 105, oxide layer 104, and It may also be included in parts of each of the insulators 103. It contains metallic element 131. The end of region 135 is shown by a dashed line in Figure 1(B) as an example. Region 135 is formed above the dashed line that indicates the edge of region 135.

[0052] Furthermore, in the oxide layer 104, region 135 is the source region of transistor 100 or It can function as a drain region. Therefore, the region sandwiched between the regions 135 of the oxide layer 104 It can function as a channel-forming region.

[0053] As shown in Figure 1(B), the height of the upper end of the insulator 110 and the conductor 109a and the conductor The height of the upper end of 109b is preferably approximately the same. Also, the insulator 110 and the conductor 1 The upper surfaces of 09a, conductor 109b, insulator 108, and insulator 107 are a continuous flat Preferably, the surface is flat, and the insulator 111 is formed on this flat surface.

[0054] Furthermore, in Figure 1, etc., the oxide layer 104 is one of the oxide layer 104a and oxide layer 104c. It is also acceptable to have a structure that does not have either of these features.

[0055] As shown in Figure 1(B), the insulator 103 may have protrusions. In that case, the oxide It is preferable that layer 104 is formed in contact with the upper part of the protrusion. Here, the height of the protrusion and the acid The sum of the thicknesses of the oxide layers 104a is equal to the sum of the thicknesses of the oxide layers 104c and 104b. In some cases, increasing the size can improve the characteristics of transistor 100. be.

[0056] Figure 59(A) shows the cross-section corresponding to the dashed line L1-L2 in Figure 1(B). A modified example is shown. One embodiment of the present invention is a semiconductor device as shown in the example in Figure 59(A). Furthermore, the insulator 107 does not need to be on the conductor 106. Also, as shown in Figure 1(B), etc. It is more preferable to have an insulator 107 on the conductor 106. Having body 107 makes it possible to stabilize the manufacturing process of transistor 100. This may occur. By stabilizing the manufacturing process, the characteristics of transistor 100 can be improved. It can be done.

[0057] Furthermore, the transistor 100 has an insulator 118 and a conductor 117 on the insulator 102, It may have. In the example shown in Figure 1(B), the conductor 117 fills the insulator 118. It is formed to fill the insulator 118, and the insulator 103 is formed to fill the insulator 1 It is formed on 18. Here, the conductor 117 is the second gate electrode of transistor 100. It is preferable that it functions in this way. The potential of the second gate electrode is the same as the potential of the first gate electrode of transistor 100. It may be set to the same potential as -, or to the ground potential (GND potential), or to any arbitrary potential. By changing the potential of the second gate electrode independently of the first gate electrode, The threshold voltage of the transistor can be changed.

[0058] By providing the conductor 106 and conductor 117 with the oxide layer 104 in between, further, By setting the potential of the electroluminescent body 106 and the conductor 117 to the same potential, carriers in the oxide layer 104 Because the region over which the carriers flow becomes larger in the film thickness direction, the amount of carrier movement increases. As a result, the on-current of transistor 100 increases, and the field-effect mobility also increases. .

[0059] Therefore, transistor 100 has a large on-current relative to its occupied area. It is a transistor. That is, the area occupied by transistor 100 relative to the required on-current. This allows for a reduction in size. Therefore, it is possible to realize a semiconductor device with a high degree of integration.

[0060] Furthermore, since the first gate electrode and the second gate electrode are formed from conductive layers, a transistor A function that prevents electric fields generated outside the device from acting on the semiconductor layer in which the channel is formed. It has an electric field shielding function against static electricity, etc. Furthermore, the second gate electrode is made from a semiconductor layer By forming a large layer and covering the semiconductor layer with a second gate electrode, the electric field shielding function is enhanced. It is possible.

[0061] Conductors 106 and 117 each have the function of shielding against an external electric field. Therefore, the charge of charged particles etc. generated above the conductor 106 and below the conductor 117 oxidizes. It does not affect the channel formation region of material layer 104. As a result, stress tests (e.g., gate Applying a negative charge to -GBT (Gate Bias-Temperature) The degradation of the test (stress test) is suppressed. In addition, conductors 106 and 117 are drain electrodes. The electric field generated from it can be blocked so that it does not act on the semiconductor layer. Therefore, the drain This can suppress fluctuations in the on-current rise voltage caused by voltage fluctuations. This effect is evident when a potential is supplied to conductors 106 and 117. It occurs in writing.

[0062] Note that the BT stress test is a type of accelerated test that shows the effects of long-term use. This allows for the rapid evaluation of changes in the characteristics of the ZISTA (changes over time). In particular, it is useful for BT stress testing. The change in the transistor's threshold voltage before and after testing is an important indicator for examining reliability. This serves as a benchmark. The smaller the fluctuation in threshold voltage before and after the BT stress test, the more reliable the result. It can be said that this is a transistor with high performance.

[0063] Furthermore, it has a conductor 106 and a conductor 117, and conductor 106 and conductor 117 By setting them to the same potential, the amount of fluctuation in the threshold voltage is reduced. Therefore, multiple transients The variation in electrical characteristics between stations is also reduced at the same time.

[0064] Furthermore, a transistor having a second gate electrode has a positive charge applied to its gate (+GB). The threshold voltage fluctuations before and after the T-stress test, as well as the transistor without a second gate electrode. It's smaller than Zista.

[0065] Furthermore, when light is incident from the second gate electrode side, the second gate electrode has light-shielding properties. By forming it with a conductive film, it prevents light from entering the semiconductor layer from the second gate electrode side. This allows for the prevention of photodegradation of the semiconductor layer and the shift in the transistor's threshold voltage. This prevents deterioration of electrical properties such as tarnish.

[0066] Furthermore, in the cross-section shown in Figure 1(B), the cross-section corresponding to the dashed line L1-L2, The end 315 of the insulator 108 is located outside the end 316 of the conductor 117, as shown in Figure 6. As shown in 0(A), the positions of end 315 and end 316 may roughly coincide. Alternatively, As shown in Figure 60(B), the end portion 315 may be located inward from the end portion 316.

[0067] Furthermore, a semiconductor device according to one aspect of the present invention includes an insulator 112 on an insulator 111 and an insulator 11 0, Contact plug 113 formed to fill in insulators 111 and 112 a, contact plug 113b, and contact plug 113c, and on the insulator 112 It may have conductors 114a, 114b, and 114c. Conductor 114 a, Conductor 114b, and Conductor 114c can be used, for example, in wiring. can.

[0068] Furthermore, in one aspect of the present invention, a semiconductor device is provided with a semiconductor element between the substrate 101 and the insulator 102. They may have children.

[0069] Figure 2(A) shows a top view of a semiconductor device according to one embodiment of the present invention. Figure 2(B) is shown in Figure 2(A) Figure 2 shows the cross-sections of the dashed lines L1-L2 and W1-W2. The semiconductor device has a transistor 100. The semiconductor device shown in Figure 2 has a transistor The structure of the insulator 108 on 100 is different from that in Figure 1. In Figure 1(B), the insulator 108 is The surface roughly coincides with the lower surface of the conductor 106, whereas in Figure 2(B), the surface below the insulator 108... The surface roughly coincides with the lower surface of the oxide layer 104c. Also, in Figure 1(B), the insulator 108 is an insulator. In contrast to the upper surface of the edge 105, in Figure 2(B), the insulator 108 is in contact with the oxide layer 104b It is in contact with the upper surface. Also, the edges of the oxide layer 104c and the insulator 105 are in contact with the upper surface in Figure 1(B). In contrast to the end of the edge 108, in Figure 2(B) it roughly coincides with the end of the conductor 106. I will do it.

[0070] Here, as shown in Figure 2(B), the transistor 100 has a side surface such as the oxide layer 104b. It may have an insulator 108b in contact with it.

[0071] Furthermore, as shown in Figure 3(A), the edge of the oxide layer 104c is longer than the edge of the insulator 108. It may be located on the outside. In the transistor 100 shown in Figure 3(A), the oxide layer 1 The end of 04c is located outside the end of the insulator 108. Also, the end of the oxide layer 104c The part is located outside the ends of the conductor 109a and conductor 109b.

[0072] Furthermore, as shown in Figure 59(B), the edge of the oxide layer 104c and the edge of the insulator 105 , may be located outside the ends of conductor 109a or conductor 109b. Also, oxidation The edges of the material layer 104c and the edges of the insulator 105 may be roughly aligned, as shown in Figure 59(B). They don't need to be perfectly aligned.

[0073] Furthermore, as shown in Figure 59(C), the end of the insulator 105 is located outside the insulator 108. Furthermore, it may be located inside the ends of the conductor 109a and the conductor 109b. In Figure 59(C), the edges of the oxide layer 104c are the edges of the conductors 109a and 109b. An example of a location on the outside of the part is shown, but it may also be located on the inside.

[0074] Furthermore, the edges of the oxide layer 104c are the edges of the conductor 109a and the edges of the conductor 109b. They may be located outside the part. In this case, conductors 109a and 109b are An oxide layer 104c is present between the insulator 103 and the oxide layer 104c.

[0075] Furthermore, as shown in Figure 4, the edge of the oxide layer 104c roughly coincides with the oxide layer 104b. That's good too.

[0076] <Description of components>

[0077] [Oxide layer 104] The oxide layer 104 consists of oxide layer 104a, oxide layer 104b, and oxide layer 104c. It is preferable to have a laminated structure.

[0078] For example, an oxide semiconductor containing indium (In) can be used as the oxide layer 104. This is preferable. For example, if the oxide semiconductor contains indium, the carrier mobility (electron mobility) is improved. The temperature (degree) increases. Furthermore, it is preferable that the oxide semiconductor contains element M.

[0079] Element M is preferably aluminum, gallium, yttrium, or tin. Other elements to which element M can be applied include boron, silicon, titanium, iron, and nickel. Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium Examples include um, tantalum, tungsten, and magnesium. However, as for element M, as mentioned above... In some cases, it is acceptable to combine multiple elements. Element M, for example, has a bonding energy with oxygen. It is an element with high energy. Element M, for example, increases the energy gap of oxide semiconductors. It is an element that has the function of reducing. Furthermore, oxide semiconductors preferably contain zinc. Semiconductors can sometimes crystallize more easily when zinc is present.

[0080] However, the oxide layer 104 is not limited to an oxide containing indium. For example, indium is found in zinc tin oxide, gallium tin oxide, gallium oxide, etc. It does not matter even if it is an oxide containing no zinc, an oxide containing gallium, an oxide containing tin, etc. It does not matter.

[0081] For example, an oxide semiconductor having a large energy gap is used for the oxide layer 104. The energy gap of the oxide semiconductor used for the oxide layer 104 is, for example, 2.5 eV or more and 4. 2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3 .5 eV or less.

[0082] The oxide semiconductor includes, but is not limited to, a sputtering method, a CVD (Chemical Vapor Dep osition) method (MOCVD (Metal Organic Chemical V apor Deposition) method, ALD (Atomic Layer Depos ition) method, thermal CVD method or PECVD (Plasma Enhanced Ch emical Vapor Deposition) method), MBE (Molecular Beam Epitaxy) method or PLD (Pulse d Laser Deposition) method may be used for film formation. The plasma CVD method can obtain a high-quality film at a relatively low temperature. When using a film formation method that does not use plasma during film formation, such as the MOCVD method, the ALD method, or the thermal CVD method, damage is less likely to occur on the surface to be formed, and a film with few defects can be obtained.

[0083] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is less affected by the shape of the object to be processed and has good step coverage. Therefore, it is a film formation method that is less affected by the shape of the object to be processed and has good step coverage. Furthermore, the ALD method has excellent step coverage and excellent thickness uniformity, thus aspect ratio This method is suitable for coating the surface of high-aperture openings, etc. However, the ALD method is relatively suitable for film formation. Because of its slow rate, it should be used in combination with other film deposition methods that have a faster deposition rate, such as CVD. In some cases, this may be preferable.

[0084] The CVD and ALD methods control the composition of the resulting film by adjusting the flow rate ratio of the source gases. This is possible. For example, in the CVD method and ALD method, the flow rate ratio of the raw material gas can be adjusted as needed. A film with the following composition can be formed. Furthermore, for example, in the CVD method and ALD method, film formation can be performed. By changing the flow rate ratio of the raw material gas while simultaneously depositing a film with a continuously changing composition. This is possible. When forming a film while changing the flow rate ratio of the raw material gas, multiple deposition chambers can be used. Compared to the method of deposition using a conveyor belt, the time required for deposition is reduced by eliminating the time spent on transport and pressure adjustment. This makes it possible to increase the productivity of transistors and semiconductor devices. There are cases where this occurs.

[0085] For example, as the oxide layer 104, InGaZnO is produced by thermal CVD. X (X>0) Deposition of a film In that case, trimethylindium (In(CH3)3), trimethylgallium (Ga( CH3)3) and dimethylzinc (Zn(CH3)2) are used. Also, combinations of these Not limited to combinations, triethylgallium (Ga(C2H5) )3) can also be used, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc. You can also use this.

[0086] For example, as oxide layer 104, InGaZnO is produced by the ALD method. X(X>0) Deposition of a film In this case, an InO2 layer is formed by sequentially introducing In(CH3)3 gas and O3 gas repeatedly. Then, Ga(CH3)3 gas and O3 gas are repeatedly introduced in sequence to form a GaO layer. Then, Zn(CH3)2 gas and O3 gas are repeatedly introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. Furthermore, using these gases, InGa Mixed compounds such as O2 layer, InZnO2 layer, GaInO layer, ZnInO layer, and GaZnO layer. A layer may be formed. Alternatively, H2 can be bubbled with an inert gas such as Ar instead of O3 gas. O gas may be used, but it is preferable to use O3 gas which does not contain H. Also, In(C) Instead of H3)3 gas, use In(C2H5)3 gas or Tris(acetylacetonate)indi You may also use um. Note that tris(acetylacetonato)indium is In(aca It is also called c)3. In addition, Ga(C2H5)3 gas or triglycerides can be used instead of Ga(CH3)3 gas. Tris(acetylacetonato)gallium may also be used. Gallium is also called Ga(acac)3. It is also known as Zn(CH3)2 gas and zinc acetate. You may also use these. These gas species are not the only ones you may use.

[0087] When depositing oxide semiconductor films using the sputtering method, to reduce the number of particles, indicators are used. It is preferable to use a target containing um. Also, oxide targets with a high atomic ratio of element M are preferable. When using a target, the conductivity of the target may decrease. Targets containing indium When using a t-type connector, the conductivity of the target can be increased, and DC and AC discharge can be easily performed. Therefore, it becomes easier to handle large-area substrates. Consequently, the productivity of semiconductor devices can be increased. It is possible.

[0088] Also, when forming an oxide semiconductor film by sputtering, the atomic ratio of the target is such that I n:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1 :1:2, 1:4:4, 4:2:4.1, etc.

[0089] Note that when forming an oxide semiconductor film by sputtering, an oxide semiconductor film with an atomic ratio deviated from the atomic ratio of the target may be formed. In particular, for zinc, the atomic ratio of the formed film may be smaller than the atomic ratio of the target. Specifically, there are cases where it is 40 atomic% or more and about 90 atomic% or less of the atomic ratio of zinc contained in the target. The oxide layer 104a and the oxide layer 104c are preferably formed of a material containing one or more of the same metal elements other than oxygen that constitute the oxide layer 104b. When using such a material, it is possible to make it difficult to generate interface levels at the interfaces between the oxide layer 104a and the oxide layer 104b, and between the oxide layer 104c and the oxide layer 104b. Therefore, it is possible to make it difficult for carrier scattering and capture to occur at the interface, and to improve the field-effect mobility of the transistor. Also, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. The thicknesses of the oxide layer 104a and the oxide layer 104c are 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. Also, the thickness of the oxide layer 104b is 3 nm or more and 2 nm or more.

[0090] The oxide layer 104a and the oxide layer 104c are preferably formed of a material containing one or more of the same metal elements other than oxygen that constitute the oxide layer 104b. When using such a material, it is possible to make it difficult to generate interface levels at the interfaces between the oxide layer 104a and the oxide layer 104b, and between the oxide layer 104c and the oxide layer 104b. Therefore, it is possible to make it difficult for carrier scattering and capture to occur at the interface, and to improve the field-effect mobility of the transistor. Also, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. The oxide layer 104a and the oxide layer 104c are preferably formed of a material containing one or more of the same metal elements other than oxygen that constitute the oxide layer 104b. When using such a material, it is possible to make it difficult to generate interface levels at the interfaces between the oxide layer 104a and the oxide layer 104b, and between the oxide layer 104c and the oxide layer 104b. Therefore, it is possible to make it difficult for carrier scattering and capture to occur at the interface, and to improve the field-effect mobility of the transistor. Also, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. Using such a material can make it difficult to generate interface levels at the interface between the oxide layer 104a and the oxide layer 104b, and at the interface between the oxide layer 104c and the oxide layer 104b. Therefore, it is possible to make it difficult for carrier scattering and capture to occur at the interface, and to improve the field-effect mobility of the transistor. Also, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics. The thicknesses of the oxide layer 104a and the oxide layer 104c are 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. Also, the thickness of the oxide layer 104b is from 3 nm to 2

[0091] The thicknesses of the oxide layer 104a and the oxide layer 104c are 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. Also, the thickness of the oxide layer 104b is 3 nm or more and 2 00nm or less, preferably 3nm to 100nm, more preferably 3nm to 50nm It should be less than or equal to nm.

[0092] Furthermore, the oxide layer 104b is In-M-Zn oxide (an oxide containing In, the element M, and Zn). And when oxide layer 104a and oxide layer 104c are also In-M-Zn oxide, Oxide layer 104a and oxide layer 104c are In:M:Zn=x1:y1:z1[number of atoms] If the oxide layer 104b is In:M:Zn=x2:y2:z2 [atomic ratio], then y Oxide layer 104a, oxide layer 104c, and acid where 1 / x1 is greater than y2 / x2 Select the ionized layer 104b. Preferably, y1 / x1 is 1.5 times larger than y2 / x2. Select oxide layer 104a, oxide layer 104c, and oxide layer 104b. More preferably, the oxide layer 104a in which y1 / x1 is at least twice as large as y2 / x2, Select oxide layer 104c and oxide layer 104b. More preferably, y1 / x1 is Oxide layer 104a, oxide layer 104c and oxide layer are larger than 3 times y2 / x2 Select layer 104b. In this case, if y1 is greater than or equal to x1 in oxide layer 104b This is preferable because it can impart stable electrical characteristics to the transistor. However, y1 is three times x1. At this point, the field-effect mobility of the transistor decreases, so y1 is three times x1. It is preferable that it be less than the above. The oxide layer 104a and oxide layer 104c have the above configuration. As a result, oxide layers 104a and 104c have more oxygen deficiencies than oxide layer 104b. This can be made into a layer where the occurrence of [unclear] is less likely to occur.

[0093] Furthermore, when the oxide layer 104a is an In-M-Zn oxide, the sum of In and M is 100a. When expressed as atomic%, preferably In is less than 50 atomic and M is 50 atomic. Higher than ic%, and more preferably In is less than 25 atomic%, and M is 75 atomic%. It should be higher than c%. Also, when the oxide layer 104b is In-M-Zn oxide, In and When the sum of M is set to 100 atomic%, preferably In is higher than 25 atomic%. M is less than 75 atomic%, and more preferably In is higher than 34 atomic%. Furthermore, M is less than 66 atomic%. Also, the oxide layer 104c is In-M-Zn oxide. When the sum of In and M is 100 atomic%, preferably In is 50 a Less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 25 at The oxidative concentration is less than 0%, and M is greater than 75 atomic%. Note that the oxide layer 104c is acidic. You may use the same type of oxide as in oxide layer 104a.

[0094] For example, an oxide layer 104a containing In or Ga, and an oxide containing In or Ga. For layer 104c, In:Ga:Zn = 1:3:2, 1:3:4, 1:3:6, 1:6: In-Ga-Zn acid formed using targets with atomic ratios such as 4 or 1:9:6 Formed using ionized materials or targets with atomic ratios such as In:Ga = 1:9 or 7:93. In-Ga oxide can be used. Also, as the oxide layer 104b, for example, Using targets with atomic ratios such as In:Ga:Zn=1:1:1 or 3:1:2, shape The resulting In-Ga-Zn oxide can be used. The atomic ratios of the ionized layer 104b are each within plus or minus 20 of the above atomic ratios, with an error margin. Includes percentage fluctuations.

[0095] Oxide layer 104b has a higher electron affinity than oxide layer 104a and oxide layer 104c. A good oxide is used. For example, as oxide layer 104b, oxide layer 104a and oxide The electron affinity of layer 104c is 0.07 eV to 1.3 eV, preferably 0.1 eV. A larger oxide with a voltage of 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. It is used. Note that electron affinity is the energy difference between the vacuum level and the lower end of the conduction band.

[0096] Furthermore, indium gallium oxide has low electron affinity and high oxygen blocking properties. Therefore, it is preferable that the oxide layer 104c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more. More preferably, it should be 90% or more.

[0097] However, if the oxide layer 104a and / or the oxide layer 104c is gallium oxide That's fine too. For example, if gallium oxide is used as the oxide layer 104c, then electrode 105a Alternatively, the leakage current generated between electrode 105b and conductor 106 can be reduced. This allows us to reduce the off-current of transistor 100.

[0098] Oxide layer 104a and oxide layer 104c have a higher electron affinity than, for example, oxide layer 104b. Because the force is small, it is closer to an insulator than oxide layer 104b. Therefore, when a gate voltage is applied... Of the oxide layers 104a, 104b, and 104c, oxide layer 104b Channels are easily formed there.

[0099] Furthermore, transistors that use oxide semiconductors in the semiconductor layer where the channel is formed ("OS transistors") Also called a "lungistor." In order to impart stable electrical properties to the oxide semiconductor, By reducing the amount of pure material and oxygen deficiency, the oxide layer 104b is made intrinsically or substantially intrinsically pure. It is preferable to use an oxide semiconductor that can be considered to have properties. For example, excess oxygen in the oxide layer 104b By supplying this, oxygen deficiency can be reduced in some cases. Also, at least one oxide layer The channel formation region in 04b is an oxide semiconductor that can be considered intrinsic or substantially intrinsic. This is preferable.

[0100] Furthermore, of the oxide layer 104, at least the oxide layer 104b contains CAAC-OS(CA xis Aligned Crystalline Oxide Semiconductor It is preferable to use tor. Note that CAAC-OS will be discussed in a later embodiment. I will explain in detail.

[0101] Here, there are few regions that are not CAAC, or regions other than those with c-axis orientation. In both cases, it is preferable that it be less than 20% of the total oxide semiconductor film used in the oxide layer 104b. .

[0102] CAAC-OS has dielectric anisotropy. Specifically, CAAC-OS has dielectric anisotropy in the a-axis direction and The dielectric constant in the c-axis direction is greater than the dielectric constant in the b-axis direction. This is the semiconductor film in which the channel is formed. A transistor in which the gate electrode is positioned in the c-axis direction using CAAC-OS is, Because of its high dielectric constant, the electric field generated from the gate electrode can easily reach the entire CAAC-OS. Therefore, the subthreshold swing value (S value) can be reduced. Transistors using CAAC-OS in the membrane are less susceptible to increased S-values ​​due to miniaturization.

[0103] Furthermore, because CAAC-OS has low dielectric constants in the a-axis and b-axis directions, the source and drain The effects of the electric field generated between the inputs are mitigated. Therefore, channel length modulation effects and short channel effects are reduced. This reduces the likelihood of defects such as bleed, thereby improving the reliability of the transistor.

[0104] Here, the channel length modulation effect occurs when the drain voltage is higher than the threshold voltage. This refers to the phenomenon where the depletion layer expands from the rain side, shortening the effective channel length. The Nell effect refers to the phenomenon where a decrease in channel length leads to a reduction in electrical characteristics, such as a decrease in threshold voltage. This refers to phenomena that cause deterioration. The smaller the transistor, the greater the degradation of its electrical characteristics due to these phenomena. This is likely to occur.

[0105] [Energy band structure of oxide semiconductor films] Here, by laminating oxide layer 104a, oxide layer 104b, and oxide layer 104c The function and effect of the constituent oxide layer 104 are shown in Figure 21(A) (energy). —This will be explained using a band structure diagram. Figure 21(A) shows Figure 1(B) with the dashed line A1-A2. The energy band structure of the region indicated by is shown. That is, Figure 21(A) shows the transistor This shows the energy band structure of the channel formation region of ZISTA 100.

[0106] In Figure 21(A), Ec382, Ec383a, Ec383b, Ec383c, Ec38 6 are insulator 103, oxide layer 104a, oxide layer 104b, and oxide layer 104, respectively. c shows the energy at the lower end of the conduction band of insulator 105. Also, Figure 21(B) shows the oxidation An example of a case where material layer 104a is not used is shown.

[0107] Here, electron affinity is the difference between the energy of the vacuum level and the energy of the upper end of the valence band ("ionized potato Also called "natural." It is the value obtained by subtracting the energy gap from ( ). The cap is a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). It can be measured using ). Furthermore, the energy difference between the vacuum level and the upper end of the valence band is measured using ultraviolet photoelectrons. Spectroscopic analysis (UPS:Ultraviolet Photoelectron Spect This can be measured using a roscopy device (PHI VersaProbe).

[0108] Furthermore, In- formed using a target with an atomic ratio of In:Ga:Zn=1:3:2 The energy gap of Ga-Zn oxide is approximately 3.5 eV, and the electron affinity is approximately 4.5 eV. Furthermore, In formed using a target with an atomic ratio of In:Ga:Zn=1:3:4 The energy gap of Ga-Zn oxide is approximately 3.4 eV, and the electron affinity is approximately 4.5 eV. Yes. Also, I formed using a target with an atomic ratio of In:Ga:Zn=1:3:6 The energy gap of n-Ga-Zn oxide is approximately 3.3 eV, and its electron affinity is approximately 4.5 eV. Furthermore, a target with an atomic ratio of In:Ga:Zn=1:6:2 was formed. The energy gap of In-Ga-Zn oxide is approximately 3.9 eV, and its electron affinity is approximately 4.3 eV. It is V. Also, it is formed using a target with an atomic ratio of In:Ga:Zn=1:6:8. The energy gap of the In-Ga-Zn oxide is approximately 3.5 eV, and its electron affinity is approximately 4.4 It is eV. Also, using a target with an atomic ratio of In:Ga:Zn=1:6:10, the shape The resulting In-Ga-Zn oxide has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4 It is 0.5 eV. Also, using a target with an atomic ratio of In:Ga:Zn=1:1:1 The energy gap of the formed In-Ga-Zn oxide is approximately 3.2 eV, and the electron affinity is approximately The voltage is 4.7 eV. Furthermore, a target with an atomic ratio of In:Ga:Zn = 3:1:2 was used. The energy gap of the In-Ga-Zn oxide formed by this process is approximately 2.8 eV, and the electron affinity is It is approximately 5.0 eV.

[0109] Since insulators 103 and 105 are insulators, Ec382 and Ec386 are Ec3 Closer to the vacuum level than 83a, Ec383b, and Ec383c (lower electron affinity). ).

[0110] Furthermore, Ec383a is closer to the vacuum level than Ec383b. Specifically, Ec383 a is 0.07 eV to 1.3 eV, preferably 0.1 eV or more, than Ec383b. The vacuum level should be 0.7 eV or less, and more preferably 0.15 eV to 0.4 eV or less, close to the vacuum level. It is preferable.

[0111] Furthermore, Ec383c is closer to the vacuum level than Ec383b. Specifically, Ec383 c is 0.07 eV to 1.3 eV, preferably 0.1 eV or more, than Ec383b. The vacuum level should be 0.7 eV or less, and more preferably 0.15 eV to 0.4 eV or less, close to the vacuum level. It is preferable.

[0112] Here, between oxide layer 104a and oxide layer 104b, It may have a mixed region with layer 104b. Also, oxide layer 104b and oxide layer 104 There may be a mixed region of oxide layer 104b and oxide layer 104c between c and the other layer. In the mixed region, the interfacial state density is low. Therefore, oxide layer 104a, oxide layer 104b The laminate of the oxide layer 104c has a continuous energy near each interface. It transforms into a band structure (also called a continuous junction).

[0113] At this time, the electrons are not in the oxide layer 104a and oxide layer 104c, but in the oxide layer It mainly moves within 104b. Therefore, oxide layer 104a and oxide layer 104b The interface state density at the interface, the interface between oxide layer 104b and oxide layer 104c By lowering the surface level density, electron movement in the oxide layer 104b is inhibited. This reduces the amount of power required, allowing for a higher on-current for transistor 100.

[0114] Furthermore, the interface between the oxide layer 104a and the insulator 103, and the interface between the oxide layer 104c and the insulator 10 Although trap levels 390 may be formed near the interface of 5 due to impurities or defects, The presence of oxide layer 104a and oxide layer 104c means that oxide layer 104b and the It can be used to move the trap level away.

[0115] Furthermore, if transistor 100 has an s-channel structure, oxide layer 104b A channel is formed throughout the entire layer. Therefore, the thicker the oxide layer 104b, the greater the channel region. This increases. In other words, the thicker the oxide layer 104b, the higher the on-current of the transistor 100. This can be achieved. For example, 20 nm or more, preferably 40 nm or more, more preferably The oxide layer 104b has a region with a thickness of 60 nm or more, more preferably 100 nm or more. This would be appropriate. However, if the productivity of the semiconductor device having transistor 100 decreases... Therefore, for example, 300 nm or less, preferably 200 nm or less, and more preferably 1 The oxide layer 104b may have a region with a thickness of 50 nm or less.

[0116] Furthermore, in order to increase the on-current of transistor 100, the thickness of the oxide layer 104c is The smaller the better. For example, less than 10 nm, preferably 5 nm or less, and even more preferably The oxide layer 104c may have regions of 3 nm or less. On the other hand, the oxide layer 104c is In the oxide layer 104b where the channel is formed, elements other than oxygen that constitute the adjacent insulator ( It has a function to block the entry of hydrogen, silicon, etc. Therefore, oxides The layer 104c preferably has a certain thickness. For example, 0.3 nm or more is preferred. Or, an oxide layer 104c having a region with a thickness of 1 nm or more, more preferably 2 nm or more. That's all you need to do.

[0117] Furthermore, to increase reliability, the oxide layer 104a should be thick and the oxide layer 104c should be thin. Preferably, 10 nm or more, preferably 20 nm or more, and even more preferably 4 The oxide layer 104a has a region with a thickness of 0 nm or more, more preferably 60 nm or more. By increasing the thickness of the oxide layer 104a, the adjacent insulator and the oxide layer 104 The distance from the interface with a to the oxide layer 104b where the channel is formed can be increased. However, the productivity of semiconductor devices having transistor 100 may decrease, for example For example, a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less. The oxide layer 104a having the region may be used.

[0118] Note that silicon in the oxide semiconductor may serve as a carrier trap or a carrier generation source. Therefore, it is preferable that the silicon concentration in the oxide layer 104b is lower. For example, between the oxide layer 104b and the oxide layer 104a, for example, in secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), there is a region with a silicon concentration of less than 1×1 0 0 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably less than 2×10 atoms / cm 18 0 3 . Also, between the oxide layer 104b and the oxide layer 104c, in SIMS, there is a region with a silicon concentration of less than 1×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably less than 2×10 atoms / cm 18 0 3 .

[0119] In addition, in order to reduce the hydrogen concentration in the oxide layer 104b, it is preferable to reduce the hydrogen concentrations in the oxide layer 104a and the oxide layer 104c. The oxide layer 104a and the oxide layer 104c have a region with a hydrogen concentration of not more than 2×10 atoms / cm 20 0 3 , preferably not more than 5×10 19 atoms / cm 3 , more preferably not more than 1×10 19 atoms / cm 3 , even more preferably not more than 5×10 atoms / cm 18 0 3 . Also, To reduce the nitrogen concentration in oxide layer 104b, oxide layer 104a and oxide layer 104 It is preferable to reduce the nitrogen concentration of c. Oxide layer 104a and oxide layer 104c are SI In MS, 5×10 19 atoms / cm 3 Less than 5 × 10 18 Atom s / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably, is 5 x 10 17 atoms / cm 3 It has a region with the following nitrogen concentrations.

[0120] Furthermore, the presence of copper in oxide semiconductors can sometimes generate electron traps. The top can cause the transistor's threshold voltage to fluctuate in the positive direction. Therefore A lower copper concentration is preferable on or inside the oxide layer 104b. For example, oxidation Material layer 104b, copper concentration is 1 × 10⁻⁶ 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 The following, or 1 × 10 18 atoms / cm 3 It is preferable to have the following regions. stomach.

[0121] The three-layer structure described above is just one example. For example, if oxide layer 104a or oxide layer 104c It may also be a two-layer structure. Alternatively, the oxide layer 104a may be above or below, or the oxide layer may be above or below. Above or below layer 104c, oxide layer 104a, oxide layer 104b and oxide layer 104 It may also be a four-layer structure having any one of the semiconductors exemplified as c. Or, an oxide On top of the material layer 104a, below the oxide layer 104a, on top of the oxide layer 104c, and on the oxide layer 104c In any two or more of the following locations, oxide layer 104a, oxide layer 104b and oxide layer 104 It can also be an n-layer structure (where n is an integer greater than or equal to 5) having any one of the semiconductors exemplified as c. No.

[0122] In particular, the transistor 100 illustrated in this embodiment exhibits oxidation in the channel width direction. The upper and side surfaces of the material layer 104b are in contact with the oxide layer 104c, and the lower surface of the oxide layer 104b is oxide It is formed in contact with layer 104a (see Figure 1(C)). Thus, oxide layer 104 By covering b with oxide layer 104a and oxide layer 104c, the above trap level The impact can be further reduced.

[0123] Furthermore, the band gaps of oxide layer 104a and oxide layer 104c are A band gap wider than that of 4b is preferable.

[0124] According to one aspect of the present invention, it is possible to realize a transistor with less variation in electrical characteristics. Yes, it is possible. Therefore, it is possible to realize a semiconductor device with less variation in electrical characteristics. According to one aspect of the invention, a transistor with good reliability can be realized. This enables the realization of highly reliable semiconductor devices.

[0125] Furthermore, since the band gap of oxide semiconductors is 2 eV or more, channels are formed in the semi-semiconductor. Transistors using oxide semiconductors as conductive films can achieve extremely low off-currents. Specifically, with a source-to-drain voltage of 3.5V and at room temperature (25°C), Off-current per 1 μm of channel width is 1 × 10⁻¹⁶ -20 Less than A, 1 x 10 -22 Less than A, there is i is 1 x 10-24 It can be less than A. That is, the on / off ratio can be 20 or more digits. It can be 0 digits or less.

[0126] According to one aspect of the present invention, a transistor with low power consumption can be realized. This makes it possible to realize semiconductor devices with low power consumption.

[0127] [Insulator 102] Insulator 102 is aluminum nitride, aluminum oxide, aluminum nitride oxide, oxide Aluminum nitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride silicon oxide nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Aluminum, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum sulfite Materials selected from licates and other sources are used in single layers or in laminated layers. In addition, oxide materials and nitrogen are used. Using a material made by mixing multiple materials from among ion materials, oxidogenic nitride materials, and nitride oxide materials That's good too.

[0128] In this specification, "nitride oxide" refers to a compound in which the nitrogen content is greater than the oxygen content. Furthermore, oxidized nitrides are compounds in which the oxygen content is higher than the nitrogen content. The element content can be determined, for example, by Rutherford backscattering (RBS). It can be measured using methods such as ckscattering (spectrometry). ru.

[0129] In particular, it is preferable to form the insulator 102 using an insulating material with low impurity permeability. For example, low oxygen permeability is preferable. Also, for example, low hydrogen permeability is preferable. These are preferred. For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum Silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium An insulating material containing um, lanthanum, neodymium, hafnium, or tantalum, in a single layer, It can be used in a laminated form. For example, as an insulating material with low impurity permeability, aluminum oxide Aluminum nitride, aluminum oxide nitride, aluminum oxide nitride, gallium oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Examples include aluminum, hafnium oxide, tantalum oxide, and silicon nitride. As the edge material 102, a highly insulating material such as indium tin zinc oxide (In-Sn-Zn oxide) is used. You may also use [this].

[0130] Furthermore, the insulator 102 may have an oxide containing indium. 2 may have an oxide containing indium and zinc. Also, the insulator 102 is It may have oxides containing indium, zinc, and element M. Oxides containing indium, or oxides containing indium and zinc, or indium, zinc By having lead and an oxide containing element M, oxygen permeability can be reduced. There are cases where this occurs.

[0131] The method for forming the insulator 102 is not particularly limited and may include sputtering, CVD, MBE, etc. Alternatively, various formation methods such as the PLD method, ALD method, and spin coating method can be used. The thickness of the edge body 102 and the insulator 110 is 10 nm or more and 500 nm or less, preferably 50 It should be between 300 nm and 300 nm.

[0132] For example, when using thermal CVD to deposit aluminum oxide as an insulator 102: This involves vaporizing a liquid (such as TMA) containing a solvent and an aluminum precursor compound to produce a raw material gas. Two types of gases, H2O and trimethylaluminum, are used as oxidizing agents. It is Al(CH3)3. Other material liquids include tris(dimethylamide)al Aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetra Examples include methyl-3,5-heptanedione.

[0133] By using an insulating material with low impurity permeability for the insulator 102, from the substrate 101 side This suppresses the diffusion of impurities and improves the reliability of the transistor. By using an insulating material with low permeability to pure substances, the diffusion of impurities from the insulator 112 side is suppressed. This can control and improve the reliability of transistors.

[0134] Multiple insulators formed from these materials may be used as the insulator 102, stacked together.

[0135] [Insulator 111 and Insulator 110b] Furthermore, the insulators 111 and 110b are made of insulating materials with low impurity permeability. It is preferable to form them in this way. For example, insulators 111 and 110b have oxygen permeability. It is preferable that the hydrogen permeability is low. Also, for example, insulators 111 and 110b have a hydrogen permeability It is preferable that the water permeability is low. Also, for example, the water permeability of insulators 111 and 110b is low. A low value is preferable. Materials that can be used for insulators 111 and 110b, For the method of manufacturing insulators 111 and 110b, refer to the description of insulator 102. It is possible.

[0136] Due to the low oxygen permeability of insulators 111 and 110b, oxide layer 104b In some cases, it may be possible to prevent excess oxygen supplied to the system from diffusing outwards.

[0137] [Insulator 103] Examples of insulator 103 include silicon oxide, silicon oxide nitride, silicon nitride oxide, Silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitride Aluminum or similar material may be used, and it may be formed in a laminated or single layer. Insulator 402 and Insulator The formation of body 412 involves sputtering, CVD (thermal CVD, MOCVD, PEC) Methods such as the VD method, MBE method, ALD method, or PLD method can be used. When the insulating film is deposited by CVD, preferably by plasma CVD, the coating properties are improved. It is preferable because it can be raised. Also, to reduce damage from plasma, thermal CV Method D, MOCVD, or ALD are preferred.

[0138] Furthermore, the insulator 103 may have a charge trapping layer. For example, as shown in Figure 4(B), The edge body 103 has a laminated structure of insulator 103a, insulator 103b, and insulator 103c. Insulator 103b includes hafnium oxide, aluminum oxide, tantalum oxide, and aluminum. The insulator 103b may be used as a charge trapping layer by using silicates or the like. For example, silicon oxide, silicon oxide nitride, and silicon nitride can be used as 103a and insulator 103c. Silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxide Aluminum, aluminum nitride, etc. can be used. Electrons are injected into the insulator 103b. This makes it possible to vary the threshold voltage of the transistor. Electron injection can be achieved, for example, by utilizing the tunneling effect. A positive voltage is applied to the conductor 117. By adding this, tunnel electrons can be injected into the insulator 103b.

[0139] The insulator 103 can be formed using the same materials and methods as the insulator 102. Furthermore, in order to prevent an increase in the hydrogen concentration in the oxide layer 104, the hydrogen concentration of the insulator 103 is controlled. It is preferable to reduce it. Specifically, the hydrogen concentration in the insulator 103 is reduced in SIMS. , 2 x 10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 More preferably 5 × 10 18 atoms / cm 3 The following applies. In addition, to prevent an increase in nitrogen concentration in oxide semiconductors, Furthermore, it is preferable to reduce the nitrogen concentration in the insulator 103. Specifically, the insulator 103 The nitrogen concentration inside was measured in SIMS at 5 × 10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0140] Furthermore, the insulator 103 is an insulator that releases oxygen upon heating ("insulator containing excess oxygen"). It is preferable to form it using oxygen, also called "body". Specifically, by TDS analysis, oxygen The amount of oxygen removed, converted to atoms, is 1.0 × 10⁻⁶. 18 atoms / cm 3 The above, preferably 3 .0 × 10 20 atoms / cm 3 It is preferable to use an insulator that meets the above criteria.

[0141] Furthermore, insulators containing excess oxygen can also be formed by adding oxygen to the insulator. Yes, it is possible. Oxygen addition can be performed through heat treatment in an oxygen atmosphere, ion implantation, or ion implantation. This can be done using a doping device or plasma processing device. Oxygen is added. As for gases, 16 O2 or 18 Oxygen gas such as O2, nitrous oxide gas or oz A gas such as oxygen can be used. In this specification, the process of adding oxygen is referred to as "oxygen addition." This is also called "oxygen addition treatment." For example, after the formation of the insulator 118, the insulator 103 This can be done after the film formation and before the formation of the oxide layer 104e, etc. Also, high-density plasma treatment Any of the following may be performed. High-density plasma can be generated using microwaves. For the Zuma treatment, an oxidizing gas such as oxygen or nitrous oxide can be used. Alternatively, acid A mixed gas of a chemical gas and a noble gas such as He, Ar, Kr, or Xe may also be used. During plasma processing, a bias may be applied to the substrate. This allows the plasma to... It can draw oxygen ions and other elements into the substrate. High-density plasma processing does not heat the substrate. It is also permissible to proceed with high-density plasma treatment instead of the above heat treatment. Similar effects can be obtained at temperatures lower than those of the heat treatment described. High-density plasma treatment is an example of For example, after the deposition of the insulator 118, after the deposition of the insulator 103, and before the deposition of the oxide layer 104e, etc. Go ahead and do it.

[0142] Here, for example, there is a processing chamber for forming an insulator 103 and a high-density plasma processing chamber. A so-called multi-chamber system having a processing chamber and a substrate processing chamber for transporting substrates between each chamber. By using a chamber apparatus, the deposition of the insulator 103 and high-density plasma treatment can be performed. Performing the process continuously without exposure to the atmosphere reduces the incorporation of impurities into the film and its interface. This is preferable because it allows for a reduction in process time, which leads to cost savings. This may be the case. Also, the yield may improve because the process can be simplified. For example, it is advisable to create a reduced-pressure atmosphere in the substrate processing chamber.

[0143] Similarly, for example, a processing chamber for forming the insulator 103 and a processing chamber for forming the oxide layer 104d A processing chamber for that purpose, a processing chamber for depositing the oxide layer 104e, and a high-density plasma processing chamber. A multi-chamber having a processing chamber for processing and a substrate transport chamber for transporting substrates between each processing chamber. By using the apparatus, the insulator 103 can be formed, high-density plasma treatment can be performed, and the oxide layer can be formed. The deposition of the 104d film and the oxide layer 104e film are carried out continuously without exposure to the atmosphere. This is preferable because it allows for this.

[0144] The thickness of the insulator 103 is preferably 1 nm to 50 nm, and preferably 3 nm to 30 nm. More preferably, and even more preferably 5 nm to 10 nm. After the formation of the oxide layer 104f Oxygen doping may be performed. Alternatively, oxygen doping may be performed after the formation of the insulator 103. This may also be done. Furthermore, heat treatment may be performed after the formation of the insulator 103. In this embodiment, For example, silicon oxide is formed as the insulator 103.

[0145] <Configuration Example 2> Figure 5(A) is a top view of a semiconductor device. Figure 6(A) shows the dashed line L shown in Figure 5. Figure 6(B) shows the cross section of 1-L2, and Figure 5(A) shows the cross section of the dashed line W1-W2. The semiconductor devices shown in Figures 5(A), 6(A), and (B) include transistor 10 Insulator 111 located above 0 and insulator 102 located below transistor 100 It has an insulator 110b surrounding the transistor 100 on all four sides. Insulator 102, insulation The transistor 100 is surrounded on all six sides by the body 111 and the insulator 110b. In 6(A), the insulator 110b is connected to the contact plug 113a and the contact plug 1 It is located outside of 13b. Also, in Figure 6(B), the insulator 110b is a contact It is located outside of the plug 113c and contact plug 113d. Here, "outside" means For example, with transistor 100 as the center, the distance from transistor 100 is longer. It refers to that.

[0146] Furthermore, as shown in Figure 5(B), insulator 102, insulator 111, and insulator 110b The structure may also consist of multiple transistors 100 surrounding each other. The semiconductor device shown in Figure 5(B) On the upper surface, two transistors 100 are surrounded by an insulator 110b. However, in the cross-section of the semiconductor device, an insulator 111 is placed above the two transistors 100. It has an insulator 102 below it. Therefore, the two transistors 100 have an insulator 1 02, the semiconductor device is surrounded on all six sides by insulators 111 and 110b. On the upper surface, it is preferable that the insulator 110b has a closed shape. Examples include polygons, circles, ellipses, and closed curves formed by connecting curves and straight lines. For example, it may be a rectangle as shown in Figure 5(A), or as shown in Figure 5(B), A quadrilateral may have rounded corners.

[0147] The characteristics of transistor 100 may change with the movement of water, hydrogen, or oxygen. The insulators 102, 111, and 110b provide six layers of insulation for transistor 100. Because the area is enclosed, hydrogen and hydrogen from outside the enclosed region to transistor 100 This suppresses contamination and the release of oxygen from transistor 100 outside the enclosed area. Therefore, fluctuations in the characteristics of transistor 100 can be suppressed.

[0148] In this embodiment, one aspect of the present invention has been described. Or, other embodiments may be described. In this context, one aspect of the present invention will be described. However, this aspect of the present invention is not limited to these. Not done. In other words, various aspects of the invention are described in this embodiment and other embodiments. Therefore, one aspect of the present invention is not limited to a specific aspect. For example, one aspect of the present invention For example, the channel formation region of transistors such as transistor 100, and the source-drain region. While examples have been shown where regions, etc., have oxide semiconductors, one aspect of the present invention is not limited thereto. Not possible. Depending on the circumstances, or depending on the situation, various transforms in one aspect of the present invention Channel formation region of a transistor, or source-drain region of a transistor. These may have various semiconductors. Depending on the circumstances, this Various transistors, channel formation regions of transistors, or, in one aspect of the invention The source and drain regions of transistors are, for example, made of silicon, germanium, silicon. Germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium It may have at least one of the following: gallium nitride, or an organic semiconductor. For example, depending on the circumstances, or depending on the situation, various challenges in one aspect of the present invention Transistor, channel formation region of a transistor, or source-drain region of a transistor The region, etc., does not necessarily have to contain an oxide semiconductor.

[0149] (Embodiment 2) This embodiment describes a method for manufacturing the semiconductor device shown in Embodiment 1.

[0150] <Manufacturing method> The method for fabricating the semiconductor device shown in Figure 1 will be explained using Figures 7 to 14.

[0151] An insulator 102 is deposited on the substrate 101. Next, an insulator 118 is deposited on the insulator 102. Next, a mask 301 is formed on the insulator 118 (see Figure 7(A)).

[0152] There are no major restrictions on the material used for the substrate 101, but it must at least withstand subsequent heat treatment. It is necessary to have a certain degree of heat resistance. For example, barium borosilicate glass or aluminum Glass substrates such as minobrosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, etc. You can use these.

[0153] Furthermore, the substrate 101 is a single-crystal semiconductor substrate made of silicon, silicon carbide, etc. Using polycrystalline semiconductor substrates, compound semiconductor substrates made of silicon germanium, etc. Also, SOI substrates and semiconductor substrates can be used to place strained transistors or FIN-type transistors. Any semiconductor element can be used. Alternatively, a high electron mobility transistor can be used. HEMT: High Electron Mobility Transis Applicable to tor) Gallium arsenide, aluminum gallium arsenide, indium gallium arsenide You may also use materials such as gallium nitride, indium phosphide, and silicon germanium. However, the substrate 101 is not merely a support substrate, but also forms other devices such as transistors. It may also be a substrate. In this case, the gate, source, or dove of transistor 100. At least one of the rains may be electrically connected to the other devices mentioned above.

[0154] Furthermore, a flexible substrate may be used as the substrate 101. When using a board, transistors, capacitive elements, etc., may be directly fabricated on the flexible substrate. Transistors, capacitive elements, etc., are fabricated on other substrates, and then peeled off and transferred to a flexible substrate. It may be placed there. In addition, in order to peel and transfer from the fabricated substrate to the flexible substrate, the fabricated substrate and the tra It is preferable to form a delamination layer between the transistor, capacitive element, etc.

[0155] Examples of flexible substrates include metals, alloys, resins, or glass, or fibers thereof. The following can be used. The more flexible the substrate used for substrate 101, the lower the coefficient of thermal expansion, the better the environment. Deformation due to is suppressed, which is preferable. The flexible substrate used for the substrate 101 has, for example, a high coefficient of linear expansion. is 1 x 10 -3 / K or less, 5×10 -5 / K or less, or 1 × 10 -5 Materials with a K or lower Any suitable material can be used. Examples of resins include polyester, polyolefin, and polyamide. (Nylon, aramid, etc.), polyimide, polycarbonate, acrylic resins, etc. In particular, aramid is suitable as a flexible substrate because of its low coefficient of thermal expansion.

[0156] The mask 301 may be fabricated, for example, by lithography using a resist. A hard mask consisting of an inorganic film or a metal film may be formed. The formation of the resist mask is This can be done using appropriate methods such as photolithography, printing, or inkjet. If a resist mask is formed using printing or inkjet methods, a photomask is not required. Therefore, manufacturing costs can be reduced.

[0157] The formation of a resist mask by photolithography involves applying a photomask to a photosensitive resist. Light is shone through the device, and the photosensitive (or unphotosensitive) areas are traced using a developing solution. Remove the resist before proceeding. The light used to irradiate the photosensitive resist is KrF excimer laser light, Ar Examples include F excimer laser light and EUV (Extreme Ultraviolet) light. In addition, immersion technology is used, in which a liquid (such as water) is filled between the substrate and the projection lens before exposure. It is also permissible to use an electron beam or an ion beam instead of the aforementioned light. Oh, when using electron beams or ion beams, a photomask is not required. Distension mask removal can be done using dry etching methods such as ashing or specialized stripping solutions. This can be done using the wet etching method. Dry etching and wet etching Both methods may be used.

[0158] Next, a portion of the insulator 118 is removed using the mask 301 to form an opening 306. (See Figure 7(B).) The insulator 118 can be removed by, for example, dry etching. good.

[0159] Next, a conductive film 117d is formed on the upper surface of the insulator 118 and inside the opening 306 (Figure 7( See C). ).

[0160] Next, a portion of the conductor 117d is removed to form the conductor 117 (Figure 7( See D). To remove the conductor 117d, for example, chemical mechanical polishing is used. It is preferable to use polishing methods such as Mechanical Polishing (CMP). It seems so. Alternatively, dry etching can be used. For example, techniques such as etch-back. You can use it.

[0161] Here, the CMP method is a method of planarizing the surface of a workpiece through a combination of chemical and mechanical actions. This is a method in which an abrasive cloth is attached to a polishing stage, and the space between the workpiece and the abrasive cloth is While supplying slurry (abrasive), the polishing stage and the workpiece are rotated or oscillated respectively. This involves a chemical reaction between the slurry and the workpiece surface, and mechanical polishing between the abrasive cloth and the workpiece. This method polishes the surface of a workpiece through the action of [a specific mechanism / action].

[0162] Next, an insulator 103, an oxide layer 104d, and an oxide layer are placed on the insulator 118 and the conductor 117. Layer 104e is deposited sequentially.

[0163] Next, impurities such as water or hydrogen contained in oxide layer 104d and oxide layer 104e To further reduce the amount of material and increase the purity of the oxide layer 104d and oxide layer 104e, Heat treatment is preferable.

[0164] For example, under reduced pressure, under inert atmospheres such as nitrogen or noble gases, under oxidizing atmospheres, or under supercharged conditions. Dry air (measured using a CRDS (Cavity Ring-Down Laser Spectroscopy) type dew point meter) When set, the moisture content is 20 ppm or less (equivalent to a dew point of -55°C), preferably 1 ppm or less. Preferably in an atmosphere of air (10 ppb or less), the oxide layer 104d and the oxide layer 10 4e is subjected to heat treatment. Note that an oxidizing atmosphere refers to an acid such as oxygen, ozone, or oxygen nitride. This refers to an atmosphere containing 10 ppm or more of an oxidizing gas. Furthermore, an inert atmosphere is defined as the aforementioned oxidizing atmosphere. This refers to an atmosphere where the concentration of the active gas is less than 10 ppm, and the atmosphere is filled with nitrogen or other noble gases.

[0165] Furthermore, by performing the heat treatment, impurities are released, and at the same time, oxygen contained in the insulator 103 is released. The oxide semiconductor layer is diffused into the oxide layer 104d and the oxide layer 104e, and is contained in the oxide semiconductor layer This can reduce oxygen deficiency. Furthermore, after heat treatment in an inert gas atmosphere, desorption To replenish the oxygen, an atmosphere containing oxidizing gas at a concentration of 10 ppm or more, 1% or more, or 10% or more is created. Heat treatment may be performed using gas. Note that the heat treatment is performed on oxide layer 104d and oxide layer 10 This can be done at any time after the formation of 4e. For example, oxide layer 104a and oxide layer 10 Heat treatment may be performed after the formation of 4b. Also, after the formation of the oxide layer 104c which is performed later. You may do so.

[0166] There are no special limitations on the heating equipment used for the heat treatment; heat conduction from heat-generating elements such as resistance heating elements is also possible. Alternatively, it may be a device that heats the object to be processed by thermal radiation. For example, an electric furnace or L RTA (Lamp Rapid Thermal Anneal) equipment, GRTA (Ga s Rapid Thermal Annealing (RTA) devices, etc. A halogen lamp (LRTA) device can be used. Metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium The light (electromagnetic waves) emitted from lamps such as mulch lamps and high-pressure mercury lamps causes the treated object to be affected. It is a device for heating. The GRTA device is a device that performs heat treatment using high-temperature gas. .

[0167] The heat treatment should be carried out at a temperature of 250°C to 650°C, preferably 300°C to 500°C. Yes, that's fine. The processing time should be within 24 hours. Heat treatment exceeding 24 hours will lead to a decrease in productivity. Therefore, it is undesirable.

[0168] Furthermore, oxygen doping treatment is performed after the formation of oxide layer 104d or oxide layer 104e. You may go.

[0169] Next, a mask 302 is formed on the oxide layer 104e (see Figure 8(A)). Mask 3 For 02, refer to mask 301. Then, use mask 302 to form oxide layer 104 Parts of e, oxide layer 104d, and insulator 103 are removed, and oxide layer 104a and Oxide layer 104b is formed (see Figure 8(B)). Oxide layer 104e, oxide layer 104 For the removal of d and the insulator 103, for example, dry etching or wet etching can be used. It is possible.

[0170] Furthermore, when etching conductors, semiconductors, and insulators using the dry etching method, A gas containing halogen elements can be used as the choke gas. Examples of chlorine include chlorine (Cl2), boron trichloride (BCl3), and silicon tetrachloride (SiCl4). ) or chlorine-based gases such as carbon tetrachloride (CCl4), or carbon tetrafluoride (CF4) ), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), or trifluoromethane (C Fluorine-based gases such as HF3, hydrogen bromide (HBr), or oxygen are used as appropriate. This can be done. Furthermore, an inert gas may be added to the etching gas used. Also, oxides... Methane (CH4) and ethane (C2) are used as etching gases for etching semiconductors. H6), propane (C3H8), or butane (C4H 10 ) and hydrocarbon gases such as A mixture of active gases may also be used.

[0171] Furthermore, as a dry etching method, there is the parallel plate type RIE (Reactive Ion Etching) method, ICP (Inductively Coupled Plasm) a: Inductively coupled plasma method, DF-CCP (Dual Frequency Capacitor) Capacitively Coupled Plasma (Dual-Frequency Excitation Capacitively Coupled Plasma) Method The following can be used. Etching conditions can be set so that the desired processing shape can be etched. (For example, the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the substrate The temperature of the electrodes on the side should be adjusted as appropriate.

[0172] Next, the top and side surfaces of the oxide layer 104b, the side surfaces of the oxide layer 104a, and the insulator On 103 are an oxide layer 104f, an insulator 105d, a conductor 106d, and an insulator 107d. The films are deposited in sequence. Then, a mask 303 is formed on the upper surface of the insulator 107d (Figure 8(C)). See reference. For mask 303, refer to mask 301.

[0173] Next, using the mask 303, portions of the insulator 107d and the conductor 106d are removed. Remove using methods such as lye etching to form the insulator 107 and conductor 106 (Figure 9) See A). ).

[0174] The conductive material for forming the conductor 106 is aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanilla Selected from among zinc, niobium, manganese, magnesium, zirconium, beryllium, etc. Materials containing one or more metallic elements can be used. Furthermore, materials containing impurity elements such as phosphorus can also be used. Highly electrically conductive semiconductors such as polycrystalline silicon and nickel silicides. Silicide may also be used. As the conductor 106, multiple conductive layers formed from these materials are used. Multiple layers may be used.

[0175] Furthermore, the conductor 106 contains indium tin oxide (ITO). de) Indium oxide containing tungsten oxide, indium containing tungsten oxide Zinc oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide Conductive materials containing oxygen, such as indium zinc oxide and silicon-added indium tin oxide. Conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can also be applied. Furthermore, a laminated structure combining the aforementioned metal element-containing material with an oxygen-containing conductive material. It is also possible to combine the aforementioned material containing the metal element with a conductive material containing nitrogen. It can also be made into a layered structure. Furthermore, it can be made from materials containing the aforementioned metal elements and oxygen. A laminated structure can also be formed by combining conductive materials and conductive materials containing nitrogen. The thickness of the conductor 106 is preferably 10 nm or more and 500 nm or less, and preferably 20 nm or more and 300 nm or less. More preferably, the wavelength is less than or equal to nm, and even more preferably between 30 nm and 200 nm. (Embodiment) Therefore, a laminate of titanium nitride and tungsten will be used as the conductive layer 126. Specifically, the thickness A 150nm thick layer of tungsten is formed on a 10nm thin titanium nitride layer.

[0176] The method for forming the conductor 106 is not particularly limited and may include vapor deposition, CVD, sputtering, etc. Various formation methods can be used.

[0177] [Metal element 131] Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as masks. (See Figure 9(C).) Note that in Figure 9(C), metallic element 131 is indicated by an arrow. The introduction of group element 131 can be performed using methods such as ion implantation or plasma doping. Yes, it is possible. In Figure 9(C), the edge of the region 135 into which the metal element 131 is introduced is shown by a dashed line. The depth of region 135 where the metal element is introduced, and the concentration of the metal element contained in region 135. This can be determined by processing conditions such as ion implantation or plasma doping. .

[0178] It is preferable to use one or more metal elements as the metal element 131. For example, metal Element 131 includes tungsten, aluminum, titanium, magnesium, vanadium, One or more elements, such as antimony, arsenic, and sulfur, may be used. The dose of metallic element 131 is 1 × 10⁻⁶ 12 ions / cm 2 The above 1 x 1016 ions / cm 2 The following is preferably 1 × 10 13 ions / cm 2 The above 1 x 10 15 ions / c m 2 The following is acceptable: The acceleration voltage when introducing metallic element 131 should be between 5kV and 50kV. The voltage should be between 10kV and 30kV. In this embodiment, metal element 131 and Tungsten is used. Conductor 106 and insulator 107 are used as masks for metal When element 131 is introduced, region 135 is formed adjacent to the channel-forming region due to self-alignment. It is possible.

[0179] Here, as metallic element 131, we have, for example, tungsten and titanium, which readily bond with oxygen. When formed with the material, an oxide of metal element 131 is formed, thereby reducing metal element 131 In the region where it is introduced, the oxygen vacancies (also called "Vo") in the oxide layer 104 increase. There is a combination. Furthermore, when hydrogen combines with Vo to form VoH, the carrier density in that region increases. The coefficient increases, and the resistivity decreases.

[0180] After introducing metal element 131, heat treatment may be performed. The heat treatment is preferably performed at 200°C. More preferably 300°C to 450°C, and even more preferably 350°C The process should be carried out at temperatures between ℃ and 400℃. This heat treatment causes hydrogen to bond to Vo, resulting in VoH. Once formed, the carrier density in that region increases further, and the resistivity decreases even more.

[0181] Therefore, region 135 in the oxide layer 104 overlaps with the conductor 106 of the oxide layer 104. The carrier density is higher and the resistivity is lower than in the channel-forming region. Therefore, oxidation occurs. Region 135 in the material layer 104 is a region that overlaps with the conductor 106 of the oxide layer 104 (channel type). The resistance may be lower than in the (compound region).

[0182] In this embodiment, tungsten is used as the metal element 131. Furthermore, ion implantation is used. This introduces tungsten into a portion of the oxide layer 104. The introduction of tungsten into the oxide layer 104 A region containing tungsten oxide is formed.

[0183] Next, an insulator 108d is formed on the insulator 105d and on the insulator 107 (Figure 9( See C). ).

[0184] Next, the insulator 108d is etched by an anisotropic dry etching method to obtain the conductor 10 An insulator 108 is formed on the side wall of 6. At this time, the insulator 105d, the insulator 108 and the conductor Regions of the electric body 106 that do not overlap with either of them are also etched, forming the insulator 105. Furthermore, the region of the oxide layer 104f that does not overlap with either the insulator 108 or the conductor 106. The area is also etched, and the oxide layer 104c is formed. Therefore, when the insulator 108 is formed... A portion of the oxide layer 104b is exposed.

[0185] At this time, a portion of the exposed oxide layer 104b is etched, resulting in an oxide layer 1 having a protrusion. O4b may be formed. Here, in Figures 20(A) and 20(B), the oxide layer A transistor 100 with a protrusion formed on 104b is shown. Figure 20(A) shows the transistor This is a plan view of the Zista 100. Also, Figure 20(B) shows the dashed line L1 shown in Figure 20(A). -L2 and the cross-section along the dashed line W1-W2.

[0186] [Insulators 107 and 108] Here, a portion of the insulator 108d is etched using an anisotropic dry etching method to create an insulator. When forming 108, it is preferable that the insulator 107 is not etched. Alternatively, The etching rate of insulator 107 is slower compared to the etching rate of insulator 108d. This is preferable. Therefore, the insulator 107 has a main element different from, for example, the main element of the insulator 108. It is preferable that it contains essential elements. Alternatively, for example, insulator 107 may be, for example, insulator 10 It is preferable that the composition differs from that of 8. The thickness of the insulator 107 is 5 nm or more and 100 nm or less. Preferably, the wavelength is 10 nm or more and more preferably 50 nm or less.

[0187] Here, as an example, silicon oxide or silicon oxide-nitride can be used as the insulator 108. Silicon nitride or silicon nitride oxide is used as the insulator 107. By making the atomic ratio of nitrogen higher than that of insulator 108, during etching of insulator 108 In some cases, this can slow down the etching rate of the insulator 107.

[0188] As another example, silicon oxide, silicon oxide nitride, and nitrogen are used as insulator 108. Using silicon oxide or silicon nitride, aluminum nitride is used as the insulator 107. When aluminum, aluminum nitride, or aluminum oxide nitride can be used. There is.

[0189] As another example, silicon oxide, silicon oxide nitride, and nitrogen are used as insulator 108. When silicon oxide or silicon nitride is used, the oxide layer 104 is used as the insulator 107. Materials that can be used as such are sometimes preferable.

[0190] Here, by etching the insulator 108d using an anisotropic dry etching method, In addition to the sidewalls of the conductor 106, an insulator may also be formed. For example, the oxide layer 104 Insulators may be formed on the side walls of b, etc.

[0191] Next, a conductor 109d is placed on the insulator 103, on the oxide layer 104b, and on the insulator 107. A film is formed (see Figure 10(B)). Here, the conductor 109d covers the side surface of the insulator 108. It is preferable that the thickness of the conductor 109d be 5 nm or more and 500 nm or less. More preferably between 0 nm and 200 nm, and even more preferably between 15 nm and 100 nm. In this embodiment, tungsten with a thickness of 20 nm is used as the conductor 109d.

[0192] Alternatively, the conductive material 109d may consist of titanium oxide with a thickness of 5 nm and a thickness of 20 nm on top of the titanium oxide. A three-layer structure is used, consisting of tungsten of nm thickness and titanium oxide with a thickness of 5 nm on top of the tungsten. It's okay to be there.

[0193] Next, a portion of the conductor 109d is removed using a mask to form the conductor 109e (Figure See 10(C). Then, the insulator 110d is deposited (see Figure 11(A)).

[0194] [Conductors 109a and 109b] Next, the insulator 110d and the conductor 109 are placed so that the upper surface is flat relative to the substrate 101. By removing a portion of e, conductors 109a and 109b are formed (Figure 1). See 1(B). By removing a portion of the conductor 109e, the conductor 109d By removing the region that overlaps with the conductor 106, the conductor 109e is separated, The electrolytic body 109a and the conductor 109b can be formed.

[0195] Here, polishing methods such as the CMP method are used to remove the insulator 110d and the conductor 109e. This can be done. Alternatively, dry etching may be used. For example, etchback You should use the appropriate method.

[0196] When using polishing methods such as CMP to remove the insulator 110d or conductor 109e, The polishing speed of the electrolytic material 109d and the insulator 110d may have a distribution within the plane of the sample. In this case, in areas where the polishing speed is high, the exposure time of the insulator 107 may be longer. The polishing speed of insulator 107 is slower compared to the polishing speed of conductor 109e and insulator 110d. It is preferable that the polishing speed of the insulator 107 is slow, which can cause the conductor 109d and the insulator to be damaged. In the polishing process of 110d, the insulator 585 acts as a polishing stopper film. It is possible.

[0197] In one embodiment of the present invention, for example, when a mask is formed using lithography... Depending on the precision of the lithography equipment, there may be a shift in the position where the mask is formed. There are cases where this occurs. In such cases, the ends of the conductors 109a and 109b and the insulator A distance is created between the end of 108. On the other hand, in one embodiment of the present invention, conductor 1 When forming 09a and the conductor 109b, it is not necessary to use a mask or the like. Therefore, The area of ​​transistor 100 as viewed from the surface can be made smaller. By making it smaller, it becomes possible to integrate the circuits contained in semiconductor devices.

[0198] Also, insulator 110, conductor 109a, conductor 109b, insulator 108, and insulator The upper surface of 107 forms a continuous flat plane. The insulator 111 is formed on this plane. For example, this can improve the coverage of the insulator 111, potentially lowering hydrogen permeability. Therefore, it is preferable. Also, the blocking ability of the insulator 111 is improved, so the insulator 111 can be made thinner. In some cases, this is possible. By thinning the insulator 111, for example, dry ec can be applied to the insulator 111. When creating openings using etching or similar methods, the etching time can be shortened. If the rendering time is too long, for example, the mask width may shrink, and the opening may become larger. This can sometimes make miniaturization difficult. By shortening the etching time, for example, finer details can be achieved. This is preferable because it allows for the creation of an opening.

[0199] Examples of conductors 109a and 109b include tungsten, polysilicon, etc. Highly embeddable conductive material can be used. Also, the sides and bottom of the material This is covered with a titanium layer, a titanium nitride layer, or a barrier layer (diffusion prevention layer) consisting of a laminate thereof. It is also possible to replace the conductor 109a with the conductor 109j, as shown in Figure 3(B), for example. Three layers of conductive material 109k and conductive material 109l, conductive material 109b, conductive material 109m, conductive material 1 A three-layer laminated structure of 09n and conductor 109o may also be used. Here, conductor 109j It is preferable to use the conductor 109m as a barrier layer. The conductive body 109o may be used as a barrier layer. Here, the conductive body 109a and conductive body 109b are electrically When functioning as an electrode, the barrier layer is sometimes included in the term "electrode."

[0200] Furthermore, the conductors 109a and 109b may be made of, for example, tungsten or titanium. When formed with a material that has the property of extracting oxygen from the oxide layer 104, the conductor 109a and The amount of Vo in the oxide layer 104 in contact with the conductor 109b increases. Of the regions 135 formed therein, the region where the conductors 109a and 109b are in contact is Carrier density increases, and resistivity decreases. Furthermore, hydrogen combines with Vo to form VoH. When this occurs, the carrier density in that region increases further, and the resistivity decreases even more.

[0201] Therefore, within the oxide layer 104, the carrier density in the region overlapping with the insulator 108 is lower than the carrier density in the region overlapping with the insulator 108. The carrier density may be high in the region where conductors 109a and 109b are in contact. Furthermore, within the oxide layer 104, the resistivity of the region overlapping with the insulator 108 is lower than that of the conductor 10 The resistivity may decrease in the region where 9a and the conductor 109b are in contact. Also, oxide Within layer 104, the resistance of the region overlapping with the insulator 108 is lower than that of conductor 109a and conductor The resistance in the region where 109b is in contact may be low.

[0202] Next, an insulator 111 is placed on top of the insulator 110, the conductors 109a and 109b, etc. Deposition is performed (see Figure 12(A)).

[0203] In this embodiment, aluminum oxide is used as the insulator 111 by sputtering. Formed. Also, an oxygen-containing gas is used as the sputtering gas. Sputtering method When the insulator 111 is formed in this way, the interface between the insulator 111 and the surface of the insulator 111 and In the vicinity, a mixed layer is formed where the two are mixed together. Specifically, the insulator 110 and the insulator A mixed layer 145 is formed at the interface of 111 and in its vicinity.

[0204] Furthermore, the mixed layer 145 contains a portion of the sputtering gas. Since an oxygen-containing gas is used as the puttering gas, oxygen is present in the mixed layer 145. Therefore, the mixed layer 145 has excess oxygen.

[0205] Next, a heat treatment is performed. The heat treatment is preferably at 200°C to 500°C, more preferably Or, if carried out at 300°C to 450°C, more preferably 350°C to 400°C Good. Note that the temperature of the heat treatment performed at this time is the same as the temperature of the heat treatment performed after the introduction of metal element 131. The temperature should be below a certain level.

[0206] The heat treatment causes the oxygen contained in the mixed layer 145 to diffuse. The excess oxygen is absorbed through insulators 110, 103, 108, 105, etc. It diffuses into oxide layer 104a, oxide layer 104b, and oxide layer 104c. Insulator 1 By using materials that are less permeable to oxygen as 11 and the insulator 102, the mixed layer 145 The excess oxygen contained is absorbed into the oxide layer 104b via the insulator 110, insulator 103, etc. Effective diffusion is possible. Figure 1 shows how excess oxygen contained in the mixed layer 145 diffuses. Indicated by an arrow in 2(B).

[0207] Next, an insulator 112 is deposited on the insulator 111. Then, insulator 112, insulator 11 An opening 307 is formed in the insulator 110 that reaches the conductor 109a, etc. (Figure 13) See A). ).

[0208] Next, a conductive film is formed on the insulator 112 and within the opening 307, and then applied to the substrate 101. By removing a portion of the conductor so that the upper surface is flat, the contact plug 113 a, forming contact plug 113b and contact plug 113c (Figure 13) See B). For example, the CMP method can be used to remove the conductor.

[0209] Contact plug 113a, contact plug 113b, and contact plug 11 For example, 3c is a highly embedding conductive material such as tungsten or polysilicon. It can be used. Also, although not shown in the illustration, the sides and bottom of the material may have a titanium layer and a nitrogen layer. It may be covered with a titanium dioxide layer or a barrier layer (diffusion prevention layer) consisting of a laminate thereof. In some cases, the term "electrode" includes the barrier layer as well.

[0210] The insulator 112 can be formed using the same materials and methods as the insulator 103. As insulator 112, polyimide, acrylic resin, benzocyclobutene resin, poly Heat-resistant organic materials such as mids and epoxy resins can be used. In addition to mechanical materials, we also handle low-dielectric materials (low-k materials), siloxane resins, and PSG (Lingara). Materials such as BPSG (Limboron glass) can be used. The insulator 112 may be formed by stacking multiple insulators.

[0211] Siloxane resins are formed using siloxane materials as the starting material, and are Si-O- This corresponds to a resin containing Si bonds. Siloxane resins use organic groups (for example, aluminum) as substituents. You may also use chloroform groups (such as aryl groups) or fluoroform groups. Furthermore, the organic group may have a fluoroform group. It's okay to be there.

[0212] The method for forming the insulator 112 is not particularly limited and can be done by sputtering, SOG, etc., depending on the material. Methods include spin coating, dip coating, spray coating, droplet ejection (such as inkjet), and printing. Printing methods (screen printing, offset printing, etc.) can be used. Firing of insulator 112 By combining this process with other heat treatment processes, it becomes possible to efficiently manufacture transistors. ru.

[0213] Next, the sample surface is chemically mechanically polished (CMP). Polishing (also known as "CMP processing") is performed (see Figure 11(A)). . ) CMP treatment reduces surface irregularities of the sample, and the insulator formed thereafter... This can improve the coverage of the conductive layer.

[0214] Subsequently, conductors 114a, 114b, and 114c are placed on the insulator 112. By forming this structure, the semiconductor device shown in Figure 1 can be fabricated (see Figure 14).

[0215] Furthermore, the deposition of insulators 118, 105d, 110d, and 112 is performed as follows: The method for forming the film of insulator 103 can be referenced. Also, insulator 118, insulator 105, The insulators 110 and 112 use the materials and configuration shown for insulator 103. It is possible.

[0216] Furthermore, the conductor 117d, the conductor 109d, the contact plugs 113a to c, and the conductor The deposition of the conductive material 114a to c can be performed by referring to the conductive material 106d. Also, the conductive material 1 17, Conductor 109a, Conductor 109b, Contact plug 113a to c, and Conductor The materials and configurations shown as the conductor 106 can be used for bodies 114a to c. .

[0217] In Figure 9(B), metal element 131 is added before forming the insulator 108. However, as shown in Figure 15(A), after Figure 9(A), before adding metal element 131, Figure 1 As shown in 5(A), an insulator 108d is formed, and then, as shown in Figure 15(B), insulation Body 108 may be formed, and then metal element 131 may be added as shown in Figure 15(C). Subsequently, insulator 110, conductor 109a, conductor 109b, insulator 111, insulator 11 2. Form the contact plug 113a, conductor 114a, etc., and create the semiconductor device shown in Figure 16. It can be manufactured. Here, in Figure 16, compared with the region below the insulator 108, In the outer regions, the concentration of metallic element 131 may be higher.

[0218] <Preparation Method 2> Next, the method for fabricating the semiconductor device shown in Figure 2 will be explained using Figures 17 to 19.

[0219] Using the methods shown in Figures 7(A) to 9(A), the insulator 102 on the substrate 101, insulation Body 118, conductor 117, insulator 103, oxide layer 104a, oxide layer 104b, oxide Layer 104f, insulator 105d, conductor 106, and insulator 107 are formed. Subsequently, the conductor Using 106 as a mask, a portion of the insulator 105d and oxide layer 104f is removed, and insulator 1 Forms 05 and oxide layer 104c (see Figure 17(A)). In Figure 17(A) The sides of the oxide layer 104c, insulator 105, conductor 106, and insulator 107 are generally one It is preferable to do so.

[0220] Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as masks. (See Figure 17(B).) In Figure 17(B), metal element 131 is indicated by an arrow, and metal element 1 The edge of region 135 where 31 is introduced is indicated by a dashed line.

[0221] Next, an insulator 108d is placed on the oxide layer 104b, on the insulator 103, and on the insulator 107. The film is formed (see Figure 17(C)). Subsequently, the conductor 10 is etched by an anisotropic dry etching method. An insulator 108 is formed on the side wall of 6 (see Figure 18(A)). Here, an anisotropic dry edge By etching the insulator 108d using the etching method, the side walls of the conductor 106 are etched in addition to the etched side walls. Insulators may also be formed. Figure 18(A) shows an insulator on the side wall of the oxide layer 104b. An example of the formation of 108b is shown.

[0222] Next, using the method shown in Figures 10(B) to 12(A), the conductor 109a, conductor 109b, insulator 110, and insulator 111 are formed (see Figure 18(B)).

[0223] In this embodiment, aluminum oxide is used as the insulator 111 by sputtering. Formed. Also, an oxygen-containing gas is used as the sputtering gas. Sputtering method When the insulator 111 is formed in this way, the interface between the insulator 111 and the surface of the insulator 111 and In the vicinity, a mixed layer is formed where the two are mixed together. Specifically, the insulator 110 and the insulator A mixed layer 145 is formed at the interface of 111 and in its vicinity.

[0224] Furthermore, the mixed layer 145 contains a portion of the sputtering gas. Since an oxygen-containing gas is used as the puttering gas, oxygen is present in the mixed layer 145. Therefore, the mixed layer 145 becomes a layer containing excess oxygen.

[0225] Next, a heat treatment is performed. The heat treatment is preferably at 200°C to 500°C, more preferably Or, if carried out at 300°C to 450°C, more preferably 350°C to 400°C Good. Note that the temperature of the heat treatment performed at this time is the same as the temperature of the heat treatment performed after the introduction of metal element 131. The temperature should be below a certain level.

[0226] The heat treatment causes the oxygen contained in the mixed layer 145 to diffuse. The excess oxygen is absorbed by the oxide layer 10 via insulators 110, 103, 108, etc. It diffuses into 4a, oxide layer 104b, and oxide layer 104c. Insulator 111 and insulation By using a material that is not easily permeable to oxygen as body 102, excess acid contained in the mixed layer 145 The element is efficiently diffused into the oxide layer 104b via insulators 110, 103, etc. This is possible. Figure 19(A) shows the diffusion of excess oxygen contained in the mixed layer 145, indicated by arrows. This is shown.

[0227] Subsequently, the insulator 112, contact plug 113a, conductor 114a, etc. are formed, as shown in Figure 2. The semiconductor device shown can be fabricated (see Figure 19(B)).

[0228] <Structure 300> In the formation of the conductors 109a and 109b shown in Figure 11(B), the substrate 101 Remove a portion of the insulator 110d and conductor 109e to make the upper surface flat. When using polishing methods such as CMP to remove the insulator 110d or conductor 109e, The polishing speed may have a distribution within the surface of the sample. In such cases, the polishing speed is faster in certain areas. In this area, excessive polishing occurs, and one of the insulators 108, insulator 107, and conductor 106 The part may be removed. Here, by densely arranging structures such as the conductor 106 This is preferable because it can suppress excessive polishing.

[0229] Figure 22(A) shows a semiconductor device having a structure 100d that becomes a transistor 100. An example of a cross-section in the length direction of the flannel is shown. Here, in Figure 22(A), in the insulator 110d The height of the upper surface between the area where structure 100d is provided and the area where structure 100d is not provided Let the difference be a length of 311. Here, a smaller length of 311 is preferable. By reducing this, insulation is obtained after the formation of conductors 109a and 109b. The flatness of the surface of body 110 can sometimes be improved.

[0230] The semiconductor device shown in Figure 22(B) consists of a structure 100d which becomes a transistor 100, and a structure It has a structure 300d which is 300. The structure 300d is adjacent to the structure 100d. The semiconductor device has a structure 300, which allows the insulator 110d and the conductor 109d to be connected. This is preferable because it can suppress excessive polishing during the removal process.

[0231] Structure 100d preferably has a conductor 106. Structure 300 (structure 30 0d) may have the same structure as transistor 100 (structure 100d). Or, Structure 300 (structure 300d) is a part of the structure of transistor 100 (structure 100d) It may have only constituent elements. In the example shown in Figure 23, structure 300d is a structure of structure 100d. Among the constituent elements, conductor 109e, conductor 106, insulator 108, insulator 107, insulator 1 05. It has an oxide layer 104c, but does not have an oxide layer 104b and an oxide layer 104a.

[0232] Furthermore, Figure 23 shows an example where the structure 300d does not have a protrusion on the insulator 103. Furthermore, the protrusions of the insulator 103 of the structure 300d are the insulator 103 of the structure 100d In some cases, the height of the protrusion is smaller than that of the insulator 110. In d, between the region where structure 100d is provided and the region where structure 300d is provided The difference in height of the top surface is defined as length 314. The semiconductor device has a structure 300d. Therefore, it is preferable that the length 314 be shorter than the length 311 shown in Figure 22(A). .

[0233] The distance between the conductor 106 of structure 100d and the conductor 106 of structure 300d. Let the length be 312. Here, for example, the length 312 is the channel direction of transistor 100. The length of the oxide layer 104b in the cross-section is 0.5 times or more and 10 times or less than 313, or 1 time or less. It is less than 5 times the maximum.

[0234] Furthermore, the structure 300 does not necessarily have to function as a semiconductor element in the semiconductor device. For example, the structure 300 does not need to be connected to the wiring. Also, the circuit of the semiconductor device In this case, the signal input to the circuit does not necessarily have to be electrically connected to the structure 300. Sometimes, structure 300 is called a dummy pattern or dummy element.

[0235] Figure 24(A) shows an example of a semiconductor device having two structures 100d. By removing a portion of the insulator 110d and the conductor 109d in Figure 24 (B As shown in (), two transistors 100 are obtained.

[0236] In Figure 24(A), when the two structures 100d are sparsely spaced, the insulator By removing 110d and a portion of the conductor 109d, as shown in Figure 24(C) In some cases, a recess may be formed in the insulator 110 between the two transistors 100. Excessive polishing occurs, causing some of the insulator 108, insulator 107, and conductor 106 to be removed. This can sometimes happen.

[0237] As shown in Figure 25(A), one or more structures 300d are adjacent to structure 100d. By forming multiple elements, when forming the conductor 109a, conductor 109b, and insulator 110... This is preferable because it can suppress excessive polishing (see Figure 25(B)). Also, the table of the insulator 110 This is preferable because it allows the surface to be made flatter. Also, the upper surface of the insulator 110 and the conductor 1 It may be possible to roughly coincide the upper end of 09a and the conductor 109b, which is preferable. stomach.

[0238] Furthermore, Figure 25(C) shows that the structure 300 consists of conductor 109a, conductor 109b, and conductor 1 06, insulator 108, insulator 107, insulator 105, oxide layer 104c, oxide layer An example without 104b and oxide layer 104a is shown. One or more structures 300d are shown. By forming multiple elements, when forming the conductor 109a, conductor 109b, and insulator 110... This is preferable because it can suppress excessive polishing.

[0239] <Method 3 of production> Next, the method for fabricating the semiconductor device shown in Figure 6 will be explained using Figure 26.

[0240] As shown in Figures 7(A) to 11(B), an insulator 102 and a conductor 11 are placed on the substrate 101. 7, Insulator 118, Insulator 103, Oxide layer 104a, Oxide layer 104b, Oxide layer 10 4c, insulator 105, conductor 106, insulator 107, insulator 108, conductor 109e, o This forms an insulator 110, etc. (see Figure 26(A)).

[0241] Next, openings reaching insulator 102 are made in insulators 110, 103, and 118. This forms part 308 (see Figure 26(B)).

[0242] Next, an insulator that will become insulator 110b is formed on insulator 110 and inside the opening 308. Afterward, the upper surface of the insulator 110 is exposed, and the upper surface of the insulator is made parallel to the substrate 101. Remove as shown, and form insulator 110b. Then, as shown in Figure 26(C), the insulator By forming an insulator 111 on 110 and insulator 110b, the semiconductor shown in Figure 6 is formed. The device can be manufactured.

[0243] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0244] (Embodiment 3) Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, and nc-O S(nanocrystalline oxide semiconductor), pseudo Amorphous-like oxide semiconductor (a-like OS) Examples include semiconductors (e) and amorphous oxide semiconductors.

[0245] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxides. They can be divided into semiconductors and crystalline oxide semiconductors. Crystalline oxide semiconductors include single-crystal oxide semiconductors and CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0246] Generally, an amorphous structure is defined as a structure that is not fixed in a metastable state and is isotropic. It is known that it does not have a heterogeneous structure. Also, the bond angles are flexible and short distance It can also be described as a structure that possesses deorderliness but lacks long-range orderliness.

[0247] Conversely, in the case of oxide semiconductors, which are inherently stable, they are perfectly amorphous (complete It cannot be called an oxide semiconductor (which is amorphous). Also, it is not isotropic. (For example, an oxide semiconductor having a periodic structure in a minute region) is subjected to complete amorphous oxidation. It cannot be called a physical semiconductor. However, a-like OS is a circumferential material in a minute region. Although it has a structural form, it is an unstable structure due to its porous nature (also called "voids"). Therefore, in terms of physical properties, it can be said to be similar to an amorphous oxide semiconductor.

[0248] <caac-os> CAAC-OS is an acid having multiple c-axis oriented crystalline parts (also called "pellets"). It is a type of ionized semiconductor.

[0249] Transmission Electron Microscope (TEM) A composite analysis image of the bright-field image and diffraction pattern of CAAC-OS (using an optical scope) Also called a "high-resolution TEM image," when observed, multiple pellets can be identified. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are visible. It is also called "Lee." ) cannot be clearly confirmed. Therefore, CAAC-OS is not This means that a decrease in electron mobility due to grain boundaries is less likely to occur.

[0250] The following describes CAAC-OS observed by TEM. Figure 27(A) The image shows a high-resolution TEM image of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. For observing high-resolution TEM images, spherical aberration correction is necessary. The n Corrector function was used. High-resolution TEM images using spherical aberration correction function were obtained. This is specifically called a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image can be done, for example, This is performed using an atomic-resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0251] Figure 27(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 27(A). Figure 27(B) shows that the metal atoms in the pellet are arranged in layers. The arrangement of metal atoms in each layer is the plane that forms the CAAC-OS film (also called the "formed surface"). .) or reflects the irregularities of the upper surface, and is parallel to the surface or upper surface of the CAAC-OS that is formed. ru.

[0252] As shown in Figure 27(B), CAAC-OS has a characteristic atomic arrangement. Figure 27(C Figures 27(B) and 27(C) show characteristic atomic arrangements indicated by auxiliary lines. ) Therefore, the size of a single pellet can be 1 nm or larger, or 3 nm or larger, It can be seen that the size of the gap created by the tilt between the toe and the pellet is approximately 0.8 nm. Therefore, pellets can also be called nanocrystals (nc). Furthermore, CAAC-OS is used in CANC (C-Axis Aligned nanocr It can also be called an oxide semiconductor containing ystals.

[0253] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on substrate 5120 are... The arrangement of the 5100 can be schematically represented as a structure resembling stacked bricks or blocks. This is the result (see Figure 27(D)). Between the pellets observed in Figure 27(C) The area where the inclination occurs corresponds to region 5161 shown in Figure 27(D).

[0254] Furthermore, Figure 28(A) shows the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. The s-corrected high-resolution TEM images are shown. Regions (1), (2), and (3) of Figure 28(A) are shown. ) are enlarged Cs-corrected high-resolution TEM images, shown in Figure 28(B), Figure 28(C), and Figure 28(C), respectively. This is shown in Figure 28(D). From Figures 28(B), 28(C), and 28(D), the pellets are It can be confirmed that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0255] Next, C was analyzed by X-ray diffraction (XRD). Let's discuss AAC-OS. For example, CAAC-OS having an InGaZnO4 crystal. When structural analysis of S is performed using the out-of-plane method, the result is as shown in Figure 29(A). In some cases, a peak may appear near a diffraction angle (2θ) of 31°. This peak is in InGa Since it is attributed to the (009) plane of the ZnO4 crystal, the CAAC-OS crystal is c-axis oriented. It can be confirmed that it possesses this property, and that the c-axis is oriented in a direction approximately perpendicular to the surface to be formed or the upper surface.

[0256] In addition, in the structural analysis using the out-of-plane method of CAAC-OS, 2θ is 31 In addition to the peak near °, a peak may also appear when 2θ is near 36°. The nearby peak indicates that some of the crystals in CAAC-OS do not exhibit c-axis orientation. This shows that a more preferable CAAC-OS is structured using the out-of-plane method. The analysis shows that 2θ shows a peak near 31°, but does not show a peak near 36°.

[0257] On the other hand, in the CAAC-OS, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-plane configuration. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. In the case of CAAC-OS, 2θ is 5 The sample is fixed at approximately 6° and analyzed while rotating it around the normal vector of the sample surface as the axis (φ axis). Even after performing a (φ scan), no clear peak appears, as shown in Figure 29(B). In contrast, with a single-crystal oxide semiconductor of InGaZnO4, if 2θ is fixed to around 56°, then φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 29(C). Six peaks are observed. Therefore, structural analysis using XRD indicates that CAAC-OS is It can be confirmed that the orientation of the a-axis and b-axis is irregular.

[0258] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGa For CAAC-OS containing ZnO4 crystals, a probe with a diameter of 300 nm is used parallel to the sample surface. When the electron beam is incident, a diffraction pattern like the one shown in Figure 30(A) is produced ("limited field transmitted electron beam"). This is also called a "diffraction pattern." Sometimes, a diffraction pattern may appear. This diffraction pattern may include InGaZn The O4 crystal contains spots originating from the (009) plane. Therefore, electron diffraction reveals However, the pellets contained in CAAC-OS have c-axis orientation, and the c-axis is on the surface to be formed or above It can be seen that it is oriented in a direction approximately perpendicular to the surface. On the other hand, for the same sample, the direction perpendicular to the sample surface is Figure 30(B) shows the diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident on the electron beam. Figure 30(B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction reveals... However, it has been found that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation. In Figure 30(B), the first ring is the (010) of the InGaZnO4 crystal. This is thought to be caused by the plane and the (100) plane, etc. Also, the second ri in Figure 30(B) The ng is thought to be caused by the (110) plane, etc.

[0259] As mentioned above, CAAC-OS is a highly crystalline oxide semiconductor. Crystallinity can decrease due to the inclusion of impurities or the formation of defects, so the opposite perspective is also possible. Therefore, CAAC-OS can be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies).

[0260] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition gold. There are group elements, for example. For example, silicon and other metal elements that make up oxide semiconductors are more acidic than the metal elements that make up oxide semiconductors. Elements with strong bonding forces can remove oxygen from oxide semiconductors, thereby altering the atomic arrangement of the oxide semiconductor. This disrupts the crystallinity and reduces its properties. Also, heavy metals such as iron and nickel, and argon, Because carbon dioxide and other elements have large atomic radii (or molecular radii), the atomic arrangement of oxide semiconductors This disrupts the crystallinity and reduces its properties.

[0261] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. Yes. For example, impurities contained in oxide semiconductors can act as carrier traps, or they can cause carriers to be trapped. It can sometimes be a source of rear emissions. Also, oxygen vacancies in oxide semiconductors can trap carriers. In some cases, it may become a carrier source by capturing hydrogen.

[0262] CAAC-OS, with its low impurity and oxygen vacancy rate, is suitable for oxide semiconductors with low carrier density. Yes, there is. Specifically, 8 x 10 11 pieces / cm 3 Less than 1 × 10 11 / cm 3 less than More preferably 1 × 10 10 pieces / cm 3 It is less than 1 × 10 -9 pieces / cm 3 The above It can be made into an oxide semiconductor with high carrier density. Such an oxide semiconductor can be made into a high-purity true These are called intrinsic or substantially high-purity oxide semiconductors. CAAC-OS has a low impurity concentration. Furthermore, it has a low defect level density. In other words, it can be said to be an oxide semiconductor with stable properties.

[0263] <nc-os> nc-OS allows for the identification of crystalline regions in high-resolution TEM images, and It has regions where a definite crystalline portion cannot be identified. The crystalline portion contained in nc-OS is They are often between 1 nm and 10 nm in size, or between 1 nm and 3 nm in size. Oh, an oxide semiconductor with a crystal size greater than 10 nm and less than 100 nm is microcrystalline acid It is sometimes called a monoxide semiconductor. nc-OS, for example, shows grain boundaries in high-resolution TEM images. In some cases, this cannot be clearly confirmed. Furthermore, nanocrystals are pellets in CAAC-OS. It may share the same origin. Therefore, below, the crystalline portion of nc-OS will be treated as a pellet. They may call.

[0264] nc-OS is used in minute regions (for example, regions between 1 nm and 10 nm, especially regions larger than 1 nm). It has periodicity in the atomic arrangement in the region of 3 nm or less. In addition, nc-OS has different properties. No regularity is observed in the crystal orientation between the letts. Therefore, no orientation is observed throughout the entire film. Therefore, depending on the analytical method, nc-OS may be a-like OS or amorphous oxide semiconductor. It can sometimes be indistinguishable from the body. For example, nc-OS has a larger diameter than pellets. When using X-rays, out-of-plane analysis shows peaks indicating crystal planes. Not detected. Also, for nc-OS, a probe diameter larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam (of a magnitude greater than nm), a diffraction pattern similar to a halo pattern is obtained. Observed. On the other hand, compared to nc-OS, the pellet size is close to or smaller than the pellet size. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots can be observed. When nanobeam electron diffraction is performed on nc-OS, a high-brightness pattern is observed, forming a circular (ring-shaped) pattern. In some cases, a region may be observed. Furthermore, multiple spots may be observed within a ring-shaped region. There are cases where this occurs.

[0265] Thus, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc -OS has RANC (Random Aligned nanocrystals) Oxide semiconductors, or NANC (Non-Aligned nanocrystals), It can also be called an oxide semiconductor having s).

[0266] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. Therefore, nc-OS has a higher defect level density compared to CAAC-OS.

[0267] <a-like OS> a-like OS is an oxide having a structure between nc-OS and amorphous oxide semiconductors. It is a semiconductor. In a-like OS, porosity may be observed in high-resolution TEM images. Yes. Furthermore, in high-resolution TEM images, there are regions where the crystalline portion can be clearly identified, It has regions where the crystalline part cannot be observed.

[0268] Due to its porous nature, a-like OS has an unstable structure. Below, a-lik This demonstrates that e OS has a less stable structure compared to CAAC-OS and nc-OS. Therefore, it shows the structural changes caused by electron irradiation.

[0269] The samples to be irradiated with electrons are a-like OS (referred to as sample A) and nc-OS. Prepare (referred to as Sample B) and CAAC-OS (referred to as Sample C). This sample is also an In-Ga-Zn oxide.

[0270] First, high-resolution cross-sectional TEM images are obtained for each sample. It can be seen that all of the materials contain crystalline parts.

[0271] The determination of which part should be considered a single crystal can be made as follows. The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn-O layer. It is known to have a structure in which a total of nine layers, consisting of six layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the spacing between the grid planes of the (009) plane (also called the "d value"). It is approximately [value], and from crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, In areas where the spacing between the fringes is between 0.28 nm and 0.30 nm, the crystal is InGaZnO4. It can be considered a part. Furthermore, the lattice pattern corresponds to the ab-plane of the InGaZnO4 crystal. ru.

[0272] Figure 31 shows an example of investigating the average size of the crystalline regions (22 to 45 locations) in each sample. However, the length of the lattice fringes mentioned above is used as the size of the crystal portion. From Figure 31, a-li It can be seen that the crystalline portion of keOS increases in proportion to the cumulative amount of electron irradiation. Specifically, as shown in (1) in Figure 31, the initial TEM observation is approximately 1.2 nm. The crystal region (also called the "initial nucleus"), which was initially a certain size, underwent a cumulative electron irradiation dose of 4.2 × 10⁻¹⁶. 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 2.6 nm. nc-OS and CAAC-OS are defined as having a cumulative electron dose of 4.2× from the start of electron irradiation. 10 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. In terms of physical properties, as shown in (2) and (3) in Figure 31, n is not affected by the cumulative dose of electrons. The crystal size of c-OS and CAAC-OS is approximately 1.4 nm and 2 nm, respectively. It can be seen that it is approximately 1 nm in size.

[0273] Thus, in a-like OS, crystalline growth can be observed upon electron irradiation. Yes. On the other hand, in nc-OS and CAAC-OS, the growth of the crystal portion by electron irradiation is almost entirely... It can be seen that it cannot be seen. In other words, a-like OS is nc-OS and CAAC- Compared to an operating system, it appears to have an unstable structure.

[0274] Furthermore, because it is porous, a-like OS is compared to nc-OS and CAAC-OS. All of them are low-density structures. Specifically, the density of a-like OS is low compared to single-layer structures of the same composition. The density of the crystal will be between 78.6% and 92.3%. Also, the density of nc-OS and CAA The density of C-OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a crystal density of less than 78% are inherently difficult to deposit into film.

[0275] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 This is how it will be. For example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also, for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0276] Note that there may be no single crystal with the same composition. In that case, by combining single crystals with different compositions in an arbitrary ratio, the density corresponding to the single crystal in the desired composition can be estimated. The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures and each has various characteristics. Note that the oxide semiconductor may be a laminated film having two or more of, for example, an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0277] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. Note that the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0278] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0279] (Embodiment 4) In this embodiment, an example of a semiconductor device using the transistor disclosed in this specification and the like will be described.

[0280] ≪Example of the structure of the semiconductor device≫ Figures 32(A) to 32(C) are cross-sectional views of the semiconductor device 400. 0 has transistor 100 and transistor 281. Note that transistor 100 is It can be replaced with other transistors shown in the above embodiment. Figure 32(A) is a transistor Figure 32(B) is a cross-sectional view of transistor 100 and transistor 281 in the channel length direction. This is a cross-sectional view in the channel width direction. Figure 32(C) shows transistor 28 in Figure 32(A). This is an enlarged view of 1.

[0281] The semiconductor device 400 uses an n-type semiconductor as the substrate 401. The transistor 281 is Channel-forming region 283, high-concentration p-type impurity region 285, insulator 286, conductor 287, It has a structure 288. In addition, a low concentration is present in the region overlapping with the structure 288 via the insulator 286. It has a p-type impurity region 284. The insulator 286 can function as a gate insulating layer. Conductor 287 can function as a gate electrode. Transistor 281 is in the channel formation region 283 This is formed on a part of the substrate 401.

[0282] The low-concentration p-type impurity region 284 is formed after the formation of the conductor 287 and before the formation of the structure 288. It can be formed by introducing impurity elements using 287 as a mask. In other words, the low-concentration p-type impurity region 284 can be formed by self-alignment. Structure After the formation of body 288, a high-concentration p-type impurity region 285 is formed. Region 284 has the same conductivity type as the high-concentration p-type impurity region 285, and the impurities that impart the conductivity type The concentration is lower than that of the high-concentration p-type impurity region 285. Also, the low-concentration p-type impurity region 284 is... It may not be necessary to provide it depending on the situation.

[0283] Transistor 281 is electrically isolated from other transistors by the element isolation layer 414. The formation of the element isolation region is LOCOS (Local Oxidation of S Methods such as ilicon and STI (Shallow Trench Isolation) These can be used.

[0284] Transistor 281 can function as a p-channel transistor. Also, An insulator 403 is formed on the sta 282, and an insulator 404 is formed on the insulator 403. The insulators 403 and 404 are formed from the same materials and in the same manner as the insulator 111. It is possible. Note that insulators 403 and 404 are oxygen, hydrogen, water, and alkali. It is formed using an insulating material that has the function of preventing the diffusion of impurities such as metallic metals and alkaline earth metals. It is preferable to do so. However, either insulator 403 or insulator 404 may be omitted. Furthermore, an insulating layer may be added.

[0285] Furthermore, the semiconductor device 400 has an insulator 405 having a flat surface on the insulator 404. The insulator 405 can be formed using the same materials and methods as the insulator 112. Alternatively, CMP treatment may be performed on the surface of the insulator 405.

[0286] Furthermore, on top of the insulator 405, there are conductors 413a, 413b, and 413c A conductor 413a, conductor 413b, and conductor 413c are formed. It can be manufactured using the same materials and methods as 109a.

[0287] Furthermore, the conductor 413a enters the high-concentration p-type impurity region 28 via the contact plug 406a. It is electrically connected to one side of 5. Conductor 413b is connected via contact plug 406b The high-concentration p-type impurity region 285 is electrically connected to the other side. Conductor 413c is connected It is electrically connected to the conductor 287 via the tact plug 406c.

[0288] Furthermore, the insulator 407 covers the conductors 413a, 413b, and 413c. The insulator 407 is formed using the same materials and methods as the insulator 405. This can be done. Furthermore, CMP treatment may be performed on the surface of the insulator 407.

[0289] Furthermore, an insulator 102 is formed on the insulator 407. Transis A transistor 100 is formed. An insulator 111 is formed on the transistor 100. The configuration of the layer above the edge 407 can be understood by referring to the above embodiment. Therefore, a detailed explanation of this embodiment will be omitted. Also, the conductor 109b is a contact plug. It is electrically connected to the conductor 413b via 112d.

[0290] <Example 1> An n-channel transistor may be provided on the substrate 401. Figures 33(A) and Figure 33(B) is a cross-sectional view of semiconductor device 410. Semiconductor device 410 is a semiconductor device 40 The configuration has an n-channel type transistor 282 added to 0. Figure 33(A) shows the transistor Cross section in the channel length direction of transistor 100, transistor 281, and transistor 282 This is a top view, and Figure 33(B) is an enlarged view of transistor 281.

[0291] In transistor 282, a channel formation region 1283 is formed in the well 220. Transistor 282 has a channel formation region 1283, a high-concentration n-type impurity region 1285, It has an insulator 286, a conductor 287, and a structure 288. Furthermore, the structure is connected via the insulator 286. It has a low-concentration n-type impurity region 1284 in the region that overlaps with body 288.

[0292] The low-concentration n-type impurity region 1284 is conductive after the formation of the conductor 287 and before the formation of the structure 288. It can be formed by introducing impurity elements using body 287 as a mask. In other words, the low-concentration n-type impurity region 1284 can be formed by self-alignment. After the formation of the material 288, a high-concentration n-type impurity region 1285 is formed. The material region 1284 has the same conductivity type as the high-concentration n-type impurity region 1285, thus conferring the conductivity type. The concentration of impurities is lower than in the high-concentration n-type impurity region 1285. Also, the low-concentration n-type impurity region 1284 may not be necessary depending on the situation.

[0293] <Modification 2> Another transistor 100 may be provided above transistor 100. Figure 34 shows This is a cross-sectional view of semiconductor device 420. Semiconductor device 420 is located on semiconductor device 410. It has a transistor 100a with the same configuration as transistor 100. Also, transistor 1 An insulator 111a is provided on 00.

[0294] Transistor 100a is provided on insulator 112 via insulator 407a. Although not shown in Figure 34, the insulator 112 and the insulator 103 of the transistor 100a are also shown. An insulator 102a may be provided between a. Insulator 407a, insulator 103a, insulator 1 02a and insulator 111a are insulator 407, insulator 103, and insulator 102, respectively. It can be provided using the same materials and methods as the insulator 111. Also, transistor 1 00a can be manufactured in the same way as transistor 100.

[0295] Furthermore, the semiconductor device 420 has capacitive elements 141 and 142. One of the conductors 413c constituting 141 forms conductors 413a and conductors 413b. A portion of the conductive layer is used to provide the conductive material 413a and conductive material 413b in the same layer. It is possible. In addition, the other conductor 109c that constitutes the capacitive element 141 is conductor 10 Using a portion of the conductive layer for forming 9a and conductor 109b, the conductive 109a and It can be provided in the same layer as the conductor 109b. Sandwiched between the conductor 109c and the conductor 413c. The resulting insulating layer can function as a dielectric layer for the capacitive element 141.

[0296] <Variation 3> Figures 35(A) to 35(C) are cross-sectional views of the semiconductor device 430. This involves converting the transistor 281 of the semiconductor device 400 to a Fin-type transistor 291. It has a modified configuration. By making the transistor a Fin type, the effective channel The width is increased, which can improve the on-characteristics of the transistor. Also, the channel formation region This allows for a higher contribution of the gate electrode's electric field to the region, thus improving the transistor's off-zone characteristics. It can improve sexual performance.

[0297] Furthermore, compared to semiconductor device 400, semiconductor device 430 has a capacitive element above the transistor. It differs in that it has a sub-element 413. The capacitive element 413 has a conductor 114b and a second conductor, It has a conductor 114 and an insulator sandwiched between the second conductor. The conductor 114b is insulator 1 It is provided on 12. Also, the conductor 114b is connected to the transistor via the contact plug 113b. Connected to a conductor 109b that functions as the drain electrode or source electrode of the zista 100, The conductor 109b is provided in the openings of the insulator 407, insulator 102, and insulator 118. The gate of transistor 291 is connected via the contact plug and conductor 413b, etc. It is connected to the conductor 287, which functions as an electrode.

[0298] [Semiconductor circuits] The transistors disclosed herein include OR circuits, AND circuits, NAND circuits, and Logic circuits such as NOR gates, inverter circuits, buffer circuits, shift register circuits, and Lip-flop circuits, encoder circuits, decoder circuits, amplifier circuits, analog switch circuits It can be used in various semiconductor circuits such as integrating circuits, differentiating circuits, and memory elements. .

[0299] In this embodiment, Figures 36(A) to 36(E) are used to describe the peripheral circuit and the pixel circuit. An example of a CMOS circuit that can be used is shown. Circuit symbol for a transistor where OS transistors are preferred in circuit diagrams, etc. The term "OS" is added to it.

[0300] The CMOS circuit shown in Figure 36(A) consists of a p-channel transistor 281 and an n-channel transistor. Two transistors of type 282 are connected in series, and their gates are connected, forming an inverter. This shows an example of a circuit configuration.

[0301] The CMOS circuit shown in Figure 36(B) consists of a p-channel transistor 281 and an n-channel transistor. This shows an example of an analog switch circuit configuration with two 282 transistors connected in parallel. .

[0302] The CMOS circuit shown in Figure 36(C) consists of transistor 281a, transistor 281b, An example of a NAND circuit configuration using transistors 282a and 282b is shown. The NAND gate is a combination of the potentials input to input terminal IN_A and input terminal IN_B. The output potential changes depending on the combination.

[0303] [Storage device] The circuit shown in Figure 37(A) connects either the source or the drain of transistor 289 to The structure of the memory connected to the gate of the transistor 1281 and one electrode of the capacitive element 257 An example is shown. Also, the circuit shown in Figure 37(B) has the source of transistor 289 and This shows an example of a memory device configuration in which one side of the drain is connected to one electrode of the capacitive element 257. Yes, they are.

[0304] The circuits shown in Figures 37(A) and 37(B) have a source or discharge of transistor 289. The charge input from the other side of the rain can be held at node 256. Transition By using an OS transistor at node 289, the charge at node 256 can be maintained for a long period of time. It is possible.

[0305] In Figure 37(A), transistor 1281 is shown as a p-channel type transistor. However, an n-channel transistor may also be used. For example, transistor 1281 and Transistor 281 or transistor 282 may be used. Also, the transistor An OS transistor may be used as the TA1281.

[0306] Here, regarding the semiconductor device (memory device) shown in Figures 37(A) and 37(B), Let me explain in detail.

[0307] The semiconductor device shown in Figure 37(A) consists of a transistor 1281 using a first semiconductor and a second semiconductor. It has a transistor 289 made of semiconductor material and a capacitive element 257.

[0308] Transistor 289 is the OS transistor disclosed in the above embodiment. Due to the low off-current of the STA289, it is possible to write to specific nodes of the semiconductor device over a long period of time. It is possible to retain the stored content. In other words, it does not require a refresh operation, or Because the refresh operation frequency can be made extremely low, low power consumption semiconductors It becomes a body device.

[0309] In Figure 37(A), wiring 251 is the source or drain of transistor 1281. One side is electrically connected, and wiring 252 is either the source or drain of transistor 1281. It is electrically connected to the other side. Also, wiring 253 is the source or slave of transistor 289. One side of the circuit is electrically connected, and wiring 254 is electrically connected to the gate of transistor 289. And the gate of transistor 1281, the source of transistor 289, The other end of the drain, and one electrode of the capacitive element 257, are electrically connected to node 256. It is also electrically connected to the other electrode of the capacitive element 257. .

[0310] The semiconductor device shown in Figure 37(A) has the special feature of being able to retain the charge applied to node 256. Having this property allows for the writing, storage, and reading of information, as shown below.

[0311] [Writing operation, holding operation] This section explains how to write and retain information. First, the potential of wiring 254 is determined by the transistor... Set the potential so that terminal 289 is turned ON. This will set the potential of wiring 253 to node 256 It is given to. That is, a predetermined charge is given (written) to node 256. Here, Charges that give two different potential levels (hereinafter referred to as "Low-level charge" and "High-level charge") It is said that either of the following is given: "charge". Then, the potential of wiring 254 is set to By setting the potential to the OFF state of lamp 289, a charge is retained at node 256. .

[0312] Furthermore, the high-level charge gives node 256 a higher potential than the low-level charge. Let the charge be as follows. Also, when a p-channel type transistor is used for transistor 1281 Both the high-level charge and the low-level charge are threshold voltages of the transistor. This is a charge that gives a higher potential than [this value]. Also, an n-channel type transistor is used with transistor 1281. When using a transistor, both high-level and low-level charges are transmitted. The potential is lower than the threshold voltage of the zista. That is, the high-level charge and L Both low-level charges are charges that provide the potential that turns the transistor off.

[0313] Because the off-current of transistor 289 is extremely small, the charge at node 256 remains constant for a long period of time. It stands and is held.

[0314] [Read operation] Next, we will explain how to read the information. Wiring 251 has a predetermined potential that is different from the potential of wiring 252. When a potential (constant potential) is applied and a read potential V is applied to wiring 255, the information held at node 256 can be read out. R

[0315] Let the potential applied by the High-level charge be V H , and the potential applied by the Low-level charge be V L . Then, the read potential V R should be set to { (Vth - V H ) + (Vth + V L )} / 2 . When not reading information, the potential of wiring 255 should be set higher than V H when using a p-channel transistor for transistor 1281, and lower than V L when using an n-channel transistor for transistor 1281. H L R H L H L

[0316] For example, when using a p-channel transistor for transistor 1281, if the Vth of transistor 1281 is -2V, V H is 1V, and V L is -1V, then V R should be set to -2V . When the potential written to node 256 is V H and V R is applied to wiring 25'5, -1V, which is V R + V H , is applied to the gate of transistor 1281. Since -1V is higher than Vth, transistor 1281 does not turn on. Therefore, the potential of wiring 252 does not change. Also, when the potential written to node 256 is V L and V R is applied to wiring '''255, V R + V L is applied to the gate of transistor 1281. H L R H R R H L When the potential written to node 256 is V L and V R is applied to wiring 255, V R + V L is applied to the gate of transistor 1281. R R L ​​​​​​​​​​​​​​​​​​​​​​​​​​​​​, sand A voltage of -3V is applied. Since -3V is lower than Vth, transistor 1281 turns on. This condition occurs. Therefore, the potential of wiring 252 changes.

[0317] Furthermore, when an n-channel type transistor is used for transistor 1281, the transistor The Vth of TA1281 is 2V, and V H V L If we set V to -1V, then V R Let's set it to 2V. That's all you need to do. The potential written to node 256 is V H At that time, V is connected to the 255 wire. R Given Then, V is applied to the gate of transistor 1281. R +V H That is, 3V is applied. 3V is Since it is higher than Vth, transistor 1281 turns on. Therefore, wiring 252 The potential changes. Also, the potential written to node 256 is V L At that time, V is connected to the 255 wire. R Given this, V is applied to the gate of transistor 1281. R +V L That is, 1V is applied It will turn on. Since 1V is lower than Vth, transistor 1281 will not turn on. Therefore, the potential of wiring 252 does not change.

[0318] By determining the potential of wiring 252, the information held in node 256 can be read. It is possible.

[0319] The semiconductor device shown in Figure 37(B) does not have transistor 1281, which is the same as in Figure 37(A). This is different from the semiconductor device shown in Figure 37(A). In this case, it operates similarly to the semiconductor device shown in Figure 37(A). This allows for the writing and retention of information.

[0320] The information readout process in the semiconductor device shown in Figure 37(B) will be explained. Wiring 25 When a potential is applied to 4 that turns on transistor 289, the floating wiring 25 3 and the capacitive element 257 become conductive, and charge is redistributed between the wiring 253 and the capacitive element 257. As a result, the potential of wiring 253 changes. The amount of change in the potential of wiring 253 is measured at node 256. It takes on different values ​​depending on the potential (or the charge accumulated at node 256).

[0321] For example, let V be the potential of node 256, C be the capacitance of capacitive element 257, and C be the capacitance of wiring 253. If the quantitative component is CB and the potential of wiring 253 before charge redistribution is VB0, then the charge redistribution The potential of wiring 253 after it has been laid is (CB × VB0 + C × V) / (CB + C). Therefore, as a state of the memory cell, the potentials of node 256 are V1 and V0 (V1 > V0) If we consider two states, the potential of wiring 253 when potential V1 is maintained is (=(CB) (×VB0+C×V1) / (CB+C)) is the value of wiring 253 when the potential V0 is maintained. It can be seen that the potential becomes higher than (=(CB×VB0+C×V0) / (CB+C)).

[0322] Then, by comparing the potential of wiring 253 with a predetermined potential, information can be read out. ru.

[0323] The semiconductor device described above uses an oxide semiconductor and has an extremely low off-current transistor. By applying this method, it becomes possible to retain memory content over a long period of time. The refresh operation will either become unnecessary or its frequency will be extremely low. This makes it possible to realize semiconductor devices with low power consumption. Also, the power supply Even in the absence of (however, it is preferable that the potential is fixed), over a long period of time It is possible to retain the contents of memory.

[0324] Furthermore, since this semiconductor device does not require a high voltage for writing information, element degradation does not occur. It is less prone to problems. For example, unlike conventional non-volatile memory, electrons to the floating gate Because no injection or electron extraction from the floating gate is performed, the insulator does not deteriorate. The problem described above does not occur at all. That is, the semiconductor device according to one aspect of the present invention is a conventional non-volatile semiconductor device. Unlike Mori, there is no limit to the number of rewrite cycles, and the reliability of the semiconductor has been dramatically improved. It is a physical device. Furthermore, information can be written depending on the conduction and non-conduction states of the transistor. This process enables high-speed operation.

[0325] 〔CPU〕 In this embodiment, as an example of a semiconductor device using the transistor described above, the CPU is configured as follows: Let me explain further. Figure 38 shows an example of a CPU configuration that uses the transistors described above in part. This is a block diagram.

[0326] The CPU shown in Figure 38 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a face 1189 (ROM I / F). The substrate 1190 is a semiconductor substrate, SOI A circuit board, glass substrate, etc. are used. ROM1199 and ROM interface1189 This may be provided on a separate chip. Of course, the CPU shown in Figure 38 has a simplified configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, a configuration including a CPU or arithmetic circuit as shown in Figure 38 is considered one core, and multiple such cores are... It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by arithmetic circuits and data buses is, for example, 8 bits, 16 bits, 32 bits, 6 bits. It can be set to 4 bits, for example.

[0327] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0328] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. It generates a dress and reads or writes to register 1196 depending on the CPU state. .

[0329] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, Instruction decoder 1193, Interrupt controller 1194, It generates signals to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0330] In the CPU shown in Figure 38, a memory cell is located in register 1196. The transistors and memory devices mentioned above can be used as memory cells for the TA1196. Cut.

[0331] In the CPU shown in Figure 38, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory elements in register 1196. If data retention in the capacitive element is selected, data rewriting to the capacitive element will not occur. This process can be performed to stop the supply of power voltage to the memory cells in register 1196. .

[0332] Figure 39 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 730 has a circuit 701 in which the stored data volatilizes when the power is cut off, and when the power is cut off the stored data Circuit 702 that prevents the data from volatilizing, switch 703, switch 704, and logic element 706 The circuit 702 includes a capacitive element 707 and a circuit 720 having a selection function. It has element 708, transistor 709, and transistor 710. Child 730 may include other elements such as diodes, resistors, and inductors as needed. It is also acceptable to have them.

[0333] Here, the memory device described above can be used in circuit 702. To memory element 730 When the power supply voltage is interrupted, the gate of transistor 709 in circuit 702 will be at ground potential. The configuration is such that a voltage of (0V) or a voltage that turns off transistor 709 is continuously input. For example The gate of transistor 709 is grounded via a load such as a resistor.

[0334] Switch 703 uses a single-conductivity (e.g., n-channel) transistor 713 The switch 704 is configured to have the opposite conductivity type to transistor 713 (e.g., p-channel). An example is shown using transistor 714 of type 703. Here, the first of switch 703 The terminals correspond to either the source or drain of transistor 713, and the second terminal of switch 703. The terminals correspond to the source and drain of transistor 713, and switch 703 is the transistor The control signal RD input to the gate of the ZISTA 713 controls the distance between the first and second terminals. The conduction or non-conductivity (i.e., the on or off state of transistor 713) is selected. The first terminal of switch 704 is connected to either the source or the drain of transistor 714. Accordingly, the second terminal of switch 704 is connected to the source and drain of transistor 714. In response, switch 704 is activated by the control signal RD input to the gate of transistor 714. , continuity or non-conductivity between the first terminal and the second terminal (i.e., the ON state of transistor 714) A state (either "state" or "off") is selected.

[0335] One of the sources and drains of transistor 709 is one of the pair of electrodes of capacitive element 708. One side is electrically connected to the gate of transistor 710. Here, the connection part This node is designated as M2. One of the sources and drains of transistor 710 is supplied with a low power supply potential. It is electrically connected to a wire that can do this (e.g., a GND wire), and the other is switch 703 It is electrically connected to the first terminal (one of the source and drain of transistor 713). The second terminal of switch 703 (the other of the source and drain of transistor 713) is the switch Electrically connected to the first terminal of transistor 704 (one of the source and drain of transistor 714). The second terminal of switch 704 (the other of the source and drain of transistor 714) It is electrically connected to wiring that can supply the power potential VDD. Switch 703 The second terminal (the other of the source and drain of transistor 713) and the first terminal of switch 704 The terminals (one of the source and drain of transistor 714) and the input terminal of logic element 706 And, one of the pair of electrodes of the capacitive element 707 is electrically connected. Here, connection Let the portion be called node M1. The other electrode of the pair of electrodes of the capacitive element 707 is subjected to a constant potential. It can be configured to be powered by a low power supply potential (GND, etc.) or a high power supply potential ( A configuration can be made in which VDD, etc. is input. The other side is electrically connected to wiring (e.g., a GND wire) that can supply a low power potential. The other electrode of the pair of electrodes in the capacitive element 708 is configured to receive a constant potential input. This is possible. For example, when a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. This configuration can be achieved. The other electrode of the pair of electrodes of the capacitive element 708 is at a low power supply potential. It is electrically connected to a power supply (e.g., a ground wire).

[0336] Furthermore, capacitive elements 707 and 708 accumulate parasitic capacitances of transistors and wiring, etc. It was possible to omit it by using it to its fullest extent.

[0337] The control signal WE is input to the gate electrode of transistor 709. Switch 703 Switch 704 is controlled by a control signal RD, which is different from the control signal WE, between the first and second terminals. A conductive or non-conductive state is selected between the terminals of one switch and the second terminal of the other switch. When the terminals of one switch are conductive, the terminals of the other switch, specifically the first and second terminals, are not conductive. This is the result.

[0338] The source and drain of transistor 709 are connected to the data held in circuit 701. The corresponding signal is input. In Figure 39, the signal output from circuit 701 is the transistor An example is shown where the source and drain of switch 709 are input to the other end. The signal output from the child (the other side of the source and drain of transistor 713) is sent to logic element 7 The logic value is inverted by 06, becoming an inverted signal, which is then sent to circuit 701 via circuit 720. It will be entered.

[0339] Note that in Figure 39, the second terminal of switch 703 (source and drain of transistor 713) The signal output from the other side of the input is sent to circuit 70 via logic element 706 and circuit 720. An example of inputting to 1 is shown, but it is not limited to this. The second terminal of switch 703 (transition The signals output from the source and drain (other side) of the 713 can have their logic values ​​inverted. It may be input to circuit 701 without any further processing. For example, input from the input terminal into circuit 701 If there is a node that holds a signal inverted from the logical value of the signal, switch 70 The signal output from the second terminal of 3 (the other of the source and drain of transistor 713) Input can be made to the node in question.

[0340] In Figure 39, transistor 709 corresponds to transistor 15, which was exemplified in Embodiment 1 above. 0 can be used. Also, a control signal WE is input to the gate electrode, and the back gate electric current A control signal WE2 can be input to the pole. The control signal WE2 is a signal with a constant potential and This is sufficient. The constant potential can be, for example, the ground potential (GND) or the power of transistor 709. A potential smaller than the S potential is selected. The control signal WE2 is the signal of transistor 709. This is a potential signal for controlling a high-value voltage, and the gate voltage of transistor 709 is 0V. The drain current at that time can be further reduced. Note that transistor 709 is the first It is also possible to use transistors that do not have two gates.

[0341] Furthermore, in Figure 39, among the transistors used in the memory element 730, Transistors other than T709 are made of a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. A transistor can be formed in which a channel is formed in a silicon layer or a silicon layer. A transistor can be used to form a channel on the recon substrate. Also, memory element 7 All transistors used in 30 are transistors whose channels are formed by an oxide semiconductor layer. It can also be a st. Alternatively, the memory element 730 is a transistor other than transistor 709. A transistor is defined as a transistor in which the channel is formed by an oxide semiconductor layer, and a transistor made of a non-oxide semiconductor. A transistor with a channel formed on a semiconductor layer or substrate 1190 is combined. It may also be used in this way.

[0342] For example, a flip-flop circuit can be used for circuit 701 in Figure 39. Furthermore, logic elements 706 can be, for example, inverters or clocked inverters. It is possible.

[0343] In one aspect of the present invention, in a semiconductor device, when the power supply voltage is not supplied to the memory element 730 The data stored in circuit 701 is transferred by the capacitive element 708 provided in circuit 702. This can then be stored in node M2.

[0344] Furthermore, as mentioned above, transistors in which channels are formed in the oxide semiconductor layer exhibit off-current The difference is extremely small. For example, the off-voltage of a transistor in which a channel is formed in an oxide semiconductor layer. The current is compared to the off-current of a transistor in which a channel is formed in crystalline silicon. It is extremely low. Therefore, by using this transistor as transistor 709... Therefore, even when the power supply voltage is not supplied to the memory element 730, the signal held in the capacitive element 708 will remain for a long time. This is maintained over the period. In this way, the memory element 730 retains the information even when the power supply voltage is interrupted. It is possible to retain the content (data).

[0345] Furthermore, by providing switches 703 and 704, the power supply voltage can be restored. Later, the time it takes for circuit 701 to re-store the original data can be shortened.

[0346] Furthermore, in circuit 702, the signal held at node M2 ​​is the gateway of transistor 710. It is input to the node. Therefore, after the power supply voltage to the memory element 730 is resumed, the node The signal held in M2 changes the state of transistor 710 (on or off). In exchange, it can be read from circuit 702. Therefore, the signal held at node M2 Even if the corresponding potential fluctuates slightly, it is possible to accurately read the original signal.

[0347] Such memory elements 730 are stored in registers and cache memory of the CPU. By using it in the device, it is possible to prevent the loss of data in the storage device due to the interruption of the power supply voltage. Yes, it is possible. Furthermore, after the power supply voltage is restored, it will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire CPU, or one or more logical components of the CPU, can be utilized. In the circuit, short-term power outages become possible, and the frequency of power outages can be increased. Therefore, power consumption can be reduced.

[0348] In this embodiment, although the memory element 730 was described as an example of being used in a CPU, the memory element 7 30 is a DSP (Digital Signal Processor), custom LS I, LSIs such as PLDs (Programmable Logic Devices), RF This can also be applied to the (Radio Frequency) tag.

[0349] [Imaging device] As an example of a semiconductor device using the transistors described above, an imaging device will be explained.

[0350] <Example configuration of imaging device 600> Figure 40(A) is a plan view showing an example configuration of the imaging device 600. The imaging device 600 is a plan view showing The element 621, the first circuit 260, the second circuit 270, the third circuit 280, and the fourth It has circuit 290. In this specification, the first circuit 260 to the fourth circuit 29 0 and others are sometimes referred to as "peripheral circuits" or "drive circuits." For example, the first circuit 26 0 can be considered part of the peripheral circuitry.

[0351] Figure 40(B) shows an example of the configuration of the pixel section 621. The pixel section 621 is p column q row ( Multiple pixels 622 (image sensor) arranged in a matrix of p and q (natural numbers greater than or equal to 2) ) has. Note that in Figure 40(B), n is a natural number between 1 and p, and m is between 1 and q. These are the natural numbers below.

[0352] For example, if you arrange 622 pixels in a 1920x1080 matrix, it becomes what is called full High-definition resolution (also known as "2K resolution," "2K1K," or "2K") An imaging device 600 capable of imaging can be realized. Also, for example, pixels 622 can be 40 When arranged in a 96x2160 matrix, it becomes what is known as ultra-high definition ("4K resolution"). Also known as "image quality," "4K2K," or "4K." ) Imaging device 6 capable of capturing images at this resolution. 00 can be achieved. Also, for example, 622 pixels can be used in a matrix of 8192 x 4320. When arranged in a cubic shape, it becomes what is known as Super Hi-Vision ("8K resolution", "8K4K", It is possible to realize an imaging device 600 capable of capturing images at a resolution of (also known as "8K"). By increasing the number of display elements, the imaging device 600 can capture images at resolutions of 16K or 32K. It is possible to achieve this.

[0353] The first circuit 260 and the second circuit 270 are connected to multiple pixels 622, and multiple pixels It has the function of supplying signals to drive 622. In addition, the first circuit 260 has the function of pixel It may also have a function to process the analog signal output from 622. The path 280 may have a function to control the operating timing of the peripheral circuit. For example, It may also have a function to generate a lock signal. Furthermore, it may have a function to generate an externally supplied clock signal. It may also have a function to convert the frequency of the third circuit 280. It may also have a function to supply signals (for example, ramp wave signals).

[0354] The peripheral circuits include at least logic circuits, switches, buffers, amplification circuits, or conversion circuits. It has one of the following. In addition, transistors and the like used in peripheral circuits are used in the pixel driving circuit 6 described later. It may also be formed using a part of the semiconductor formed to fabricate 10. Also, the peripheral circuit It may be implemented partially or entirely using semiconductor devices such as ICs.

[0355] Furthermore, the peripheral circuitry includes at least one of the first circuit 260 to the fourth circuit 290. This may be omitted. For example, the function of either the first circuit 260 or the fourth circuit 290 may be the In addition to the other of the first circuit 260 or the fourth circuit 290, the first circuit 260 or the fourth One of the circuits 290 may be omitted. Also, for example, the second circuit 270 or the third circuit By adding one function of circuit 280 to the other of the second circuit 270 or the third circuit 280, Either the second circuit 270 or the third circuit 280 may be omitted. Also, for example, the first The function of other peripheral circuits is added to any one of the circuits 260 to the fourth circuit 290. Therefore, other peripheral circuits can be omitted.

[0356] Furthermore, as shown in Figure 41, the first to fourth circuits 260 are located along the outer circumference of the pixel section 621. Circuit 290 may be provided. Also, in the pixel section 621 of the imaging device 600, pixel 6 Pixel 22 may be positioned at an angle. By positioning pixel 622 at an angle, the row and column directions can be adjusted. The pixel spacing (pitch) in the direction can be shortened. This allows imaging by the imaging device 600. The quality of the resulting image can be further improved.

[0357] Furthermore, as shown in Figure 42, the first circuit 260 to the fourth circuit 290 are superimposed on top of each other. An element 621 may be provided. Figure 42(A) shows the first circuit 260 to the fourth circuit 290 This is a top view of an imaging device 600 in which a pixel section 621 is formed by overlapping parts. Also, Figure 42(B) This is a perspective view illustrating the configuration of the imaging device 600 shown in Figure 42(A).

[0358] By providing the pixel section 621 on top of the first circuit 260 to the fourth circuit 290, The area occupied by the pixel section 621 relative to the size of the imaging device 600 can be increased. This improves the light-receiving sensitivity of the imaging device 600. Also, the die of the imaging device 600 The optical range can be improved. Furthermore, the resolution of the imaging device 600 can be improved. This is possible. Furthermore, it is possible to improve the reproducibility of images captured by the imaging device 600. This allows for an improvement in the integration density of the imaging device (600).

[0359] [Color filters, etc.] The image capture device 600 uses its pixels 622 as sub-pixels, and each of the multiple pixels 622 By adding a filter (color filter) that transmits light in different wavelength ranges, a color image can be created. Information necessary to display the information can be obtained.

[0360] Figure 43(A) is a plan view showing an example of 623 pixels for acquiring a color image. Figure 43(A) shows pixel 62 equipped with a color filter that transmits light in the red (R) wavelength range. 2 (hereinafter also referred to as "pixel 622R"), a color fill that transmits light in the green (G) wavelength range. Pixel 622 (hereinafter also referred to as "pixel 622G") with a marker and the blue (B) wavelength range Pixel 622 (hereinafter also referred to as "pixel 622B") is equipped with a color filter that transmits light. It has (u). Pixels 622R, 622G, and 622B are combined into one pixel 623. To make it function as such.

[0361] Furthermore, the color filters used for pixel 623 are limited to red (R), green (G), and blue (B). It does not use a color filter that transmits cyan (C), yellow (Y), and magenta (M) light. It may be. A single pixel 623 detects light in at least three different wavelength ranges. By providing 22, a full-color image can be obtained.

[0362] Figure 43(B) shows a color filter that transmits red (R), green (G), and blue (B) light, respectively. In addition to the 622 pixels equipped with filters, a color filter that transmits yellow (Y) light is provided. An example is shown of a pixel 623 having the pixel 622. Figure 43(C) shows cyan (C), pixels equipped with color filters that transmit yellow (Y) and magenta (M) light. In addition to 622, there is a pixel 622 that is equipped with a color filter that transmits blue (B) light. This illustrates a pixel 623. A single pixel 623 can detect light from four or more different wavelength ranges. By providing the pixel 622, the color reproduction accuracy of the acquired image can be further improved. .

[0363] Also, the pixel ratio (or light-receiving area) of pixels 622R, 622G, and 622B. The ratio does not necessarily have to be 1:1:1. As shown in Figure 43(D), the pixel ratio ( A Bayer array with a light-receiving area ratio of red:green:blue = 1:2:1 may also be used. The numerical ratio (light-receiving area ratio) can also be set to red:green:blue = 1:6:1.

[0364] Note that while one pixel 622 may be used for pixel 623, two or more are preferable. By providing two or more pixels 622 that detect light in the same wavelength range, redundancy is increased, and the imaging device This can improve the reliability of the 600.

[0365] Furthermore, as a filter, it absorbs or reflects light with wavelengths below the wavelength of visible light, thus blocking infrared light. By using an IR (Infrared) filter that transmits light, infrared light can be detected. This enables the realization of an imaging device 600. Furthermore, as a filter, waves longer than the wavelength of visible light can be used. UV (Ultraviolet) light absorbs or reflects light with a certain wavelength and transmits ultraviolet light. By using a (let) filter, it is possible to realize an imaging device 600 that detects ultraviolet light. It can do that. Also, a scintillator that converts radiation into ultraviolet or visible light is used as a filter. This allows the imaging device 600 to function as a radiation detector that detects X-rays, gamma rays, and the like. It's also possible.

[0366] Additionally, an ND (Neutral Density) filter can be used as a filter (reduces When a large amount of light is incident on a photoelectric conversion element (light receiving element) using an optical filter, This prevents the phenomenon of output saturation (hereinafter also referred to as "output saturation"). By using a combination of ND filters with different light intensities, the dynamic range of the imaging device can be increased. It can be made larger.

[0367] In addition to the filter mentioned above, a lens may be provided at pixel 622. (See Figure 44) Using a cross-sectional view, an example of the arrangement of pixels 622, filter 624, and lens 625 will be explained. By providing the lens 625, incident light can be efficiently received by the photoelectric conversion element. Specifically, as shown in Figure 44(A), the lens 625 formed on the pixel 622, the filter 624 (filter 624R, filter 624G, filter 624B), and pixel drive cycle The structure can be configured to allow light 660 to be incident on the photoelectric conversion element 601 through a path 610, etc. .

[0368] However, as shown in the area enclosed by the dashed line, a portion of the light 660 indicated by the arrow is connected to the wiring group 62 Part of 6, transistors, and / or capacitive elements may block the light. Therefore, as shown in Figure 44(B), the lens 625 is on the side of the photoelectric conversion element 601. A filter 624 is formed to efficiently receive the incident light into the photoelectric conversion element 601. This may also be done. By injecting light 660 from the photoelectric conversion element 601 side, a camera with high light-receiving sensitivity can be used. An imaging device 600 can be provided.

[0369] Figures 45(A) to 45(C) show a pixel driving circuit 6 that can be used in the pixel section 621. Here is one example. The pixel driving circuit 610 shown in Figure 45(A) includes transistor 602, It has a transistor 604 and a capacitive element 606, and is connected to a photoelectric conversion element 601. One of the sources or drains of transistor 602 is electrically connected to the photoelectric conversion element 601. The source or drain of transistor 602 is connected to node 607 (charge storage section). It is electrically connected to the gate of transistor 604 via ).

[0370] It is preferable to use an OS transistor for transistor 602. This allows the off-current to be made extremely small, thus enabling the capacitive element 606 to be made smaller. Yes, it is possible. Alternatively, the capacitive element 606 can be omitted, as shown in Figure 45(B). Furthermore, if an OS transistor is used as transistor 602, the potential of node 607 changes. It is difficult to move. Therefore, it is possible to realize an imaging device that is less susceptible to noise. Alternatively, an OS transistor may be used for transistor 604.

[0371] The photoelectric conversion element 601 has pn-type and pin-type junctions formed on the silicon substrate. Diode elements can be used, or amorphous silicon films or microcrystalline silicon films, etc. A pin-type diode element using this may also be used. Alternatively, a diode-connected transistor may be used. A photoelectric resistor may also be used. In addition, a variable resistor utilizing the photoelectric effect can be made of silicon, germanium, etc. It may also be formed using elements such as um and selenium.

[0372] Furthermore, as a photoelectric conversion element, a material capable of absorbing radiation and generating electric charge is used. It may be formed by absorbing radiation and generating an electric charge. Examples include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

[0373] The pixel driving circuit 610 shown in Figure 45(C) includes transistors 602 and 603 It has transistor 604, transistor 605, and capacitive element 606, and photoelectric conversion element It is connected to child 601. Note that the pixel driving circuit 610 shown in Figure 45(C) is a photoelectric conversion This shows the case where a photodiode is used as element 601. One of the drains or the other is electrically connected to the cathode of the photoelectric conversion element 601, and the other is It is electrically connected to node 607. The anode of photoelectric conversion element 601 is connected to wiring 611. It is electrically connected to the node. Either the source or drain of transistor 603 is connected to the node. One end is electrically connected to 607, and the other end is electrically connected to wiring 608. Transistor The gate of node 604 is electrically connected to node 607, and either the source or drain is wired. It is electrically connected to 609, and the other end is connected to either the source or drain of transistor 605. They are electrically connected. The source or drain of transistor 605 is connected to the other wire 60 It is electrically connected to 8. One electrode of the capacitive element 606 is electrically connected to node 607. The other electrode is then electrically connected to the wiring 611.

[0374] Transistor 602 can function as a transfer transistor. The transfer signal TX is supplied to the transistor. Transistor 603 is a reset transistor. It can function. The gate of transistor 603 is supplied with the reset signal RST. Transistor 604 can function as an amplifying transistor. Transistor 605 is a selection transistor. It can function as a zista. The gate of transistor 605 is supplied with the selection signal SEL. Additionally, VDD is supplied to wiring 608 and VSS is supplied to wiring 611.

[0375] Next, the operation of the pixel driving circuit 610 shown in Figure 45(C) will be explained. First, the transistor Turn on ZISTA 603 and supply VDD to node 607 (reset operation). After that, when transistor 603 is turned off, VDD is held at node 607. When transistor 602 is turned ON, the amount of light received by photoelectric conversion element 601 is controlled. The potential of transistor 607 changes (storage operation). Then, transistor 602 is turned off. Then, the potential of node 607 is maintained. Next, when transistor 605 is turned ON, A potential corresponding to the potential of node 607 is output from wiring 609 (selection operation). Wiring 60 By detecting the potential at 9, the amount of light received by the photoelectric conversion element 601 can be determined.

[0376] OS transistors can be used for transistors 602 and 603. This is preferable. As mentioned earlier, OS transistors can have extremely low off-currents. Therefore, the capacitance element 606 can be made smaller. Alternatively, the capacitance element 606 can be omitted. This is possible. Also, as transistors 602 and 603, OS transistors Using this method, the potential of node 607 is less likely to fluctuate. Therefore, it is less susceptible to noise. An imaging device can be realized.

[0377] Pixel 6 using any of the pixel driving circuits 610 shown in Figures 45(A) to 45(C) By arranging the 22s in a matrix, a high-resolution imaging device can be realized.

[0378] For example, if the pixel driving circuit 610 is arranged in a 1920 x 1080 matrix, Loose Full HD (also known as "2K resolution," "2K1K," or "2K") An imaging device capable of capturing images at a resolution of 6 can be realized. Also, for example, a pixel driving circuit 6 Arranging 10 in a 4096 x 2160 matrix results in what is known as ultra-high definition. Capable of capturing images at a resolution (also known as "4K resolution," "4K2K," or "4K"). An imaging device can be realized. Also, for example, the pixel driving circuit 610 can be set to 8192 x 43 When arranged in a matrix of 20, it becomes what is known as Super Hi-Vision ("8K resolution"), It is also called "8K4K" or "8K". The goal is to realize an imaging device capable of capturing images at this resolution. This is possible. By increasing the number of display elements, it is possible to create an imaging device capable of capturing images at resolutions of 16K or 32K. It is possible to achieve this.

[0379] Figure 46 shows an example of the structure of pixel 622 using the transistor described above. Figure 46 shows pixel 622 This is a cross-sectional view of part of 2.

[0380] The pixel 622 shown in Figure 46 uses an n-type semiconductor as the substrate 401. A p-type semiconductor 221 of the photoelectric conversion element 601 is provided in 01. Also, the substrate 401 A portion of it functions as the n-type semiconductor 223 of the photoelectric conversion element 601.

[0381] Furthermore, transistor 604 is provided on the substrate 401. Transistor 604 is n It can function as a channel-type transistor. Also, a portion of the substrate 401 contains a p-type semiconductor. Well 220 is provided. Well 220 is provided in the same manner as the formation of the p-type semiconductor 221. It is possible to do so. Also, the well 220 and the p-type semiconductor 221 can be formed at the same time. For example, the transistor 282 mentioned above can be used as transistor 604. It is possible.

[0382] Furthermore, insulators 403 and 40 are placed on the photoelectric conversion element 601 and the transistor 604. 4, and an insulator 405 are formed. The substrate 401 of the insulators 403 to 405 An opening 224 is formed in the region overlapping with (n-type semiconductor 223), and insulator 403 to insulator 4 An opening 225 is formed in the region overlapping with the p-type semiconductor 221 of 05. Also, an opening 224 And a contact plug 406 is formed in the opening 225. Contact plug 40 6 can be provided in the same manner as the contact plug 113a described above. Furthermore, the opening 22 There are no particular restrictions on the number or arrangement of 4 and opening 225. Therefore, the degree of layout freedom is high. This enables the realization of high-performance imaging devices.

[0383] Furthermore, conductors 421, 422, and 429 are formed on the insulator 405. The conductor 421 is connected via the contact plug 406 provided in the opening 224. It is electrically connected to the n-type semiconductor 223 (substrate 401). Also, the conductor 429 is open The p-type semiconductor 221 is electrically connected via the contact plug 406 provided in port 225. The conductor 422 can function as one electrode of the capacitive element 606.

[0384] Furthermore, an insulator 407 is formed covering the conductors 421, 429, and 422. The insulator 407 can be formed using the same materials and methods as the insulator 405. It is possible to perform CMP treatment on the surface of the insulator 407. This reduces surface irregularities in the sample, thereby improving the coverage of the insulating and conductive layers formed thereafter. Yes, it is possible. Conductors 421, 422, and 429 are the same as the aforementioned conductor 114a. It can be formed using the same materials and methods as described above.

[0385] Furthermore, an insulator 102 is formed on top of the insulator 407, and a conductor 427 is formed on top of the insulator 102. A conductor 119 and an electrode 273 are formed. The conductor 427 is a contact plug. It is electrically connected to the conductor 429 via the transistor 602. It can function as a back gate. Electrode 273 acts as the other electrode of the capacitive element 606. It is possible. Transistor 602 can, for example, use the transistor 100 mentioned above. can.

[0386] Furthermore, the conductor 109a is electrically connected to the conductor 427 via a contact plug. Yes, they are.

[0387] <Example 1> Figure 47 shows an example of a different pixel 622 configuration from Figure 46. This is a view drawing.

[0388] The pixel 622 shown in Figure 47 is connected to transistor 604 and transistor 605 on the substrate 401. A feature is provided. Transistor 604 can function as an n-channel transistor. Transistor 605 can function as a p-channel transistor. For example, the transistor 282 mentioned above can be used as transistor 604. For example, the transistor 281 mentioned above can be used as transistor 605.

[0389] Conductors 413a to 413d are formed on the insulator 405. Conductor 41 3a is electrically connected to either the source or drain of transistor 604, and conductor 4 13b is electrically connected to the other side of the source or drain of transistor 604. Conductor 413c is electrically connected to the gate of transistor 604. Conductor 41 3b is electrically connected to either the source or drain of transistor 605, and conductor 4 13d is electrically connected to the other side of the source or drain of transistor 605.

[0390] Conductors 109b and 413c are electrically connected via contact plug 112d. In addition, an insulator 4 is placed on the conductor 114a, the conductor 114b, and the insulator 112. 15 is formed. The insulator 415 is formed using the same material and method as the insulator 111. It is possible.

[0391] Furthermore, the pixel 622 shown in Figure 47 has a photoelectric conversion element 601 provided on the insulator 415. Furthermore, an insulator 442 is provided on the photoelectric conversion element 601, and a conductor is provided on the insulator 442. 488 is provided. The insulator 442 is formed of the same material and in the same manner as the insulator 415. It is possible.

[0392] The photoelectric conversion element 601 shown in Figure 47 consists of a conductor 686 made of a metal material and a light-transmitting material. A photoelectric conversion layer 681 is provided between the conductive layer 682 and the photoelectric conversion layer 681. In Figure 47, a selenium-based material is photoelectrically converted. The form used in layer 681 is shown. The photoelectric conversion element 601 using selenium-based material is visible It possesses the characteristic of high external quantum efficiency for light. In this photoelectric conversion element, the avalanche phenomenon occurs. This allows for a highly sensitive sensor with a large amplification of electrons in response to the amount of incident light. Furthermore, selenium-based materials have a high light absorption coefficient, which offers the advantage of making the photoelectric conversion layer 681 thinner. do.

[0393] As selenium-based materials, amorphous selenium or crystalline selenium can be used. For example, selenium can be obtained by heat-treating amorphous selenium after film formation. By making the crystal grain size of crystalline selenium smaller than the pixel pitch, the variation in characteristics from pixel to pixel is reduced. It can be reduced. Also, crystalline selenium has better spectral properties in visible light than amorphous selenium. It possesses characteristics such as high sensitivity and light absorption coefficient.

[0394] Although the photoelectric conversion layer 681 is shown as a single layer, there are holes on the light-receiving surface side of the selenium-based material. A blocking layer such as gallium oxide or cerium oxide is provided, and electron injection is performed on the conductor 686 side. It is also possible to configure the system to include nickel oxide or antimony sulfide as an intrusion blocking layer. .

[0395] Furthermore, the photoelectric conversion layer 681 is a layer containing a copper, indium, and selenium compound (CIS). Alternatively, a layer containing a copper, indium, gallium, and selenium compound (CIGS) may be used. In CIS and CIGS, the avalanche phenomenon occurs, similar to a selenium monolayer. It is possible to form usable photoelectric conversion elements.

[0396] Furthermore, CIS and CIGS are p-type semiconductors, and to form a junction, an n-type semiconductor is required. Cadmium sulfide or zinc sulfide may be placed in contact with it.

[0397] In order to generate the avalanche phenomenon, a relatively high voltage (for example, 1) is applied to the photoelectric conversion element. It is preferable to apply a voltage of 0V or higher. OS transistors are more powerful than Si transistors. Because it has high rain resistance characteristics, it is possible to apply relatively high voltages to the photoelectric conversion element. It is easy. Therefore, an OS transistor with a high drain breakdown voltage and a selenium-based material for photoelectric transformation. By combining it with a photoelectric conversion element as a replacement layer, a highly sensitive and reliable imaging device can be created. It is possible.

[0398] The translucent conductive layer 682 contains, for example, indium tin oxide, silicon-containing indium tin oxide. Oxides, zinc-containing indium oxide, zinc oxide, gallium-containing zinc oxide, aluminum Zinc oxide containing zinc oxide, tin oxide containing fluorine, tin oxide containing antimony, or graphite Engravers and the like can be used. Also, the translucent conductive layer 682 is not limited to a single layer, but can be made of layers of different films. It may also be a layer. Also, in Figure 47, the translucent conductive layer 682 and the wiring 487 are conductor 48 The diagram illustrates a configuration in which the electrical connections are made via 8 and contact plug 489, but light transmission The conductive layer 682 and the wiring 487 may be in direct contact.

[0399] Furthermore, even if the conductor 686 and wiring 487 have a configuration in which multiple conductive layers are stacked... Good. For example, the conductor 686 can be made into two layers, conductor 686a and conductor 686b, and the wiring 487 This can be made into two layers of conductor 487a and conductor 487b. Also, for example, conductor 6 86a and the conductor 487a are formed by selecting a low-resistance metal, and the conductor 686b and When the conductive material 487b is formed by selecting a metal or the like that has good contact characteristics with the photoelectric conversion layer 681, Good. This configuration can improve the electrical characteristics of the photoelectric conversion element. Furthermore, some metals may undergo galvanic corrosion upon contact with the translucent conductive layer 682. Even if such a metal is used for the conductor 487a, by using the conductor 487b as an intermediary... This can prevent galvanic corrosion.

[0400] Conductors 686b and 487b include, for example, molybdenum and tungsten. It can be used. Also, the conductors 686a and 487a can be, for example, aluminum. Laminations can be used in which nium, titanium, or aluminum are sandwiched between layers of titanium.

[0401] Furthermore, the insulator 442 may be configured to be multilayered. The partition wall 477 may be an inorganic insulator or an insulating material. It can be formed using an organic resin or the like. Also, the partition wall 477 is used in transistors, etc. To block light and / or to determine the area of ​​the light-receiving part per pixel, black or similar colors are used. It may be colored.

[0402] Furthermore, the photoelectric conversion element 601 uses an amorphous silicon film or a microcrystalline silicon film. An in-type diode element may also be used. The photodiode is an n-type semiconductor layer. It has a configuration in which an i-type semiconductor layer and a p-type semiconductor layer are stacked in order. It is preferable to use amorphous silicon for the conductive layer. Also, p-type semiconductor layer and n-type The semiconductor layer contains amorphous silicon or microcrystalline silicon containing dopants that impart each conductivity type. Amorphous silicon can be used. The device has high sensitivity in the visible light wavelength range and can easily detect weak visible light.

[0403] Furthermore, pn-type and pin-type diode elements are designed so that the p-type semiconductor layer becomes the light-receiving surface. It is preferable to use a p-type semiconductor layer as the light-receiving surface, which allows the output of the photoelectric conversion element 601 to be used. The current can be increased.

[0404] The photoelectric conversion element 601 formed using the selenium-based material or amorphous silicon described above is The semiconductor is manufactured using common semiconductor fabrication processes such as thin-film deposition, lithography, and etching. It is possible to manufacture it.

[0405] [Display device] As an example of a semiconductor device using the transistors described above, a display device will be described. Display devices (such as liquid crystal displays and light-emitting displays) that have display elements come in various forms. It can use a specific configuration or have various elements.

[0406] Display devices include, for example, EL (electroluminescent) elements (organic and inorganic materials). (Includes EL elements, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chips) LED chips, green LED chips, blue LED chips, etc.), transistors (depending on the current) Transistors that emit light, electron emission elements, display elements using carbon nanotubes, liquid Crystal elements, electronic inks, electrowetting elements, electrophoretic elements, MEMS (microphones) Display elements using an electromechanical system (for example, a grating) GLV (Glycerid Valve), Digital Micromirror Device (DMD), DMS (Digital Micromirror Device) • Micro shutter), MIRASOL (registered trademark), IMOD (interferer) MEMS (Morphin Modulation) elements, shutter-type MEMS display elements, optical interference type MEMS MS display elements, piezoelectric ceramic displays, etc., or quantum dots, etc. I also have one.

[0407] In addition to these, display devices control contrast, brightness, etc., through electrical or magnetic effects. The display medium may have a change in reflectance, transmittance, etc. For example, the display device may have a plasma A digital display (PDP) is also acceptable.

[0408] An example of a display device using EL elements is an EL display. An example of a display device using this technology is a field emission display (FED). or SED type flat-panel display (SED: Surface-conduction Examples include Electron-emitter Displays.

[0409] An example of a display device that uses quantum dots for each pixel is a quantum dot display. Yes, they exist. However, quantum dots are not used as display elements, but rather as backings for liquid crystal displays and the like. It may be installed in part of the light. By using quantum dots, a display with high color purity can be achieved. It is possible.

[0410] An example of a display device using liquid crystal elements is a liquid crystal display device (transmissive liquid crystal display, Semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection type Examples include LCD displays.

[0411] Furthermore, when realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, pixels The electrodes can be made to function as reflective electrodes, either partially or entirely. The pixel electrodes may be made of aluminum, silver, or the like, either partially or entirely. Furthermore, in that case, it is also possible to install memory circuits such as SRAM below the reflective electrode. This further reduces power consumption.

[0412] Examples of display devices using electronic ink, electronic powder fluid (registered trademark), or electrophoretic elements. Examples include e-paper.

[0413] Furthermore, when using LED chips as display elements, the electrodes of the LED chip and nitride semiconductors... Graphene or graphite may be placed below it. Graphene or graphite may be multiple Multiple layers can be stacked to form a multilayer film. In this way, graphene or graphite can be incorporated. By doing so, a nitride semiconductor, such as an n-type GaN semiconductor layer having crystals, is placed on top of it. It can be easily formed into a film. Furthermore, a p-type GaN semiconductor layer having crystals can be formed on top of it. By providing this, an LED chip can be constructed. Furthermore, graphene and graphite, An AlN layer may be provided between the n-type GaN semiconductor layer having a crystal. The GaN semiconductor layer in the device may be deposited by MOCVD. However, if graphene is provided... By doing so, the GaN semiconductor layer on the LED chip can also be deposited by sputtering. It is Noh.

[0414] Furthermore, in display elements using MEMS, the space in which the display element is sealed (for example) , an element substrate on which display elements are arranged, and a counter substrate arranged opposite to the element substrate. A desiccant may be placed between the two. By placing a desiccant, MEMS and other materials will retain moisture. This prevents the device from becoming difficult to move or from deteriorating easily.

[0415] <Example of pixel circuit configuration> Next, we will explain a more specific example of the display device configuration using Figure 48. Figure 48(A ) is a block diagram illustrating the configuration of the display device 3100. The display device 3100 is It has a display area 3131, a circuit 3132, and a circuit 3133. Circuit 3132 is, for example, For example, it functions as a scan line driving circuit. Also, circuit 3133 can function as, for example, a signal line driving circuit. It functions.

[0416] Furthermore, the display devices 3100 are arranged approximately parallel to each other and are powered by the circuit 3132. m scan lines 3135 whose position is controlled, and each of them is arranged approximately parallel to the circuit 3133 It has n signal lines 3136 whose potential is controlled by a signal. Furthermore, it has a display area 313 1 has multiple pixels 3130 arranged in an m x n matrix. Note that m and n are Both are natural numbers greater than or equal to 2.

[0417] In the display area 3131, each scan line 3135 corresponds to one of the rows of pixels 3130. It is electrically connected to n pixels 3130 arranged on the . In addition, each signal line 3136 is connected to the pixel m pixels 3130 located in any of the rows of element 3130 are electrically connected. .

[0418] Also, as shown in Figure 49(A), the display area 3131 is separated from the circuit 3132. A circuit 3152 may be provided at this position. Also, as shown in Figure 49(B), the display area 31 Circuit 3153 may be placed opposite circuit 3133 with 31 in between. Figure 49(A In Figure 49(B), circuit 3152 is connected to scan line 3135 in the same way as circuit 3132. This shows an example. However, it is not limited to this; for example, circuit 3 connected to scan line 3135. You can change 132 and circuit 3152 every few rows. In Figure 49(B), circuit 3153 is changed Show an example of connecting to signal line 3136, similar to line 3133. However, this is not limited to this example. Alternatively, circuits 3133 and 3153 connected to signal line 3136 may be changed every few lines. Furthermore, circuits 3132, 3133, 3152, and 3153 are located at pixel 3130 It may have functions other than driving the motor.

[0419] Furthermore, circuits 3132, 3133, 3152, and 3153 are connected to the drive circuit section. In some cases, this may be the case. Pixel 3130 has a pixel circuit 3137 and a display element. Circuit 3137 is a circuit that drives the display elements. The transistors in the drive circuit section are for the pixels. It can be formed simultaneously with the transistors that make up circuit 3137. Also, the drive circuit section Part or all of it may be formed on another substrate and electrically connected to the display device 3100. For example, a part or all of the drive circuit section may be formed using a single crystal substrate, and the display device 3100 It may also be electrically connected to it.

[0420] Figures 48(B) and 48(C) are used for the pixels 3130 of the display device 3100. This shows possible circuit configurations.

[0421] An example of a pixel circuit for a light-emitting display device. Figure 48(B) shows an example of a pixel circuit that can be used in a light-emitting display device. The pixel circuit 3137 shown in the image comprises a transistor 3431, a capacitive element 3233, and a transistor It has a sta 3232 and a transistor 3434. Furthermore, the pixel circuit 3137 displays It is electrically connected to a light-emitting element 3125 that can function as an element.

[0422] One of the source and drain electrodes of transistor 3431 receives a data signal. It is electrically connected to the nth signal line 3136 (hereinafter referred to as signal line DL_n). Furthermore, the gate electrode of transistor 3431 is on the mth scan line 3 to which the gate signal is applied. It is electrically connected to 135 (hereinafter referred to as scan line GL_m).

[0423] Transistor 3431 controls the function of writing data signals to node 3435. To possess.

[0424] One of the pair of electrodes of the capacitive element 3233 is electrically connected to node 3435, and the other is It is electrically connected to node 3437. Also, the source electrode of transistor 3431 and The other end of the drain electrode is electrically connected to node 3435.

[0425] Capacitive element 3233 is used as a holding capacity to hold the data written to node 3435. It has a function.

[0426] One of the source and drain electrodes of transistor 3232 is connected to the potential supply line VL_a One is electrically connected to node 3437, and the other is electrically connected to node 3437. Furthermore, the transistor The gate electrode of terminal 3232 is electrically connected to node 3435.

[0427] One of the source and drain electrodes of transistor 3434 is connected to the potential supply line VL_c One is electrically connected to node 3437, and the other is electrically connected to node 3437. Furthermore, the transistor The gate electrode of TA3434 is electrically connected to the scan line GL_m.

[0428] One of the light-emitting element 3125, either the anode or the cathode, is electrically connected to the potential supply line VL_b. One end is connected, and the other is electrically connected to node 3437.

[0429] For example, the light-emitting element 3125 is an organic electroluminescent element (organic EL element and (Also known as) etc. can be used. However, it is not limited to this, for example, from inorganic materials Inorganic EL elements may also be used.

[0430] For example, the potential supply line VL_a has the function of supplying VDD. Also, the potential supply line VL _b has the function of supplying VSS. Also, the potential supply line VL_c is a device that supplies VSS. To have the ability.

[0431] Here, we will explain an example of the operation of a display device having the pixel circuit 3137 shown in Figure 48(B). First, the pixel circuit 3137 of each row is sequentially selected by the circuit 3132, and transistor 3 Turn on 431 to write the data signal (potential) to node 3435. Next, Turn on the zista 3434 and set the potential of node 3437 to VSS.

[0432] Subsequently, the data written to node 3435 with transistor 3431 in the OFF state The signal is held. Next, transistor 3434 is turned off. Transistor 3232 The amount of current flowing between the source and drain corresponds to the data signal written to node 3435. It is determined accordingly. Therefore, the light-emitting element 3125 emits light with a brightness corresponding to the amount of current flowing through it. By performing this step by step for each row, the image can be displayed.

[0433] Furthermore, multiple pixels 3130 are used, each as a sub-pixel, and different values ​​are obtained from each sub-pixel. By emitting light in a specific wavelength range, a color image can be displayed. For example, red Pixel 3130 emitting light in the wavelength range, pixel 3130 emitting light in the green wavelength range, and blue wave Pixel 3130, which emits long-range light, is used as a single pixel.

[0434] Furthermore, the wavelength range of light to be combined is not limited to red, green, and blue, but also includes cyan, yellow, and It may also be magenta. A sub-element that emits light from at least three different wavelength ranges in one pixel. By adding pixels, color images can be displayed.

[0435] In addition, add one or more colors such as yellow, cyan, magenta, and white to red, green, and blue. This is also fine. For example, adding sub-pixels that emit light in the yellow wavelength range in addition to red, green, and blue. That's good. You can also add one or more colors such as red, green, blue, and white to cyan, yellow, and magenta. For example, adding subpixels that emit light in the blue wavelength range, in addition to cyan, yellow, and magenta. It is also possible to provide subpixels that emit light in four or more different wavelength ranges within a single pixel. This can further improve the color reproduction accuracy of the displayed images.

[0436] Furthermore, the ratio of red, green, and blue pixels (or luminescence area ratio) used in a single pixel is not necessarily It doesn't have to be 1:1:1. For example, the pixel ratio (light emission area ratio) can be red:green:blue = 1:1: It may also be set to 2. Alternatively, the pixel ratio (light-receiving area ratio) may be set to red:green:blue = 1:2:3. .

[0437] Furthermore, by combining sub-pixels that emit white light with color filters such as red, green, and blue, It is also possible to implement a red display. Furthermore, sub-pixels that emit light in the red, green, or blue wavelength range can be used. Each of these can be combined with a color filter that transmits light in the red, green, or blue wavelength range. good.

[0438] However, the present invention is not limited to color display devices, but also includes monochrome display devices. It can also be applied to display devices.

[0439] An example of a pixel circuit for a liquid crystal display device. Figure 48(C) shows an example of a pixel circuit that can be used in a liquid crystal display device. The pixel circuit 3137 shown in the diagram has a transistor 3431 and a capacitive element 3233. Furthermore, the pixel circuit 3137 is electrically connected to the liquid crystal element 3432, which can function as a display element. It continues.

[0440] The potential of one of the pair of electrodes of the liquid crystal element 3432 is set appropriately according to the specifications of the pixel circuit 3137. The settings are configured. The liquid crystal contained in the liquid crystal element 3432 is used to write data to node 3436. The orientation state is set by the liquid crystal elements of each of the multiple pixel circuits 3137. A common potential may be applied to one of the pair of electrodes of sub-electrode 3432.

[0441] Examples of modes for the liquid crystal element 3432 include TN mode, STN mode, and VA mode. , ASM(Axially Symmetric Aligned Micro-cel l) Mode, OCB (Optically Compensated Birefringence) gence) mode, FLC (Ferroelectric Liquid Crystal) al) mode, AFLC (AntiFerroelectric Liquid Cry stal) mode, MVA mode, PVA (Patterned Vertical A Ignition mode, IPS mode, FFS mode, or TBA (Transv You may also use modes such as (Bend Alignment). Also, see other examples. And, ECB (Electrically Controlled Birefringence) ence) mode, PDLC (Polymer Dispersed Liquid Crystal C (rystal) mode, PNLC (Polymer Network Liquid Crystal C There are modes such as (original) mode and guest host mode. However, it is not limited to these, Various modes can be used.

[0442] Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element 3432 may be configured in this way. The liquid crystal exhibiting the blue phase has a response speed of 1 mse Because it is short (less than c) and optically isotropic, orientation processing is unnecessary, and it has low field-of-view angle dependence. Sai.

[0443] In the pixel circuit 3137 of row m, column n, the source electrode and the dot of transistor 3431 One end of the rain electrode is electrically connected to the signal line DL_n, and the other end is electrically connected to node 3436. They are connected precisely. The gate electrode of transistor 3431 is electrically connected to scan line GL_m. Transistor 3431 controls the writing of data signals to node 3436. It has a function.

[0444] One of the pair of electrodes of the capacitive element 3233 is connected to a wiring to which a specific potential is supplied (hereinafter referred to as "capacitive element"). Also called "Line CL". It is electrically connected to ( ), and the other end is electrically connected to node 3436. Furthermore, the other electrode of the pair of electrodes of the liquid crystal element 3432 is electrically connected to node 3436. The potential value of the capacitance line CL is set appropriately according to the specifications of the pixel circuit 3137. The quantitative element 3233 is a memory capacity that holds the data written to node 3436. To have the ability.

[0445] Here, we will explain an example of the operation of a display device having the pixel circuit 3137 shown in Figure 48(C). First, the pixel circuit 3137 of each row is sequentially selected by the circuit 3132, and the transition Turn on station 3431 and write the data signal to node 3436.

[0446] Next, the data signal written to node 3436 with transistor 3431 in the OFF state It holds the number. In response to the data signal written to node 3436, the liquid crystal element 3432 The amount of transmitted light is determined. By performing this sequentially for each row, the image can be displayed in the display area 3131. Cut.

[0447] <Example of display device configuration> Using the transistor shown in the above embodiment, a part of the drive circuit including the transistor Alternatively, the entire system can be integrally formed on the same substrate as the pixel section, thus forming a system-on-panel. The above embodiment describes an example of a display device configuration that can use the transistor shown above. This will be explained using Figures 50 and 51.

[0448] [Liquid crystal display devices and electroluminescent display devices] Examples of display devices include a display device using liquid crystal elements and a display device using EL elements. Let me explain. In Figure 50(A), the pixel section 40 provided on the first substrate 4001 A sealing material 4005 is provided surrounding 02, and it is sealed by the second substrate 4006. In Figure 50(A), the sealing material 4005 on the first substrate 4001 is used. In a region different from the enclosed area, a single-crystal semiconductor or polycrystalline semiconductor is placed on a separately prepared substrate. A signal line drive circuit 4003 and a scan line drive circuit 4004, both made of semiconductors, are mounted. Also, the signal line drive circuit 4003, the scan line drive circuit 4004, or the pixel unit 4002 The various signals and potentials applied to the FPC (Flexible Printed Circuit) are It is supplied from cuit)4018a and FPC4018b.

[0449] In Figures 50(B) and 50(C), the pixel section 4 provided on the first substrate 4001 A sealing material 4005 is provided so as to surround 002 and the scan line drive circuit 4004. Furthermore, a second substrate 4006 is provided on top of the pixel section 4002 and the scan line driving circuit 4004. Therefore, the pixel section 4002 and the scan line driving circuit 4004 are connected to the first substrate 400 The display element is sealed together with the sealing material 4005 and the second substrate 4006. In Figures 50(B) and 50(C), the sealing material 4005 on the first substrate 4001 is shown. In a region different from the region enclosed by the, a single-crystal semiconductor or A signal line driving circuit 4003 made of polycrystalline semiconductor is mounted. Figure 50(B) and In Figure 50(C), the signal line drive circuit 4003, the scan line drive circuit 4004, or the image The various signals and potentials supplied to the element unit 4002 are provided by the FPC 4018.

[0450] Furthermore, in Figures 50(B) and 50(C), the signal line drive circuit 4003 is formed separately. The example shown is mounted on the first substrate 4001, but the configuration is not limited to this. Alternatively, a separate line drive circuit may be formed and implemented, or it may be part of the signal line drive circuit or the scan line drive circuit. It is also acceptable to separately form and implement only a portion of the path.

[0451] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and wired connections are available. Ding, COG (Chip On Glass), TCP (Tape Carrier) Packages, COF (Chip On Film), etc., can be used. Figure 50(A) shows the implementation of the signal line drive circuit 4003 and the scan line drive circuit 4004 using COG. This is an example, and Figure 50(B) shows an example of implementing the signal line drive circuit 4003 using a COG. Figure 50(C) shows an example of implementing the signal line drive circuit 4003 using TCP.

[0452] Furthermore, the display device includes a panel in which the display elements are sealed, and a control on the panel This may include modules that have ICs, etc., mounted on them, including those containing R.

[0453] Furthermore, the pixel section and scanning line driving circuit provided on the first substrate have multiple transistors. Therefore, the transistor shown in the above embodiment can be applied.

[0454] Figures 51(A) and 51(B) show the region indicated by the dashed line N1-N2 in Figure 50(B). This is a cross-sectional view showing the cross-sectional configuration. The display device shown in Figures 51(A) and 51(B) has electrodes 40 It has 15, and the electrode 4015 has terminals on the FPC 4018 and an anisotropic conductive layer 4019 They are electrically connected via the insulating layer 4112 and the insulating layer 4 111, and electrically connected to the wiring 4014 at the opening formed in the insulating layer 4110 It is being done.

[0455] Electrode 4015 is formed from the same conductive layer as the first electrode layer 4030, and wiring 4014 is Source and drain electrodes of transistors 4010 and 4011 It is formed from the same conductive layer.

[0456] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple transistors, and in Figures 51(A) and 51(B), the pixel section 4002 The transistor 4010 included and the transistor 40 included in the scan line drive circuit 4004 Figure 51(A) illustrates transistors 4010 and 4 An insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 are provided on 011, as shown in Figure 5. In 1(B), a partition wall 4510 is formed on top of the insulating layer 4112.

[0457] Furthermore, transistors 4010 and 4011 are provided on the insulating layer 4102. It is also provided with an insulating layer 410. 2 has an electrode 4017 formed on it, and an insulating layer 4103 is formed on the electrode 4017. ru. Electrode 4017 can function as a back gate electrode.

[0458] Transistors 4010 and 4011 are the transistors shown in the above embodiment. A transistor can be used. The transistor exemplified in the above embodiment has electrical characteristic fluctuations. This is suppressed and electrically stable. Therefore, as shown in Figures 51(A) and 51(B) The display device of this embodiment can be made into a highly reliable display device.

[0459] Note that in Figures 51(A) and 51(B), transistor 4010 and transistor As transistor 4011, a transistor having the same structure as transistor 160 shown in the above embodiment. This provides an example of using a transistor.

[0460] Furthermore, the display devices shown in Figures 51(A) and 51(B) have a capacitive element 4020. Capacitive element 4020 is connected to either the source electrode or the drain electrode of transistor 4010. It has a portion and a region where the electrode 4021 overlaps via the insulating layer 4103. The electrode 4021 is It is formed from the same conductive layer as electrode 4017.

[0461] Generally, the capacitance of a capacitive element in a display device is determined by the capacitance of a transistor located in the pixel. The capacitive element is set to retain charge for a predetermined period, taking into account leakage current and other factors. The capacitance should be set considering the transistor's off-current, etc.

[0462] For example, by using OS transistors in the pixel section of a liquid crystal display device, the capacitance of the capacitive element can be reduced. The quantity can be set to 1 / 3 or less, or 1 / 5 or less, of the liquid crystal capacity. By using a converter, the formation of capacitive elements can be omitted.

[0463] The transistor 4010 provided in the pixel section 4002 is electrically connected to the display element. Figure 51(A) is an example of a liquid crystal display device using liquid crystal elements as display elements. In this, the liquid crystal element 4013, which is a display element, has a first electrode layer 4030 and a second electrode layer It includes 4031 and a liquid crystal layer 4008. Furthermore, an alignment film and An insulating layer 4032 and an insulating layer 4033 are provided that function as such. It is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are liquid They are superimposed via crystal layer 4008.

[0464] Furthermore, the spacer 4035 is a columnar space obtained by selectively etching the insulating layer. This is a control of the gap (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. It is provided for control purposes. A spherical spacer may also be used.

[0465] When using liquid crystal elements as display elements, thermotropic liquid crystals, low molecular weight liquid crystals, and polymer liquid crystals are used. Liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials, depending on the conditions, can be classified into cholesteric phase, smectic phase, cubic phase, and It exhibits iralnematic phase, isotropic phase, etc.

[0466] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Therefore, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears immediately before. The blue phase only appears within a narrow temperature range, so the temperature range needs to be modified. To improve performance, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. Because it is short and optically isotropic, orientation processing is unnecessary and it has low dependence on the viewing angle. Since a film does not need to be formed, rubbing treatment is also unnecessary, thus preventing the effects caused by rubbing treatment. This prevents electrostatic discharge damage caused by friction, reducing defects and damage to liquid crystal displays during the manufacturing process. This makes it possible to improve the productivity of liquid crystal display devices.

[0467] Furthermore, a pixel is divided into several subpixel regions, each in a different direction. This is called multi-domainization or multi-domain design, which is a method of knocking down molecules. A method can be used.

[0468] Furthermore, the resistivity of the liquid crystal material is 1 × 10⁻⁶ 9 The value is Ω·cm or greater, preferably 1 × 10⁻⁶. 1 1 It is Ω·cm or greater, and more preferably 1 × 10⁻⁶ 12 It is greater than Ω·cm. The resistivity values ​​in the detailed specifications shall be those measured at 20°C.

[0469] The OS transistor used in this embodiment has an off-state current value (off-current value) This can be made lower. Therefore, the holding time of electrical signals such as image signals can be extended. Furthermore, the write interval can be set to be longer when the power is on. Therefore, the frequency of refresh operations can be set. Because it can reduce power consumption, it has the effect of suppressing power consumption.

[0470] Furthermore, OS transistors can achieve relatively high field-effect mobility, enabling high-speed operation. Therefore, by using the above transistor in the pixel section of the display device, high-quality images can be produced. This can provide the following: Furthermore, the drive circuit section or pixel section can be manufactured separately on the same substrate. This makes it possible to reduce the number of parts in the display device.

[0471] Furthermore, in a display device, a black matrix (light-shielding layer), a polarizing member, a phase difference member, and a reverse Optical components (optical substrates) such as anti-radiation members may be provided as appropriate. For example, polarizing substrate and Circularly polarized light using a phase difference substrate may also be used. Furthermore, backlights and sidelights can be used as light sources. You may also use the following:

[0472] Furthermore, the display element included in the display device utilizes light emission that employs electroluminescence. Elements can be applied. Light-emitting devices that utilize electroluminescence are light-emitting materials They are distinguished by whether the substance is an organic compound or an inorganic compound; generally, the former is organic EL elements, and the latter are called inorganic EL elements.

[0473] Organic EL elements emit electrons and positive voltages from a pair of electrodes when a voltage is applied to the light-emitting element. Each pore is injected into a layer containing a luminescent organic compound, and an electric current flows through it. The recombination of carriers (electrons and holes) causes the luminescent organic compound to form an excited state. It then emits light when the excited state returns to the ground state. From this mechanism, These light-emitting elements are called current-excited light-emitting elements.

[0474] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements depending on their element configuration. It is classified as follows: Dispersed inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. It possesses a donor-acceptor level, and the luminescence mechanism utilizes donor-acceptor levels. This is acceptor-recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism involves the inner-shell electron transition of metal ions. The localized light emission method used is localized light emission. For this explanation, an organic EL element is used as the light-emitting element. do.

[0475] A light-emitting element only needs to have at least one of its pair of electrodes transparent in order to extract light. Then, a transistor and a light-emitting element are formed on the substrate, and light is emitted from the side opposite to the substrate. Top emission structures that emit light from the top surface, and bottom emission structures that extract light from the substrate side. (Bottom emission) structure, or double-sided emission (dual emission) that extracts light from both sides. There are light-emitting elements with an (n) structure, and any light-emitting element with an injection structure can be applied.

[0476] Figure 51(B) shows a light-emitting display device ("EL display device") that uses a light-emitting element as a display element. It is also called.) This is an example. The light-emitting element 4513, which is a display element, is provided in the pixel section 4002. It is electrically connected to the transistor 4010. The configuration of the light-emitting element 4513 is as follows: The structure is a stacked structure consisting of an electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031. The configuration is not limited to this. Depending on the direction of light extracted from the light-emitting element 4513, The configuration of 4513 can be changed as needed.

[0477] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, photosensitive resin Using a lipid material, an opening is formed on the first electrode layer 4030, and the side surface of the opening is continuous. It is preferable to form the surface so that it is an inclined surface with curvature.

[0478] Even if the light-emitting layer 4511 consists of a single layer, it is configured so that multiple layers are stacked. Either way is fine.

[0479] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4513, the second electrode A protective layer may be formed on layer 4031 and partition wall 4510. As the protective layer, silica nitride Cone, silicon nitride, aluminum oxide, aluminum nitride, aluminum oxide nitride Aluminum nitride, DLC (Diamond-Like Carbon), etc. This can be achieved. Also, the first substrate 4001, the second substrate 4006, and the sealing material 4 The space sealed by 005 is filled with a filler material 4514 and sealed in this manner. Therefore, a protective film with high airtightness and minimal degassing (laminate film) is used to prevent exposure to the outside air. It is preferable to package (enclose) the product with film, UV-curing resin film, or other covering material. It seems so.

[0480] In addition to inert gases such as nitrogen and argon, filler material 4514 can also be UV-curing resin. Alternatively, thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resin, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's all you need to do.

[0481] Additionally, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. Even if optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters are appropriately provided, Good. Alternatively, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, due to surface irregularities... It is possible to apply an anti-glare treatment that diffuses reflected light and reduces glare.

[0482] A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer, In the counter electrode layer (also called the counter electrode layer), the direction of the light to be extracted, the location where the electrode layer is provided, and Transmittance and reflectivity can be selected based on the pattern structure of the electrode layer.

[0483] The first electrode layer 4030 and the second electrode layer 4031 are made of indium containing tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide The materials used are transparent conductive materials such as indium tin oxide with added silicon dioxide. It is possible.

[0484] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) and molybdenum. N (Mo), Zirconium (Zr), Hafnium (Hf), Vanadium (V), Niobium ( Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), chromium (Cr), cobalt (Co), nickel (Ni), chromium (Cr), cobalt (Co), cobalt (Co), cobalt (Ni), cobalt (Co Gold, such as tungsten (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag). It can be formed using one or more of the genus, its alloys, or its metal nitrides. ru.

[0485] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 are made of conductive polymer (conductive polymer It can be formed using a conductive composition containing a conductive polymer (also called a rimer). Therefore, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, Alternatively, derivatives thereof may be mentioned.

[0486] Furthermore, transistors are susceptible to damage from static electricity, etc., so a protective circuit is needed to protect the drive circuit. It is preferable to provide a path. The protection circuit is preferably constructed using nonlinear elements.

[0487] By using the transistor shown in the above embodiment, a highly reliable display device can be provided. It is possible to achieve high resolution by using the transistor shown in the above embodiment. Furthermore, it is possible to create large-area displays and provide display devices with good display quality. This allows for the provision of a display device with reduced power.

[0488] [Display Module] As an example of a semiconductor device using the transistors described above, we will explain a display module. To clarify, the display module 6000 shown in Figure 52 consists of an upper cover 6001 and a lower cover 60 Between 02 and FPC6003, touch sensors 6004 and FPC6005 are connected to FPC6003. The following components were connected: display panel 6006, backlight unit 6007, frame 6009, and pre- It has a circuit board 6010 and a battery 6011. Furthermore, the backlight unit 6007, The battery 6011, touch sensor 6004, etc., may not be provided in all cases.

[0489] A semiconductor device according to one aspect of the present invention includes, for example, a touch sensor 6004 and a display panel 6006. It can be used for integrated circuits mounted on printed circuit board 6010, for example, display The aforementioned display device can be used on panel 6006.

[0490] The upper cover 6001 and lower cover 6002 are connected to the touch sensor 6004 and the display panel. The shape and dimensions can be appropriately modified to match sizes such as 6006.

[0491] The touch sensor 6004 is a resistive or capacitive touch sensor that can be used on a display panel. It can be used superimposed on 6006. The display panel 6006 has a touch sensor function. It is also possible to add touch sensor electrodes within each pixel of the display panel 6006. It is also possible to add a capacitive touch panel function by providing a table. A light sensor is provided in each pixel of the display panel 6006, adding the functionality of an optical touch sensor. It is also possible to do such things.

[0492] The backlight unit 6007 has a light source 6008. It may also be provided at the end of the unit 6007 and configured to use a light diffuser plate. When using a light-emitting display device or the like in part 6006, the backlight unit 6007 may be omitted. It is possible.

[0493] Frame 6009 has a protective function for the display panel 6006, as well as a function on the printed circuit board 6010 side. It has the function of an electromagnetic shield to block the electromagnetic waves generated. 6009 may also function as a heat sink.

[0494] Printed circuit board 6010 is for power supply circuits, video signals, and clock signals. It includes signal processing circuits, etc. The power supply for the power supply circuit is battery 6011. It may be a commercial power source, or it may be a commercial power source. This allows for the omission of battery 6011.

[0495] Furthermore, components such as polarizing plates, phase difference plates, and prism sheets are added to the display module 6000. They may also be provided.

[0496] This embodiment can be appropriately combined with other embodiments and examples shown in this specification. It is possible.

[0497] [RF Tag] As an example of a semiconductor device using the transistors described above, we will explain the RF tag. .

[0498] An RF tag according to one aspect of the present invention has a memory circuit (storage device) inside, and the memory circuit contains information It stores information and exchanges information with the outside world using contactless means, such as wireless communication. Due to these characteristics, RF tags can identify items by reading individual information about those items. It can be used in individual authentication systems and the like. High reliability is required for this purpose.

[0499] The configuration of an RF tag will be explained using Figure 53. Figure 53 shows an example of an RF tag configuration. This is a block diagram.

[0500] As shown in Figure 53, the RF tag 800 is connected to the communicator 801 (interrogator, reader / writer, etc.) An antenna that receives a radio signal 803 transmitted from antenna 802 connected to (also known as) It has 804. The above-mentioned transistor may be used for the communicator 801. Also, RF tag 8 00 represents the rectifier circuit 805, the constant voltage circuit 806, the demodulation circuit 807, the modulation circuit 808, and the logic circuit. It has a path 809, a memory circuit 810, and a ROM 811. It is also included in the demodulation circuit 807. The semiconductor of the transistor that exhibits a rectifying effect is capable of sufficiently suppressing reverse current. For example, an oxide semiconductor may be used. This eliminates the rectification effect caused by reverse current. This suppresses the drop and prevents the output of the demodulation circuit from saturating. In other words, the input to the demodulation circuit The output of the corresponding demodulation circuit can be made closer to linear. The data transmission format is one-to-one. An electromagnetic coupling method in which coils are placed opposite each other and communication is performed by mutual induction, using an induced electromagnetic field They are broadly classified into three types: electromagnetic induction methods for communication, and radio wave methods for communication using radio waves. RF tags The 800 can be used in either of these methods.

[0501] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with the antenna 802. Also, a rectifier circuit... 805 processes the input AC signal generated by receiving a wireless signal with antenna 804. For example, a half-wave voltage doubling rectifier is used, and the rectified signal is smoothed by a subsequent capacitive element. This is a circuit for generating the input potential. Note that this is either the input or output side of the rectifier circuit 805. It may have a limiter circuit. A limiter circuit is used when the amplitude of the input AC signal is large. When the internally generated voltage is high, control is implemented to prevent power exceeding a certain level from being input to the subsequent circuit. This is a circuit for that purpose.

[0502] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is the circuit. Note that the constant voltage circuit 806 has a reset signal generation circuit inside. Good. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 8. This is a circuit for generating the 09 reset signal.

[0503] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 is used to process the data output from the antenna 804. This is a circuit for modulating accordingly.

[0504] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is It is a circuit that holds the input information, such as a row decoder, column decoder, and memory area. It has the following. Furthermore, ROM811 stores a unique number (ID), etc., and outputs according to the processing. This is the circuit for performing the action.

[0505] Furthermore, the circuits described above can be selected or omitted as appropriate.

[0506] The memory device described above can be used in the memory circuit 810. The device is suitable for RF tags because it can retain information even when the power is cut off. Furthermore, in one aspect of the present invention, the storage device has a power (voltage) required for writing data that is Because it is lower than conventional non-volatile memory, the maximum communication distance during data reading and writing is It is also possible to avoid any discrepancies. Furthermore, if there is insufficient power during data writing, malfunctions may occur. This can help prevent errors or mistakes from occurring.

[0507] Furthermore, a storage device according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will apply to ROM811. A separate command is provided for writing data, preventing users from freely overwriting it. It is preferable that the producer writes a unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, only the good quality tags that are shipped will have a unique number assigned to them. This makes it possible to assign a unique number to each individual product, preventing discontinuity in the unique numbers of products after shipment. This eliminates the need for customer management after product shipment, making it easier to handle customer issues related to the product after it has been shipped.

[0508] An example of the use of an RF tag according to one aspect of the present invention will be explained with reference to Figure 54. Its uses are wide-ranging, including banknotes, coins, securities, bearer bonds, driver's licenses, and resident registration documents. Certificates such as tickets (see Figure 54(A)), recording media such as DVD software and videotapes (Figure 54(A)) See 54(B).), containers such as plates, cups, and bottles (see Figure 54(C)), wrapping paper and boxes and Packaging materials such as ribbons, mobile devices such as bicycles (see Figure 54(D)), personal belongings such as bags and glasses. The following items are prohibited: personal belongings, plants, animals, human bodies, clothing, household goods, medical supplies including drugs and pharmaceuticals, or electronic devices. Devices (for example, liquid crystal displays, EL displays, television equipment, or mobile phones), etc. The items, or the tags attached to each item (see Figures 54(E) and 54(F)). It can be installed and used anywhere.

[0509] An RF tag 800 according to one aspect of the present invention can be attached to or embedded in the surface of an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 800 is designed to be small, thin, and lightweight, and even after being attached to an item, it does not affect the design of the item itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. An RF tag 800 according to one aspect of the present invention can be provided with an authentication function, and this authentication By utilizing this function, counterfeiting can be prevented. Furthermore, packaging containers, recording media, and personal devices... An RF tag 800 according to one aspect of the present invention is attached to a product, clothing, household goods, or electronic device. By installing it, the efficiency of systems such as inspection systems can be improved. Also, By attaching an RF tag 800 according to one aspect of the present invention to a mobile object, theft and other theft can be prevented. This can enhance security. As described above, RF tag according to one aspect of the present invention The 800 can be used for each of the applications described above.

[0510] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0511] (Embodiment 5) <Package using a lead frame type interposer> Figure 55(A) shows the cross-sectional structure of a package using a lead frame type interposer. A perspective view is shown. The package shown in Figure 55(A) is a semiconductor device according to one aspect of the present invention. The corresponding chip 551 is attached to the end of the interposer 550 by wire bonding. It is connected to child 552. Terminal 552 is connected to the chip 551 of interposer 550. It is positioned on the surface that is being molded. The tip 551 is made of molded resin 553. They may be sealed, but a portion of each terminal 552 is exposed when sealed. .

[0512] Figure 55(B) shows an example of the configuration of an electronic device in which the package is mounted on a circuit board. The electronic device shown in Figure 55(B) is installed in, for example, a mobile phone. The sub-device has a package 562 and a battery 564 mounted on a printed circuit board 561. Furthermore, a printed circuit board 561 is provided on the panel 560 on which the display element is located. It is implemented by C563.

[0513] This embodiment can be appropriately combined with other embodiments and examples shown in this specification. It is possible.

[0514] (Embodiment 6) This embodiment describes an example of an electronic device using a semiconductor device according to one aspect of the present invention. explain.

[0515] As an electronic device using a semiconductor device according to one aspect of the present invention, a display device such as a television or monitor Lighting fixtures, desktop or notebook personal computers, word processors Data can be stored on recording media such as DVDs (Digital Versatile Discs). Image playback device for playing back still images or videos, portable CD player, radio, tape Pre-recorders, headphone stereos, stereos, desk clocks, wall clocks, cordless phone cords Transceivers, car phones, mobile phones, personal digital assistants, tablet devices, portable gaming devices Fixed game machines such as pachinko machines, calculators, electronic organizers, e-book readers, and electronic translators. , audio input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. High-frequency heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, Air conditioning equipment such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, and clothing. Dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, Examples include flashlights, tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Furthermore, guide lights, traffic lights, conveyor belts, elevators, escalators, and industrial robots. Industrial equipment such as power storage systems, energy leveling systems, and energy storage devices for smart grids. These include engines that use fuel, and electric motors that use electricity from energy storage devices. Moving objects can also sometimes be included in the category of electronic devices. Examples of such moving objects include, for example... Electric vehicles (EVs), hybrid electric vehicles (HEVs) that combine internal combustion engines and electric motors, plastic PHEVs, tracked vehicles that replace these tires and wheels with tracks, Motorized bicycles including electric assist bicycles, motorcycles, electric wheelchairs, golf carts, Small or large vessels, submarines, helicopters, aircraft, rockets, satellites, space probes and Examples include planetary probes and spacecraft.

[0516] The portable game console 2900 shown in Figure 56(A) consists of a casing 2901, a casing 2902, and a display unit. 2903, display unit 2904, microphone 2905, speaker 2906, operation keys 290 It has seven elements. The portable game console shown in Figure 25(A) has two display units 2903 and It has a display unit 2904, but the number of display units is not limited to this. Display unit 2903 It is equipped with a touchscreen as an input device and can be operated using a stylus 2908, etc. It is possible to create it.

[0517] The information terminal 2910 shown in Figure 56(B) consists of a housing 2911, a display unit 2912, and a microphone 2 917, speaker unit 2914, camera 2913, external connection unit 2916, and operating button It has a tan 2915, etc. The display section 2912 has a display panel made of a flexible substrate and It is equipped with a touchscreen. The information terminal 2910 is, for example, a smartphone or mobile phone. , as tablet information terminals, tablet personal computers, e-book readers, etc. It can be used.

[0518] The notebook personal computer 2920 shown in Figure 56(C) has a casing 2921 and a display It includes a section 2922, a keyboard 2923, and a pointing device 2924, etc.

[0519] The video camera 2940 shown in Figure 56(D) consists of a housing 2941, a housing 2942, and a display unit 2 It has 943, an operation key 2944, a lens 2945, and a connecting part 2946, etc. - 2944 and lens 2945 are provided in housing 2941, and display unit 2943 is housing It is provided in body 2942. And housing 2941 and housing 2942 are connected by connection part 2946 They are connected by, and the angle between housing 2941 and housing 2942 is determined by the connecting part 2946 The structure is designed to be interchangeable. Depending on the angle of housing 2942 relative to housing 2941 This includes changing the orientation of the image displayed on the display unit 2943, and switching the display / hide status of the image. It is possible to do so.

[0520] Figure 56(E) shows an example of a bangle-type information terminal. The information terminal 2950 is housed in casing 295 1, and a display unit 2952, etc. The display unit 2952 is located on a curved housing 2951. It is supported. The display unit 2952 is equipped with a display panel using a flexible substrate. This allows us to provide the 2950, ​​a flexible, lightweight, and user-friendly information terminal.

[0521] Figure 56(F) shows an example of a wristwatch-type information terminal. The information terminal 2960 is housed in casing 2961 Display unit 2962, band 2963, buckle 2964, operation button 2965, input / output terminals It is equipped with sub-units 2966, etc. Information terminal 2960 is a mobile phone, email, document viewing and creation Various applications such as music playback, internet communication, and computer games. It can be executed.

[0522] The display surface of the display unit 2962 is curved, and the display can be displayed along the curved surface. The display unit 2962 is equipped with a touch sensor, allowing you to touch the screen with your finger or stylus. It can be operated by doing so. For example, the icon 2967 displayed on the display unit 2962 By touching it, you can launch the application. Operation button 2965 is for time. In addition to settings, it also controls power on / off, wireless communication on / off, and silent mode activation. It can be equipped with various functions such as disabling, activating and deactivating power saving mode, etc. The operating system built into the information terminal 2960 controls the operation buttons 296 You can also configure function 5.

[0523] Furthermore, the information terminal 2960 is capable of performing standardized short-range wireless communication. For example, by communicating with a wireless headset, hands-free communication is possible. It can also speak. Furthermore, the information terminal 2960 is equipped with input / output terminals 2966, and other information terminals Data can be exchanged directly via the connector. Also, input / output terminal 29 Charging can also be performed via 66. Note that the charging operation does not use input / output terminal 2966. This may also be done by wireless power transfer.

[0524] Figure 56(G) shows an electric refrigerator as an example of a household electrical appliance. Electric refrigerator 2970 is It includes a housing 2971, a refrigerator door 2972, and a freezer door 2973, etc.

[0525] Figure 56(H) is an external view showing an example of an automobile. Automobile 2980 is a vehicle body 2981 It has wheels 2982, a dashboard 2983, and lights 2984, etc.

[0526] The electronic device shown in this embodiment includes the transistor or semiconductor device described above. It is equipped with it.

[0527] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0528] (Embodiment 7) In this embodiment, there is a deposition chamber in which a sputtering target can be installed. The film deposition apparatus (sputtering apparatus) described in this embodiment is Used in parallel plate type sputtering equipment and opposing target type sputtering equipment. It is possible.

[0529] In film deposition using a counter-target sputtering apparatus, damage to the surface to be deposited is minimal. Because it can be easily split, it is easy to obtain highly crystalline films. In other words, for film deposition of CAAC-OS, In some cases, it is preferable to use a target-type sputtering apparatus.

[0530] Furthermore, the film deposition method using a parallel plate sputtering apparatus is called PESP (Parallel It can also be called Electrode Sputtering. The film deposition method using a sputtering apparatus is called VDSP (Vapor Deposit). It can also be called (on Sputtering).

[0531] First, regarding the configuration of a film deposition apparatus that minimizes the inclusion of impurities in the film during film formation, see Figure 57 and This will be explained using Figure 58.

[0532] Figure 57 schematically shows a top view of a single-wafer multi-chamber film deposition apparatus 2700. The film deposition apparatus 2700 has a cassette port 2761 for housing the substrate and a substrate alignment An alignment port 2762 for performing an atmospheric substrate supply chamber 2701 and an atmospheric substrate From the board supply room 2701, the substrate is transported to the atmospheric substrate transport room 2702, and the substrate is brought in. Furthermore, a load lock chamber that switches the pressure inside the room from atmospheric pressure to reduced pressure, or from reduced pressure to atmospheric pressure. 2703a, and the removal of the substrate, and the room pressure from reduced pressure to atmospheric pressure, or from atmospheric pressure Unload lock chamber 2703b for switching to reduced pressure, and transport chamber 2 for transporting substrates in vacuum. 704, a substrate heating chamber 2705 for heating the substrate, and a target for film deposition. It has a film chamber 2706a, a film deposition chamber 2706b, and a film deposition chamber 2706c. Rooms 2706a, 2706b, and 2706c shall be constructed in accordance with the configuration of the above-described deposition rooms. It is possible.

[0533] Furthermore, the atmospheric substrate transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber. It is connected to the loading lock chamber 2703b, and the load lock chamber 2703a and the unload lock chamber 270 3b is connected to the transport chamber 2704, which in turn is connected to the substrate heating chamber 2705 and the film deposition chamber 2 706a is connected to deposition chambers 2706b and 2706c.

[0534] Furthermore, a gate valve 2764 is provided at the connection point of each chamber, and the atmospheric substrate supply chamber 2 With the exception of 701 and the atmospheric substrate transport chamber 2702, each chamber can be maintained in a vacuum state independently. Yes, it is possible. In addition, the atmospheric substrate transport chamber 2702 and transport chamber 2704 are connected to the transport robot 276 It has 3 and can transport substrates.

[0535] Furthermore, it is preferable that the substrate heating chamber 2705 also serve as a plasma processing chamber. (Film deposition apparatus 2700) This allows for the transport of substrates without exposure to the atmosphere between processing steps, thus preventing the substrates from being exposed to air. It can suppress the adsorption of pure substances. Furthermore, it allows for the free arrangement of the sequence of processes such as film formation and heat treatment. This can be done. Furthermore, the transport chamber, film deposition chamber, load lock chamber, unload lock chamber, and substrate heating chamber are also available. The number of rooms is not limited to the number mentioned above; the optimal number can be determined as needed, depending on the installation space and process conditions. It can be established.

[0536] Next, in Figure 57, the dotted lines X1-X2 and Y1-Y2 of the film deposition apparatus 2700, Figure 58 shows the cross-section corresponding to the dashed line Y2-Y3.

[0537] Figure 58(A) shows a cross-section of the substrate heating chamber 2705 and the transport chamber 2704, and the substrate heating The heating chamber 2705 has multiple heating stages 2765 that can accommodate substrates. The substrate heating chamber 2705 is connected to the vacuum pump 2770 via a valve. Vacuum pumps 2770 include, for example, dry pumps and mechanical booster pumps. You can use things like p.

[0538] Furthermore, heating mechanisms that can be used in the substrate heating chamber 2705 include, for example, resistance heating. It may also be a heating mechanism that uses the body or other objects to heat. Alternatively, it may use a heated gas or other medium. A heating mechanism that heats by heat conduction or thermal radiation may also be used. For example, GRTA, L You can use RTA (Real-Time Attack) and other similar speedrunning methods.

[0539] Furthermore, the substrate heating chamber 2705 is connected to the purification unit 27 via the mass flow controller 2780. It is connected to 81. Note that the mass flow controller 2780 and the purifier 2781 are connected to Although there are as many heating chambers as there are types of substrates, only one is shown for ease of understanding. Substrate heating chamber 2705 The gas introduced is one with a dew point of -80°C or lower, preferably -100°C or lower. This can be done, for example, by using oxygen gas, nitrogen gas, and noble gases (such as argon gas). ru.

[0540] The transport room 2704 has a transport robot 2763. The transport robot 2763 is each The substrate can be transported to the chamber. Furthermore, the transport chamber 2704 is connected to a vacuum pump via a valve. 2770 is connected to the cryopump 2771. The transport chamber 2704 can change from atmospheric pressure to low or medium vacuum (approximately 0.1 to several hundred Pa). The system is evacuated using the 2770 air pump, and the valve is switched to change from medium vacuum to high vacuum or ultra-high vacuum. Empty (0.1 Pa to 1 × 10⁻⁶ Pa) -7 Up to Pa, the exhaust is performed using the cryopump 2771. ru.

[0541] Furthermore, for example, two or more cryopumps 2771 can be connected in parallel to the transport chamber 2704. You may continue. With this configuration, one cryopump is in the process of regeneration. However, it is possible to evacuate using the remaining cryopump. "Ne" refers to the process of releasing molecules (or atoms) accumulated inside a cryopump. A lyopump's exhaust capacity decreases if it accumulates too many molecules (or atoms). Regeneration occurs periodically.

[0542] Figure 58(B) shows the deposition chamber 2706b, the transport chamber 2704, and the load lock chamber 2703a. This shows a cross-section.

[0543] Here, we will explain the details of the deposition chamber (sputtering chamber) using Figure 58(B). The deposition chamber 2706b shown in Figure 58(B) contains target 2766a and target 276 6b, target shield 2767a, target shield 2767b, magnet The components include the power unit 2790a, the magnet unit 2790b, the substrate holder 2768, and the power supply Source 2791 and, although not shown, target 2766a and target 276 Each of the 6b components is secured to the target holder via a backing plate. Power supply 2791 is electrically connected to target 2766a and target 2766b. Magnet unit 2790a and magnet unit 2790b are each These are placed on the back of target 2766a and target 2766b. Shield 2767a and target shield 2767b are each attached to target 2766 It is positioned to surround the edges of a and target 2766b. Note that here the substrate holder The substrate 2769 is supported by the 2768. The substrate holder 2768 is a variable member 27 It is fixed to the deposition chamber 2706b via 84. The variable member 2784 controls the target 2 The substrate extends to the region between 766a and target 2766b (also called the inter-target region). The holder 2768 can be moved. For example, a substrate holder supporting a substrate 2769 Placing 2768 in the inter-target region can reduce plasma damage. In some cases, the substrate holder 2768, although not shown in the figure, holds the substrate 2769. The device may also include a holding mechanism or a heater for heating the substrate 2769 from the back.

[0544] Additionally, the target shield 2767 prevents sputtering from the target 2766. This can suppress the accumulation of particles in unwanted areas. Target Shield 2767 is It is desirable to process the surface in a way that prevents the accumulated sputtered particles from peeling off. For example, surface roughening Blasting to increase the thickness, or creating irregularities on the surface of the target shield 2767 That's good too.

[0545] Furthermore, the film deposition chamber 2706b is connected to the mass flow controller 2 via the gas heating mechanism 2782. Connected to 780, the gas heating mechanism 2782 precisely controls the flow rate via the mass flow controller 2780. It is connected to the fabrication machine 2781. It is introduced into the film deposition chamber 2706b by the gas heating mechanism 2782. The gas is heated to a temperature of 40°C to 400°C, preferably 50°C to 200°C. Yes, it is possible. Note that the gas heating mechanism 2782, mass flow controller 2780, and purification machine are also included. Although there are as many 2781 elements as there are gas species, only one is shown for the sake of clarity. The gas introduced into room 2706b has a dew point of -80°C or lower, preferably -100°C or lower. Gases can be used, for example, oxygen gas, nitrogen gas, and noble gases (argon gas) Use (etc.).

[0546] Furthermore, if a purification unit is installed immediately before the gas inlet, the distance from the purification unit to the film deposition chamber 2706b The length of the piping shall be 10m or less, preferably 5m or less, and more preferably 1m or less. By limiting the length to 10m or less, 5m or less, or 1m or less, the impact of gases released from the piping can be reduced. This can be reduced according to the length. Furthermore, the gas piping contains iron fluoride, aluminum oxide, and acid It is preferable to use metal piping with an internal coating of chromium oxide or similar material. The aforementioned piping is, for example, made of stainless steel (SUS). Compared to 316L-EP piping, the amount of gas containing impurities released is reduced, and impurities do not enter the gas. This reduces clogging. Additionally, high-performance, ultra-compact metal gasket fittings (UPG) are used for pipe joints. It is advisable to use fittings. Also, by constructing the entire piping out of metal, it is possible to achieve the same results as when using resin, etc. In comparison, this method is preferable because it reduces the impact of emitted gas and external leaks.

[0547] Furthermore, the deposition chamber 2706b is connected to the turbomolecular pump 2772 and the vacuum pump via a valve. It connects to P2770.

[0548] Furthermore, a cryotrap 2751 is installed in the film deposition chamber 2706b.

[0549] The Cryotrap 2751 adsorbs molecules (or atoms) with relatively high melting points, such as water. This is a mechanism that can do so. The turbomolecular pump 2772 can handle large-...

Claims

1. A first conductor and The first insulator on the first conductor, The first oxide semiconductor layer on the first insulator, The second oxide semiconductor layer on the first oxide semiconductor layer, A third oxide semiconductor layer on the second oxide semiconductor layer, The second insulator on the third oxide semiconductor layer, The second conductor on the second insulator, The third insulator on the second conductor, A fourth insulator having a region in contact with the second oxide semiconductor layer, a region in contact with the side surface of the second insulator, a region in contact with the side surface of the second conductor, and a region in contact with the side surface of the third insulator, A third conductor and a fourth conductor having a region in contact with the first insulator, a region in contact with the second oxide semiconductor layer, and a region in contact with the side surface of the fourth insulator, A fifth insulator having a region in contact with the third conductor and the fourth conductor, A sixth insulator having a region in contact with the upper surface of the third insulator, a region in contact with the upper surfaces of the third conductor and the fourth conductor, and a region in contact with the upper surface of the fifth insulator, It has, A semiconductor device wherein the atomic ratio of nitrogen in the third insulator is higher than that of nitrogen in the fourth insulator.

2. In claim 1, The first to third oxide semiconductor layers are semiconductor devices having indium.

3. In claim 1 or claim 2, A semiconductor device having a seventh insulator having a region located between the sidewall of the second oxide semiconductor layer and the sidewall of the second conductor, and a region located between the sidewall of the second oxide semiconductor layer and the sidewall of the third conductor.

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