Semiconductor equipment

Abstract

We propose a semiconductor device that is less susceptible to a decrease in breakdown voltage when the temperature rises. [Solution] A semiconductor device comprising: an outer peripheral p-type layer in contact with an element p-type layer within an outer peripheral region; an outer peripheral n-type layer spaced apart from the outer peripheral p-type layer and positioned further outward than the outer peripheral p-type layer; a breakdown voltage p-type layer positioned between the outer peripheral p-type layer and the outer peripheral n-type layer and including a portion of the upper surface of the semiconductor substrate; a drift n-type layer extending to the upper surface between the breakdown voltage p-type layer and the outer peripheral n-type layer; a protective electrode positioned above the breakdown voltage p-type layer via an interlayer insulating film and electrically connected to the upper electrode; and a layer covering the upper surface between the protective electrode and the outer peripheral n-type layer, which has a voltage of 1 × 10 at 25°C. 8 Ωcm or greater and 1 × 10⁻⁶ 14 It has a semi-insulating film having a resistivity of Ωcm or less.

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices.

[0002] The semiconductor device disclosed in Patent Document 1 has an element region provided with semiconductor elements and an outer peripheral region provided around the element region. In the outer peripheral region, a breakdown voltage structure such as a RESURF layer and a guard ring is provided. In this semiconductor device, the surface of the semiconductor substrate in the outer peripheral region is covered with a semi-insulating film. Also, in this semiconductor device, an n+-type semiconductor region is provided on the outer peripheral side of the breakdown voltage structure. The semi-insulating film electrically connects the upper electrode in the element region and the n+-type semiconductor layer. Since a minute current flows through the semi-insulating film, a potential difference occurs inside the semi-insulating film. Due to the potential difference generated in the semi-insulating film, the bias of the potential distribution in the semiconductor layer in the outer peripheral region is suppressed. Therefore, this semiconductor device has a high breakdown voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The resistivity of the semi-insulating film decreases as the temperature rises. When the resistivity of the semi-insulating film decreases, the potential difference generated in the semi-insulating film becomes smaller, and electric field concentration occurs at a position close to the element region in the outer peripheral region. Thus, the breakdown voltage structure using the conventional semi-insulating film has a reduced breakdown voltage when the temperature of the semiconductor device rises. In this specification, a semiconductor device that is difficult to have a reduced breakdown voltage when the temperature rises is proposed.

Means for Solving the Problems

[0005] A semiconductor device disclosed herein includes a semiconductor substrate, an upper electrode in contact with the upper surface of the semiconductor substrate, and a lower electrode in contact with the lower surface of the semiconductor substrate. The semiconductor substrate has an element region located below the upper electrode and an outer peripheral region located between the element region and the outer peripheral end face of the semiconductor substrate. The semiconductor substrate has an element p-type layer, an outer peripheral p-type layer, an outer peripheral n-type layer, a breakdown voltage p-type layer, and a drift n-type layer. The element p-type layer is located within the element region and is in contact with the upper electrode. The outer peripheral p-type layer is located within the outer peripheral region, in a range including the upper surface, and is in contact with the element p-type layer. The outer peripheral n-type layer is located within the outer peripheral region, in a range including the upper surface, and is spaced apart from the outer peripheral p-type layer and located further outward than the outer peripheral p-type layer. The breakdown voltage p-type layer is located within the outer peripheral region and is in a range including a part of the upper surface located between the outer peripheral p-type layer and the outer peripheral n-type layer. The drift n-type layer is distributed from the bottom of the element p-type layer to the bottom of the outer n-type layer, has a lower n-type impurity concentration than the outer n-type layer, and extends to the upper surface between the breakdown p-type layer and the outer n-type layer. The semiconductor device has a protective electrode and a semi-insulating film. The protective electrode is located on top of the breakdown p-type layer via an interlayer insulating film and is electrically connected to the upper electrode. The semi-insulating film covers the upper surface between the protective electrode and the outer n-type layer and has a temperature of 1 × 10⁻¹⁶ at 25°C. 8 Ωcm or greater and 1 × 10⁻⁶ 14 It has a resistivity of Ωcm or less and electrically connects the protective electrode and the outer n-type layer.

[0006] In this specification, the outer periphery refers to the side closer to the outer edge of the semiconductor substrate.

[0007] Furthermore, the pressure-resistant p-type layer may be a resurf layer, a guard ring, or may include both.

[0008] Furthermore, the semi-insulating film covering the upper surface of the semiconductor substrate may or may not be in contact with the upper surface of the semiconductor substrate. For example, another layer (e.g., an interlayer insulating film) may exist between the semi-insulating film and the upper surface of the semiconductor substrate.

[0009] In this semiconductor device, a protective electrode is present above the breakdown voltage p-type layer. The protective electrode is electrically connected to the upper electrode and has approximately the same potential as the upper electrode. Therefore, even if the resistivity of the semi-insulating film decreases, electric field concentration in the semiconductor layer on the inner side of the protective electrode is suppressed. Consequently, in this semiconductor device, the breakdown voltage does not easily decrease when the temperature rises. [Brief explanation of the drawing]

[0010] [Figure 1] A top view of the semiconductor device of the embodiment. [Figure 2] Longitudinal section view along line AA in Figure 1. [Figure 3] This figure shows the potential distribution (i.e., the distribution of equipotential lines) when the rated voltage is applied to the semiconductor device of the example at room temperature. [Figure 4] This figure shows the potential distribution when the rated voltage is applied to the semiconductor device of the comparative example at room temperature. [Figure 5] This figure shows the potential distribution when the rated voltage is applied to the semiconductor device of the example at a high temperature. [Figure 6] This figure shows the potential distribution when the rated voltage is applied to the semiconductor device of the comparative example at a high temperature. [Figure 7] A longitudinal cross-sectional view corresponding to Figure 2 of the semiconductor device of the first modified example. [Figure 8] A longitudinal cross-sectional view corresponding to Figure 2 of the semiconductor device of the second modified example. [Figure 9] A longitudinal cross-sectional view corresponding to Figure 2 of the semiconductor device of the third modified example. [Modes for carrying out the invention]

[0011] In one exemplary form disclosed in this specification, the pressure-resistant p-type layer may be in contact with the outer peripheral p-type layer, shallower than the outer peripheral p-type layer, and have a lower p-type impurity concentration than the outer peripheral p-type layer. The outer peripheral end of the protection electrode may be located on the inner peripheral side of the outer peripheral end of the pressure-resistant p-type layer.

[0012] According to this configuration, it is possible to disperse the electric field concentration points within the outer peripheral region, and a high breakdown voltage can be realized.

[0013] In one exemplary form disclosed in this specification, the outer peripheral end of the protection electrode may be located on the inner peripheral side of the inner peripheral end of the depletion layer formed in the RESURF layer when a rated voltage is applied between the upper electrode and the lower electrode at 25°C.

[0014] According to this configuration, since the protection electrode does not affect the potential distribution within the depletion layer at room temperature, a high breakdown voltage can be realized at room temperature.

[0015] In one exemplary form disclosed in this specification, the thickness of the semi-insulating film may be distributed so as to become thinner from the inner peripheral side toward the outer peripheral side.

[0016] According to this configuration, the electric field concentration in the outer peripheral region can be more effectively suppressed.

[0017] In one exemplary form disclosed in this specification, the resistivity of the semi-insulating film may be distributed so as to increase from the inner peripheral side toward the outer peripheral side.

[0018] According to this configuration, the electric field concentration in the outer peripheral region can be more effectively suppressed.

Example

[0019] The semiconductor device 10 in the embodiment shown in Figure 1 has a semiconductor substrate 12. An upper electrode 14 is provided on the upper part of the semiconductor substrate 12. The upper electrode 14 is made of AlSi or the like. The upper electrode 14 is provided in the center of the upper surface of the semiconductor substrate 12. The upper electrode 14 is in contact with the upper surface of the semiconductor substrate 12. Hereinafter, the semiconductor region below the contact portion between the upper electrode 14 and the upper surface of the semiconductor substrate 12 will be referred to as the element region 20. Also below, the semiconductor region of the semiconductor substrate 12 surrounding the element region 20 will be referred to as the outer peripheral region 40. That is, the outer peripheral region 40 is the semiconductor region between the element region 20 and the outer peripheral end face 12c of the semiconductor substrate 12. In the outer peripheral region 40, the upper electrode 14 is not in contact with the upper surface of the semiconductor substrate 12.

[0020] As shown in Figure 2, the upper electrode 14 is in contact with the upper surface 12a of the semiconductor substrate 12 within the element region 20. A lower electrode 16 is provided at the bottom of the semiconductor substrate 12. The lower electrode 16 is in contact with the lower surface 12b of the semiconductor substrate 12 in a range that spans the element region 20 and the outer peripheral region 40.

[0021] Within the element region 20, a lower n-type layer 26, a drift n-type layer 24, and an element p-type layer 22 are provided.

[0022] The lower n-type layer 26 has a high concentration of n-type impurities. The lower n-type layer 26 is distributed across the device region 20 and the outer peripheral region 40. The lower n-type layer 26 is in ohmic contact with the lower electrode 16 in the area spanning the device region 20 and the outer peripheral region 40.

[0023] The drift n-type layer 24 has a lower n-type impurity concentration than the lower n-type layer 26. The drift n-type layer 24 is distributed across the device region 20 and the outer peripheral region 40. The drift n-type layer 24 is in contact with the lower n-type layer 26 from above in the area spanning the device region 20 and the outer peripheral region 40.

[0024] The device p-type layer 22 has a high p-type impurity concentration. The device p-type layer 22 is in contact with the drift n-type layer from above within the device region 20. The device p-type layer 22 is provided in a region including the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 14.

[0025] Within the element region 20, a diode is formed by a lower n-type layer 26, a drift n-type layer 24, and an element p-type layer 22. The element p-type layer 22 functions as the anode layer, and the lower n-type layer 26 functions as the cathode layer. In other embodiments, other semiconductor elements may be formed within the element region 20. For example, a FET (field effect transistor) or an IGBT (insulated gate bipolar transistor) may be provided within the element region 20. If an FET is provided within the element region 20, the element p-type layer 22 may function as the body layer (i.e., the layer where the channel is formed), and the lower n-type layer 26 may function as the drain layer. If an IGBT is provided within the element region 20, the element p-type layer 22 may function as the body layer (i.e., the layer where the channel is formed), and a p-type collector region may be provided instead of the lower n-type layer 26. The semiconductor element provided within the element region 20 can be any semiconductor element that is capable of passing current between the upper electrode 14 and the lower electrode 16.

[0026] Within the outer peripheral region 40, an outer peripheral p-type layer 42, a pressure-resistant p-type layer 44, and an outer peripheral n-type layer 46 are provided.

[0027] The outer p-type layer 42 is located in a region that includes the upper surface 12a of the semiconductor substrate 12. The outer p-type layer 42 is distributed from the upper surface 12a to below the lower edge of the device p-type layer 22. The outer p-type layer 42 has a lower p-type impurity concentration than the device p-type layer 22. The outer p-type layer 42 is in contact with the device p-type layer 22 from the outer periphery side.

[0028] The outer n-type layer 46 is located in a region that includes the upper surface 12a of the semiconductor substrate 12. The outer n-type layer 46 is located at a distance from the outer p-type layer 42 and further outward than the outer p-type layer 42. More specifically, the outer n-type layer 46 is located in a region that includes the outer edge of the upper surface 12a and the upper edge of the outer edge face 12c. The outer n-type layer 46 has a higher n-type impurity concentration than the drift n-type layer 24.

[0029] The pressure-resistant p-type layer 44 is located in a region that includes a portion of the upper surface 12a, situated between the outer peripheral p-type layer 42 and the outer peripheral n-type layer 46. In this embodiment, the pressure-resistant p-type layer 44 is a resurf layer. The pressure-resistant p-type layer 44 is in contact with the outer peripheral p-type layer 42 from the outer peripheral side. A gap is provided between the pressure-resistant p-type layer 44 and the outer peripheral n-type layer 46. The pressure-resistant p-type layer 44 is distributed from the upper surface 12a to above the lower end of the outer peripheral p-type layer 42. That is, the pressure-resistant p-type layer 44 is distributed in a region shallower than the outer peripheral p-type layer 42. The pressure-resistant p-type layer 44 has a lower p-type impurity concentration than the outer peripheral p-type layer 42.

[0030] As described above, the drift n-type layer 24 is distributed across the element region 20 and the outer peripheral region 40. The drift n-type layer 24 is in contact with the outer peripheral p-type layer 42, the breakdown p-type layer 44, and the outer peripheral n-type layer 46 from below. Furthermore, the drift n-type layer 24 extends to the upper surface 12a at a position between the breakdown p-type layer 44 and the outer peripheral n-type layer 46. The breakdown p-type layer 44 is separated from the outer peripheral n-type layer 46 by the drift n-type layer 24.

[0031] An interlayer insulating film 50, a protective electrode 52, an EQR (Equi-potential Ring) electrode 54, a semi-insulating film 56, and an insulating protective film 58 are provided on the upper part of the semiconductor substrate 12 within the outer peripheral region 40.

[0032] The interlayer insulating film 50 covers the upper surface 12a within the range where the outer p-type layer 42, the pressure-resistant p-type layer 44, the drift n-type layer 24, and the outer n-type layer 46 are exposed. The interlayer insulating film 50 is in contact with the upper surface 12a.

[0033] The protective electrode 52 is placed on the interlayer insulating film 50. The protective electrode 52 is made of AlSi or the like. As shown in Figure 1, the protective electrode 52 extends in an annular shape so as to surround the upper electrode 14. As shown in Figure 2, the protective electrode 52 extends from the top of the outer p-type layer 42 to the top of the breakdown p-type layer 44. The outer peripheral end 52a of the protective electrode 52 is placed on the top of the breakdown p-type layer 44. That is, the outer peripheral end 52a of the protective electrode 52 is placed on the inner peripheral side (i.e., closer to the element region 20) than the outer peripheral end 44a of the breakdown p-type layer 44. The protective electrode 52 is connected to the outer p-type layer 42 via a contact hole provided in the interlayer insulating film 50. However, in other embodiments, the protective electrode 52 may be separated from the outer p-type layer 42 by the interlayer insulating film 50.

[0034] A gap is provided between the protective electrode 52 and the upper electrode 14. As shown in Figure 1, a wiring layer 60 is provided on a part of the periphery of the upper electrode 14. The protective electrode 52 and the upper electrode 14 are electrically connected by the wiring layer 60. Therefore, the protective electrode 52 has the same potential as the upper electrode 14. In other embodiments, a wiring layer (e.g., a gate wiring layer) insulated from the protective electrode 52 and the upper electrode 14 may be provided on the interlayer insulating film 50 at a position between the protective electrode 52 and the upper electrode 14. Also, if there is no wiring layer at the position between the protective electrode 52 and the upper electrode 14, the protective electrode 52 may be directly connected to the upper electrode 14.

[0035] As shown in Figure 2, the EQR electrode 54 is placed on the interlayer insulating film 50. The EQR electrode 54 is made of AlSi or the like. The EQR electrode 54 is placed on top of the outer n-type layer 46. As shown in Figure 1, the EQR electrode 54 extends in an annular shape along the outer edge of the semiconductor substrate 12. As shown in Figure 2, the EQR electrode 54 is connected to the outer n-type layer 46 via a contact hole provided in the interlayer insulating film 50.

[0036] The semi-insulating film 56 is composed of SInSiN (Semi-insulating Silicon Nitride). The semi-insulating film 56 has a density of 1 × 10⁻¹⁶ at 25°C. 8 Ωcm or greater and 1 × 10⁻⁶ 14 The semi-insulating film 56 has a resistivity of Ωcm or less. The semi-insulating film 56 has the characteristic that its resistivity decreases with increasing temperature. The semi-insulating film 56 extends from the upper surface of the protective electrode 52 to the upper surface of the EQR electrode 54. The semi-insulating film 56 covers the upper surface 12a between the protective electrode 52 and the EQR electrode 54. In this embodiment, the semi-insulating film 56 is placed on the interlayer insulating film 50 between the protective electrode 52 and the EQR electrode 54. However, in other embodiments, the semi-insulating film 56 may be in contact with the upper surface 12a of the semiconductor substrate 12. The protective electrode 52 is electrically connected to the outer n-type layer 46 via the semi-insulating film 56 and the EQR electrode 54.

[0037] The insulating protective film 58 is positioned at the top of the outer peripheral region 40. The insulating protective film 58 covers the interlayer insulating film 50, the protective electrode 52, the EQR electrode 54, and the semi-insulating film 56.

[0038] When a higher potential is applied to the lower electrode 16 than to the upper electrode 14, a depletion layer extends from the p-type layer, which is composed of the element p-type layer 22, the outer p-type layer 42, and the breakdown p-type layer 44, to the drift n-type layer 24. As a result, almost the entire drift n-type layer 24 is depleted. Also, because the p-type impurity concentration of the breakdown p-type layer 44 is low, a depletion layer extends from the drift n-type layer 24 into the breakdown p-type layer 44. The voltage between the lower electrode 16 and the upper electrode 14 is maintained by the depletion layer that spreads within the breakdown p-type layer 44 and the drift n-type layer 24.

[0039] Figure 3 schematically shows the potential distribution inside the semiconductor device 10 when the rated voltage is applied in a direction in which the lower electrode 16 has a higher potential than the upper electrode 14. Figure 3 shows the potential distribution at room temperature. Since the potential of the lower electrode 16 is higher than the potential of the upper electrode 14, the potential is distributed such that it decreases from the bottom to the top within the device region 20. Also, the potential of the outer peripheral edge 12c of the semiconductor substrate 12 is approximately equal to the potential of the lower electrode 16. That is, the potential of the outer n-type layer 46 and the ECR electrode 54 is approximately equal to the potential of the lower electrode 16. Therefore, the potential is distributed such that it decreases from the outer peripheral side to the inner peripheral side within the outer peripheral region 40.

[0040] When the rated voltage is applied to the lower electrode 16, a depletion layer extends from the outer peripheral edge 44a of the withstand voltage p-type layer 44 toward the inner peripheral side (i.e., the interior of the withstand voltage p-type layer 44). In Figures 3 to 6, position X1 indicates the position of the inner peripheral end of the depletion layer within the withstand voltage p-type layer 44. That is, the withstand voltage p-type layer 44 is depleted beyond position X1. Therefore, a potential difference is generated inside the withstand voltage p-type layer 44 beyond position X1.

[0041] As described above, the outer n-type layer 46 has a potential approximately equal to that of the lower electrode 16. The protective electrode 52 also has a potential approximately equal to that of the upper electrode 14. Since the outer edge 52a of the protective electrode 52 is located on the inner side of position X1, the protective electrode 52 does not disturb the potential distribution on the outer side of position X1 (i.e., the potential distribution in the depletion layer within the breakdown p-type layer 44). In this way, electric field concentration is suppressed in the region on the outer side of position X1. The electric field is concentrated in the range Y1 directly below position X1 (i.e., directly below the edge of the depletion layer). Also, since the outer p-type layer 42 protrudes below the breakdown p-type layer 44, the electric field is concentrated in the range Y2 below the boundary between the outer p-type layer 42 and the breakdown p-type layer 44. In this way, the electric field concentration points are dispersed between range Y1 and range Y2, so the generation of excessively high electric fields is suppressed. Therefore, at room temperature, the semiconductor device 10 of the embodiment has a high breakdown voltage.

[0042] Figure 4 shows the potential distribution when the rated voltage is applied to the comparative semiconductor device at room temperature. Note that the comparative semiconductor device lacks a protective electrode 52 above the breakdown voltage p-type layer 44, and the semi-insulating film 56 connects the EQR electrode 54 and the upper electrode 14. In other respects, the structure of the comparative semiconductor device is the same as that of the example semiconductor device. As shown in Figure 4, in the comparative semiconductor device, similar to the example semiconductor device 10, the electric field concentration points are distributed between ranges Y1 and Y2. Therefore, at room temperature, the comparative semiconductor device has the same breakdown voltage as the example semiconductor device 10.

[0043] Figure 5 shows the potential distribution when the rated voltage is applied to the semiconductor device 10 of the example at a high temperature. Figure 6 shows the potential distribution when the rated voltage is applied to the semiconductor device of the comparative example at a high temperature. As described above, when the temperature of the semi-insulating film 56 rises, the resistivity of the semi-insulating film 56 decreases. When the resistivity of the semi-insulating film 56 decreases, the potential difference generated within the semi-insulating film 56 becomes smaller. Therefore, the spacing between equipotential lines within the semi-insulating film 56 widens.

[0044] As shown in Figure 6, in the comparative semiconductor device, the distribution range of the depletion layer expands due to the widening of the equipotential lines within the semi-insulating film 56. As a result, the position X1 of the edge of the depletion layer moves closer to the vicinity of the outer p-type layer 42. When the edge of the depletion layer is located near the outer p-type layer 42 in this way, the electric field concentration is not dispersed. That is, the electric field is concentrated in one place in the area Y2 below the boundary between the outer p-type layer 42 and the breakdown voltage p-type layer 44, and an excessively high electric field is generated in area Y2. Thus, in the comparative semiconductor device, the breakdown voltage decreases as the temperature rises.

[0045] In contrast, as shown in Figure 5, in the semiconductor device 10 of the embodiment, a protective electrode 52 fixed at the same potential as the upper electrode 14 is present above the breakdown voltage p-type layer 44, so the depletion layer cannot extend inward beyond the protective electrode 52. Therefore, even if the resistivity of the semi-insulating film 56 decreases, the position X1 of the end of the depletion layer is located further outward than the protective electrode 52. This prevents position X1 from getting too close to the outer p-type layer 42. As a result, in Figure 5, the electric field concentration points are dispersed between the range Y2 and the range Y3 below the outer edge 52a of the protective electrode 52. That is, it prevents the electric field from concentrating in one place in the range Y2. This suppresses the generation of excessively high electric fields. As described above, the semiconductor device 10 of the embodiment has high breakdown voltage even when the temperature rises.

[0046] As described above, the structure of the semiconductor device 10 in the embodiment enables high breakdown voltage at both room temperature and high temperature. In experiments, this structure reduced the breakdown voltage drop at high temperatures of 40°C or higher by approximately 100V.

[0047] In the embodiment, the protective electrode 52 spanned from the upper part of the outer p-type layer 42 to the upper part of the pressure-resistant p-type layer 44. However, as shown in Figure 7, the protective electrode 52 may be located above the pressure-resistant p-type layer 44 but not above the outer p-type layer 42. With this configuration, high pressure resistance can be achieved at both room temperature and high temperature, similar to the embodiment. In this case, the protective electrode 52 may be made of a highly processable material such as polysilicon.

[0048] The resistance when a minute current flows through the semi-insulating film 56 (more specifically, the resistance when the minute current flows from the outer circumference to the inner circumference) may increase as you move from the inner circumference to the outer circumference. For example, as shown in Figure 8, the thickness of the semi-insulating film 56 may decrease as you move from the inner circumference to the outer circumference. Alternatively, the resistivity of the semi-insulating film 56 at 25°C may be distributed such that it increases as you move from the inner circumference to the outer circumference. In this configuration, equipotential lines tend to be denser on the outer circumference than on the inner circumference inside the semi-insulating film 56. This can mitigate electric field concentration near the end 52a of the protective electrode 52 at high temperatures.

[0049] Furthermore, in the embodiment described above, the pressure-resistant p-type layer 44 was a resurf layer, but as shown in Figure 9, the pressure-resistant p-type layer 44 may be a guard ring. In this configuration as well, when the resistivity of the semi-insulating film 56 decreases due to a rise in temperature, the protective electrode 52 can prevent the depletion layer from approaching the outer p-type layer 42.

[0050] Although the examples have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0051] 10: Semiconductor device, 12: Semiconductor substrate, 14: Top electrode, 24: Drift n-type layer, 42: Outer p-type layer, 44: Withstand voltage p-type layer, 46: Outer n-type layer, 52: Protective electrode, 56: Semi-insulating film

Claims

1. A semiconductor device, A semiconductor substrate (12) and The upper electrode (14) is in contact with the upper surface (12a) of the semiconductor substrate, The lower electrode (16) in contact with the lower surface (12b) of the semiconductor substrate, It has, The aforementioned semiconductor substrate The element region (20) located below the contact portion between the upper electrode and the upper surface, An outer peripheral region (40) located between the element region and the outer peripheral edge of the semiconductor substrate, It has, The aforementioned semiconductor substrate The element p-type layer (22) is arranged within the element region and is in contact with the upper electrode, An outer peripheral p-type layer (42) is located within the outer peripheral region, including the upper surface, and is in contact with the element p-type layer. An outer n-type layer (46) is arranged within the outer peripheral region, including the upper surface, and is spaced apart from the outer p-type layer and positioned further outward than the outer p-type layer, A pressure-resistant p-type layer (44) is located within the outer peripheral region and is positioned in a range including a part of the upper surface located between the outer peripheral p-type layer and the outer peripheral n-type layer, A drift n-type layer (24) is distributed from the lower part of the element p-type layer to the lower part of the outer peripheral n-type layer, has a lower n-type impurity concentration than the outer peripheral n-type layer, and extends to the upper surface between the breakdown p-type layer and the outer peripheral n-type layer. It has, A protective electrode (52) is positioned on the upper part of the breakdown p-type layer via an interlayer insulating film (50) and is electrically connected to the upper electrode, The protective electrode and the outer n-type layer cover the upper surface, and at 25°C, it is 1 × 10 ８ Ωcm or more and 1 × 10⁻⁶ １４ A semi-insulating film (56) having a resistivity of Ωcm or less, electrically connecting the protective electrode and the outer n-type layer, A semiconductor device having the following features.

2. The pressure-resistant p-type layer is in contact with the outer p-type layer, is shallower than the outer p-type layer, and has a lower p-type impurity concentration than the outer p-type layer. The outer peripheral end (52a) of the protective electrode is located on the inner peripheral side of the outer peripheral end (44a) of the pressure-resistant p-type layer. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 2, wherein when a rated voltage is applied between the upper electrode and the lower electrode at 25°C, the outer edge of the protective electrode is located on the inner side of the inner edge (X1) of the depletion layer formed in the voltage-resistant p-type layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the semi-insulating film is distributed such that it becomes thinner from the inner circumference to the outer circumference.

5. The semiconductor device according to any one of claims 1 to 3, wherein the resistivity of the semi-insulating film is distributed such that it increases from the inner circumference to the outer circumference.

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