Flip-flop circuit and data transfer circuit

Abstract

This invention provides a flip-flop circuit that eliminates metastableness in principle with a simple circuit configuration. [Solution] The pre-stage latch 11 operates synchronously with the control clock signal CLK3P to capture input data DIN having a data change timing according to the clock signal CLK1 and output it to node N2. The post-stage latch 12 operates synchronously with the clock signal CLK2 to capture and output data from node N2. The clock control circuit 15 receives the clock signals CLK1 and CLK2 and generates the control clock signal CLKP3. The control clock signal CLKP3 is generated such that a predetermined period of forced suspension of the capture of input data DIN by the pre-stage latch 11 is provided before and after the data change timing, which is defined by a predetermined delay time from the edge of the clock signal CLK1, for a predetermined duration.

Description

Technical Field

[0001] The present disclosure relates to a flip-flop circuit and a data transfer circuit to which the flip-flop circuit is applied.

Background Art

[0002] In a flip-flop, it is known that a problem called metastable state occurs. As is well known, when the signal value of the input data also changes within a certain period before and after the timing when the input clock changes from "0" to "1", the output data of the flip-flop does not become definite as "0" or "1", and a metastable state occurs. When a metastable state occurs, the output data probabilistically converges to "0" or "1" over time, so there is a risk that the stable operation of the circuit will be impaired.

[0003] Generally, as a countermeasure, a time for the metastable state to converge is ensured by delaying the propagation of the signal at the subsequent stage of the flip-flop where a metastable state may occur. For example, it is possible to provide a delay by connecting flip-flops in multiple stages at the subsequent stage of the flip-flop. However, depending on the number of stages of the flip-flop, there is a trade-off between signal delay, circuit scale, and metastable state convergence.

[0004] Japanese Patent Application Laid-Open No. 6-45880 (Patent Document 1) discloses a technique for avoiding the occurrence of a metastable state by providing a signal control circuit for not changing the signal at the data input terminal of a flip-flop only when the setup or hold time is not satisfied. The signal control circuit is composed of a monostable multivibrator and a logic gate.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] However, the flip-flop shown in Patent Document 1 has several problems. First, because there is a minimum constraint on the input pulse width of a monostable multivibrator, there is a risk that stable operation cannot be ensured if the input pulse width falls below a certain value. Also, in the flip-flop of Patent Document 1 (Figure 1), there are concerns that the circuit size will be large because five pulse generation circuits are arranged.

[0007] This disclosure was made to solve these problems, and the purpose of this disclosure is to provide a flip-flop circuit that eliminates metastableness in principle with a simple circuit configuration. [Means for solving the problem]

[0008] In certain aspects of this disclosure, a flip-flop circuit is provided. The flip-flop circuit comprises a pre-stage latch, a post-stage latch, and a clock control circuit. The pre-stage latch operates synchronously with a control clock signal to capture input data having data change timing according to a first clock signal and output it to an internal node. The post-stage latch operates synchronously with a second clock signal different from the first clock signal to capture the output value of the pre-stage latch from the internal node and output it as output data. The clock control circuit receives the first clock signal and the second clock signal to generate a control clock signal. The clock control circuit generates an internal control clock signal such that a predetermined period of forced suspension of input data capture by the pre-stage latch is provided before and after the data change timing defined by a first delay time from the edge of the first clock signal.

[0009] In another aspect of this disclosure, a data transfer circuit is provided. The data transfer circuit comprises a first flip-flop that operates synchronously with a first clock signal, a second flip-flop configured by the flip-flop circuit described above, and a third flip-flop that operates synchronously with a second clock signal. The second flip-flop is positioned downstream of the first flip-flop to receive the output data of the first flip-flop at an input data terminal. The third flip-flop is positioned downstream of the second flip-flop to receive the output data of the second flip-flop, or a data value obtained by processing said output data, at an input data terminal. [Effects of the Invention]

[0010] According to this disclosure, it is possible to provide a flip-flop circuit that eliminates metastableness in principle with a simple circuit configuration, and a data transfer circuit to which this flip-flop circuit is applied. [Brief explanation of the drawing]

[0011] [Figure 1] This is a diagram showing the configuration of a data transfer circuit related to a comparative example. [Figure 2] This is a diagram showing the configuration of a data transfer circuit to which the flip-flop circuit according to this embodiment is applied. [Figure 3] This is a circuit diagram illustrating an example of the configuration of a flip-flop circuit according to this embodiment. [Figure 4] Figure 3 is a circuit diagram illustrating an example of the configuration of a clock control circuit. [Figure 5] This is a first timing chart illustrating an example of the operation of the flip-flop circuit according to this embodiment. [Figure 6] This is a second timing chart illustrating an example of the operation of the flip-flop circuit according to this embodiment. [Figure 7] This is a third timing chart illustrating an example of the operation of the flip-flop circuit according to this embodiment. [Modes for carrying out the invention]

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

[0013] FIG. 1 is a configuration diagram of a data transfer circuit according to a comparative example using a conventional flip-flop.

[0014] The data transfer circuit 100♯ according to the comparative example includes flip-flops FF1 to FF3 and a processing circuit 20.

[0015] The flip-flop FF1 operates in synchronization with the clock signal CLK1, and the flip-flops FF2 and FF3 operate in synchronization with the clock signal CLK2.

[0016] The flip-flop FF1 captures the input data D0 at the rising edge where the clock signal CLK1 input to the clock terminal changes from "0" to "1", and transmits it to the output data Q0. Until the next rising edge of the clock signal CLK1 arrives, the logical value of the captured input data Q0 is latched internally, and the logical value of the output data Q0 is also maintained.

[0017] The flip-flop FF2 receives the output data Q0 of the flip-flop FF1 at the data input terminal. Therefore, the timing at which the input data value of the flip-flop FF2 changes is defined by the clock signal CLK1.

[0018] The flip-flop FF2 captures the input data (Q0) at the rising edge where the clock signal CLK1 input to the clock terminal changes from "0" to "1", and transmits it to the output data Q1. Until the next rising edge of the clock signal CLK2 arrives, the captured input data value is latched inside the flip-flop FF2, and the output data Q1 is also maintained.

[0019] The output data Q1 of flip-flop FF2 is input to processing circuit 20. Processing circuit 20 outputs data D1, which is the execution result of processing predetermined by the circuit designer, for the output data Q1.

[0020] Flip-flop FF3 receives the data D1 output from processing circuit 20 at its data input terminal. Flip-flop FF3 captures the input data (D1) at the data input terminal at the rising edge when the clock signal CLK1 changes from "0" to "1" and transmits it to the output data value. The captured input data value is latched internally and the output data value is also maintained until the next rising edge of clock signal CLK2 arrives.

[0021] In data transfer circuit 100♯, flip-flop FF2 captures data Q0 whose value changes in synchronization with clock signal CLK1 in synchronization with clock signal CLK2 and transfers it to the subsequent circuit.

[0022] In flip-flop FF2, if the interval between the change timing of the data Q0 at the data input terminal (hereinafter referred to as data change timing) and the change timing of the clock signal CLK2 input to the clock terminal (hereinafter referred to as clock change timing) is too short, a metastable state occurs in the output data Q1. Specifically, it is known that a metastable state occurs when the setup time Ts or hold time Th, which is predetermined as a standard value for ensuring the stable operation of the flip-flop (FF2), cannot be ensured and the above two change timings occur continuously.

[0023] On the other hand, since clock signals CLK1 and CLK2 are generated independently, it is not always possible to ensure the setup time Ts and hold time Th between the above two change timings. Therefore, there is a concern that an incorrect value of data D1 may be captured by flip-flop FF3 due to the occurrence of a metastable state in the output data Q1 of flip-flop FF2, destabilizing the operation of the subsequent circuit.

[0024] Figure 2 shows a diagram of a data transfer circuit to which the flip-flop circuit according to this embodiment is applied. In the data transfer circuit 100 of Figure 2, the flip-flop FF2 is replaced with the flip-flop circuit 10 according to this embodiment, which has a function to prevent the occurrence of metastable events.

[0025] The flip-flop circuit 10 according to this embodiment is configured to control the operating timing of the internal circuit by further using a clock signal CLK1 that defines the timing of the change in input data (Q0), in addition to the clock signal CLK2 similar to that in Figure 1. As a result, in the data transfer circuit 100, the flip-flop FF3, which is downstream of the flip-flop FF2 (flip-flop circuit 10), can correctly capture the non-metastable data D1.

[0026] In the data transfer circuit 100 of Figure 2, the flip-flop FF1, which operates synchronously with the clock signal CLK1, corresponds to one embodiment of the "first flip-flop," and the flip-flop FF2, which is composed of the flip-flop circuit 10, corresponds to one embodiment of the "second flip-flop." Furthermore, the flip-flop FF3, which operates synchronously with the clock signal CLK2, corresponds to one embodiment of the "third flip-flop." In addition, in the data transfer circuit 100, the arrangement of the processing circuit 20 may be omitted, and the output data Q1 of the flip-flop FF2 (flip-flop circuit 10) may be directly input to the data input terminal of the flip-flop FF3.

[0027] Figure 3 is a circuit diagram illustrating an example of the configuration of the flip-flop circuit 10 according to this embodiment.

[0028] As shown in Figure 3, the flip-flop circuit 10 according to this embodiment includes a pre-stage latch 11, a post-stage latch 12, and a clock control circuit 15.

[0029] The clock control circuit 15 receives clock signals CLK1 and CLK2 and outputs control clock signals CLK3P and CLK3N. The clock control circuit 15 also outputs clock signal CLK2P, which is the same signal as clock signal CLK2, and clock signal CLK2N, which is the inverted version of clock signal CLK2. As will be described later, control clock signal CLK3P is a signal obtained by masking (setting to "0") a portion of the "1" interval of clock signal CLK2. Control clock signal CLK3N is the inverted version of control clock signal CLK3P.

[0030] The pre-stage latch 11 includes transfer gates T1 and T2 and NOT gates I1 and I2. Transfer gate T1 is connected between the data input terminal Ni and node N1 and switches on and off in response to the control clock signals CLK3N and CLK3P. NOT gate I1 inverts the signal from node N1 and outputs it to node N2.

[0031] NOT gate I2 inverts the signal from node N2 and outputs it to node N3. Transfer gate T2 is connected between node N3 and node N1. Transfer gate T2 turns on and off in a complementary manner with transfer gate T1 in response to the control clock signals CLK3P and CLK3N.

[0032] Therefore, the operating state of the pre-stage latch 11 changes when the control clock signal CLK3P changes from "0" to "1" or from "1" to "0" by switching the on / off state of the transfer gates T1 and T2. More specifically, the pre-stage latch 11 operates to capture and hold the input data DIN of the data input terminal Ni at the rising edge when the control clock signal CLK3P changes from "0" to "1". In other words, the pre-stage latch 11 operates in synchronization with the control clock signal CLK3P.

[0033] The subsequent latch 12 has transfer gates T3 and T4 and NOT gates I3 and I4. Transfer gate T3 is connected between nodes N2 and N4 and switches on and off in response to clock signals CLK2N and CLK2P. NOT gate I1 inverts the signal from node N4 and outputs it to node N5, which corresponds to data output terminal No.

[0034] NOT gate I4 inverts the signal from node N5 and outputs it to node N6. Transfer gate T4 is connected between node N6 and node N4. Transfer gate T4 turns on and off in a complementary manner with transfer gate T3 in response to clock signals CLK2P and CLK2N.

[0035] Therefore, the operating state of the downstream latch 12 changes when the clock signal CLK2 changes from "0" to "1" or from "1" to "0" by switching the on / off state of the transfer gates T3 and T4. More specifically, the downstream latch 12 operates to capture and hold the data value of node N2 (the output value from the upstream latch 11) at the rising edge when the clock signal CLK2 changes from "0" to "1". In other words, the downstream latch 12 operates in synchronization with the clock signal CLK2.

[0036] First, the operation of the pre-stage latch 11 will be explained in detail. In the pre-stage latch 11, during the period when the control clock signal CLK3P = "1", the transfer gate T2 is turned on while the transfer gate T1 is turned off. Therefore, the logical inversion value of the signal at node N2 by the NOT gate I2 is set at nodes N3 and N1. Also, the inverted logical value of node N1 by the NOT gate I1 is set at node N2. In other words, during the period when the control clock signal CLK3P = "1", even if the value of the input data DIN changes, the value held by the pre-stage latch 11 does not change.

[0037] In contrast, in the preceding latch 11, during the period when the control clock signal CLK3P = "0", the transfer gate T1 is turned on while the transfer gate T2 is turned off. Therefore, the current value of the input data DIN is set to node N1, and further, the inverted logic value of the signal at node N1 by the NOT gate I1 is set to node N2. Furthermore, the logical inverted value of the signal at node N2 by the NOT gate I2 is set to node N3. In other words, when the logic value of the input data DIN of the flip-flop circuit 10 changes during the period when the control clock signal CLK3P = "0", the logic values ​​of nodes N1, N2, and N3 change sequentially. At this time, the time required for the logic value of the input data DIN to propagate to node N3 is defined as the setup time Ts.

[0038] If the control clock signal CLK3P changes from "0" to "1" between the time the logic value of the input data DIN of the flip-flop circuit 10 changes and the setup time Ts has elapsed, there is a risk that a metastable state will occur where the logic values ​​of nodes N1, N2, and N3 inside the preceding latch 11 are not determined to be "0" or "1", even within the period when the control clock signal CLK3P is "1".

[0039] Conversely, it is known that metastable may occur if the logic value of the input data DIN of the flip-flop circuit 10 changes between the time the control clock signal CLK3P changes from "1" to "0" and the hold time Th has elapsed. The setup time Ts and the hold time Th are constant values ​​determined during the design of the flip-flop circuit 10.

[0040] Next, the operation of the downstream latch 12 will be explained. In the downstream latch 12, during the period when the clock signal CLK2P = "0", the transfer gate T3 is turned off while the transfer gate T4 is turned on. Therefore, the logical inversion value of the node N5 (data output terminal No.) signal by the NOT gate I4 is set to nodes N6 and N4. Also, the inverted logical value of node N4 by the NOT gate I3 is set to node N5 (data output terminal No.). In other words, during the period when the clock signal CLK2P = "0", even if the logical value of node N2, which is the output value of the upstream latch 11, changes, the internal state of the downstream latch 12 does not change, and the logical value of the output data DOUT also does not change.

[0041] In contrast, in the downstream latch 12, during the period when the clock signal CLK2P = "1", the transfer gate T3 is turned on while the transfer gate T4 is turned off. Therefore, the logical value of node N2, which is the output value of the upstream latch 11, is set to node N4, and furthermore, the inverted logical value of the signal of node N4 by the NOT gate I3 is set to node N5 (data output terminal No.). Furthermore, the logical inverted value of the signal of node N5 by the NOT gate I4 is set to node N6. In other words, when the logical value of node N2 (the logical value of the output of the upstream latch 11) changes during the period when the clock signal CLK2P = "1", the logical values ​​of nodes N4, N5, and N6 change sequentially.

[0042] Similar to the preceding latch 11, the subsequent latch 12 may also experience metastable if the clock signal CLK2P changes from "1" to "0" between the time the logical value of node N2 (the output of the preceding latch 11) changes and the setup time Ts has elapsed, or if the logical value of node N2 changes between the time the clock signal CLK2P changes from "1" to "0" and the hold time Th has elapsed.

[0043] However, as will be explained later, the control clock signal CLK3P of the preceding latch 11 and the clock signal CLK2P used by the succeeding latch 12 have the same frequency, and the timing of their change from "1" to "0" is the same. For this reason, it is generally easy to design the succeeding latch 12 so that metastable does not occur. Specifically, there is a delay caused by the transfer gate T1 and the NOT gate I1 between the timing when the control clock signal CLK3P changes from "1" to "0" and the timing when the logic value of node N2 changes. Therefore, when the succeeding latch 12 captures the logic value of node N2, the change in the logic value of the input data DIN has not yet reached node N2. Due to the existence of this delay, if the frequencies of the clock signal CLK1 that defines the change period of the input data DIN and the clock signal CLK2P (CLK2) are different, the occurrence of metastable in the succeeding latch 12 can be naturally avoided.

[0044] In the configuration shown in Figure 3, if clock signals CLK2P and CLK2N are input to transfer gates T1 and T2, and transfer gates T1 and T4 are switched on and off at the same time, and transfer gates T2 and T3 are also switched on and off at the same time, the normal operation of the flip-flop FF2 described in Figure 1 is achieved.

[0045] In this embodiment, the clock signal CLK1 corresponds to one embodiment of the "first clock signal," the clock signal CLK2 corresponds to one embodiment of the "second clock signal," and the control clock signal CLK3P corresponds to one embodiment of the "control clock signal." Furthermore, node N2 between the pre-stage latch 11 and the post-stage latch 12 corresponds to one embodiment of the "internal node."

[0046] Figure 4 is a circuit diagram illustrating an example configuration of the clock control circuit 15 shown in Figure 3. As shown in Figure 4, the clock control circuit 15 includes a mask generation circuit 16, a NAND gate NA2, and NOT gates I6 and I7.

[0047] The mask generation circuit 16 includes delay circuits 17 and 18, a NOT gate I5, and a NAND gate NA1. Delay circuit 17 delays the clock signal CLK1 by a delay time DLY1 and outputs it to node N7. Delay circuit 18 delays the clock signal CLK1 by a delay time DLY2 and outputs it to node N8. NOT gate I5 outputs the logic inverted signal of node N8. NAND gate NA1 outputs the result of a NAND operation between the signal of node N7 and the inverted signal of node N8 (the output signal of NOT gate I5) as the mask signal MSK to node N9.

[0048] The NAND gate NA2 outputs the result of a NAND operation between the mask signal MSK of node N9 and the clock signal CLK2 as the control clock signal CLK3N. The NOT gate I6 outputs the logic inverted signal of the output of the NAND gate NA2 as the control clock signal CLK3P.

[0049] Furthermore, the clock signal CLK2P is the same signal as the clock signal CLK2. The NOT gate I7 ​​outputs the logic inverted signal of the clock signal CLK2 as the clock signal CLK2N.

[0050] Figures 5 to 7 are timing charts illustrating an example of the operation of the flip-flop circuit 10 according to this embodiment. Figures 5 to 7 commonly show the waveforms of the clock signals CLK2P and CLK2N and the control clock signals CLK3P and CLK3N generated by the clock control circuit 15.

[0051] Referring to Figure 5, the input data DIN of the flip-flop circuit 10 (flip-flop FF2) corresponds to the output data (Q0: Figure 2) of the preceding flip-flop FF1, which operates synchronously with the clock signal CLK1. Therefore, the input data DIN changes at a timing after the delay time Td has elapsed from the rising edge of the clock signal CLK1.

[0052] In Figure 4, the value of the input data DIN changes from S1 to S2 at time t1, after a delay time Td has elapsed from time t0, which corresponds to the rising edge of the clock signal CLK1. This delay time Td is a constant value predetermined by the characteristics of the flip-flop FF1.

[0053] Node N7 outputs a signal in which the clock signal CLK1 is delayed by a delay time DLY1 via the delay circuit 17. Node N8 also outputs a signal in which the clock signal CLK1 is delayed by a delay time DLY2 via the delay circuit 18.

[0054] As a result, the mask signal MSK output from the NAND gate NA1 is set to "0" during the period from time tx (after delay time DLY1 has elapsed from time t0) to time ty (after delay time DLY2 has elapsed from time t0), and to "1" during the rest of the period.

[0055] Therefore, the control clock signal CLK3P obtained by the NAND operation result of the clock signal CLK2 and the mask signal MSK is a signal in which the interval from the rising edge to time ty is masked and maintained as "0" relative to the clock signal CLK2.

[0056] From the above-described explanation of the operation of the pre-stage latch 11, it can be understood that metastable can be avoided in principle by providing a "forced stop period" for the acquisition of input data DIN by the pre-stage latch 11, so that the hold time Th and setup time Ts are secured based on the timing of the change in input data DIN of the flip-flop circuit 10 (time t1).

[0057] In other words, the above-mentioned forced stop period can be provided by providing a period from a timing that is a hold time Th before time t1 to a timing that is a setup time Ts after time t1 during which the control clock signal CLK3P of the preceding latch 11 does not change from "0" to "1" (is forcibly maintained at "0").

[0058] Specifically, in the clock control circuit 15, by setting the delay time DLY1 of the delay circuit 17 to DLY1 ≤ Td-Th and the delay time DLY2 of the delay circuit 18 to DLY2 ≥ Td+Ts, a period can be provided during which the control clock signal CLK3P is forcibly maintained at "0" as described above. In principle, as shown in Figures 5 to 7, metastable can be avoided by setting DLY1 = Td-Th and DLY2 = Td+Ts, but a margin can be provided in the direction of the inequality.

[0059] In this embodiment, the time t1 at which the value of the input data DIN changes, as defined by the rising edge of the clock signal CLK1 and the delay time Td, corresponds to the "data change timing". Furthermore, the delay time Td corresponds to the "first delay time", the delay time DLY1 to the "second delay time", and the delay time DLY2 to the "third delay time".

[0060] Figure 5 shows an example of the operation of the flip-flop circuit 10 when the clock signal CLK2P changes from "0" to "1" without a setup time Ts being secured.

[0061] Referring to Figure 5, at time t1, which is the timing of the change in input data DIN, the value of input data DIN changes from S1 to S2. At this timing, the control clock signal CLK3P = "0", so the logical values ​​of nodes N1 to N3 of the preceding latch 11 change from S1 or / S1 to S2 or / S2 due to the turning on of transfer gate T1 (T2 is off). On the other hand, since the clock signal CLK2 (CLK2P) is "0", the logical values ​​of nodes N4 to N6 of the subsequent latch 12 remain S1 or / S1, without reflecting the change in input data DIN, due to the turning off of transfer gate T3 (T4 is on).

[0062] In the example shown in Figure 5, the clock signal CLK2 changes from "0" to "1" at a time t1, which is the timing of the change in input data DIN, before the setup time Ts has elapsed. In response to this, the transfer gate T3 is turned on (T4 is turned off), causing the logical values ​​of nodes N4 to N6 of the subsequent latch 12 to change from S1 or / S1 to S2 or / S2.

[0063] In the comparative example shown in Figure 1, when the clock signal CLK2 changes from "0" to "1" at such a timing, the setup time Ts is not secured, and the preceding latch 11 takes in the input data DIN, which may cause metastable events in the flip-flop FF2.

[0064] However, in the flip-flop circuit 10 according to this embodiment, the end timing of the period during which the mask signal MSK is "0" is set according to the delay time DLY2 set as described above. While the mask signal MSK is "0", even if the clock signal CLK2 changes from "0" to "1", the control clock signal CLK3P is forcibly maintained at "0". Therefore, the control clock signal CLK3N remains at "0" and does not change to "1" until at least the setup time Ts has elapsed from time t1.

[0065] As a result, the preceding latch 11 can avoid capturing the input data DIN before the setup time Ts has elapsed from time t1, which is the timing of the change in input data DIN, thus preventing metastable events.

[0066] As shown in Figure 5, the data retention period for the pre-stage latch 11, during which the logical values ​​of nodes N1 to N3 do not change even when the input data DIN changes, is the period when the control clock signal CLK3P is "1". Similarly, the data retention period for the post-stage latch 12, during which the logical values ​​of nodes N4 to N6 do not change even when the input data DIN changes, is the period when the clock signal CLK2P is "0".

[0067] Next, using Figure 6, an example of the operation of the flip-flop circuit 10 when the value of the input data DIN changes without a hold time Th being secured is shown.

[0068] In Figure 6, as in Figure 5, the value of the input data DIN changes from S1 to S2 at time t1, which is the timing of the change in the input data DIN. Accordingly, the logical values ​​of nodes N1 to N3 of the pre-stage latch 11 and the logical values ​​of nodes N4 to N6 of the post-stage latch 12 also change in the same way as in Figure 5.

[0069] In the example in Figure 6, the timing of the change in input data DIN (time t1) occurs between the time the clock signal CLK2P changes from "0" to "1" and the time the hold period Th has elapsed.

[0070] In the comparative example shown in Figure 1, there is a risk that metastable may occur in the flip-flop FF2 because, in response to the change in input data DIN at such timing (from S1 to S2), the preceding latch 11 takes in the input data DIN without securing a hold time Th.

[0071] However, in the flip-flop circuit 10 according to this embodiment, the start timing of the period during which the mask signal MSK is "0" is set according to the delay time DLY1 set as described above. While the mask signal MSK is "0", even if the clock signal CLK2 changes from "0" to "1", the control clock signal CLK3P is forcibly maintained at "0".

[0072] Therefore, the control clock signal CLK3N remains at "0" for at least the hold time Th before time t1, which corresponds to the data change timing of the input data DIN, and does not change to "1".

[0073] As a result, the control clock signal CLK3N changes from "0" to "1", preventing the input data DIN from changing before the hold time Th has elapsed after the preceding latch 11 starts the operation to acquire the input data DIN, thus preventing metastable events.

[0074] Furthermore, in Figure 6, the data retention period for the pre-stage latch 11, during which the logical values ​​of nodes N1 to N3 do not change even when the input data DIN changes, is the period when the control clock signal CLK3P is "1". Similarly, the data retention period for the post-stage latch 12, during which the logical values ​​of nodes N4 to N6 do not change even when the input data DIN changes, is the period when the clock signal CLK2P is "1".

[0075] In this embodiment, the clock control circuit 15 further generates the control clock signal CLK3N (CLK3P). Depending on the timing, there may be cases where a difference in the number of pulses occurs between the clock signal CLK2 used by the downstream latch 12 and the control clock signal CLK3N used by the upstream latch 11. Therefore, Figure 7 illustrates that no problems occur in the operation of the flip-flop circuit 10 even in such cases.

[0076] In the example in Figure 7, unlike in Figures 5 and 6, the clock signal CLK2 (CLK2P) changes from "0" to "1" before time tx, when the mask period (period of "0") of the mask signal MSK begins. Furthermore, the clock signal CLK2 (CLK2P) changes from "1" to "0" after time ty, when the mask period (period of "0") of the mask signal MSK ends.

[0077] In this case, the period during which the mask signal MSK is set to "0" is included in the period during which the clock signal CLK2 (CLK2P) is "1". Therefore, during the period when the clock signal (CLK2P) is "1", the control clock signal CLK3P changes from "1" to "0", and then changes again from "0" to "1". In other words, as a result of one pulse of the clock signal CLK2 (CLK2P) being masked, two pulses are generated in the control clock signal CLK3P.

[0078] In this case, the width of the first pulse of the control clock signal CLK3P is denoted as W1 (hereinafter referred to as pulse width W1), the width of the second pulse as W3 (hereinafter referred to as pulse width W3), and the width between the two pulses (i.e., the pulse width of the control clock signal CLK3N) as W2 (hereinafter referred to as pulse width W2). In a typical flip-flop, minimum values ​​for pulse width and pulse interval are defined, and if these constraints are violated (minimum pulse width violation), the flip-flop may not operate correctly.

[0079] Therefore, we will consider the conditions under which metastable occurs in the preceding latch 11 due to a violation of the minimum pulse width.

[0080] In the preceding latch 11, a stable state is assumed where the control clock signal CLK3P is "1", the logical values ​​of nodes N1 and N3 are "0", and the logical value of node N2 is "1". In this state, if the input data DIN is set to "1", the control clock signal CLK3P is changed to "0" for a very short period of time, and then changed back to "1", metastable occurs.

[0081] This is because, due to the logical value of node N1 being different from the logical value of input data DIN, the logical values ​​of nodes N1 to N3 attempt to be sequentially inverted within a very short period of time during which the control clock signal CLK3P is set to "0". However, in the unstable state before each inversion is complete, the control clock signal CLK3P returns to "1", closing the loop.

[0082] Furthermore, in the example where the logical values ​​of nodes N1~N3 and input data DIN are inverted from the above, if the control clock signal CLK3P changes from "1" to "0" in a short period of time and then returns from "0" to "1", a similar metastable occurs inside the preceding latch 11.

[0083] However, in the flip-flop circuit 10 according to this embodiment, the occurrence of metastable due to the shortening of pulse widths W1 to W3 can be avoided for the reasons described below.

[0084] First, let's consider the relationship between pulse width W2 and the occurrence of metastable. As can be seen from Figure 7, pulse width W2 corresponds to the length of time the mask signal MSK is "0", which is determined by the difference between delay times DLY1 and DLY2 (DLY2-DLY1). Therefore, from the conditions of delay times DLY1 and DLY2 described above, it can be seen that W2≧(Ts+Th) is ensured. Consequently, the pulse width W2 is not set such that the control clock signal CLK3P changes from "1" to "0" and then returns from "0" to "1" in a short time that would cause metastable.

[0085] Furthermore, a time elapsed from the time t1 when the input data DIN changes to the time ty when the control clock signal CLK3P changes from "0" to "1" is ensured to be greater than or equal to the setup time Ts. For these reasons, metastable does not occur due to the pulse width W2 becoming extremely short.

[0086] Next, let's consider the case where the pulse width W1 becomes very short. In this case, there is an elapsed time equivalent to the sum of the pulse width W1 and the hold time Th between the time the control clock signal CLK3P changes from "0" to "1" and the time the input data DIN changes (from S1 to S2).

[0087] Furthermore, since the period of the clock signal CLK1 is generally sufficiently longer than the hold time Th, the value of the input data DIN stabilizes at S1 well before the timing when the control clock signal CLK3P changes from "0" to "1".

[0088] Therefore, at the timing when the control clock signal CLK3P changes from "0" to "1", the logical values ​​of nodes N1 and N3 of the pre-stage latch 11 are stable at S1, and the logical value of node N2 is stable at / S1 (the inverted logical value of S1). Here, it is understood that even if the value of the input data DIN remains S1 and the control clock signal CLK3P becomes "1" for a period of a very short pulse width W1, the logical values ​​of nodes N1 to N3 will not change. Therefore, metastable does not occur in the pre-stage latch 11 even if the pulse width W1 becomes very short.

[0089] In this case, the control clock signal CLK3P is set to "1" with pulse width W1, and then set to "1" again with pulse width W3. However, it is guaranteed that the timing at which the control clock signal CLK3P changes from "0" to "1" at the start of pulse width W3 is after the setup time Ts has elapsed from the timing of the change in input data DIN (time t1). Therefore, metastable does not occur in the preceding latch 11.

[0090] Finally, let's consider the case where the pulse width W3 becomes very short. At the starting point of pulse width W3, starting from time t1 when the value of input data DIN changes from S1 to S2, at time ty, which is longer than or equal to the setup time Ts, the control clock signal CLK3P changes from "0" to "1". At this point, in the preceding latch 11, the values ​​of nodes N1 and N3 are stable at S1, and the value of node N2 is stable at / S2 (the logical inversion of S2).

[0091] From this state, it can be understood that even if the input data DIN remains at S2 and the control clock signal CLK3P becomes "1" for a very short pulse width W3 period, the logical values ​​of nodes N1 to N3 will not change. Therefore, even if the pulse width W3 becomes very short, metastable will not occur in the preceding latch 11.

[0092] As explained above in Figure 7, in the flip-flop circuit 10 according to this embodiment, even if there is a difference in the number of pulses between the control clock signal CLK3P and the original clock signal CLK2, and as a result the control clock signal CLK3P becomes "1" with a very short pulse width, metastable does not occur.

[0093] As described above, in the flip-flop circuit according to this embodiment, a period can be provided in which the control clock signal CLK3P, which prevents the operation state of the pre-stage latch 11 from changing, is forcibly maintained at "0" before and after the timing of the change in input data DIN (time t1: Figures 5 to 7), regardless of the value of the clock signal CLK2 (a forced stop period for input data acquisition by the pre-stage latch 11). Furthermore, since this forced stop period starts at least the hold time Th before the timing of the change in input data DIN and ends at least the setup time Ts, the occurrence of metastable in the flip-flop circuit 10 can be eliminated in principle. Depending on the characteristics of the pre- or post-stage circuits of the flip-flop circuit 10, the delay times DLY1 and DLY2 may be set so that only one of the above-mentioned inequalities "DLY1≦Td-Th" and "DLY2≧Td+Ts" holds true, thereby providing a "forced stop period (time tx~ty)" for input data acquisition by the pre-stage latch 11.

[0094] Furthermore, as shown in Figure 4, metastable can be avoided with a simple circuit configuration that only requires adding a clock control circuit 15, which includes one pulse generation circuit for generating the control clock signal CLK3P (CLK3N), to the pre-stage latch 11 and post-stage latch 12 that constitute a normal flip-flop circuit.

[0095] In particular, while the flip-flop in Patent Document 1 (Figure 1) is a concern because it has to be large in scale due to the arrangement of five pulse generation circuits, the flip-flop circuit according to this embodiment can be realized with a simple configuration.

[0096] Furthermore, in the flip-flop described in Patent Document 1, the analog circuit (monostable multivibrator) that generates pulses is arranged in series, raising concerns about an increase in the defect rate and a decrease in yield due to the accumulation of manufacturing variations. In contrast, the flip-flop circuit according to this embodiment does not have a configuration in which the pulse generation circuits are connected in series, making it less likely for a decrease in yield due to the accumulation of manufacturing variations to occur.

[0097] <Note> The embodiments and variations described above include the following technical concepts.

[0098] [Example 1] A pre-stage latch (11) that takes in input data (DIN) having data change timing according to the first clock signal (CLK1) and outputs it to an internal node (N2), A subsequent latch (12) operates in synchronization with a second clock signal (CLK2) that is different from the first clock signal, and takes the output value of the preceding latch from the internal node and outputs it as output data, The system includes a clock control circuit (15) that receives the first clock signal and the second clock signal and generates a control clock signal (CLK3P), The preceding latch operates in synchronization with the control clock signal of the clock control circuit. The clock control circuit is a flip-flop circuit (10) that generates the control clock signal such that a predetermined period of time (tx~ty) is provided before and after the data change timing (t1), which is defined by a first delay time (Td) from the edge of the first clock signal, during which the acquisition of the input data by the preceding latch is forcibly stopped.

[0099] [Example 2] The flip-flop circuit (10) according to Example 1, wherein the start timing (tx) of the forced stop period is set at least a predetermined hold time (Th) of the flip-flop circuit before the data change timing (t1).

[0100] [Example 3] The clock control circuit (15) generates the control clock signal (CLK3P) such that the forced stop period (tx~ty) begins at a timing (tx) after a predetermined second delay time (DLY1) has elapsed from the edge of the first clock signal (CLK1), The flip-flop circuit (10) according to Example 2, wherein the second delay time is set to be less than or equal to the value obtained by subtracting the hold time from the first delay time (Td-Th).

[0101] [Example 4] The flip-flop circuit (10) according to Example 1 or Example 2, wherein the end timing (ty) of the forced stop period is set to be at least the predetermined setup time (Ts) of the flip-flop circuit, which is later than the data change timing (t1).

[0102] [Example 5] The clock control circuit (15) generates the control clock signal (CLK3P) such that the forced stop period (tx~ty) ends at a timing (ty) after a predetermined third delay time (DLY2) has elapsed from the edge of the first clock signal (CLK1). The flip-flop circuit (10) described in Example 4 is configured such that the third delay time is set to be greater than or equal to the sum of the first delay time and the setup time (Td + Ts).

[0103] [Example 6] A first flip-flop (FF1) that operates synchronously with the first clock signal (CLK1), A second flip-flop (FF2) is constructed using the flip-flop circuit (10) described in any one of Examples 1 to 5, It comprises a third flip-flop (FF3) that operates synchronously with the second clock signal (CLK2), The second flip-flop is positioned after the first flip-flop so as to receive the output data (Q0) of the first flip-flop at its input data terminal. The third flip-flop is a data transfer circuit (100) positioned downstream of the second flip-flop to receive the output data (Q1) of the second flip-flop, or the data value (D1) obtained by processing the output data, at its input data terminal.

[0104] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended. [Explanation of symbols]

[0105] 10 Flip-flop circuit, 11 Pre-stage latch, 12 Post-stage latch, 15 Clock control circuit, 16 Mask generation circuit, 17,18 Delay circuit, 20 Processing circuit, 100,100# Data transfer circuit, CLK1,CLK2,CLK2P,CLK2N Clock signal, CLK3P,CLK3N Control clock signal, DIN Input data, DLY1,DLY2,Td Delay time, DOUT Output data, FF1,FF2,FF3 Flip-flop, MSK Mask signal, N1~N9 Node, Ni Data input terminal, No Data output terminal, T1~T4 Transfer gate, Th Hold time, Ts Setup time.

Claims

1. A pre-stage latch that captures input data having data change timing according to the first clock signal and outputs it to an internal node, A subsequent latch operates in synchronization with a second clock signal different from the first clock signal, and takes the output value of the preceding latch from the internal node and outputs it as output data. The system includes a clock control circuit that receives the first clock signal and the second clock signal and generates a control clock signal, The preceding latch operates in synchronization with the control clock signal of the clock control circuit. The clock control circuit generates the control clock signal such that a predetermined period of time is provided before and after the data change timing, which is defined by a first delay time from the edge of the first clock signal, during which the acquisition of the input data by the preceding latch is forcibly stopped. (Flip-flop circuit)

2. The flip-flop circuit according to claim 1, wherein the start timing of the forced stop period is set to be at least a predetermined hold time of the flip-flop circuit before the data change timing.

3. The clock control circuit generates the control clock signal such that the forced stop period begins when a predetermined second delay time has elapsed from the edge of the first clock signal. The flip-flop circuit according to claim 2, wherein the second delay time is set to be less than or equal to the value obtained by subtracting the hold time from the first delay time.

4. The flip-flop circuit according to claim 1, wherein the timing of the end of the forced stop period is set to be at least a predetermined setup time for the flip-flop circuit that is later than the timing of the data change.

5. The clock control circuit generates the control clock signal such that the forced stop period ends when a predetermined third delay time has elapsed from the edge of the first clock signal. The flip-flop circuit according to claim 4, wherein the third delay time is set to be greater than or equal to the sum of the first delay time and the setup time.

6. A first flip-flop that operates in synchronization with the first clock signal, A second flip-flop configured by a flip-flop circuit according to any one of claims 1 to 5, It comprises a third flip-flop that operates synchronously with the second clock signal, The second flip-flop is positioned after the first flip-flop so as to receive the output data of the first flip-flop at its input data terminal. The third flip-flop is a data transfer circuit positioned downstream of the second flip-flop to receive the output data of the second flip-flop, or the data value obtained by processing the output data, at its input data terminal.

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