Method for manufacturing structures and semiconductor devices

Abstract

The present invention provides a structure with improved crack resistance and a method for manufacturing a semiconductor device. [Solution] A method for manufacturing a semiconductor device according to one embodiment includes forming a structure with a recess on a substrate on a first surface, providing a plurality of insulating particles inside the recess up to the upper end of the recess or below the upper end, annealing the plurality of insulating particles inside the recess, and filling the gaps between the annealed plurality of insulating particles inside the recess with a liquid insulator.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for manufacturing a structure and a semiconductor device.

Background Art

[0002] A NAND-type flash memory is known as a semiconductor memory device. This NAND-type flash memory includes a memory cell array and its control circuit. As a method for manufacturing a semiconductor memory device, a method is known in which a memory cell array chip and a control circuit chip are formed on separate substrates and then bonded together later. In a method for manufacturing a semiconductor device in which a memory cell array chip is bonded to a substrate on which a control circuit chip is formed, a large gap exists between adjacent memory cell array chips, and it is necessary to fill this gap.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] [[ID=5九]]To provide a structure with improved crack resistance and a method for manufacturing a semiconductor device. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to one embodiment includes forming a structure with a recess on a substrate on a first surface, providing a plurality of insulating particles inside the recess up to the upper end of the recess or below the upper end, annealing the plurality of insulating particles inside the recess, and filling the gaps between the annealed plurality of insulating particles inside the recess with a liquid insulator. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view illustrating a structure according to one embodiment of the present disclosure. [Figure 2] This is a cross-sectional view illustrating a method for manufacturing a structure according to one embodiment of the present disclosure. [Figure 3] This is a cross-sectional view illustrating a method for manufacturing a structure according to one embodiment of the present disclosure. [Figure 4] This is a cross-sectional view illustrating a method for manufacturing a structure according to one embodiment of the present disclosure. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a structure according to one embodiment of the present disclosure. [Figure 6] This is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present disclosure. [Figure 7] This is an enlarged cross-sectional view illustrating a semiconductor device according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0007] The structure and semiconductor device manufacturing method according to this embodiment will be described in detail below with reference to the drawings. In the following description, elements having substantially the same function and configuration are denoted by the same reference numeral or by an alphabet letter added to the same reference numeral, and will be described redundantly only when necessary. The embodiments shown below illustrate devices and methods for realizing the technical idea of ​​this embodiment. Various modifications can be made to the embodiments without departing from the spirit of the invention. These embodiments and their variations are included in the scope of the invention and its equivalents as described in the claims.

[0008] While drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation, these are merely examples and do not limit the interpretation of the present invention. In this specification and in each drawing, elements having the same function as those described in previously shown drawings are denoted by the same reference numerals, and redundant explanations may be omitted.

[0009] In this specification, expressions such as "α includes A, B, or C" do not exclude cases where α includes multiple combinations of A, B, and C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0010] The following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0011] <First Embodiment> [Structure structure] The structure of the semiconductor device according to this embodiment will be explained with reference to Figure 1. Figure 1 is a cross-sectional view illustrating the semiconductor device structure 1 according to this embodiment.

[0012] As shown in Fig. 1, the structure 1 includes a layer 2, insulating particles 3, and an insulator 4. The layer 2 includes a recess 2b having an opening on the first surface 2a. A plurality of insulating particles 3 are provided in the recess 2b of the layer 2. The insulator 4 is provided in a region other than the plurality of insulating particles 3 in the recess 2b of the layer 2. The insulator 4 is filled in the gaps between the plurality of insulating particles 3 in the recess 2b of the layer 2.

[0013] The insulating particles 3 are spherical, and preferably have an average particle size in the range of 100 nm or more and 1000 nm or less. Also, the particle sizes of the insulating particles 3 may be single or plural. The total volume of the insulating particles 3 is preferably in the range of 40% by volume or more and 80% by volume or less with respect to the volume of the recess 2b of the layer 2. When the average particle size of the insulating particles 3 increases, the number of contact points between adjacent insulating particles 3 decreases, the gaps between adjacent insulating particles 3 become larger, and the binding force as an aggregate of the insulating particles 3 may become poor. When the average particle size of the insulating particles 3 decreases, the number of contact points between the insulating particles 3 increases, and it may not be able to accept deformation due to stress, and the mechanical strength may be impaired.

[0014] Preferably, the insulating particles 3 do not protrude from the first surface 2a of the layer 2. The insulating particles 3 are preferably embedded up to the upper end (first surface 2a) of the recess 2b or below the upper end. In Fig. 1, a configuration is shown in which the tangent planes of the plurality of insulating particles 3 are flush with the first surface 2a of the layer 2. However, it is not limited to this, and the number of the plurality of insulating particles 3 may be less than this. In this case, the plurality of insulating particles 3 are stacked from the bottom surface of the recess 2b and may not reach the first surface 2a of the layer 2. The insulating particles 3 may not be provided in the upper part of the recess 2b. The region where the insulating particles 3 are not provided in the upper part of the recess 2b is preferably in the range within the average particle size of the insulating particles 3 from the upper end (first surface 2a) of the recess 2b.

[0015] The insulating particles 3 may contain silicon and oxygen, and may contain silicon dioxide (SiO2). However, it is not limited to this, and the insulating particles 3 may contain alumina (Al2O3), zirconia (ZrO2), silicon nitride (SiN), or aluminum nitride (AlN). The surface of the insulating particles 3 is preferably lyophilic.

[0016] The insulator 4 preferably does not protrude from the first surface 2a of the layer 2. The insulator 4 is preferably a material whose polymerization is completed by low-temperature firing. For example, when there is copper wiring in the layer 2, or due to the crack resistance of the insulator 4, it is preferably a material whose polymerization is completed at 400 °C or lower. If the content rate of the insulator 4 is large, the crack resistance of the insulator 4 may become weak. If the content rate of the insulator 4 is small, the mechanical strength may be impaired.

[0017] The insulator 4 may be a SOD (Spin-on-Dielectric) material. The insulator 4 may contain silicon, oxygen and hydrogen, and may contain hydrogen silsesquioxane. However, it is not limited thereto, and the insulator 4 may contain methyl silsesquioxane, organosiloxane, or polysilazane.

[0018] The size of the recess 2b is, for example, such that the width or depth is 10 μm or more. In FIG. 1, the recess 2b is a bottomed hole having an opening in the first surface 2a of the layer 2. However, it is not limited thereto, and the recess 2b may be between convex portions protruding from the bottom surface of the recess 2b and may not be surrounded by the convex portions. The insulating particles 3 and the insulator 4 are filled in such a recess 2b. The first surface 2a of the layer 2 is preferably lyophobic. The inner surface and the bottom surface of the recess 2b are preferably lyophilic.

[0019] The inner surface and the bottom surface of the recess 2b may have minute slits or gaps. The size of the minute slits or gaps is, for example, such that the width or depth is less than the average particle diameter of the insulating particles 3. Therefore, only the insulator 4 is filled in such minute slits or gaps.

[0020] The structure 1 according to this embodiment can improve crack resistance by filling a large volume recess 2b with a plurality of insulating particles 3 and an insulator 4. This can improve the manufacturing efficiency of the semiconductor device according to this embodiment.

[0021] [Method for manufacturing the structure] Figures 2 to 5 are cross-sectional views illustrating a method for manufacturing a semiconductor device structure according to this embodiment.

[0022] As shown in Figure 2, a recess 2b is formed on the first surface 2a of layer 2. The recess 2b may be formed by arranging a plurality of protrusions on the bottom surface of the recess 2b. For example, the recess 2b may be formed by arranging a memory cell array chip on a control circuit substrate, which will be described later. The first surface 2a of layer 2 is preferably hydrophobic. The first surface 2a may be treated to be hydrophobic by silylation treatment in a WET apparatus. The inner surface and bottom surface of the recess 2b of layer 2 are preferably hydrophilic. The inner surface and bottom surface of the recess 2b may be treated to be hydrophilic by removing the silylation by plasma treatment.

[0023] Next, insulating particles 3 are applied to the recess 2b as shown in Figure 3. After applying multiple insulating particles 3 to the first surface 2a of layer 2 and the interior of the recess 2b using a coating device, some of the insulating particles 3 provided on the first surface 2a may be removed as shown in Figure 4. Some of the insulating particles 3 may be removed, for example, by low-load brush cleaning or low-load chemical mechanical polishing (CMP) equipment.

[0024] In the manufacturing method of the semiconductor device structure according to this embodiment, a plurality of insulating particles 3 provided on the first surface 2a are removed before the annealing process described later. If the plurality of insulating particles 3 provided on the first surface 2a are removed after the annealing process, the film thickness of the insulating particles 3 on the first surface 2a will be the same as, for example, the depth of the recess 2b. The amount of insulating particles 3 corresponding to the plurality of insulating particles 3 applied inside a recess 2b with a width or depth of, for example, 10 μm or more will be a thick film, requiring a long polishing or etching time, making manufacturing difficult. Furthermore, if the plurality of insulating particles 3 are removed after annealing, for example with a chemical mechanical polishing device, polishing particles may clog the gaps between the insulating particles 3. Alternatively, if the plurality of insulating particles 3 are removed after annealing, for example with RIE (Reactive Ion Etching), the etching rate may differ depending on the presence or absence of the insulating particles 3, and flattening to remove only the particle layer on the first surface 2a may become very difficult. Since there are no bonds between the multiple insulating particles 3 before the annealing process, the multiple insulating particles 3 on the first surface 2a can be easily removed even if the film thickness of the insulating particles 3 on the first surface 2a is thick.

[0025] As shown in Figures 3 and 4, the process is not limited to coating the recess 2b with insulating particles 3 and removing the multiple insulating particles 3 provided on the first surface 2a. The insulating particles 3 may also be embedded only inside the recess 2b of layer 2, as shown in Figure 4. The multiple insulating particles 3 may be embedded only inside the recess 2b of layer 2 by a CMP apparatus that supplies the multiple insulating particles 3 instead of slurry. In this case, the multiple insulating particles 3 will not be deposited on the first surface 2a of layer 2, as shown in Figure 3. The fact that the first surface 2a of layer 2 is hydrophobic and the inner and bottom surfaces of the recess 2b are hydrophilic makes it easier to embed the multiple insulating particles 3, whose surfaces are hydrophilic, inside the recess 2b of layer 2.

[0026] Next, the insulating particles 3 provided in the recess 2b are annealed. The annealing conditions may be appropriately set depending on the configuration of the insulating particles 3, the insulator 4, and layer 2. For example, if copper wiring is present in layer 2, or depending on the crack resistance of the insulator 4, annealing may be performed at 400°C or below.

[0027] Next, as shown in Figure 5, an insulator 4 is applied to the first surface 2a and the interior of the recess 2b of layer 2. The insulator 4 is applied by a spin coating apparatus, with the liquid insulator material being applied to the first surface 2a and the interior of the recess 2b of layer 2. The liquid insulator material flows into the gaps between the multiple insulating particles 3 inside the recess 2b, filling the interior of the recess 2b. The hydrophilicity of the surfaces of the multiple insulating particles 3 and the inner and bottom surfaces of the recess 2b of layer 2 facilitates the filling of the liquid insulator material into the recess 2b of layer 2. Before applying the insulator 4, for example, surface control using a surfactant may be performed on the surfaces of the multiple insulating particles 3 and the inner and bottom surfaces of the recess 2b of layer 2 to increase hydrophilicity and suppress void formation. Alternatively, after applying the liquid insulator material 4, the insulator 4 may be reflowed by low-temperature heating. Furthermore, by adjusting the molecular weight of the liquid insulator 4 material, it becomes easier to fill the recess 2b of layer 2 with the liquid insulator 4 material, thereby suppressing the formation of voids inside the recess 2b.

[0028] The material of the insulator 4 applied to the first surface 2a and the interior of the recess 2b of layer 2 may be polymerized by low-temperature firing to form the insulator 4. The low-temperature firing conditions may be appropriately set depending on the material of the insulator 4. For example, if copper wiring is present in layer 2, or depending on the crack resistance of the insulator 4, low-temperature firing may be performed at 400°C or below.

[0029] The insulator 4 formed on the first surface 2a of layer 2 may be removed. The insulator 4 formed on the first surface 2a of layer 2 can be removed by CMP equipment or dry etching until the first surface 2a of layer 2 is exposed, thereby forming the structure 1 shown in Figure 1. The manufacturing method of the semiconductor device structure according to this embodiment allows for easy filling of large-volume recesses 2b and facilitates flattening of the first surface 2a of layer 2.

[0030] <Second Embodiment> [Configuration of semiconductor device] The configuration of the semiconductor device 1a according to this embodiment will be described with reference to Figures 6 and 7. Figure 6 is a cross-sectional view showing the overall configuration of the semiconductor device 1a. Figure 7 is an enlarged cross-sectional view showing the basic configuration of the semiconductor device 1a.

[0031] As shown in Figure 6, the semiconductor device 1a is a bonded substrate and comprises a memory cell array chip 100 and a control circuit (CMOS circuit) chip 200. The memory cell array chip 100 and the control circuit chip 200 are connected at a connection surface C1. A second region R2 on the upper surface of the control circuit chip 200, which is different from the first region R1 on which the memory cell array chip 100 is provided, is embedded with a plurality of insulating particles 3 and an insulator 4. In Figure 6, the memory cell array chip 100 of the second embodiment bonded to the substrate on which the control circuit chip 200 is formed (thick line) corresponds to layer 2 including the recess 2b of the first embodiment. The first surface 2a of the memory cell array chip 100 on the substrate 10 side is preferably hydrophobic. The side surface of the memory cell array chip 100 and the second region R2 of the control circuit chip 200 are preferably hydrophilic.

[0032] The semiconductor device 1a is fixed to the wiring board 30 via an adhesive layer 40 on the side with the control circuit chip 200. The wiring board 30 may be a printed circuit board or an interposer including a wiring layer and an insulating layer. Multiple insulating particles 3 and an insulator 4 of the semiconductor device 1a have through holes 5 that expose the second region R2 of the control circuit chip 200. Bonding wires 50 are placed in the through holes 5. The bonding wires 50 electrically connect the metal pads WP of the control circuit chip 200 and the wiring board 30 via the through holes 5.

[0033] In this embodiment, an example is shown in which one semiconductor device 1a is arranged on the wiring board 30. However, the embodiment is not limited to this, and multiple semiconductor devices 1a may be arranged on the wiring board 30. The multiple semiconductor devices 1a may be arranged side by side, for example, or they may be stacked in a stepped manner so as to expose the connection portions of the bonding wires 50.

[0034] [Structure of a memory cell array chip] As shown in Figure 7, the memory cell array chip 100 has a plurality of electrode layers 16 and a memory-side wiring layer 17. The plurality of electrode layers 16 are stacked alternately one layer at a time with a plurality of insulating layers on the substrate 10. Semiconductor pillars 15 are arranged perpendicular to the substrate 10, penetrating the stacked plurality of electrode layers 16. Each semiconductor pillar 15 functions as a plurality of transistors, including memory cells, by being combined with the plurality of electrode layers 16 via an insulating layer. That is, in the memory cell array region 11 (upper right portion of Figure 7), a plurality of transistors, including memory cells, are arranged in three dimensions. The semiconductor pillar 15 is electrically connected to a source line at one end (on the substrate 10 side) and electrically connected to a memory-side wiring layer 17, including a bit line BL, at the other end (opposite side from the substrate 10). Connection terminals for connecting to a control circuit chip 200 are arranged on the connection surface C1 of the memory-side wiring layer 17.

[0035] On the substrate, a contact area 12 (upper left portion in Figure 7) is arranged alongside the memory cell array area 11. In the contact area 12, multiple electrode layers 16 each have terminal portions extended in a stepped manner. Each terminal portion is connected to vertical wiring through contact holes opened in the insulating film. These vertical wirings are electrically connected to the memory-side wiring layer 17 and connected to the control circuit chip 200 via connection terminals.

[0036] [Structure of the control circuit chip] As shown in Figure 7, the control circuit chip 200 includes a substrate 20, a plurality of transistors 26 constituting the control circuit, and a circuit-side wiring layer 27. The plurality of transistors 26 are formed on the substrate 20 and are electrically connected to the circuit-side wiring layer 27 on the side opposite to the substrate 20. Connection terminals for connecting to the memory cell array chip 100 are arranged on the connection surface C1 of the circuit-side wiring layer 27. The substrate 20 may be a semiconductor wafer such as a silicon substrate. [Explanation of symbols]

[0037] 1 Structure, 2 Layers, 2a First surface, 2b Recess, 3 Insulating particles, 4 Insulator, 5 Through-hole, 30 Wiring board, 40 Adhesive layer, 50 Bonding wire, 100 Memory cell array chip, 200 Control circuit chip

Claims

1. A structure including a recess is formed on the substrate on the first surface. A plurality of insulating particles are provided inside the recess, extending to the upper end of the recess or below the upper end. The plurality of insulating particles inside the recess are annealed. A method for manufacturing a semiconductor device, comprising filling the gaps between the annealed plurality of insulating particles inside the recess with a liquid insulator.

2. A method for manufacturing a semiconductor device according to claim 1, wherein a plurality of insulating particles are provided inside the recess using a chemical mechanical polishing apparatus.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of insulating particles are provided inside the first surface and the recess using a coating apparatus.

4. The method for manufacturing a semiconductor device according to claim 3, further comprising removing the plurality of insulating particles provided on the first surface from the plurality of insulating particles using a low-load brush cleaning or low-load chemical mechanical polishing apparatus before annealing.

5. A structure including a recess is formed on the substrate on the first surface. Using a coating device, a plurality of insulating particles are provided on the first surface and inside the recess. Using a low-load brush cleaning or low-load chemical mechanical polishing apparatus, remove a portion of the plurality of insulating particles that are provided on the first surface. A method for manufacturing a semiconductor device, comprising filling the gaps between the plurality of insulating particles inside the recess with a liquid insulator.

6. The method for manufacturing a semiconductor device according to claim 5, further comprising removing the plurality of insulating particles provided on the first surface from the plurality of insulating particles, and then annealing the plurality of insulating particles inside the recess.

7. A structure including a recess is formed on the substrate on the first surface. Using a chemical mechanical polishing device, multiple insulating particles are placed inside the recess. A method for manufacturing a semiconductor device, comprising filling the gaps between the plurality of insulating particles inside the recess with a liquid insulator.

8. The method for manufacturing a semiconductor device according to any one of claims 1 to 7, wherein the structure includes a memory cell array chip and a control circuit chip.

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