electronic machines

Abstract

The aim is to reduce the number of CPU pins used in the key matrix. [Solution] The electronic device includes a plurality of scan signal lines 31, a plurality of key signal lines 32, a plurality of switches provided at the intersections of the plurality of scan signal lines 31 and the plurality of key signal lines 32, a CPU 33 that has a plurality of pins connected to the plurality of scan signal lines 31 and the plurality of key signal lines 32 and detects operations on the plurality of switches, and a generation means that generates an inverted signal of the scan signal output from each of the scan signal lines 31, and the CPU 33 detects operations on the plurality of switches using a combination of logical values ​​of the plurality of scan signals.

Description

Technical Field

[0001] The present invention relates to an electronic device.

Background Art

[0002] An image forming apparatus includes a display panel and a touch panel provided so as to overlap the display surface of the display panel. The display panel displays, for example, an operation menu of the image forming apparatus and information indicating the status of the image forming apparatus by a liquid crystal method or an organic EL (Electro-Luminescence) method. The touch panel detects an operation by a user's fingertip by, for example, a capacitance method or a surface acoustic wave method. The image forming apparatus controls each part according to the operation detected by the touch panel. The touch panel includes a key matrix. In the key matrix, scan signals become HIGH at different timings for a plurality of rows, and the switch that has been pressed is determined based on the level of the key signal of a plurality of switches provided in the row where the scan signal has become HIGH. Therefore, the number of pins of the CPU (Central Processing Unit) used in the conventional key matrix is the sum of the number of rows and the number of switches in each row. Since the CPU is more expensive as the number of pins increases, if the number of pins can be reduced, the cost can be reduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Conventionally, techniques have been considered to reduce the number of terminals and signal lines in circuits equipped with a key matrix. For example, Patent Document 1 proposes transmitting the output control signal from the key scan control unit to the key matrix and the output control signal from the LCD unit control unit to the LCD unit via a common signal line using time-division control by the selector unit. Patent Document 2 proposes sharing the signal lines used for the key matrix and the signal lines used for the display unit, and performing time-division control of the timing of key input and the timing of display signal output. However, the configurations proposed in Patent Documents 1 and 2 cannot reduce the number of pins of the CPU used in the key matrix.

[0005] In consideration of the above circumstances, the present invention aims to reduce the number of CPU pins used in the key matrix. [Means for solving the problem]

[0006] To solve the above problems, the electronic device according to the present invention comprises a plurality of scan signal lines, a plurality of key signal lines, a plurality of switches provided at the intersections of the plurality of scan signal lines and the plurality of key signal lines, a CPU having a plurality of pins connected to the plurality of scan signal lines and the plurality of key signal lines and detecting operations on the plurality of switches, and generation means for generating inverted signals of scan signals output from each of the scan signal lines, wherein the CPU detects operations on the plurality of switches using a combination of logical values ​​of the plurality of scan signals.

[0007] If CMX is the number of combinations when X scan signals are selected from the M scan signals, then the maximum number of switches that the CPU can detect, MAX, is expressed as MAX = CMX × 2X × N.

[0008] The generation means may be transistors provided on each of the plurality of scan signal lines. [Effects of the Invention]

[0009] According to the present invention, the number of CPU pins used in the key matrix can be reduced. [Brief explanation of the drawing]

[0010] [Figure 1] This is a perspective view showing the external appearance of a printing apparatus according to one embodiment of the present invention. [Figure 2] This is a schematic right-side view showing the internal configuration of a printing apparatus according to one embodiment of the present invention. [Figure 3] This is a circuit diagram of a key matrix provided on a touch panel according to one embodiment of the present invention. [Figure 4] This figure shows a combination of a scan signal and a key signal according to one embodiment of the present invention. [Figure 5] This is a timing diagram of a scan signal according to one embodiment of the present invention. [Figure 6] This is a circuit diagram of the key matrix found in conventional touch panels. [Figure 7] This is a timing diagram of a conventional scan signal. [Modes for carrying out the invention]

[0011] The following describes a printing apparatus 1 according to one embodiment of the present invention, with reference to the drawings.

[0012] Figure 1 is a perspective view showing the external appearance of the printing device 1. Figure 2 is a schematic right side view showing the internal configuration of the printing device 1. In each figure, U, Lo, L, R, Fr, and Rr indicate top, bottom, left, right, front, and back, respectively. Note that these directions are defined only for the sake of explanation.

[0013] The printing device 1 (see Figures 1 and 2) comprises a rectangular parallelepiped main body housing 3. Inside the lower part of the main body housing 3, there is a paper feed cassette 4 in which sheets S are stored, and a paper feed roller 5 that feeds the sheets S backward from the paper feed cassette 4. Above the paper feed cassette 4, there is an imaging device 6 that forms a toner image using an electrophotographic method, and above and behind the imaging device 6, there is a fixing device 7 that fixes the toner image onto the sheet S. Above the fixing device 7, there is an discharge roller 8 that discharges the sheet S with the toner image fixed on it, and an discharge tray 9 on which the discharged sheets S are stacked.

[0014] Inside the main housing 3, a transport path 10 is provided, which runs from the paper feed roller 5 through the image creation device 6 and the fixing device 7 to the discharge roller 8. The transport path 10 is mainly formed of plate-shaped members that face each other with gaps between them to allow the sheet S to pass through, and transport rollers 17 that grip and transport the sheet S are provided at multiple locations in the transport direction Y. A registration roller 18 is provided upstream of the image creation device 6 in the transport direction Y. Behind the fixing device 7, a reversal transport path 10R is provided. The reversal transport path 10R branches off from the transport path 10 at a branching point located downstream of the fixing device 7 in the transport direction Y, and rejoins the transport path 10 at a confluence point located upstream of the registration roller 18 in the transport direction Y.

[0015] The image forming device 6 includes four sets of image forming units 6U and an intermediate transfer unit 15. The image forming unit 6U includes a photosensitive drum 11 whose potential changes upon irradiation with light, a charging device 12 for charging the photosensitive drum 11, an exposure device 13 that emits laser light according to image data, a developing device 14 that supplies toner to the photosensitive drum 11, and a cleaning device 16 that removes the toner remaining on the photosensitive drum 11. The intermediate transfer unit 15 includes an endless intermediate transfer belt 15B wound around a driving roller 15D and a driven roller 15N, a primary transfer roller 151 that faces the inner peripheral surface of the intermediate transfer belt 15B at a position corresponding to the photosensitive drum 11 and generates a primary transfer bias, and a secondary transfer roller 152 that faces the outer peripheral surface of the intermediate transfer belt 15B at a position corresponding to the driving roller 15D and generates a secondary transfer bias. A toner container 20 that supplies toner to the developing device 14 is connected to the developing device 14. The image forming device 6 forms a color image by overlapping four-color toner images on the intermediate transfer belt 15B. Note that the printing device 1 may include two sets, three sets, or five or more sets of image forming units 6U.

[0016] The control unit 2 includes an arithmetic unit and a storage unit (not shown). The arithmetic unit is, for example, a CPU (Central Processing Unit). The storage unit includes storage media such as a ROM (Read Only Memory), a RAM (Random Access Memory), and an EEPROM (Electrically Erasable Programmable Read Only Memory). The arithmetic unit performs various processes by reading and executing the control programs stored in the storage unit. Note that the control unit 2 may be realized only by an integrated circuit without using software.

[0017] The display operation unit 19 includes a display panel 19A and a touch panel 19B provided so as to overlap the display surface of the display panel 19A. The control unit 2 causes the display panel 19A to display a screen representing the operation menu, status, etc. of the printing device 1, and controls each part of the printing device 1 according to the operation detected by the touch panel 19B.

[0018] When a print job is input to the printing apparatus 1, the paper feed roller 5 feeds the sheet S from the paper feed cassette 4 into the conveyance path 10, the registration roller 18 whose rotation has been stopped corrects the posture of the sheet S, and the registration roller 18 feeds the sheet S to the image forming apparatus 6 at a predetermined timing. In the image forming apparatus 6, the charging device 12 charges the photosensitive drum 11 to a predetermined potential, the exposure device 13 writes a latent image on the photosensitive drum 11, and the developing device 14 develops the latent image using the toner supplied from the toner container 20 to form a toner image. The primary transfer roller 151 transfers the toner image to the intermediate transfer belt 15B, and the secondary transfer roller 152 transfers the toner image to the sheet S.

[0019] Subsequently, the fixing device 7 sandwiches and conveys the sheet S while melting the toner image to fix the toner image on the sheet S, and the discharge roller 8 discharges the sheet S to the discharge tray 9. In the case of double-sided printing, the sheet S with the toner image fixed on the first side is fed into the conveyance path 10 via the reverse conveyance path 10R, so that the toner image is transferred to the second side.

[0020] FIG. 6 is a circuit diagram of a key matrix provided in the conventional touch panel 19B. FIG. 7 is a timing diagram of the conventional scan signal. The display operation unit 19 causes a software keyboard (not shown) to be displayed on the display panel 19A, detects the key operated by the user on the software keyboard by the touch panel 19B, and transmits a signal indicating the detected key to the control unit 2. The touch panel 19B specifies the coordinates of the location where the user's fingertip has touched by a method such as a capacitance method or a surface acoustic wave method, and outputs a signal indicating the key corresponding to the specified coordinates.

[0021] The key matrix has multiple scan signal lines 31 and multiple key signal lines 32 that intersect with the scan signal lines 31. In the display panel 19A, the keys of the software keyboard are arranged at the intersections of the scan signal lines 31 and the key signal lines 32. In the touch panel 19B, a switch SW1 or the like is provided at the intersection of the scan signal lines 31 and the key signal lines 32, which detects user presses using methods such as capacitive or surface acoustic wave.

[0022] In the examples shown in Figures 6 and 7, switches SW1 to SW4 are provided at the four intersections of the two scan signal lines 31 and the two key signal lines 32. Transistors QF1 and QF2 are provided on the two scan signal lines 31, respectively. For example, when the scan signal SCAN1 is at a high level, transistor QF1 turns ON. In this case, switches SW1 and SW2 connected to transistor QF1 are checked by the CPU 33. If switch SW1 is pressed while the scan signal SCAN1 is at a high level, the key signal KEY1 becomes low, and the press of switch SW1 is detected.

[0023] In this example, one key signal can be connected to multiple scan signals, and one scan signal can be connected to multiple key signals. When one key signal can be connected to multiple scan signals, the timing at which the scan signals reach a high level differs, as shown in Figure 7. For example, in the example in Figure 6, different scan signals are connected to switches SW1 and SW3, but the key signals connected to switches SW1 and SW3 are the same. With this configuration, the CPU 33 recognizes that switch SW1 is pressed when key signal KEY1 is at a low level during the period when scan signal SCAN1 is at a high level. On the other hand, the CPU 33 recognizes that switch SW3 is pressed when key signal KEY1 is at a low level during the period when scan signal SCAN2 is at a high level.

[0024] In the same circuit configuration as in Figure 6, the maximum number of switches that the CPU 33 can recognize is the product of the number of scan signals and the number of key signals. Key signals and scan signals are input and output by connecting the key signal line 32 and the scan signal line 31 to the pins of the CPU 33. Key signals are input to the CPU 33 using GPIO (General Purpose Input / Output) input mode, and scan signals are output from the CPU 33 using GPIO output mode. The total number of pins required is the sum of the number of scan signals and the number of key signals. Since the CPU 33 becomes more expensive as the number of pins increases, it is desirable to reduce the number of pins in order to control costs. Therefore, in this embodiment, the number of pins of the CPU 33 is reduced by the following configuration.

[0025] The arithmetic mean and geometric mean of the number of scan signals and the number of key signals are equal when the number of scan signals and the number of key signals are equal. For example, when using a circuit configuration similar to that in Figure 6 to control 64 switches, the minimum number of pins is 16, with 8 scan signals and 8 key signals.

[0026] In the circuit configuration shown in Figure 6, the switch is checked using only one state (H level) of a single scan signal. In contrast, in the embodiment shown below, the switch is checked using a combination of multiple scan signals. For example, consider a configuration having two scan signals, SCAN1 and SCAN2, and two key signals, KEY1 and KEY2.

[0027] Figure 3 is a circuit diagram of the key matrix provided on the touch panel 19B. Figure 4 is a diagram showing the combinations of scan signals SCAN1 and SCAN2 and key signals KEY1 and KEY2. Figure 5 is a timing diagram of the scan signals. In the circuit configuration of Figure 3, transistors QD1 and QD2 are provided to generate inverted signals of scan signals SCAN1 and SCAN2. Two transistors (for example, QD3 and QD4 for SW1 and SW2) are provided for each row of switches (for example, SW1 and SW2 are in one row), and each row of switches is checked only by a specific combination of the two scan signals SCAN1 and SCAN2. For example, switches SW3 and SW4 are checked when transistors QD5 and QD6 are ON. Transistors QD5 and QD6 are ON when scan signal SCAN1 is at a high level and scan signal SCAN2 is at a low level.

[0028] Figures 4 and 5 show that in the circuit configuration shown in Figure 3, each switch is checked when the logical values ​​of the two scan signals SCAN1 and SCAN2 are in a specific combination. Therefore, eight switches SW1 to SW8 can be checked using the two scan signals SCAN1 and SCAN2 and the two key signals KEY1 and KEY2. In contrast, in the conventional circuit configuration (see Figure 6), only a maximum of four switches can be checked.

[0029] In this embodiment, the general formula for the maximum number of switches that can be checked with M scan signals and N key signals, MAX, is given by equation (1). Here, a row of switches is checked using a combination of X logical values ​​of the scan signals out of the M. MAX=CMX×2X×N...Formula (1) However, CMX is the number of combinations when X scan signals are selected from M scan signals. 2X is the number of all possible logical value combinations for X scan signals.

[0030] In the example shown in Figure 3, with a configuration of two key signals KEY1 and KEY2 and two scan signals SCAN1 and SCAN2, both scan signals SCAN1 and SCAN2 are used. Therefore, in equation (1), M=2, N=2, and X=2, indicating that a maximum of eight switches can be checked.

[0031] For example, if we consider controlling 64 switches, a conventional circuit configuration (see Figure 6) would require a total of 16 pins corresponding to 8 key signals and 8 scan signals.

[0032] On the other hand, in this embodiment (see Figure 3), M=5, X=2 gives CMX=10, 2X=4, N=2, so MAX=80. In other words, the required number of pins is M+X=7. That is, by using a total of 7 pins corresponding to 5 scan signals and 2 key signals, and by combining 2 of the 5 scan signals to check one row of switches, it is possible to check up to 80 switches.

[0033] There is no limit to the number of scan signals that can be combined to check a single row of switches. For example, a configuration that can check more switches by combining three scan signals is possible.

[0034] The electronic device according to the embodiment described above includes a plurality of scan signal lines 31, a plurality of key signal lines 32, a plurality of switches provided at the intersections of the plurality of scan signal lines 31 and the plurality of key signal lines 32, a CPU 33 having a plurality of pins connected to the plurality of scan signal lines 31 and the plurality of key signal lines 32 and detecting operations on the plurality of switches, and a generation means for generating inverted signals of scan signals output from each of the scan signal lines 31, wherein the CPU 33 detects operations on the plurality of switches using a combination of logical values ​​of the plurality of scan signals. With this configuration, the number of pins of the CPU 33 used in the key matrix can be reduced.

[0035] Furthermore, according to the electronic device of this embodiment, if CMX is the number of combinations when X scan signals are extracted from M scan signals, then the maximum number of switches that the CPU 33 can detect, MAX, is expressed as MAX = CMX × 2X × N. With this configuration, the number of pins of the CPU 33 used in the key matrix can be reduced.

[0036] Furthermore, according to the electronic device of this embodiment, the generation means is a transistor provided on each of the multiple scan signal lines 31. With this configuration, the generation means can be realized in a low-cost configuration. [Explanation of Symbols]

[0037] 31 scan signal line 32 Key signal lines 33 CPU QD1, QD2 transistors

Claims

1. Multiple scan signal lines, Multiple key signal lines, Multiple switches provided at the intersections of multiple scan signal lines and multiple key signal lines, A CPU having multiple pins connected to multiple scan signal lines and multiple key signal lines, which detects operations on multiple switches, The system includes a generation means for generating an inverted signal of the scan signal output from each of the scan signal lines, The CPU is characterized by detecting operations on multiple switches using a combination of logical values ​​of multiple scan signals.

2. If CMX is the number of combinations when X scan signals are extracted from the M scan signals, then the maximum number of switches that the CPU can detect, MAX, is: The electronic device according to claim 1, characterized in that MAX = CMX × 2X × N.

3. The electronic device according to claim 1 or 2, characterized in that the generating means is a transistor provided on each of the plurality of scan signal lines.

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