memory circuit

Abstract

Reduces dynamic power consumption during memory access operations. [Solution] The memory circuit includes multiple memory groups, each containing multiple memories containing multiple memory cells, multiple memory group control units, a first memory control unit that outputs a request signal received from the outside to an adjacent memory group control unit, and a first data conversion unit that divides a first write data signal received from the first memory control unit into n second write data signals and outputs them sequentially to adjacent memory group control units. If the write address signal included in the request signal indicates a corresponding memory group, the multiple memory group control units sequentially write n second write data signals to one of the memories in the corresponding memory group, and if the write address signal does not indicate a corresponding memory group, they transfer the request signal and the n second write data signals to a subsequent memory group control unit.

Description

Technical Field

[0001] The present invention relates to a memory circuit.

Background Art

[0002] There is known a memory circuit in which memories and memory control units for controlling the memories are repeatedly arranged, and the memory control unit sequentially transfers a control signal to a subsequent memory control unit. Each memory control unit outputs a memory access request to the corresponding memory when the address included in the memory access request indicates the corresponding memory, and outputs the memory access request to the subsequent memory control unit when the address included in the memory access request indicates other than the corresponding memory (see, for example, Patent Documents 1 and 2).

[0003] There is known an SRAM (Static Random Access Memory) having a plurality of memory cells connected to one word line, a sense amplifier shared by the plurality of memory cells, and a selection switch disposed between the plurality of memory cells and the sense amplifier, and capable of burst read operation and burst write operation. In this type of SRAM, in a burst read operation, data signals read out in parallel from a plurality of memory cells by activation of a word line are sequentially amplified by a sense amplifier and output as a serial data signal. Further, in a burst write operation, the memory cell array writes a serial data signal as a parallel data signal to the memory cells by selection switches sequentially turned on. The word line is activated only at the beginning of a burst access operation or during a burst access operation (see, for example, Patent Documents 3 and 4).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

[0005] For example, during a read operation, if only a portion of the data read from multiple memory cells connected to the word line and amplified by the sense amplifier is output to the external terminal, the amplification of data not output from the external data terminal becomes wasted, resulting in unnecessary power consumption. Furthermore, the larger the bit width of the data signals input and output to a memory block containing memory cells, the larger the charging and discharging current of the data lines transmitting data signals within the memory block, and the greater the dynamic power. In particular, in memory circuits where memory and memory control units are repeatedly arranged, data lines tend to be long, and the impact of the charging and discharging current of the data lines on the dynamic power of the memory circuit becomes significant.

[0006] The present invention has been made in view of the above points, and aims to reduce dynamic power consumption during memory access operations. [Means for solving the problem]

[0007] In one aspect of the present invention, the memory circuit includes a plurality of memory groups, each including a plurality of memories containing a plurality of memory cells, which perform write or read operations in response to a request signal; a plurality of memory group control units provided corresponding to each of the plurality of memory groups; a first memory control unit that outputs a request signal received from the outside to an adjacent memory group control unit; and a first data conversion unit that divides a first write data signal received from the first memory control unit into n (where n is an integer of 2 or more) second write data signals and sequentially outputs the second write data signals to the adjacent memory group control units. The plurality of memory group control units sequentially write the n second write data signals to one of the memories in the corresponding memory group if the write address signal included in the request signal received from the first memory control unit or the preceding memory group control unit indicates a corresponding memory group, and if the write address signal does not indicate a corresponding memory group, they transfer the request signal and the n second write data signals to the subsequent memory group control unit. [Effects of the Invention]

[0008] According to the disclosed technology, dynamic power consumption during memory access operations can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing an example of the configuration of a memory circuit according to the first embodiment. [Figure 2] Figure 1 is a block diagram showing an example of a memory control unit. [Figure 3] Figure 1 is a block diagram showing an example of the memory block configuration. [Figure 4] This block diagram shows an example of the configuration of a memory group in Figure 3. [Figure 5] Figure 4 is a block diagram showing an example of the configuration of a memory unit. [Figure 6]It is a block diagram showing an example of the internal configuration of the memory MEM included in the memory unit of FIG. 5. [Figure 7] It is a block diagram showing the read operation by the column circuit shown in FIG. 6 from the viewpoint of individual read data signals. [Figure 8] It is a block diagram showing the write operation by the column circuit shown in FIG. 6 from the viewpoint of individual write data signals. [Figure 9] An example of a memory circuit including a memory block that receives a 512-bit write data signal from a memory control unit and outputs a 512-bit read data signal to the memory control unit is shown. [Figure 10] It is a block diagram showing an example of the internal configuration of the sub-memory shown in FIG. 9. [Figure 11] It is a timing diagram showing an overview of the read operations of the memory MEM included in the memory unit of the memory circuit of FIG. 6 and the sub-memory included in the memory block of the memory circuit of FIG. 10. [Figure 12] It is a timing diagram showing an example of the read and write operations of the memories of FIGS. 6, 7, and 8. [Figure 13] It is a timing diagram showing an example of the read and write operations of the sub-memory of FIG. 10. [Figure 14] It is a block diagram showing an example of the configuration of the memory group control unit of FIG. 1. [Figure 15] It is a timing diagram showing an example of generating a memory clock signal MCLK from a memory clock signal MCLKxN. [Figure 16] It is a state transition diagram showing an example of the transition of the operation states of the memory unit of FIG. 4. [Figure 17] It is a flowchart showing an example of the operation of the memory group control unit of FIG. 14. [Figure 18] It is a flowchart showing an example of step S100 of FIG. 17. [Figure 19] It is a flowchart showing an example of step S200 of FIG. 17. [Figure 20] It is a flowchart showing an example of step S220 of FIG. 19. [Figure 21] It is a flowchart showing an example of step S300 in FIG. 17. [Figure 22] It is an explanatory diagram showing an example of an operation for transitioning a memory unit to an active mode in the memory circuit of FIG. 1. [Figure 23] It is a timing diagram showing an example of the timing of signals when transitioning to the active mode in FIG. 22. [Figure 24] It is a timing diagram showing the continuation of FIG. 23. [Figure 25] It is an explanatory diagram showing an example of a writing operation of the memory circuit of FIG. 1. [Figure 26] It is a timing diagram showing an example of the timing of signals during the writing operation in FIG. 18. [Figure 27] It is a timing diagram showing the continuation of FIG. 26. [Figure 28] It is an explanatory diagram showing an example of a reading operation of the memory circuit of FIG. 1. [Figure 29] It is a timing diagram showing an example of the timing of signals during the reading operation in FIG. 28. [Figure 30] It is a timing diagram showing the continuation of FIG. 29. [Figure 31] It is a timing diagram showing the continuation of FIG. 30. [Figure 32] It is a timing diagram showing the continuation of FIG. 31. [Figure 33] It is a timing diagram showing another example of the timing of signals during the reading operation of the memory circuit of FIG. 1. [Figure 34] It is a timing diagram showing the continuation of FIG. 33. [Figure 35] It is a timing diagram showing the continuation of FIG. 34. [Figure 36] It is a timing diagram showing the continuation of FIG. 35. [Figure 37] It is a block diagram showing an example of the configuration of the memory circuit of the second embodiment. [Figure 38] It is a block diagram showing an example of the configuration of a system in which the memory circuit of FIG. 1 is mounted. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. In the following, the same symbols as the signal names will be used for signal lines through which information such as signals is transmitted. Also, signal lines shown with thick lines indicate that they consist of multiple bits. Note that signal lines shown with single lines may also consist of multiple bits.

[0011] Figure 1 shows an example of the configuration of a memory circuit in the first embodiment. The memory circuit 100 shown in Figure 1 is mounted on a semiconductor device such as a system LSI that processes image data. For example, a semiconductor device including the memory circuit 100 is mounted on an imaging device such as a surveillance camera, a head-mounted device such as AR / VR (Augmented Reality / Virtual Reality) glasses, or a digital camera, and generates moving image data, etc., to be displayed on a display device.

[0012] The memory circuit 100 includes a memory block MBLK, a memory control unit 200 (input side) and a data conversion unit PSCNV connected in series to the input side of the memory block MBLK, and a data conversion unit SPCNV and a memory control unit 200 (output side) connected in series to the output side of the memory block MBLK. The memory control unit 200 (input side) is an example of a first memory control unit, and the memory control unit 200 (output side) is an example of a second memory control unit. Hereafter, when describing the memory control unit 200 (input side) and 200 (output side) without distinction, they will be referred to as the memory control unit 200.

[0013] The memory block MBLK comprises multiple memory groups MG arranged in one direction and containing multiple memory cells, and multiple memory group control units MCNTs positioned on the signal input side of each of the memory groups MG. The memory block MBLK also has a memory group control unit MCNT positioned on the signal output side of the final stage memory group MG. For example, each memory group MG is positioned between a pair of memory group control units MCNT. In other words, the memory group control units MCNT and memory groups MG are arranged alternately. The memory group control units MCNT function as interface circuits for signals input and output between the memory control unit 200 and the memory groups MG, or as interface circuits for signals input and output between the memory group control units MCNT.

[0014] Each memory group control unit (MCNT) has a flip-flop circuit (FF) that receives access request signals (control signal CMD, address signal A, etc.), write data signals D, and read data signals Q, respectively. When each memory group control unit (MCNT) receives an access request signal for an adjacent memory group MG (hereinafter also referred to as its own memory group MG) on its output side, it outputs the access request signal to its own memory group MG.

[0015] In this case, each memory group control unit (MCNT) suppresses the output of access request signals to subsequent memory group control units (MCNTs), except for the signals used by the final-stage memory group control unit (MCNT). The subsequent memory group control unit (MCNT) is the memory group control unit (MCNT) located on the output side of the memory control unit 200, separated from the memory group control unit (MCNT) of interest by one memory group MG.

[0016] Furthermore, when each memory group control unit (MCNT) receives an access request signal for a memory group MG other than its own, it forwards the access request signal to the next memory group control unit (MCNT). In this case, each memory group control unit (MCNT) suppresses the output of the access request signal for its own memory group MG.

[0017] Each memory group control unit (MCNT) transfers the read data signal Q read from its own memory group MG or the read data signal Q transferred from the preceding memory group control unit (MCNT) to the subsequent memory group control unit (MCNT). The preceding memory group control unit (MCNT) is a memory group control unit located on the input side of the memory control unit 200 (with one memory group MG in between) relative to the memory group control unit (MCNT) of interest.

[0018] In this way, the memory block MBLK can control access for each memory group MG by the memory group control unit MCNT. In the memory block MBLK, the control line CMD, address line A, write data line D, and read data line Q are not wired over long distances across multiple memory groups MG, thus suppressing an increase in wiring load. As a result, it is possible to suppress an increase in the access time of the memory circuit 100 while suppressing an increase in dynamic power, which is the power consumed during access operations.

[0019] Furthermore, the clock cycles required for the transfer of the access request signal, write data signal D, and read data signal Q between the pair of memory group control units MCNT located on either side of the memory group MG are set to be the same for both. This makes it easier to design timing even when increasing or decreasing the number of memory groups MG to design other memory circuits with different storage capacities.

[0020] The memory control unit 200 is connected to the system bus SBUS of the semiconductor device and to a peripheral bus that inputs and outputs various control signals CNTL. While not particularly limited, the system bus SBUS may, for example, input and output signals based on ARM's AXI4 (Advanced eXtensible Interface 4). The memory control unit 200 functions as an interface circuit between signals input and output to the system bus SBUS and signals input and output to the memory group control unit MCNT.

[0021] Figure 1 shows an example in which rows of memory group control units MCNT and memory group MG are arranged in series between the memory control unit 200 (input side) and the memory control unit 200 (output side). However, the rows of memory group control units MCNT and memory group MG may also be arranged in a U-shape. In this case, the memory control unit 200 (input side) and the memory control unit 200 (output side) are arranged together at one end of the arrangement area for the memory group control units MCNT and memory group MG.

[0022] The memory control unit 200 (input side) receives request signals REQ, address signals ADR, and write data signals WD from a higher-level controller such as the CPU (Central Processing Unit) via the system bus SBUS, which prompt the memory circuit 100 to perform a memory access operation (read or write operation). The request signal REQ corresponds to an access request signal that prompts the memory group MG to perform a write or read operation. The access request signal indicates a write request or a read request. Note that in Figure 1, only the flow of major information signals is shown for the sake of simplification. Although not shown in the diagram, there are also additional information signals, signals indicating the validity or invalidity of each signal, and control signals indicating output or capture instructions for data signals.

[0023] The memory control unit 200 (input side) generates a control signal CMD containing additional information for accessing the memory within the memory group MG, based on the address signal ADR and the request signal REQ which includes information such as the request ID or access size. The memory control unit 200 (input side) outputs the generated control signal CMD to the first-stage memory group control unit MCNT.

[0024] For example, the memory control unit 200 (input side) outputs a 512-bit write data signal D to the data conversion unit PSCNV every eight times it receives a 64-bit write data signal WD. The write data signal WD is an example of a third write data signal. The data conversion unit PSCNV sequentially converts the 512-bit write data signal D output from the memory control unit 200 (input side) into four 128-bit write data signals D, and sequentially outputs the four converted write data signals D to the first-stage memory group control unit MCNT. The 512-bit write data signal D is an example of a first write data signal, the four 128-bit write data signals D are an example of a second write data signal, and the data conversion unit PSCNV is an example of a first data conversion unit.

[0025] Furthermore, the memory control unit 200 (input side) receives a control signal CNTL via the peripheral bus that sets the operating specifications of at least one of the memory group MG and the memory group control unit MCNT. In addition, the memory control unit 200 (input side) outputs the operating specifications of at least one of the memory group MG and the memory group control unit MCNT as a control signal CNTL to the peripheral bus. For example, the peripheral bus is a slower interface than the system bus SBUS.

[0026] The memory control unit 200 (output side) receives access control signals such as the control signal CMD and address signal A from the final stage memory group control unit MCNT. The memory control unit 200 (output side) also receives the read data signal Q from the final stage memory group control unit MCNT via the data conversion unit SPCNV and outputs it to the system bus SBUS as a read data signal RD. The read data signal RD is an example of a third read data signal. For example, each time the memory control unit 200 (output side) receives the 512-bit read data signal Q from the data conversion unit SPCNV, it outputs the 64-bit read data signal RD eight times. In other words, the memory control unit 200 converts the parallel read data signal Q read from the memory group MG and output from the data conversion unit SPCNV into a serial read data signal RD and outputs it to the system bus SBUS.

[0027] The data conversion unit SPCNV converts the four 128-bit read data signals Q sequentially output from the final stage memory group control unit MCNT into a 512-bit read data signal Q, and outputs the converted read data signal Q to the memory control unit 200 (output side). The four 128-bit read data signals Q are an example of the first read data signals, and the 512-bit read data signal Q is an example of the second read data signals.

[0028] The data conversion unit SPCNV has four flip-flop circuits (FF) connected in series. Each flip-flop circuit (FF) holds a 128-bit read data signal Q and outputs it to the memory control unit 200 (output side). All flip-flop circuits (FF), except for the final stage, output the held 128-bit read data signal Q to the next stage flip-flop circuit (FF). The data conversion unit SPCNV is an example of a second data conversion unit.

[0029] In this embodiment, the 512-bit write data signal D output from the memory control unit 200 (input side) is converted by the data conversion unit PSCNV into four 128-bit write data signals D and supplied to the memory block MBLK. Therefore, the number of write data lines D wired within the memory block MBLK can be reduced to one-quarter compared to the case where the data conversion unit PSCNV is not used.

[0030] Similarly, the four 128-bit read data signals Q output from the memory block MBLK are converted into 512-bit read data signals Q by the data conversion unit SPCNV and output to the memory control unit 200 (output side). Therefore, the number of read data lines Q wired within the memory block MBLK can be reduced to one-quarter compared to the case where the data conversion unit SPCNV is not used.

[0031] The 128-bit data signals input to and output to the memory block MBLK are twice the number of 64-bit data signals input to and output to the system bus SBUS. Therefore, ideally, the operating frequency of the memory block MBLK can be set to half the operating frequency of the system bus SBUS. Consequently, power consumption during access operations of the memory block MBLK can be reduced compared to when 64-bit data signals are input and output to the memory block MBLK. Because the operating frequency of the memory block MBLK can be lowered, there can be more operating margin for the memory group control unit MCNT and the memory group MG, making it easier to implement circuit timing design and other related processes.

[0032] The number of bits in the data signals input to and output to the memory block MBLK should be 2 to the power of k times the number of bits in the data signals input to and output to the system bus SBUS (where k is an integer greater than or equal to 1; in this example, k=1).

[0033] Figure 2 shows an example of the circuit block of the memory control unit 200 in Figure 1. The memory control unit 200 (input side) includes a system bus input control unit 202, buffers 204 and 206, peripheral bus control unit 208, overall management unit 210, memory state management unit 212, and input interface control unit 214. The memory control unit 200 (output side) includes an output interface control unit 220, buffers 222 and 224, and system bus output control unit 226.

[0034] The system bus input control unit 202 generates an address signal A and a control signal CMD containing additional information for memory control from the address signal ADR and the request signal REQ which contains information such as the request ID or access size, and stores them in the buffer 204. The system bus input control unit 202 stores a total of 513 bits (hereinafter, unless otherwise specified, the explanation of the Last signal will be omitted and the total will be 512 bits) of the 512-bit data signal, which is received up to 8 times from the system bus SBUS, and 1 bit of additional information (Last information) in the buffer 206.

[0035] Buffers 204 and 206 are, for example, FIFO (First-In First-Out) buffers. Buffer 204 outputs the control signal CMD and address signal A to the input interface control unit 214 in the order in which they are held. Buffer 206 outputs the write data signal WD to the input interface control unit 214 in the order in which it is held.

[0036] The input interface control unit 214 outputs the control signal CMD and address signal A, etc., to the memory block MBLK if the control signal CMD received from the buffer 204 is valid, causing the memory block MBLK to perform a write or read operation. The input interface control unit 214 also outputs a 512-bit write data signal D corresponding to the write request signal indicating a write request from the buffer 204 to the data conversion unit PSCNV.

[0037] The peripheral bus control unit 208 outputs various control signals CNTL received from the peripheral bus to the overall management unit 210. The peripheral bus control unit 208 also outputs various control signals CNTL received from the overall management unit 210 to the peripheral bus.

[0038] The overall management unit 210 has several registers (not shown) for setting the operating specifications, such as the operating mode, of the memory group MG (Figure 1). The overall management unit 210 sets the registers according to various control signals CNTL from the peripheral bus. For example, the operating modes include shutdown mode, sleep mode, and active mode. For example, the shutdown mode, sleep mode, and active mode can be switched on a unit basis of the memory unit MU, which will be described later. Note that the unit for switching between the shutdown mode, sleep mode, and active mode is not limited to the memory unit MU.

[0039] For example, in shutdown mode, the power to the memory cell area of ​​the memory unit MU to be shut down is cut off, and the power to peripheral circuits other than the memory cell area that are not related to shutdown and sleep control is cut off. In sleep mode, the power to the memory cell area of ​​the memory unit MU to be put into sleep is reduced to a low voltage that can maintain the data held in the memory cells, and the power to peripheral circuits other than the memory cell area that are not related to shutdown and sleep control is cut off.

[0040] In this embodiment, an example is described in which the memory block MBLK itself incorporates a power supply circuit for shutdown and sleep functions. However, even if the memory block MBLK itself does not have a power supply circuit, if a power supply circuit provided outside the memory block MBLK can adjust the power supply voltage of the memory cell area and adjust or cut off the power supply of peripheral circuits other than the memory cell area on a per-memory unit MU or per-memory group MG basis, then switching between shutdown mode, sleep mode, and active mode is possible.

[0041] In active mode, write or read operations can be performed. Additionally, the registers of the memory state management unit 212 may contain a time limit for transitioning to sleep mode if there is no access during active mode.

[0042] The memory state management unit 212 manages the operating mode of the memory unit MU based on the settings of several built-in registers. The memory state management unit 212 may also maintain fault information indicating the location of a faulty memory cell within the memory group MG, and may perform fault recovery management by accessing a normal memory cell instead of the faulty memory cell.

[0043] The output interface control unit 220 stores the control signal CMD and address signal A received from the memory block MBLK in the buffer 222 during the read operation of the memory block MBLK. The output interface control unit 220 also stores the 512-bit read data signal Q received from the data conversion unit SPCNV in the buffer 224.

[0044] Buffers 222 and 224 are, for example, FIFO buffers. Buffer 222 outputs the control signal CMD and address signal A, which contain additional information for memory control, to the system bus output control unit 226 in the order in which they were held. Buffer 224 outputs the 512-bit read data signal Q received from the output interface control unit 220 to the system bus output control unit 226.

[0045] The memory control unit 200 has a function to convert between the frequencies of data signals input and output to the system bus SBUS and the frequencies of data signals input and output to the memory block MBLK. For example, in the memory control unit 200, the input side of buffers 204 and 206 operates with the system clock signal SCLK used by the system bus SBUS. In the memory control unit 200, the output side of buffers 204 and 206 operates with the memory clock signal MCLK used by the memory block MBLK.

[0046] Similarly, in the memory control unit 200, the input side of buffers 222 and 224 operates with the memory clock signal MCLK used in the memory block MBLK. In the memory control unit 200, the output side of buffers 222 and 224 operates with the system clock signal SCLK used in the system bus SBUS. Thus, buffers 204, 206, 222, and 224 also function as clock swapping circuits.

[0047] The system bus output control unit 226 receives the control signal CMD and address signal A, which include additional information for memory control, output from buffer 222, and the 512-bit read data signal Q, which is output from buffer 224. In response to the control signal CMD and address signal A, which include additional information for memory control, the system bus output control unit 226 sequentially outputs the 512-bit read data signal Q to the system bus SBUS as up to eight 64-bit read data signals RD. Depending on the size information included in the address signal A and the additional information, the 512-bit read data signal Q may include data signals that are not to be accessed. Only the data signals that are to be accessed are output to the system bus SBUS.

[0048] Figure 3 shows an example of the configuration of the memory block MBLK in Figure 1. Hereafter, the memory block MBLK will be described as having four memory groups MG (MG1, MG2, MG3, MG4). Each memory group MG has four memory units MU. Note that the number of memory groups MG mounted on the memory block MBLK, and the number of memory units MU mounted on each memory group MG, are not limited to the example shown in Figure 3.

[0049] Each memory block MBLK has a memory group control unit MCNT (MCNT1, MCNT2, MCNT3, MCNT4) located on the input side of each memory group MG. Furthermore, the memory block MBLK also has a memory group control unit MCNT5 located on the output side of the final stage memory group MG4.

[0050] While not particularly limited, the size of each memory unit MU is 8k words × 128 bits (= 1M bits), and each memory unit MU inputs and outputs 128 bits of data signals. The size of a memory group MG containing four memory units MU is 32k words × 128 bits (= 4M bits). The size of a memory block MBLK containing four memory groups MG is 128k words × 128 bits (= 16M bits).

[0051] In this embodiment, the unit for switching between shutdown mode, sleep mode, and active mode is the memory unit MU. Sleep mode is an example of a low-power mode. Note that the shutdown mode, sleep mode, and active mode may be switched on a unit basis of two memory units MU, or on a unit basis of columns obtained by further subdividing the memory units MU into multiple columns. Furthermore, the shutdown mode, sleep mode, and active mode may be switched on a unit basis of memory group MG.

[0052] For example, in each memory unit (MU), the power consumption in shutdown mode is about one-tenth of the standby power consumption in active mode, and the power consumption in sleep mode is about one-third of the standby power consumption in active mode.

[0053] Each memory group control unit MCNT adjacent to the input side of each memory group MG outputs a control signal CMD, an address signal A, and a write data signal D to the memory group MG and the memory group control unit MCNT on the output side of the memory group MG. Each memory group MG outputs a read data signal Q to the memory group control unit MCNT on the output side. As shown in Figure 3, the control line CMD and address line A are wired on a unit basis for each memory group MU and are not wired across multiple memory groups MG. Therefore, the increase in the wiring load of the control line CMD and address line A can be suppressed, and the increase in power consumption can be suppressed while suppressing the increase in access time of the memory circuit 100.

[0054] Figure 4 shows an example of the configuration of the memory group MG in Figure 3. The memory group MG is described as having four memory units MU (MU0-MU3). The code (i) appended to the end of a signal indicates an input signal, and the code (o) appended to the end of a signal indicates an output signal. The memory group MG receives the memory clock signal MCLKxN, 16 chip enable signals CEB[15:0], write enable signal WEB, and bit write enable signal BWEB[127:0] as the control signal CMD in Figure 3 from the memory group control unit MCNT. The 16 chip enable signals CEB are supplied in groups of four to the memory units MU (MU0-MU3) and are used to select the memory units MU and the four memory MEM (MEM0-MEM3 in Figure 5) within each memory unit MU shown in Figure 3. The memory group MG also receives a 128-bit write data signal D[127:0] from the memory group control unit MCNT. In the memory group MG, the number of data terminals that receive the write data signal D is one-quarter of the number of data terminals that output the write data signal D in the memory control unit 200.

[0055] Signals with the sign B at the end are negative logic signals, and signals without the sign B at the end are positive logic signals. The bit write enable signal BWEB[127:0] controls the writing of data signals bit by bit, and the bits of the bit write enable signal BWEB corresponding to the bits that mask the write in the write data signal D are set to high level.

[0056] For example, the memory clock signal MCLKxN is a clock signal obtained by multiplying the frequency of the memory clock signal MCLK by four. The number of multiplication factors for the memory clock signal MCLKxN can be set to be equal to the number of memory units MEM mounted on each memory unit MU. In other words, the number of multiplication factors for the memory clock signal MCLKxN can be set to be equal to the number of read data signals Q that are continuously read from the memory unit MU by a read operation performed in response to a single read command RCMD (Figure 12). Similarly, the number of multiplication factors for the memory clock signal MCLKxN can be set to be equal to the number of write data signals D that are continuously written to the memory unit MU by a write operation performed in response to a single write command WCMD (Figure 12).

[0057] Furthermore, the memory group MG receives address signal A and four 128-bit write data signals D[127:0] corresponding to address signal A, and outputs four 128-bit read data signals Q[127:0]. The number of data terminals that output read data signals Q in the memory group MG is one-quarter of the number of data terminals that receive read data signals Q in the memory control unit 200.

[0058] Four 128-bit write data signals D are supplied to one of the four memory units MU0-MU3 within the memory group MG. The memory group MG has multiple selectors SEL that sequentially select one of the 128-bit read data signals Q output from the four memory units MU and output it to a memory group control unit MCNT (not shown).

[0059] Furthermore, the memory group MG receives shutdown signals SD (SD0-SD3) and sleep signals SLP (SLP0-SLP3) from the memory group control unit MCNT, which is not shown as the control signal CMD in Figure 3. As explained in Figure 3, in this embodiment, switching between shutdown mode, sleep mode, and active mode is performed on a per-memory unit MU basis. Therefore, the shutdown signals SD and sleep signals SLP are supplied for each memory unit MU.

[0060] Figure 5 shows an example of the configuration of the memory unit MU in Figure 4. The memory unit MU has four memory MEMs. The size of each memory MEM is 2k words × 128 bits (= 256k bits). Memories MEM0-MEM3 are enabled when their corresponding chip enable signals CEB[0]-CEB[3] are at an effective level (e.g., low level). Then, one of the enabled memory MEMs (any of MEM0-MEM3) performs a read or write operation depending on the logical level of the write enable signal WEB.

[0061] The 128-bit read data signal Q[127:0] read from the memory MEM performing the read operation is output as the read data signal Q[127:0](o) from the memory unit MU via one or more selectors SEL. The memory MEM performing the write operation receives the 128-bit write data signal D[127:0] and writes it to the memory cell (not shown). For example, the memory MEM has multiple SRAM memory cells, but it may also have memory cells of other volatile memory. In addition, the memory MEM may have memory cells of non-volatile memory such as MRAM (Magnetoresistive Random Access Memory) or ReRAM (Resistive Random Access Memory). Note that the number of memory MEMs mounted on the memory unit MU is not limited to the example shown in Figure 5.

[0062] Furthermore, the shutdown signal SD and sleep signal SLP may be further subdivided. For example, the peak current can be further suppressed by supplying a shutdown signal SD and a sleep signal SLP to each of the two memory units MEM.

[0063] Figure 6 shows an example of the internal configuration of the memory MEM included in the memory unit MU of Figure 5. The memory MEM includes a row decoder RDEC, a memory array control circuit MEMCNT, a memory cell array ARY, a precharge circuit PRE, a sense amplifier SA, a read latch RLT, and a data input / output circuit I / O. The data input / output circuit I / O includes a read switch RSW and a buffer BUF (not shown). Hereafter, the precharge circuit PRE, sense amplifier SA, read latch RLT, read switch RSW, and buffer BUF will also be referred to as column circuits. The read latch RLT is an example of a data latch, and the read switch RSW is an example of a data selection unit.

[0064] For example, a memory cell array ARY has 512 word lines WL extending horizontally in Figure 6, 512 complementary bit line pairs BL and BLB extending vertically in Figure 6, and a plurality of memory cells MC arranged in a matrix. Each memory cell MC is located at the intersection of the word line WL and the complementary bit line pair BL and BLB. Each word line WL is commonly connected to the 512 memory cells MC arranged horizontally.

[0065] The command signal CMD shown in Figure 3 includes the read command RCMD and the write command WCMD. In response to the read command RCMD, the write enable signal (memory command signal) WEB in Figures 4 and 5 is controlled to a high level, and the memory (MEM0-MEM3) operates in read mode. On the other hand, in response to the write command WCMD, the write enable signal (memory command signal) WEB in Figures 4 and 5 is controlled to a low level, and the memory (MEM0-MEM3) operates in write mode.

[0066] As explained in Figure 12, data signals are simultaneously read from 512 memory cells MC on the word line WL, selected based on a single read command RCMD recognized by the control signal CMD (Figure 3). The read data signals are transmitted to 128 sets of four pre-charge circuits PRE, sense amplifiers SA, read latches RLT, and read switches RSW. In the first clock cycle, the first data signal from each set of four is selected by the read switch RSW and output as a 128-bit read data signal Q[127:0].

[0067] From the second to the fourth clock cycle, the next data signal is sequentially selected by the read switch RSW every four units and output as a 128-bit read data signal Q[127:0]. Ultimately, 512 read data signals Q are output over four clock cycles. Note that Figure 6 shows the circuitry used in the read operation, omitting the circuitry used only in the write operation.

[0068] Figure 7 shows the read operation by the column-type circuit shown in Figure 6, from the perspective of individual read data signals. In Figure 7, the 512 memory cells MC connected to the word line WL are shown in units of four as MC[k]_0, MC[k]_1, MC[k]_2, MC[k]_3 (where k=0 to 127). A precharge circuit PRE, a sense amplifier SA, and a read latch RLT are provided in a one-to-one relationship with the bit line pairs BL and BLB connected to the memory cells MC, and all data read to the bit line pairs BL and BLB are simultaneously latched to the read latch RLT via the sense amplifier SA.

[0069] During the read operation, after the pre-charging of the bit line pairs BL and BLB by the pre-charge circuit PRE is stopped, a data signal is read from one of the 512 memory cells MC connected to one of the word lines WL selected by the row decoder RDEC and amplified by the sense amplifier SA. The data signal amplified by the sense amplifier SA is latched by the read latch RLT.

[0070] Subsequently, the 512 data signals latched by the read latch RLT are selected 128 at a time per read cycle by four column read signals COL_R[3:0] generated by the memory array control circuit MEMCNT and supplied to the read switch RSW. In the first clock cycle, the read switch RSW receiving the column read signal COL_R[0] is selected, and the 128 data signals read from memory cell MC[k]_0 (where k=0 to 127) are output as read data signals Q[k] (where k=0 to 127) via buffer BUF.

[0071] From the second to the fourth clock cycle, the read switch RSW that receives the column read signals COL_R[1], COL_R[2], and COL_R[3] is sequentially selected. Then, for each clock cycle, 128 data signals read from memory cells MC[k]_1, MC[k]_2, and MC[k]_3 are output as the read data signal Q[k] via the buffer BUF. Finally, using four clock cycles, all the data held in the 512 memory cells MC is output. In this embodiment, the case of four column read signals is shown, but it is not limited to eight or sixteen signals. Also, the column read signals COL_R[0]-COL_R[3] are generated by the memory array control circuit MEMCNT independently of the external address signals supplied to the memory MEM in Figure 6.

[0072] Furthermore, to prevent hazards from occurring in each bit of the read data signal Q[127:0] when the column read signal COL_R[3:0] is switched, it is also possible to place a latch between each read switch RSW and the buffer BUF, for example.

[0073] Figure 8 shows the writing operation using the column-type circuit shown in Figure 6, from the perspective of individual write data signals. In addition to the circuit shown in Figure 6, the writing operation uses a flip-flop circuit D-FF, a write selector WSEL, a write latch WLT, and a write buffer WBUF. The write selector WSEL is an example of a data selection unit, and the write latch WLT is an example of a data latch.

[0074] A flip-flop circuit D-FF is provided for each bit of the write data signal D[127:0]. Each of the 128 bits of the write data signal D is selected by one of four write selectors WSEL that receive four column write signals COL_W[3:0] sequentially generated by the memory array control circuit MEMCNT. A write latch WLT, a write buffer WBUF, and a precharge circuit PRE are provided in a one-to-one relationship with the bit line pairs BL and BLB. The write latch WLT is selectively connected to the output of the flip-flop circuit D-FF via the write selector WSEL for each write cycle. The write buffer WBUF drives the bit line pairs BL and BLB according to the data of the write latch WLT. The precharge circuit PRE precharges the bit line pairs BL and BLB.

[0075] In the first clock cycle, the write data signal is latched to the write latch WLT connected to the memory cell MC[k]_0 (where k=0 to 127) system via the write selector WSEL, which is selected by the column write signal COL_W[0]. In the second to fourth clock cycles, the write selectors WSEL that receive the column write signals COL_W[1], COL_W[2], and COL_W[3] are selected, respectively. Then, the write data signal is sequentially latched to the write latch WLT connected to one of the memory cell systems MC[k]_1, MC[k]_2, and MC[k]_3 (where k=0 to 127) via the write selector WSEL selected each clock cycle.

[0076] Over four clock cycles, the write data signal is latched to all write latches WLT connected to memory cells MC[k]_0, MC[k]_1, MC[k]_2, and MC[k]_3. The latched write data signal is then written to the 512 memory cells MC selected by the word line WL via the write buffer WBUF. When the write cycle is performed over four cycles, the corresponding write buffer WBUF is enabled in each clock cycle to sequentially confirm the data for the bit line pairs BL and BLB. In the clock cycle following the completion of the fourth clock cycle, the desired word line WL is activated to write all the write data to the memory cells MC. This suppresses unnecessary charge and discharge current to the bit line pairs BL and BLB due to pseudo-reads when the word line WL is activated.

[0077] Figure 9 shows an example of a memory circuit 110 including a memory block MBLK120 that receives a 512-bit write data signal D from the memory control unit 200 and outputs a 512-bit read data signal Q to the memory control unit 200. Detailed explanations of elements similar to those in Figure 1 are omitted. The memory circuit 110 shown in Figure 9 does not have the data conversion units PSCNV and SPCNV of Figure 1. The memory circuit 110 has the same configuration as the memory circuit 100 in Figure 1, except that a 512-bit write data signal D is simultaneously transmitted within the memory block MBLK120 during a write operation, a 512-bit read data signal Q is simultaneously transmitted within the memory block MBLK120 during a read operation, and that it has a memory group MGb instead of the memory group MG in Figure 1. Each memory group MGb has four memory units MUb (MUb0-MUb3), and each memory unit MUb has four memories MEMb (MEMb0-MEMb3). Each memory module (MEMb) has a sub-memory module (SubMEMb) that reads and writes 128-bit data, which is obtained by dividing 512-bit data into four parts.

[0078] Figure 10 shows an example of the internal configuration of the sub-memory SubMEMb shown in Figure 9. The memory MEM in Figure 6 can access data equivalent to 512 bits in 128 bits x 4 clock cycles for a single memory access request. However, the sub-memory SubMEMb in Figure 10, for example, accesses 128 bits once for a single memory access request. Therefore, either four memory access requests are made to access data equivalent to 512 bits (128 bits x 4), or, as shown in Figure 9, a data width of 512 bits is used, and four sub-memory SubMEMb systems are arranged vertically to allow access to 512 bits of data in a single operation.

[0079] Furthermore, Figure 6 shows a one-to-one relationship between the bit line pairs BL and BLB and the precharge circuit PRE, sense amplifier SA, read latch RLT, and read switch RSW, whereas Figure 10 differs in that the bit line pairs BL and BLB and the precharge circuit PRE are configured in a four-to-one relationship with respect to the sense amplifier SA and read latch RTL via the multiplexer MUX. Also, comparing the operation of the word line WL and the bit line pairs BL and BLB, the memory MEM in Figure 6 outputs 512 bits of data in 128 bits every four clock cycles, with the activation and deactivation of the word line WL and the bit line pairs BL and BLB occurring only once, whereas the sub-memory SubMEMb in Figure 10 differs in that the activation and deactivation of the word line WL and the bit line pairs BL and BLB occur repeatedly every four clock cycles. Note that Figure 10 differs from Figure 6 in that the multiplexer MUX is placed between the pre-charge circuit PRE and the sense amplifier SA, and does not have a reed switch RSW. However, the multiplexer MUX may be configured with a reed switch RSW.

[0080] The memory array control circuit MEMCNT (not shown in the diagram) sets one of the four decode signals COL_R[3:0] to an active level by decoding the address signal A input from outside the sub-memory SubMEMb. A multiplexer MUX is placed for every four memory cells MC. The multiplexer MUX selectively inputs 128 pairs (128 bits) of data signals from the 512 pairs (512 bits) output from the corresponding memory cell MC to the sense amplifier SA via the multiplexer MUX. Each sense amplifier SA differentially amplifies the input data signal and outputs it to the read latch RLT. Then, a 128-bit read data signal Q[127:0] is output via the read latch RLT.

[0081] In the memory circuit 110 shown in Figure 10, during a read operation, only 128 bits of the 512-bit data signal read from the memory cell MC are output as the read data signal Q[127:0], while the other 384 bits of the data signal are not output. In read and write operations of memory circuits such as SRAM, the power consumption due to the charging and discharging of the bit line pairs BL and BLB is dominant compared to the overall power consumption. For this reason, for example, the power consumption per bit of the data signal read during the read operation of the memory circuit 110 is nearly four times the power consumption per bit of the data signal read during the read operation of the memory MEM in Figure 6, resulting in wasted power.

[0082] Figure 11 shows an overview of the timing of the read operation between the memory MEM included in the memory unit MU of the memory circuit 100 in Figure 6 and the sub-memory SubMEMb included in the memory block MBLK120 of the memory circuit 110 in Figure 10. For example, the memory MEM in Figure 6 and the sub-memory SubMEMb in Figure 10 operate in synchronization with the memory clock signal MCLKxN.

[0083] The memory unit MU (Figure 5) of the memory circuit 100 decodes the upper two bits of the address signal A (=RA0) received along with the read command RCMD to generate a chip enable signal CEB[3:0] (Figure 5) and selects one of the memories MEM0, MEM1, MEM2, or MEM3. The row decoder RDEC in the selected memory MEM decodes the 9 bits from the 3rd to the 11th bits of the address signal RA0, selects, for example, word line WL0 from the 512 word lines WL, and reads a 512-bit data signal from the memory cell array ARY.

[0084] Subsequently, the memory MEM decodes the lower two bits of the address signal RA0 within the memory array control circuit MEMCNT, sequentially generating the column read signal COL_R[3:0], and outputs the 128-bit data signal in four parts as read data signals Qa, Qb, Qc, and Qd. This output data is output to the read data terminal Q[127:0](o) of the memory unit MU via the selector SEL (Figure 5) within the memory unit MU. This allows all data signals read from memory MEM by a single read command RCMD to be output outside the memory circuit 100. In the case of memory MEM, since the column read signal COL_R[3:0] is generated by the memory array control circuit MEMCNT, the lower two bits of the address signal RAn mentioned above are unnecessary.

[0085] In the case of the sub-memory SubMEMb of the memory circuit 110, it is necessary to sequentially generate four address signals A (=RA0-RA3) for one read command RCMD. The sub-memory SubMEMb sequentially selects word lines WL0-WL3 corresponding to address signals RA0-RA3, and selects 128 bits of data signals from the 512 bits of data signals read from the memory cell MC connected to each of the selected word lines WL0-WL3 using the column read signal COL_R[3:0]. Then, the memory block MBLK120 sequentially outputs 128 bits of read data signals Qa, Qb, Qc, and Qd for each read command RCMD. Note that the address signal A received with the read command RCMD may be the same, and the same word line WL may be selected four times. In the case of the sub-memory SubMEMb, the column read signal COL_R[3:0] is generated by decoding the lower two bits of the external address RAn.

[0086] Figure 12 shows an example of the timing of read and write operations for memory MEM in Figures 6, 7, and 8. The read and write operations shown in Figure 12 assume a burst length of 4 and a read latency of 1. In Figure 12, the sign [j] of the word line WL represents an arbitrary number.

[0087] At the beginning of the timing diagram, during the period when the chip enable signal CEB is high, the memory MEM is set to the standby state and all word lines WL are deactivated to a low level. The precharge circuit PRE receives the precharge signal NPCG, which is low to enable, and precharges the bit line pairs BL and BLB to a high level.

[0088] Memory MEM receives a low-level chip enable signal CEB and a high-level write enable signal WEB along with address signal A (=RA0) during clock cycle CYC1, and recognizes a read operation. The five clock cycles after the read operation is recognized constitute the read cycle.

[0089] The memory MEM activates the word line WL, indicated by the address signal RA0, to a high level. During the activation period of the word line WL, the memory MEM controls the precharge signal NPCG to a high level, thereby stopping the precharge operation of the bit line pairs BL and BLB by the precharge circuit PRE and setting the bit line pairs BL and BLB to a high-level floating state. Then, by activating the word line WL, the memory MEM reads data signals from the 512 memory cells MC to the 512 bit line pairs BL and BLB.

[0090] The 512 data signals read to the bit line pairs BL and BLB do not have sufficient amplitude. Therefore, the memory MEM differentially amplifies each of the 512 data signals using 512 sense amplifiers SA. The memory MEM latches all 512 data signals amplified by the sense amplifiers SA to the read latches RLT (Figure 7), which correspond one-to-one with the sense amplifiers SA. After latching the 512 data signals to the read latches RLT, the memory MEM deactivates the word line WL and stops the operation of the sense amplifiers SA. The memory MEM also precharges the bit line pairs BL and BLB to a high level by changing the precharge signal NPCG to a low level.

[0091] In clock cycles CYC2-CYC5, the memory array control circuit MEMCNT sequentially generates column read signals COL_R[3:0], outputting 512-bit data signals read from the 512 memory cells MC each held in the read latch RLT in 128-bit increments via the read switch RSW (Figure 7). The data signals output sequentially from the read switch RSW are output as a read data signal Q via the buffer BUF, and the read cycle ends. In Figure 12, the memory MEM sequentially generates four column read signals COL_R[3:0] and outputs the read data signal Q in four clock cycles, but it is not limited to this, and the read data signal Q may be output in eight or sixteen clock cycles. Also, in Figure 12, the clock cycle in which the read data is first output is CYC2, i.e., read latency = 1, but for example, read latency = 2 or 3 may also be used.

[0092] In the write cycle, memory MEM receives the low-level chip enable signal CEB and the low-level write enable signal WEB along with the address signal A (=WA0) in clock cycle CYC6, and recognizes the write operation. The five clock cycles after the write operation is recognized constitute the write cycle. When memory MEM recognizes that it is a write cycle in clock cycle CYC5, it controls the precharge signal NPCG to a high level, releasing the precharge state of the bit line pairs BL and BLB.

[0093] The memory MEM sequentially generates column write signals COL_W[3:0] during clock cycles CYC6 to CYC9. Synchronized with each column write signal COL_W[3:0], the memory MEM selects 128 bits of write data signal D in each clock cycle using the write selector WSEL (Figure 8) and sequentially latches them into the corresponding write latches WLT. Each write latch WLT sequentially outputs the latched data signal towards the write buffer WBUF (Figure 8), transmitting the data signal D to the corresponding bit line pairs BL and BLB, thereby finalizing the data for 512 bit line pairs BL and BLB.

[0094] In clock cycle CYC10, memory MEM activates the word line WL corresponding to address signal A (=WA0) and writes the logical values ​​of the 512-bit data signals transmitted to each bit line pair BL and BLB to memory cell MC. After writing the data to memory cell MC, memory MEM deactivates the word line WL to a low level, precharges the bit line pairs BL and BLB by setting the precharge signal NPCG to a low level, and ends the write cycle.

[0095] In Figure 12, four column write signals COL_W[0:3] are generated sequentially during the write cycle, and the write data signal D is latched to the write latch WLT and written to the memory cell MC in four clock cycles. However, this is not limited to this, and the write data signal D may be latched to the write latch WLT in eight or sixteen clock cycles. Also, in Figure 12, the cycle in which data is written to the memory cell MC is limited to the clock cycle following the latching of the write data signal D to all write latch WLTs. However, this is not limited to this, and the clock cycle in which data is written to the memory cell MC may be the clock cycle in which the last data is latched, or two clock cycles after the last data is latched. Furthermore, the number of cycles in which data is written to the memory cell MC may be one clock cycle, two clock cycles, or three clock cycles.

[0096] Figure 13 shows an example of the timing of read and write operations for the sub-memory SubMEMb shown in Figure 10. Detailed explanations of operations similar to those in Figure 12 are omitted. The waveforms of the memory clock signal MCLKxN, the chip enable signal CEB, and the write enable signal WEB are the same as in Figure 12.

[0097] During a read cycle, the sub-memory SubMEMb receives address signals A (RA0-RA3) along with the read command RCMD every four clock cycles (CYC1-CYC4), and selects the word line WL corresponding to address signals RA0-RA3. Even if the same word line WL is selected in each clock cycle (CYC1-CYC4), it is necessary to activate and deactivate the word line WL repeatedly with each clock cycle. As a result, the 512 bit line pairs BL and BLB also repeatedly perform data signal readout and precharge operations.

[0098] The sub-memory SubMEMb reads data signals from 512 memory cells MC to 512 bit line pairs BL and BLB for each word line WL selected. The memory block MBLK120 decodes the 2 bits assigned to address signal A to generate the column read signal COL_R[3:0]. Of the 512 bits of data signal read from the memory cell MC, 128 bits of data signal are sequentially selected via the column read signal COL_R[3:0] for each clock cycle CYC1 to CYC4 through the multiplexer MUX and amplified by the sense amplifier SA (Figure 10).

[0099] The sub-memory SubMEMb sequentially outputs a 128-bit read data signal Q with each read operation, ending the read cycle. Of the 512 data signals read from the memory cell MC, 384 bits of data signals are not output from the memory circuit 110.

[0100] During a write cycle, the sub-memory SubMEMb receives the write command WCMD along with address signals A (WA0-WA3) and a 128-bit write data signal D every four clock cycles, from CYC5 to CYC8. The sub-memory SubMEMb first latches the 128-bit write data signal D, then decodes the two bits contained in address signal A to generate the column write signal COL_W[0:3].

[0101] The sub-memory SubMEMb selects the word line WL corresponding to the address signals WA0-WA3 and reads the 512 bits of data held in the memory cell MC as data signals to the bit line pairs BL and BLB. Meanwhile, the latched 128 bits of write data selectively drives the write buffer in response to the column write signal COL_W[0:3] and writes the data to the memory cell MC by overwriting the data read to the corresponding bit line pairs BL and / BL. Of the 512 bits of read data, 128 bits are overwritten, and the remaining 384 bits of read data are not used and are pre-charged along with the deactivation of the word line WL. A similar operation is repeated for four clock cycles, from write cycle CYC5 to CYC8, while sequentially activating the column write signal COL_W[0:3].

[0102] Figure 14 shows an example of the configuration of the memory group control unit MCNT in Figure 1. The memory group control unit MCNT has multiple flip-flop circuits FF (FF1, FF2, FF3, FF4, FF5, FF6, FF7), a relay control unit RCNT, and multiple mask circuits MSK (MSKC, MSKW1, MSKW2, MSKR). Multiple flip-flop circuits FF are connected to thick signal lines. Signals with (i) appended to the end indicate input signals, and signals with (o) appended to the end indicate output signals.

[0103] The memory clock signals MCLK, MCLKxN, and clock enable signal MCLK_E are supplied to buffer BUF1. The memory clock signals MCLK, MCLKxN, and clock enable signal MCLK_E output from buffer BUF1 are output to the next-stage memory group control unit MCNT via buffer BUF2. In addition, the memory clock signals MCLK and MCLKxN output from buffer BUF1 are output to the current memory group MG (the next-stage memory group MG) as memory clock signals IMCLK and IMCLKxN via buffer BUF3.

[0104] The memory clock signals MCLK and MCLKxN are also transmitted to each synchronization circuit within the memory group control unit MCNT via buffer BUF1. That is, each synchronization circuit within the memory group control unit MCNT operates in synchronization with the memory clock signal MCLK or the memory clock signal MCLKxN. For example, the memory clock signal MCLK is used to control the command address signal CAWD (control signal CMD and address signal A), and the memory clock signal MCLKxN is used to control the write data signal D and the read data signal Q.

[0105] The flip-flop circuit FF1 holds and outputs the received command address signal CAWD when the command address enable signal CAEN is at an effective level. The command address enable signal CAEN is output from the memory control unit 200 along with the control signal CMD and address signal A. The flip-flop circuit FF2 forwards the command address enable signal CAEN, which it receives from the memory control unit 200 or the preceding memory group control unit MCNT, to the subsequent memory group control unit MCNT.

[0106] The flip-flop circuit FF3 holds and outputs the received 128-bit write data signal D[127:0] when the write data enable signal WDEN is at an effective level. The write data enable signal WDEN is output from the memory control unit 200 along with the write data signal D. The flip-flop circuit FF4 forwards the write data enable signal WDEN, received from the memory control unit 200 or the preceding memory group control unit MCNT, to the subsequent memory group control unit MCNT.

[0107] The selector SELQ selects either a 128-bit read data signal Q[127:0] read from the preceding memory group MG or a 129-bit read data signal Q[128:0] transferred from the preceding memory group control unit MCNT, depending on the level of the control signal from the relay control unit RCNT. The selector SELQ outputs the selected read data signal Q to the flip-flop circuit FF5. The selector SELQ allows the memory group control unit MCNT to act as a relay circuit to transfer the read data signal Q to the memory control unit 200, regardless of the position of the memory group MG that performs the read operation and outputs the read data signal Q.

[0108] The flip-flop circuit FF5 operates when the read data enable signal RDEN, received from the preceding memory group control unit MCNT, is at an effective level. For example, the effective level of the read data enable signal RDEN is high. The read data enable signal RDEN is output from either the preceding stage or the memory group control unit MCNT preceding it.

[0109] The flip-flop circuit FF5 receives and holds a 129-bit read data signal Q[128:0] (1 bit is Last information) from the preceding memory group control unit MCNT or a 128-bit read data signal Q[127:0] from the preceding memory group MG via the selector SELECTQ. The flip-flop circuit FF5 outputs the held read data signal Q to the mask circuit MSKR.

[0110] Here, the preceding memory group MG is a memory group MG positioned adjacent to the memory control unit 200 (input side) with respect to the memory group control unit MCNT of interest. The operation of the preceding memory group MG is controlled by the memory group control unit MCNT preceding the memory group control unit MCNT of interest.

[0111] The flip-flop circuit FF6 holds the read data enable signal RDEN received from the preceding memory group control unit MCNT and transfers it to the subsequent memory group control unit MCNT via the OR circuit. Note that the first-stage memory group control unit MCNT does not receive the read data signal Q from memory group MG. The second-stage memory group control unit MCNT does not receive the read data signal Q from other memory group control unit MCNTs.

[0112] The flip-flop circuit FF7 receives and holds the read data enable signal IRDEN output from the relay control unit RCNT, and outputs it to the OR circuit. The read data enable signal IRDEN is set to an active level when a data signal is read from its own memory group MG.

[0113] The relay control unit RCNT controls its own operation as well as the operation of the subsequent memory group MG. The subsequent memory group MG is a memory group MG located adjacent to the memory group control unit MCNT of interest on the memory control unit 200 (output side) side, and its operation is controlled by the memory group control unit MCNT of interest.

[0114] The relay control unit RCNT operates based on the logical value of the parameter signal PARAM output from the memory control unit 200 for each memory group control unit MCNT. The memory control unit 200 outputs a parameter signal PARAM, which has a logical value corresponding to the position of the memory group control unit MCNT, to the corresponding memory group control unit MCNT. In other words, the parameter signal PARAM has a unique logical value for each memory group control unit MCNT, indicating which stage the memory group control unit MCNT is in.

[0115] The relay control unit RCNT can detect the memory group MG that is performing a write or read operation by decoding the command address signal CAWD (control signal CMD and address signal A) from the flip-flop circuit FF1. If the relay control unit RCNT determines that a write operation is being performed on the subsequent memory group MG, it outputs a low-level chip enable signal CEB, a low-level write enable signal WEB, address A, and bit write enable signal BWEB to the subsequent memory group MG. The chip enable signal CEB and the write enable signal WEB are generated corresponding to each of the four memory units MU within the subsequent memory group MG.

[0116] When the relay control unit RCNT determines that a read operation is being performed on the subsequent memory group MG, it outputs a low-level chip enable signal CEB, a high-level write enable signal WEB, and address A to the memory unit MU being read. When the relay control unit RCNT determines that the subsequent memory group MG is transitioning to sleep mode or shutdown mode, it outputs a predetermined logical level sleep signal SLP and shutdown signal SD to the memory unit MU being controlled. The sleep signal SLP and shutdown signal SD are generated corresponding to each of the four memory units MU within the subsequent memory group MG.

[0117] When the relay control unit RCNT determines that the downstream memory group MG has been released from sleep mode or shutdown mode, it outputs a low-level sleep signal SLP and a low-level shutdown signal SD to the downstream memory group MG. Here, the release from sleep mode or shutdown mode occurs when a write operation or read operation is performed.

[0118] For example, during shutdown mode, the sleep signal SLP and shutdown signal SD are set to low and high levels, respectively. During sleep mode, the sleep signal SLP and shutdown signal SD are set to high and low levels, respectively. During active mode, both the sleep signal SLP and shutdown signal SD are set to low levels.

[0119] When the memory circuit 100 is started, the sleep signal SLP and the shutdown signal SD are set to low and high levels, respectively, and all memory groups MG are set to shutdown mode. After this, only the memory unit MU to be operated transitions from shutdown mode to active mode, and a write or read operation is performed. Furthermore, if there is no access for a predetermined period in active mode, the memory unit MU in active mode transitions to sleep mode under the control of the corresponding memory group control unit MCNT. The predetermined period for determining the transition from active mode to sleep mode can be changed by the setting value of the register in the memory state management unit 212 shown in Figure 2.

[0120] Furthermore, memory units MU in sleep mode or active mode can transition to shutdown mode based on instructions from the memory control unit 200. In this way, memory units MU in which write or read operations are performed are set to active mode, while other memory units MU are set to sleep mode or shutdown mode. By minimizing the number of memory units MU set to active mode, the power consumption of the memory circuit 100 can be reduced.

[0121] The relay control unit RCNT detects, based on the control signal CMD and address signal A received from the preceding memory group control unit MCNT, that a read data signal Q is output from the preceding or preceding memory group MG. If a read data signal Q is output from the preceding memory group MG, the relay control unit RCNT selects the read data signal Q from the preceding memory group MG using the selector SELECTQ. If a read data signal Q is output from a memory group MG that precedes the preceding stage, the relay control unit RCNT selects the read data signal Q to be transferred from the preceding memory group control unit MCNT using the selector SELECTQ.

[0122] The relay control unit RCNT releases the mask state of the mask circuit MSKR when the read data enable signal RDEN is at an active level, and sets the mask circuit MSKR to a mask state when the read data enable signal RDEN is at an inactive level. As a result, when the memory group control unit MCNT receives a 128-bit read data signal Q from the preceding memory group MG, it can relay the read data signal Q to the subsequent memory group control unit MCNT.

[0123] Furthermore, if the relay control unit RCNT does not receive a read data signal Q from the preceding stage, it suppresses the transfer of the invalid read data signal Q from the preceding stage to the subsequent memory group control unit MCNT. This prevents the transfer of the invalid read data signal Q between the memory group control unit MCNTs preceding the memory group MG in which the read operation is performed, thereby reducing power consumption during the read operation.

[0124] The relay control unit RCNT detects that a read data signal Q is output from its own memory group MG based on the control signal CMD, address signal A, and command address signal CAWD, which includes additional information, received from the preceding memory group control unit MCNT. When a read data signal Q is output from its own memory group MG, the relay control unit RCNT outputs a read data enable signal IRDEN at an effective level to the flip-flop circuit FF7. The flip-flop circuit FF7 outputs the read data enable signal IRDEN to the subsequent memory group control unit MCNT via an OR circuit.

[0125] The relay control unit RCNT outputs the read data enable signal IRDEN in the same clock cycle as the chip enable signal CEB, which causes the subsequent memory group MG to perform a read operation. Therefore, the read data enable signal RDEN output from the flip-flop circuit FF7 is supplied to the subsequent memory group control unit MCNT one clock cycle after the subsequent memory group MG starts its read operation. Consequently, the subsequent memory group control unit MCNT can hold the read data signal Q received from the corresponding memory group MG in the flip-flop circuit FF5.

[0126] When a read operation is performed in the preceding or preceding memory group MG, the relay control unit RCNT releases the mask state of the mask circuit MSKR in order to transfer the read data signal Q to the subsequent memory group control unit MCNT. In a read operation, the final-stage memory group control unit MCNT can perform control to output the control signal CMD, the address signal A, the command address signal CAWD including additional information, and the read data signal Q to the memory control unit 200.

[0127] Furthermore, when a write operation is performed in a subsequent memory group MG, or a memory group MG further behind it, the relay control unit RCNT releases the mask state of the mask circuit MSKW1 in order to transfer the write data signal D to the subsequent memory group control unit MCNT. In addition, to suppress the transfer of the write data signal D to its own memory group MG, the mask circuit MSKW2 is set to the mask state.

[0128] The relay control unit RCNT releases the mask state of the mask circuit MSKC in order to transfer the control signal CMD, address signal A, and command address signal CAWD, which includes additional information, to the subsequent memory group control unit MCNT. Also, when a write operation is performed in a subsequent memory group MG, the relay control unit RCNT releases the mask state of the mask circuit MSKC in order to transfer the control signal CMD, address signal A, and command address signal CAWD, which includes additional information, to the subsequent memory group control unit MCNT. When a write operation is performed in its own memory group MG, the relay control unit RCNT sets the mask circuit MSKC to the mask state in order to suppress the transfer of the command address signal CAWD to the subsequent memory group control unit MCNT.

[0129] When a write operation is performed in its own memory group MG, the relay control unit RCNT sets the mask circuit MSKW1 to the masked state in order to suppress the transfer of the write data signal D to the memory group control unit MCNT. Furthermore, it releases the mask state of the mask circuit MSKW2 in order to transfer the write data signal D to its own memory group MG.

[0130] When a write operation is performed in a subsequent memory group MG, the relay control unit RCNT releases the mask state of the mask circuit MSKW1 in order to transfer the write data signal D to the subsequent memory group control unit MCNT. When a write operation is performed in a subsequent memory group MG, the relay control unit RCNT sets the mask circuit MSKW2 to the mask state in order to suppress the transfer of the write data signal D to its own memory group MG.

[0131] Figure 15 shows an example of generating the memory clock signal MCLK from the memory clock signal MCLKxN. For example, each memory group control unit MCNT may receive the memory clock signal MCLK and the clock enable signal MCLK_EN from the memory control unit 200 and generate the memory clock signal MCLK by dividing the frequency of the memory clock signal MCLKxN by 4. In this case, each memory group control unit MCNT generates the memory clock signal MCLK in synchronization with the rising edge of the memory clock signal MCLKxN that appears during the high-level period of the clock enable signal MCLK_EN. Note that the method of generating the memory clock signal MCLK is not limited to the method shown in Figure 15.

[0132] Figure 16 shows an example of the transitions in the operating states of the memory unit MU in Figure 4. The state transitions in Figure 16 are managed by the memory group control unit MCNT, which controls the operation of the memory unit MU. However, the transition to shutdown mode SD is performed by register settings in the memory state management unit 212 of the memory control unit 200.

[0133] Figure 16 shows the state transitions at the level of switching between shutdown mode SD, sleep mode SLP, and active mode ACT. Therefore, when the unit for switching between shutdown mode SD, sleep mode SLP, and active mode ACT is the memory group MG, Figure 16 shows the state transitions of the memory group MG. When the switching of the operating mode is performed at the level of memory MEM within the memory unit MU, Figure 16 shows the state transitions at the level of memory MEM. Below, an example of control at the level of the memory unit MU is described.

[0134] When the memory circuit 100 in Figure 1 is started, the state of all memory units MU is set to shutdown mode SD. When a write or read request occurs in a memory unit MU, it transitions from shutdown mode SD to active transition mode ATRNS, and, for example, power is turned on to peripheral circuits other than the memory cell area. Then, after a period of time for the power supply to stabilize, the memory unit MU transitions to active mode ACT, and a write or read operation is performed. In active mode ACT, a write or read operation is performed each time a write or read request occurs in the memory unit MU.

[0135] In active mode (ACT), if a predetermined period of time passes without any write or read requests, the memory unit (MU) transitions to sleep mode (SLP). Sleep mode (SLP) is an example of a low-power mode that suppresses power consumption while retaining data within the memory unit (MU). By switching a memory unit (MU) that has not performed any write or read operations for a predetermined period from active mode (ACT) to sleep mode (SLP), the power consumption of the memory circuit (100) can be reduced. In sleep mode (SLP), if a write or read request occurs in the memory unit (MU), it transitions to active transition mode (ATRNS).

[0136] When a shutdown instruction for the memory unit MU is received in active mode ACT or sleep mode SLP, the memory unit MU transitions to shutdown mode SD. The shutdown instruction is performed, for example, by register setting in the memory state management unit 212 based on the reception of the control signal CNTL shown in Figure 2. Depending on the application, it is also possible to implement an embodiment in which the memory unit MU transitions to shutdown mode SD if sleep mode SLP continues for a predetermined period of time. In this case, the duration of sleep mode SLP may be pre-set in the register of the overall management unit 210 shown in Figure 2.

[0137] Automatic transition to shutdown mode SD is appropriate, for example, in video processing, when frame image data held in memory circuit 100 is guaranteed to be accessed within a certain time frame, and when it can be guaranteed that the data held there will not be used if there is no access for a certain period of time or longer. For example, if memory access processing is performed at a certain screen size, and then the screen size is switched to a smaller screen size and the memory access processing continues, unused memory areas will be created from the memory area used when processing at the initial screen size when the screen size is switched to the smaller screen size. In such cases, by automatically transitioning to the shutdown signal SD based on the duration of sleep mode SLP, access control of memory circuit 100 can be made easier compared to issuing a shutdown command from the outside.

[0138] Furthermore, the duration of sleep mode SLP until transitioning to shutdown mode SD may be set based on statistical information such as access frequency. In this case, the memory control unit 200 is further equipped with an acquisition circuit for acquiring statistical information such as the time from transitioning to the sleep state to the active state, the frequency of transitions from the active state to the sleep state, and the frequency of access in the active state, as well as a circuit for calculating the duration.

[0139] Figures 17 to 21 show an example of the operation of the memory group control unit MCNT in Figure 14. The processes shown in Figures 17 to 21 are executed for each memory unit MU by the relay control unit RCNT of the multiple memory group control units MCNT within the memory circuit 100. In the processes shown in Figures 17 to 21, an example is shown where the unit for switching between shutdown mode SD, sleep mode SLP, and active mode ACT is the memory unit MU.

[0140] First, in step S10, the relay control unit RCNT waits until it detects a positive edge of the system clock signal SCLK. If it detects a positive edge, it executes step S12. In step S12, if a state transition request is issued, the relay control unit RCNT executes step S100 (state transition processing). If no state transition request is issued, it executes step S14. An example of step S100 is shown in Figure 18.

[0141] State transition requests are active commands to transition to active mode (ACT), sleep commands to transition to sleep mode (SLP), or shutdown commands to transition to shutdown mode (SD). For example, an active command is issued by the corresponding relay control unit (RCNT) based on a write or read request when the memory unit MU to be accessed is in shutdown mode (SD) or sleep mode (SLP). A shutdown command is issued by the memory control unit (200) based on a request issued to the memory circuit (100) via the system bus (SBUS). A sleep command is issued by the corresponding relay control unit (RCNT) to transition the memory unit MU from active mode (ACT) to sleep mode (SLP). Note that the sleep command may also be issued by the memory control unit (200) based on a request issued to the memory circuit (100) via the system bus (SBUS).

[0142] In step S14, the relay control unit RCNT executes step S200 (read operation) if a read request is issued, and executes step S16 if no read request is issued. An example of step S200 is shown in Figures 19 and 20. In step S16, the relay control unit RCNT executes step S300 (write operation) if a write request is issued, and returns to step S10 if no write request is issued. An example of step S300 is shown in Figure 21.

[0143] In step S100, the relay control unit RCNT executes the state transition process shown in Figure 18 and returns to step S10. In step S200, the relay control unit RCNT executes the read process shown in Figures 19 and 20 and returns to step S10. In step S300, the relay control unit RCNT executes the write process shown in Figure 21 and returns to step S10.

[0144] Figure 18 shows an example of step S100 (state transition processing) in Figure 17. First, in step S102, the relay control unit RCNT determines whether the address signal A received along with the state transition command indicates its own memory group MG. The own memory group MG is the memory group MG that the memory group control unit MCNT accesses and executes a write or read operation on. If the address signal A indicates its own memory group MG, the relay control unit RCNT executes step S104; if the address signal A does not indicate its own memory group MG, it executes step S116.

[0145] In step S104, if the state transition command is an active command or a sleep wake command, the relay control unit RCNT executes step S106. If the state transition command is not an active command or a sleep wake command, the relay control unit RCNT executes step S108.

[0146] In step S106, the relay control unit RCNT outputs a low-level (L) sleep signal SLP and a low-level shutdown signal SD to the memory unit MU, which is the target of the active mode indicated by address signal A. As a result, the target memory unit MU transitions to active mode ACT. After step S106, step S114 is executed.

[0147] In step S108, the relay control unit RCNT executes step S110 if the state transition command is a sleep command, and executes step S112 if the state transition command is not a sleep command.

[0148] In step S110, the relay control unit RCNT outputs a high-level (H) sleep signal SLP and a low-level shutdown signal SD to the memory unit MU, which is the active target (the one to be transitioned to active mode ACT) indicated by address signal A. As a result, the active target memory unit MU transitions to sleep mode SLP. After step S110, step S114 is executed.

[0149] In step S112, the relay control unit RCNT outputs a low-level sleep signal SLP and a high-level shutdown signal SD to the memory unit MU, which is the active target indicated by address signal A. As a result, the active target memory unit MU transitions to shutdown mode SD. After step S112, step S114 is executed.

[0150] In step S114, the relay control unit RCNT suppresses the transfer of the control signal CMD and the address signal A to the memory group control unit MCNT by setting the mask circuit MSKC to the masked state, and terminates the process shown in Figure 18. On the other hand, in step S116, the relay control unit RCNT allows the transfer of the control signal CMD and the address signal A to the memory group control unit MCNT by setting the mask circuit MSKC to the unmasked state, and terminates the process shown in Figure 18.

[0151] Figure 19 shows an example of step S200 (read operation) in Figure 17. First, in step S202, the relay control unit RCNT determines whether the address signal A received along with the read request signal indicating a read request indicates its own memory group MG. If the address signal A indicates its own memory group MG, the relay control unit RCNT executes step S204; if the address signal A does not indicate its own memory group MG, it executes step S210.

[0152] In step S204, the relay control unit RCNT outputs a low-level chip enable signal CEB to the memory unit MU to be read, indicated by the address signal A. The relay control unit RCNT outputs a high-level chip enable signal CEB to the memory unit MU that is not to be read.

[0153] Next, in step S206, the relay control unit RCNT outputs a high-level write enable signal WEB and a high-level bit write enable signal BWEB to its own memory group MG. The relay control unit RCNT outputs the received address signal A along with the control signal CMD to its own memory group MG.

[0154] Next, in step S208, the target relay control unit RCNT corresponding to the memory group MG to be read outputs a high-level read data enable signal RDEN. The target relay control unit RCNT causes the selector SELC to select the invalid read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELC to select the invalid read data signal Q from the preceding memory group MG. After step S208, step S220 is executed.

[0155] In step S210, the relay control unit RCNT outputs a high-level chip enable signal CEB, a high-level write enable signal WEB, and a high-level bit write enable signal BWEB to each memory unit MU. The relay control unit RCNT also outputs a low-level address signal A to each memory unit MU. By not changing the logic level of the address signal A, power consumption during read operations can be reduced.

[0156] In step S212, the relay control unit RCNT determines whether the address signal A received along with the read request signal indicates the memory group MG on the preceding stage (the preceding stage or before the preceding stage). If the address signal A indicates the memory group MG on the preceding stage, the relay control unit RCNT executes step S214; if the address signal A does not indicate the memory group MG on the preceding stage, it executes step S216.

[0157] In step S214, the relay control unit RCNT outputs a low-level read data enable signal RDEN. The relay control unit RCNT also causes the selector SELC to select either the read data signal Q from the preceding memory group MG or the read data signal Q from the preceding memory group control unit MCNT. This allows the read data signal Q read from either the memory unit MU of the preceding memory group MG to be transferred to the subsequent stage. The relay control unit RCNT also receives the high-level read data enable signal RDEN output from the preceding memory group control unit MCNT via an OR circuit and transfers it to the subsequent memory group control unit MCNT. After step S214, step S220 is executed.

[0158] In step S216, the relay control unit RCNT outputs a low-level read-enable signal RDEN. The relay control unit RCNT also causes the selector SELC to select an invalid read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELC to select an invalid read data signal Q from the preceding memory group MG. After step S216, step S220 is executed.

[0159] In step S220, the relay control unit RCNT sets the mask state of the mask circuits MSKC and MSKR and terminates the operation shown in Figure 12.

[0160] Figure 20 shows an example of step S220 in Figure 19. First, in step S222, the relay control unit RCNT sets the mask circuit MSKC to the unmasked state and permits the transfer of the control signal CMD and the subsequent memory group control unit MCNT to address signal A.

[0161] Next, in step S224, the relay control unit RCNT determines whether or not the preceding memory group MG will perform a read operation based on the address signal A received along with the read request signal. If the preceding memory group MG will perform a read operation, step S226 is executed. If the preceding memory group MG will not perform a read operation, step S228 is executed.

[0162] In step S226, the relay control unit RCNT sets the mask circuit MSKR to an unmasked state, enabling the transfer of the read data signal Q from the preceding memory group MG or the read data signal Q from the preceding memory group control unit MCNT to the subsequent stage. After step S226, step S230 is executed.

[0163] In step S228, the relay control unit RCNT sets the mask circuit MSKR to the mask state because the read data signal Q from the preceding memory group MG or the read data signal Q from the preceding memory group control unit MCNT is not transferred. By suppressing the transfer of the invalid read data signal Q, power consumption during read operations can be reduced. After step S228, step S230 is executed.

[0164] In step S230, the relay control unit RCNT sets the mask circuits MSKW1 and MSKW2 to the masked state and terminates the operation shown in Figure 20. Power consumption can be reduced by suppressing the transfer of invalid write data signals D and invalid write data signals D.

[0165] Figure 21 shows an example of step S300 (write operation) in Figure 17. First, in step S302, the relay control unit RCNT determines whether the address signal A received along with the write request signal indicates its own memory group MG. If the address signal A indicates its own memory group MG, the relay control unit RCNT executes step S304; if the address signal A does not indicate its own memory group MG, it executes step S312.

[0166] In step S304, the relay control unit RCNT outputs a low-level chip enable signal CEB and a low-level write enable signal WEB to the memory unit MU to be written to, indicated by address signal A. The relay control unit RCNT outputs a high-level chip enable signal CEB and a high-level write enable signal WEB to the memory unit MU that is not to be written to.

[0167] Next, in step S306, the relay control unit RCNT outputs to its own memory group MG the bit write enable signal BWEB included in the control signal CMD and the address signal A received together with the control signal CMD.

[0168] Next, in step S308, the relay control unit RCNT outputs a low-level read-enable signal RDEN. The relay control unit RCNT causes the selector SELC to select an invalid read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELC to select an invalid read data signal Q from the preceding memory group MG.

[0169] Next, in step S310, the relay control unit RCNT sets mask circuits MSKC and MSKW1 to the masked state, sets mask circuit MSKW2 to the unmasked state, and terminates the operation shown in Figure 21. By setting mask circuit MSKC to the masked state, the transfer of control signal CMD and address signal A to the subsequent stage, which are unrelated to the write operation, is suppressed, thereby reducing power consumption during the write operation. By setting mask circuit MSKW1 to the masked state, the transfer of write data signal D to the subsequent stage is suppressed, thereby reducing power consumption during the write operation. By setting mask circuit MSK2 to the unmasked state, the write data signal D can be transferred to the memory unit MU to be written to.

[0170] In step S312, the relay control unit RCNT outputs a high-level chip enable signal CEB, a high-level write enable signal WEB, and a high-level bit write enable signal BWEB to each memory unit MU. The relay control unit RCNT also outputs a low-level address signal A to each memory unit MU. This reduces power consumption during the write operation, similar to step S210 in Figure 19.

[0171] Next, in step S314, the relay control unit RCNT outputs a low-level read-enable signal RDEN. The relay control unit RCNT causes the selector SELC to select an invalid read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELC to select an invalid read data signal Q from the preceding memory group MG.

[0172] Next, in step S316, the relay control unit RCNT sets the mask state or unmasked state of the mask circuits MSKC, MSKR, MSKW1, and MSKW2. First, the relay control unit RCNT sets the mask circuit MSCR to the mask state. Next, based on the address signal A received along with the write request signal, the relay control unit RCNT determines whether or not the preceding memory group MG will perform a write operation.

[0173] The relay control unit RCNT sets the mask circuits MSKC, MSKW1, and MSKW2 to the masked state when the preceding memory group MG performs a write operation. If the preceding memory group MG does not perform a write operation, the relay control unit RCNT sets the mask circuits MSKC and MSKW1 to the unmasked state and the mask circuit MSKW2 to the masked state. Then, the relay control unit RCNT terminates the operation shown in Figure 21. By setting the mask circuits MSKC and MSKW1 to the masked state when the access request signal and the write data signal D are not transferred to the subsequent stage, power consumption during the write operation can be reduced.

[0174] Figure 22 shows an example of the operation to transition the memory unit MU to active mode ACT in the memory circuit 100 of Figure 1. Figure 22 explains the operation when the memory unit MU, which is shaded within the memory group MG2, is transitioned to active mode. The memory unit MU, which is shaded within the memory group MG2, is also called the target memory unit MU (labeled as the active target MU in the figure). Figure 22 shows only the signals used for the transition to active mode ACT.

[0175] When the memory control unit 200 receives an access request signal (write request signal or read request signal) while in shutdown mode SD, it outputs a state transition request to transition the memory unit MU to active mode ACT from shutdown mode SD. Furthermore, when the memory control unit 200 receives an access request signal while in sleep mode SLP, it outputs a state transition request to transition the memory unit MU to active mode ACT from sleep mode SLP.

[0176] Each memory group control unit (MCNT) follows instructions from the memory control unit (200) and, if it is a memory state transition request for a memory unit (MU) within its own memory group (MG), it outputs a low-level shutdown signal (SD) and a low-level sleep signal (SLP) to the corresponding memory unit (MU).

[0177] The memory control unit 200 outputs a state transition request to the first-stage memory group control unit MCNT1 to set the target memory unit MU to an active state. Based on the address signal A included in the state transition request, the memory group control unit MCNT1 determines that the memory unit MU included in its own memory group MG1 is not the target memory unit MU. Therefore, the memory group control unit MCNT1 forwards the state transition request to the subsequent memory group control unit MCNT2.

[0178] The memory group control unit MCNT2 determines, based on the address signal A included in the state transition request, that the memory unit MU included in its own memory group MG2 is the target memory unit MU. The memory group control unit MCNT2 then outputs a low-level sleep signal SLP and a low-level shutdown signal SD to the target memory unit MU in memory group MG2. Since the memory group control unit MCNT2 has determined that the memory unit MU in its own memory group MG2 includes the target memory unit MU, it does not forward the state transition request to the subsequent memory group control units MCNT3 and MCNT4.

[0179] Figures 23 and 24 show an example of signal timing during the transition to the active mode ACT in Figure 22. Figures 23 and 24 show the timing waveforms of various signals corresponding to the operation described in Figure 22. In Figures 23, 24, and the timing diagrams described later, the code (i) at the end of a signal indicates an input signal to the target circuit, and the code (o) at the end of a signal indicates an output signal from the target circuit. Hereafter, each signal may be described by its code rather than its signal name. The signal names shown in the waveforms of the timing diagrams from Figure 23 onwards may differ from the signal names described above. For example, the code ID indicates command signals such as various commands, the code ADR indicates address signal A, and the code ETC indicates other control signals, etc. The codes AWID(i), AWetc(i), and AWVLD(i) indicate the request signal REQ from the system bus SBUS. The code AWA(i) indicates the address signal ADR from the system bus SBUS. The code AWRDY(o) indicates an acknowledgment signal to the system bus SBUS.

[0180] The system bus input control unit 202 in Figure 2 detects from the system bus SBUS that valid AWID, AWA, and AWetc signals, which are examples of the request signal REQ and address signal ADR, are supplied from the system bus SBUS, based on a high-level AWVLD signal (an example of the request signal REQ and address signal ADR) input from the system bus SBUS. The AWID signal contains information that identifies a state transition request, the AWA signal indicates the address to be used in the state transition request, and the AWetc signal indicates additional information to be used in the state transition request.

[0181] The system bus input control unit 202 stores (pushes) the CAWD signal (data), which includes the control signal CMD containing additional information and the 512-bit address A, which is the memory access unit, into the buffer 204. This CAWD signal is converted from the AWID, AWA, and AWetc signals received during the high-level period of the AWVLD signal. After confirming that there is space in the buffer 204 based on the low-level CAFULL signal, the system bus input control unit 202 outputs a high-level AWRDY signal (acknowledgment signal) to the system bus SBUS to indicate that the state transition request has been accepted. The CAFULL signal is set to high when there is no space in the buffer 204. The CAPUSH signal indicates the timing of storage into the buffer 204.

[0182] The input interface control unit 214 checks the information held in the buffer 204 and detects the memory unit MU that is the target of the state transition based on the address information. The input interface control unit 214 receives the state of the memory unit MU that is the target of the state transition as an MST signal from the memory state management unit 212.

[0183] For example, suppose the MST signal is in the shutdown state (SD) or sleep state (SLP). In this case, the input interface control unit 214 outputs an instruction to change to the active state and information indicating the memory unit MU to be activated to the first-stage memory group control unit MCNT1. The instruction to change to the active state and the information indicating the memory unit MU to be activated are output to the memory group control unit MCNT1 as the CAWD signal, synchronized with the high level of the CAEN signal.

[0184] The instruction to change to the active state is also output to the memory state management unit 212. In the clock cycle following the receipt of the instruction to change to the active state, the memory state management unit 212 changes the MST signal from the shutdown state SD to the transition state TOACT for the active mode ACT. Furthermore, after the elapsed time T1, the memory state management unit 212 sets the MST signal to the active state ACT.

[0185] In Figure 24, the symbol (A) indicates the timing of the symbol (A) in Figure 23. There is a physical distance between the output of the input interface control unit 214 and the input of the memory group control unit MCNT1. Therefore, the signal output from the input interface control unit 214 reaches the memory group control unit MCNT1 after time Td. In this example, the memory unit MU, which is the target of the state transition, is included in the memory group MG downstream of the memory group control unit MCNT2 and is controlled by the memory group control unit MCNT2. Therefore, the memory group control unit MCNT1 receives the CAWD signal indicating a change instruction to the active state and forwards it to the memory group control unit MCNT2 as a CAWD signal after one clock cycle.

[0186] The memory group control unit MCNT2 detects that the memory unit MU within its own memory group MG is the target of activation based on the address contained in the received CAWD signal. The memory group control unit MCNT2 then sets the shutdown terminal SD of the target memory unit MU from high level to low level, transitioning it to the active state. Since the memory group control unit MU has been detected as the target of activation, the memory group control unit MCNT2 masks the output of the CAWD(o) and CAEN(o) signals to the subsequent memory group control unit MCNT3 and does not transfer them.

[0187] Figure 25 shows an example of the writing operation of the memory circuit 100 in Figure 1. Detailed explanations of operations similar to those in Figure 22 are omitted. Figure 25 explains the operation when data is written to the memory unit MU, which is shaded within the memory group MG2.

[0188] When the memory control unit 200 receives a write request signal, it sequentially stores 512 bits (up to eight 64-bit write data signals WD) received via the system bus SBUS, along with a 1-bit LAST signal (the explanation of the LAST signal will be omitted unless otherwise specified), into the buffer 206 shown in Figure 2, as described in Figure 2. If the memory unit MU containing the memory cell MC to be written to is in a shut-down state, the memory control unit 200 transitions the target memory unit MU to an active state, as shown in Figure 22, and then performs the operation shown in Figure 25.

[0189] The memory control unit 200 outputs, for example, a 512-bit write data signal D to the data conversion unit PSCNV, which converts it into four 128-bit series write data signals D. The four series write data signals D are supplied to the first-stage memory group control unit MCNT1 along with the control signal CMD and the address signal A. Based on the received address signal A, the memory group control unit MCNT1 determines that its own memory group MG1 is not a target for writing. Therefore, the memory group control unit MCNT1 forwards the control signal CMD, the address signal A, and the write data signals D to the subsequent memory group control unit MCNT2.

[0190] The memory group control unit MCNT2 determines, based on the received address signal A, that its own memory group MG2 is the target for writing. The memory group control unit MCNT2 then outputs the control signal CMD and address signal A to the memory unit MU that is the target for writing. The memory group control unit MCNT2 also sequentially outputs four 128-bit write data signals D to the memory unit MU that is the target for writing. The data is then written to the memory cell MC that is the target for writing.

[0191] As shown in Figure 25, the memory group control unit MCNT2 masks the transfer of the control signal CMD, address signal A, and write data signal D to the subsequent memory group control unit MCNT3 because the address signal received along with the write request signal indicates its own memory group MG. Each memory group control unit MCNT transfers the write request signal and address signal to the subsequent memory group control unit MCNT if the address signal received along with the write request signal indicates a memory group other than its own memory group MG.

[0192] This allows for the suppression of charge and discharge currents for the control line CMD, address line A, and write data line D compared to, for example, supplying the control signal CMD, address signal A, and write data signal D to each memory group MG in common. As a result, it is possible to suppress an increase in dynamic power while suppressing an increase in the access time of the memory circuit 100.

[0193] Figures 26 and 27 show an example of signal timing during the write operation shown in Figure 25. Detailed explanations of operations similar to those shown in Figures 23 and 24 are omitted. Figures 26 and 27 show the timing waveforms of various signals corresponding to the write operation described in Figure 25.

[0194] The system bus input control unit 202 in Figure 2 detects that a valid WDATA signal (data), etc., is being supplied based on a high-level WVLD signal. The WDATA signal includes the data to be written to the memory cell MC by the write operation and the write address, etc.

[0195] The system bus input control unit 202 temporarily stores the DWATA signal received during the high-level period of the WVLD signal internally, and then combines up to eight data signals into 512 bits and stores (pushes) them into buffers 204 and 206. After confirming that buffers 204 and 206 are free based on the low-level WFULL signal, the system bus input control unit 202 outputs a high-level WRDY signal (acknowledgment signal) to the system bus SBUS to indicate that a write request has been accepted.

[0196] The WPUSH signal indicates the timing for storing write data signals, etc., into buffers 204 and 206. In this embodiment, every eight 64-bit data signals received from the system bus SBUS, a 512-bit data signal is stored together in buffer 206. At this time, a WLAST signal, indicating that the data signal from the system bus SBUS is the last, is stored in buffer 204. In the write data signal D, "not-last" indicates that it is not the last data, and "last" indicates that it is the last data.

[0197] When the input interface control unit 214 detects a write request from the information held in buffer 204, it reads the control signal CMD, address signal A, and write data signal D from buffers 204 and 206. The input interface control unit 214 determines whether it is the last write data signal D using last and not-last in WDRD. In this example, it is shown that the 512-bit write data signal D is obtained twice from buffer 206.

[0198] The input interface control unit 214 generates the CAWD signal, CAEN signal, write data signal D, and WDEN signal based on the control signal CMD, address signal A, and write data signal D read from buffers 204 and 206. The input interface control unit 214 outputs the CAWD signal, CAEN signal, and WDEN signal to the first-stage memory group control unit MCNT1, and outputs the write data signal D to the data conversion unit PSCNV.

[0199] In Figure 27, the symbol (B) indicates the timing of the symbol (B) in Figure 26. The memory group control unit MCNT1 receives the signal output from the input interface control unit 214 after time Td. Based on the received control signal CMD and address signal A, the memory group control unit MCNT1 determines that its own memory group MG is not a target for write access. Therefore, the memory group control unit MCNT1 forwards the signal received from the input interface control unit 214 to the subsequent memory group control unit MCNT2.

[0200] The memory group control unit MCNT1 receives four 128-bit write data signals D output from the input interface control unit 214 in synchronization with the memory clock signal MCLKxN. The memory group control unit MCNT1 then transfers the four received write data signals D to the memory group control unit MCNT2 in synchronization with the memory clock signal MCLKxN. The codes D1-D8 shown in the write data signals D represent the eight write data signals WD that the system bus input control unit 202 in Figure 2 receives sequentially. That is, each of the four 128-bit write data signals D contains the data of two write data signals WD.

[0201] The memory group control unit MCNT2 detects that the memory unit MU within its own memory group MG is the target of writing, based on the received control signal CMD and address signal A. The memory group control unit MCNT2 then sets the CEB and WEB terminals of the target memory unit MU to a low level. The memory group control unit MCNT2 also sequentially receives four write data signals D in synchronization with the memory clock signal MCLKxN.

[0202] The memory group control unit MCNT2 outputs address A and bit write enable signal BWEB to terminals A and BWEB of the memory unit MU to be written, and sequentially outputs four write data signals D to terminal D of the memory unit MU in synchronization with the memory clock signal MCLKxN. As a result, data is written to the memory cell MC of the memory unit MU. Since the address signal A received along with the write request signal indicates its own memory group MG, the memory group control unit MCNT2 masks the transfer of signals CAWD(o), CAEN(o), D(o), and WDEN(o) to the subsequent memory group control unit MCNT3.

[0203] Figure 28 shows an example of the read operation of the memory circuit 100 in Figure 1. Detailed explanations of operations similar to those in Figures 22 and 25 are omitted. Figure 28 explains the operation when data is read from the memory unit MU, which is shaded within the memory group MG2.

[0204] When the memory control unit 200 receives a read request, it operates in the same manner as when it receives a write request, except that it does not receive the write data signal D. Furthermore, if the memory unit MU containing the memory cell MC to be read is in a shut-down state, the memory control unit 200 transitions the target memory unit MU (labeled as "active target MU" in the figure) to an active state, as shown in Figure 22, and then performs the operation shown in Figure 28.

[0205] The memory control unit 200 (output side) outputs the control signal CMD and address signal A to the first-stage memory group control unit MCNT1. Based on the received address signal A, the memory group control unit MCNT1 determines that its own memory group MG1 is not a target for reading. Therefore, the memory group control unit MCNT1 forwards the control signal CMD and address signal A to the subsequent memory group control unit MCNT2.

[0206] The memory group control unit MCNT2 determines, based on the received address signal A, that its own memory group MG2 is the target for reading. The memory group control unit MCNT2 outputs a control signal CMD and address signal A to each of the memory units MU that are to be read. Then, the read data signal Q is read from the memory cell MC and output to the subsequent memory group control unit MCNT3.

[0207] The memory group control unit MCNT3 forwards the received control signal CMD, address signal A, and read data signal Q to the next memory group control unit MCNT4. The memory group control unit MCNT4 forwards the received control signal CMD, address signal A, and read data signal Q to the next memory group control unit MCNT5. Based on the received control signal CMD and address signal A, the memory group control unit MCNT5 outputs the received read data signal Q to the memory control unit 200 (output side) via the data conversion unit SPCNV.

[0208] The data conversion unit SPCNV converts four sequentially received 128-bit read data signals Q into a 512-bit read data signal Q and outputs it to the memory control unit 200. The memory control unit 200 outputs the received 512-bit read data signal Q in multiple installments as a series read data signal DT (for example, 64 bits).

[0209] The read data lines on which the read data signal Q is transferred are wired for each memory group MG and are sequentially electrically connected via the memory group control unit MCNT. Therefore, when memory group MG2 performs a read operation, the read data signal Q is not transmitted to the read data lines of memory group MG1, which is upstream of memory group MG2. This reduces the dynamic power consumption of the memory block MBLK during read operations compared to the case where a common read data line is wired to all memory groups MG.

[0210] During a read operation, the memory block MBLK can receive an access request signal from the memory control unit 200 (input side) and output a read data signal Q to the memory control unit 200 (output side). This makes it possible to keep the sum of the length of the signal line that transfers the access request signal from the memory control unit 200 to the memory group MG to be read, and the length of the signal line that transfers the read data signal Q to the memory control unit 200, approximately constant regardless of the access position. As a result, it is possible to suppress fluctuations in the read access time depending on the position of the memory group MG in which the read operation is performed.

[0211] Each memory group control unit (MCNT) outputs a read request signal to its own memory group MG if the address signal A included in the read request signal indicates its own memory group MG. If the address signal included in the read request signal indicates a memory group other than its own memory group MG, each memory group control unit (MCNT) forwards the read request signal to the next memory group control unit (MCNT).

[0212] Figures 29 to 32 show an example of signal timing during the read operation in Figure 28. Detailed explanations of operations similar to those in Figures 23, 24, 26, and 27 are omitted. Figures 29 to 32 show the timing waveforms of various signals corresponding to the read operation described in Figure 28. The codes ARID(i), ARetc(i), and ARVLD(i) indicate the request signal REQ from the system bus SBUS. The code ARAD(i) indicates the address signal ADR from the system bus SBUS. The code ARRDY(o) indicates the acknowledgment signal to the system bus SBUS.

[0213] In Figure 29, the system bus input control unit 202 in Figure 2 stores (pushes) the CAWD signal (data), which includes additional information CMD and address A, which is the storage location for a 512-bit (four 128-bit) memory access unit, into buffer 204. This CAWD signal is converted from the ARID signal (command), ARAD signal (address), and ARetc signal (other signals), which are examples of the request signal REQ and address signal ADR received from the system bus SBUS, during the high-level period of the ARVLD signal (an example of the request signal REQ and address signal ADR) input from the system bus SBUS. The CAWD signal includes the control signal CMD, which contains additional information, and address A, which indicates the storage location for a 512-bit (four 128-bit) memory access unit. After confirming that buffer 204 is free based on the low-level CAFULL signal input from the system bus SBUS, the system bus input control unit 202 outputs a high-level ARRDY signal (acknowledgment signal) to the system bus SBUS to indicate that a read request has been received. The CAPUSH signal indicates the timing of storing the read request signal and other data included in the read request into buffer 204.

[0214] When the input interface control unit 214 detects a read request from the information held in the buffer 204, it reads the control signal CMD and address signal A, etc., from the buffer 204. Based on the control signal CMD and address signal A, etc., read from the buffer 204, the input interface control unit 214 outputs the information to be used for read access to the first-stage memory group control unit MCNT1. For example, the signals output for use in read access are the CAWD signal, CAEN signal, and WDEN signal. Note that the write data line D is not used in read operations.

[0215] If the burst length (the number of outputs of the read data signal RD for a single read request) is large, a read request may not be completed in a single access by the memory unit MU. In this case, the input interface control unit 214 generates a second and subsequent read request. "not-last" in CAWD indicates that the read request is not the last, while "last" indicates that it is the last. Assume that four 128-bit read data signals Q are read in one burst operation.

[0216] In Figure 30, the symbol (A) indicates the timing of the symbol (A) in Figure 29. The memory group control unit MCNT1 receives the signal output from the input interface control unit 214 after time Td. Based on the received control signal CMD and address signal A, the memory group control unit MCNT1 determines that its own memory group MG is not a target for read access. Therefore, the memory group control unit MCNT1 forwards the signal received from the input interface control unit 214 to the subsequent memory group control unit MCNT2.

[0217] The memory group control unit MCNT2 detects that the memory unit MU within its own memory group MG is the target of reading based on the received control signal CMD and address signal A. The memory group control unit MCNT2 then sets the CEB terminal of the target memory unit MU to a low level and the WEB terminal to a high level. The memory group control unit MCNT2 also outputs address A to the A terminal of the target memory unit MU. As a result, four 128-bit data points are sequentially read from the memory cell MC of the target memory unit MU.

[0218] The memory group control unit MCNT2 generates a read data enable signal IRDEN (Figure 14) to transfer the read data signal Q to the subsequent memory group control unit MCNT. The read data enable signal IRDEN is output to the memory group control unit MCNT3 as a read data enable signal RDEN.

[0219] Furthermore, the memory group control unit MCNT2 sequentially transfers the four 128-bit read data signals Q, which are read sequentially from the memory unit MU, to the memory group control unit MCNT3 in synchronization with the memory clock signal MCLKxN. The codes Q1-Q8 shown on the Q terminal of the MU being read represent the eight read data signals RD that are sequentially output by the system bus output control unit 226 in Figure 2. That is, each of the four 128-bit read data signals Q contains the data of the two read data signals RD.

[0220] If the burst length is 8, two pulses of the read data enable signal RDEN are generated, and the memory group control unit MCNT2 sequentially transfers four 128-bit read data signals Q to the memory group control unit MCNT3 for each pulse of the read data enable signal RDEN.

[0221] During the read operation, the read data signal Q read from the memory unit MU is converted in series to parallel by the system bus output control unit 226 and output to the system bus SBUS as the read data signal RD. For this reason, the memory group control unit MCNT2 outputs the received control signal CMD and address signal A, along with the read data signal Q, to the memory group control unit MCNT3.

[0222] In Figure 31, the symbols (B), (C), and (D) indicate the timing of the symbols (B), (C), and (D) in Figure 30. The memory group control unit MCNT3 receives the signal output from the memory group control unit MCNT2 after time Td. The memory group control unit MCNT3 forwards the received control signal CMD, address signal A, and read data signal Q to the memory group control unit MCNT4. The memory group control unit MCNT4 forwards the received control signal CMD, address signal A, and read data signal Q to the memory group control unit MCNT5. The memory group control unit MCNT5 outputs the received control signal CMD and address signal A to the memory control unit 200, and sequentially outputs the received read data signal Q to the data conversion unit SPCNV.

[0223] In Figure 32, the symbols (E) and (F) indicate the timing of the symbols (E) and (F) in Figure 31. The data conversion unit SPCNV sequentially sums the four 128-bit read data signals Q it receives for each burst operation to form a 512-bit read data signal Q, which it outputs to the memory control unit 200. The output interface control unit 220 of the memory control unit 200 stores (pushes) the received control signal CMD and address signal A into the buffer 222, and stores (pushes) the read data signal Q received from the data conversion unit SPCNV into the buffer 224.

[0224] The system bus output control unit 226 of the memory control unit 200 refers to the CRAVLD signal output from buffer 222 and the RDVLD signal output from buffer 224, and waits for buffers 222 and 224 to become readable (valid). When buffers 222 and 224 become readable and the system bus SBUS is ready (RRDY=H), the system bus output control unit 226 generates the RID signal and RDATA signal to be output to the system bus SBUS. The RID signal and RDATA signal use the control signal CMD and address signal A held in buffer 222 and the read data signal Q held in buffer 224 to generate the read data signal RDATE (an example of the read data signal RD) and additional information RID and RLAST to be sent to the system bus side.

[0225] Furthermore, the system bus output control unit 226 sets the RVLD signal, which indicates that the output signal to the system bus SBUS is valid, to the valid level (RVLD=H). While the read data signal from the memory block MBLK is in 512-bit units, the read data signal on the system bus SBUS side is in 64-bit units. Therefore, the read data signal is output to the system bus SBUS in up to 8 separate outputs. When the CRAPOP and RDPOP signals are set to the valid level (H), the following control signals CMD, address signal A, and read data signal Q are output to buffers 222 and 224.

[0226] In the example shown in Figure 32, the system bus output control unit 226 sequentially selects the 512-bit read data signals Q read from the memory block MBLK to match the 64-bit data bus width on the system bus SBUS side. The first 64-bit data signals Q1.1 to Q1.8 are output to the system bus SBUS in 8 clock cycles. Furthermore, the next 512-bit read data signals Q from the memory block MBLK are also output to the system bus SBUS in 8 clock cycles, from data signals Q2.1 to Q2.8. Finally, when the last read data signal Q, data signal Q2.8, is output, the system bus output control unit 226 sets RLAST to an active level (e.g., high level) and completes the read operation.

[0227] Figures 33 to 36 show another example of the signal timing during the read operation of the memory circuit 100 in Figure 1. Figures 33 to 36 show an example in which a read request is issued to the memory unit MU of memory group MG4, and then to the memory unit MU of memory group MG1.

[0228] The operation of each circuit element in Figures 33 to 36 is the same as that of each circuit element shown in Figures 29 to 32, except that two read requests are issued sequentially. In other words, the operation for each read request in Figures 33 to 36 is the same as that shown in Figures 29 to 32.

[0229] In this embodiment, the access request signal, the write data signal D, and the read data signal Q can be pipelined between the memory group control unit MCNT. Therefore, for example, other read requests can be sequentially supplied to the memory block MBLK before the read data signal Q responding to one read request is output from the memory block MBLK. As a result, as shown in Figures 33 to 36, a read access to memory group MG1 can be performed in the clock cycle following a read access to memory group MG4.

[0230] In the first embodiment described above, the data conversion unit PSCNV converts a 512-bit write data signal D into four 128-bit write data signals D and supplies them to the memory block MBLK. Therefore, the number of write data lines D wired within the memory block MBLK can be reduced to one-quarter compared to the case where the data conversion unit PSCNV is not used.

[0231] Similarly, the data conversion unit SPCNV converts four 128-bit read data signals Q output from the memory block MBLK into a 512-bit read data signal Q. As a result, the number of read data lines Q wired within the memory block MBLK can be reduced to one-quarter compared to when the data conversion unit SPCNV is not used.

[0232] The control line CMD, address line A, and write data line D are wired for each memory group MG and are sequentially electrically connected via the memory group control unit MCNT. The control signal CMD, address signal A, and write data signal D are not transferred to memory groups MG downstream of the memory group MG to which the write data signal D is written. As a result, the charging and discharging currents of the control line CMD, address line A, and write data signal D can be suppressed compared to the case where the control line CMD, address signal A, and write data signal D are wired in common to each memory group MG and supplied in common to each memory group MG. Consequently, power consumption during writing operations can be reduced while suppressing an increase in the access time of the memory circuit 100.

[0233] The read data lines on which the read data signal Q is transferred are wired for each memory group MG and are sequentially electrically connected via the memory group control unit MCNT. Therefore, the read data signal Q is not transmitted to the read data lines of memory group MGs prior to the memory group MG performing the read operation. This reduces the power consumption of the memory block MBLK during read operations compared to the case where a common read data line is wired to all memory group MGs.

[0234] Each memory MEM has 512 memory cells MC connected to a word line WL. Based on a single read command RCMD, data signals are simultaneously read from the selected memory cells MC on the word line WL. The read data is controlled in units of four, and 128 bits can be sequentially output as a read data signal Q in four clock cycles. In addition, based on a single write command WCMD recognized by the control signal CMD, write data signals D can be sequentially received in four clock cycles and written simultaneously to all memory cells MC.

[0235] Each memory group control unit (MCNT) sets the memory unit MU that will perform a write or read operation to active mode (ACT), and sets the other memory units MU to shutdown mode (SD) or sleep mode (SLP). This reduces the power consumption of the memory circuit 100. Furthermore, each memory group control unit (MCNT) can further reduce the power consumption of the memory circuit 100 by switching the memory unit MU that will not perform a write or read operation for a predetermined period from active mode (ACT) to sleep mode (SLP).

[0236] The memory group control unit MCNT is operated in synchronization with the memory clock signal MCLK, and the memory group MG is operated in synchronization with the memory clock signal MCLKxN, which is obtained by multiplying the memory clock signal MCLK by four. As a result, even when a 512-bit write data signal D is converted into four 128-bit write data signals D by the data conversion unit PSCNV and written to the memory unit MU, the same write rate can be achieved as when the 512-bit write data signal D is written to the memory unit MU in synchronization with the memory clock signal MCLK.

[0237] Furthermore, even when four 128-bit read data signals Q read from the memory unit MU are converted into 512-bit read data signals Q by the data conversion unit SPCNV, the same read rate can be achieved as when the 512-bit read data signals Q are read from the memory unit MU in synchronization with the memory clock signal MCLK.

[0238] The memory control unit 200 and the data conversion unit PSCNV convert eight write data signals WD, which are sequentially received from the system bus SBUS, into four write data signals D, and sequentially output the four converted write data signals D to the memory block MBLK to execute the write operation. In addition, the memory control unit 200 and the data conversion unit SPCNV convert four read data signals Q, which are sequentially read from the memory block MBLK, into eight read data signals RD, and sequentially output them to the system bus SBUS. As a result, the operating frequency of the memory block MBLK can be made lower than the operating frequency of the system bus SBUS, and the power consumption of the memory block MBLK can be reduced. Because the operating frequency of the memory block MBLK can be lowered, there can be more operating margin for the memory group control unit MCNT and the memory group MG, making it easier to design the timing of the circuit.

[0239] The memory circuit 100 has memory group control units MCNT and memory group MG alternately arranged between the memory control unit 200 (input side) and the memory control unit 200 (output side). In a read operation, the memory block MBLK receives an access request signal from the memory control unit 200 (input side) and outputs a read data signal Q to the memory control unit 200 (output side). This makes it possible to keep the sum of the length of the signal line that transfers the access request signal from the memory control unit 200 to the memory group MG to be read, and the length of the signal line that transfers the read data signal Q to the memory control unit 200, approximately constant regardless of the access position. As a result, it is possible to suppress fluctuations in the read access time depending on the position of the memory group MG performing the read operation.

[0240] The control line CMD, through which the access request signal is transferred, and the address line A, through which the address signal A is transferred, are wired for each memory group MG and are sequentially electrically connected via the memory group control unit MCNT. This allows each memory group control unit MCNT to control access for each memory group MG. Since the control line CMD and address line A are not wired across multiple memory groups MG, the increase in wiring load can be suppressed. As a result, power consumption can be reduced while suppressing the increase in access time of the memory circuit 100.

[0241] The number of clock cycles (e.g., the number of MCLKxN clock cycles) required for the transfer of the access request signal, write data signal D, and read data signal Q between the pair of memory group control units MCNT located on either side of the memory group MG is set to be the same for both. This makes timing design easier even when increasing or decreasing the number of memory groups MG to design other memory circuits with different storage capacities.

[0242] Figure 37 shows an example of the configuration of a memory circuit in the second embodiment. Detailed explanations of elements similar to those in Figure 1 are omitted. In the memory circuit 102 shown in Figure 37, the memory block MBLK has nine memory group control units MCNT1-MCNT9 and eight memory groups MG1-MG8, each positioned between adjacent memory group control units MCNT. The configuration of each memory group control unit MCNT is the same as that of the memory group control unit MCNT shown in Figure 14. The configuration of each memory group MG is the same as that of the memory group MG shown in Figure 4. Therefore, the memory circuit 102 has a storage capacity of 32M bits (256k words × 128 bits), which is twice that of the memory circuit 100 shown in Figure 3.

[0243] In this embodiment, the control line CMD, address line ADR, write data line D, and read data line Q are folded back at the middle memory group control unit MCNT5 of the nine memory group control units MCNT1-MCNT9. This allows the input-side memory control unit 200 and the output-side memory control unit 200 shown in Figure 3 to be arranged as a single unit. The configuration of the memory control unit 200 is the same as the configuration of the memory control unit 200 shown in Figure 2.

[0244] Then, the 512-bit write data signal D output from the memory control unit 200 is output to the memory group control unit MCNT1 as four 128-bit write data signals D via the data conversion unit PSCNV. The four 128-bit read data signals Q output from the memory group control unit MCNT9 are output to the memory control unit 200 as 512-bit read data signals Q via the data conversion unit SPCNV.

[0245] As described above, the same effects as in the first embodiment can be obtained in the second embodiment as well. For example, the number of write data lines D wired in the memory block MBLK can be reduced to one-quarter compared to the case where the data conversion unit PSCNV is not used. Similarly, the number of read data lines Q wired in the memory block MBLK can be reduced to one-quarter compared to the case where the data conversion unit SPCNV is not used. As a result, power consumption during read operations can be reduced compared to the case where 512 bits of data signals are input and output to the memory block MBLK.

[0246] Compared to the case where the control line CMD, address line A, and write data line D are wired in common across multiple memory groups MG, and the control line CMD, address signal A, and write data signal D are supplied in common to each memory group MG, the charging and discharging currents of the control line CMD, address line A, and write data line D can be suppressed. As a result, power consumption during writing operations can be reduced while suppressing an increase in the access time of the memory circuit 100.

[0247] The memory group control unit MCNT is operated in synchronization with the memory clock signal MCLK, and the memory group MG is operated in synchronization with the memory clock signal MCLKxN, which is obtained by multiplying the memory clock signal MCLK by four. As a result, even when a 512-bit write data signal D is converted into four 128-bit write data signals D by the data conversion unit PSCNV and written to the memory unit MU, the same write rate can be achieved as when the 512-bit write data signal D is written to the memory unit MU in synchronization with the memory clock signal MCLK.

[0248] Furthermore, even when four 128-bit read data signals Q read from the memory unit MU are converted into 512-bit read data signals Q by the data conversion unit SPCNV, the same read rate can be achieved as when the 512-bit read data signals Q are read from the memory unit MU in synchronization with the memory clock signal MCLK. As a result, the dynamic power of the memory circuit can be reduced by reducing the charging and discharging current of the data lines without reducing access efficiency.

[0249] Furthermore, in the second embodiment, by folding the rows of memory group control units MCNT and memory units MU, the input-side memory control unit 200 and the output-side memory control unit 200 can be combined into a single unit. As a result, for example, even when the storage capacity is doubled compared to the memory circuit 100 in Figure 1, the memory circuit 102 can be laid out compactly.

[0250] Figure 38 shows an example of the configuration of a system 300 in which the memory circuit 100 of Figure 1 is installed. Note that the system 300 may also be equipped with the memory circuit 102 shown in Figure 37 instead of the memory circuit 100. For example, system 300 could be a head-mounted device such as AR / VR glasses capable of processing moving images, a digital camera, or a game console. System 300 could also be an image processing system installed in a vehicle. Furthermore, the system in which the memory circuit 100 is installed is not limited to the configuration of system 300.

[0251] The system 300 includes a controller 310, an imaging device 320, a display device 330, and an external memory 340. The controller 310 includes a CPU 311, an image processing unit 312, a display processing unit 313, an encoder / decoder 314, an external memory control unit 315, and the memory circuit 100 shown in Figure 1, all interconnected via a system bus SBUS. For example, the controller 310 may be designed as a system LSI.

[0252] The CPU 311 controls the entire system 300. The image processing unit 312 processes the image data acquired by the imaging device 320, converts the processed image data into frame image data that can be displayed on the display device 330, and stores the frame image data in the memory circuit 100. The display processing unit 313 reads the frame image data from the memory circuit 100 and displays the image on the display device 330. The encoder / decoder 314 encodes the image data before it is stored in the memory circuit 100 and decodes the compressed image data read from the memory circuit 100. The external memory control unit 315 controls access to external memory 340 such as DRAM (Dynamic Random Access Memory).

[0253] For example, the resolution of the video images handled by system 300 may be VGA (Video Graphics Array), Full HD, or 4K. The memory circuit 100 of system 300 is equipped with a number of memory groups MG (not shown) corresponding to the resolution of the video images. As described above, even if the number of memory groups MG increases or decreases, the clock cycle required for signal transfer between memory group control units MCNT remains unchanged, making timing design easier and suppressing increases in access time.

[0254] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application. [Explanation of Symbols]

[0255] 100, 102, 110 memory circuits 200 Memory Control Unit 202 System Bus Input Control Unit 204, 206 buffers 208 Peripheral Bus Control Unit 210 General Management Department 212 Memory State Management Unit 214 Input Interface Control Unit 220 Output Interface Control Unit 222, 224 Buffer 226 System Bus Output Control Unit 300 System 310 Controller 311 CPU 312 Image Processing Unit 313 Display Processing Unit 314 Encoder / Decoder 315 External Memory Control Unit 320 Imaging Device 330 Display Device 340 External Memory A Address Signal ACT Active Mode ARY Memory Cell Array ATRNS Active Transition Mode BL, BLB Bit Line Pair BUF, BUF1, BUF2, BUF3 Buffer CMD Control Signal CNTL Control Signal COL_R Column Read Signal COL_W Column Write Signal D Write Data Signal D-FF Flip-Flop Circuit I / O Data Input / Output Circuit MBLK, MBLK120 Memory Block MC Memory Cell MCLK, MCLKxN Memory Clock Signal MCLK_EN Clock Enable Signal MCNT Memory Group Control Unit MEM, MEMb Memory MG, MGb Memory Group MSKC, MSKR, MSKW1, MSKW2 Mask Circuit MU, MUb Memory Unit MEMCNT Memory Array Control Circuit<> MUX Multiplexer PRE (Pre-charge circuit) Q Readout data signal RCNT Relay Control Unit RD readout data signal RDEC Raw Decoder RLT Lead Latch RSW Reed Switch SA Sense Amplifier SBUS System Bus SCLK System Clock Signal SD Shutdown Mode SEL, SELQ selector SLP Sleep Mode SubMEM Submemory WBUF (Write Buffer) WD, WDD write data signal WL Word Line WLT Light Latch WSEL Light Selector

Claims

1. Multiple memory groups, each containing multiple memory cells, and performing write or read operations in response to request signals, A plurality of memory group control units are provided corresponding to each of the plurality of memory groups, A first memory control unit that outputs a request signal received from an external source to an adjacent memory group control unit, The system includes a first data conversion unit that divides a first write data signal received from the first memory control unit into n (where n is an integer of 2 or more) second write data signals, and sequentially outputs the second write data signals to the adjacent memory group control units. The plurality of memory group control units, if the write address signal included in the request signal received from the first memory control unit or the preceding memory group control unit indicates a corresponding memory group, sequentially write the n second write data signals, which are divided into one of the memories in the corresponding memory group, to the memory in the same memory group; if the write address signal does not indicate a corresponding memory group, transfer the request signal and the n second write data signals to the subsequent memory group control unit. Memory circuit.

2. Each of the plurality of memory groups has a write data line that sequentially transfers the write data signal via the memory group control unit in the subsequent stage. The transfer of the aforementioned write data signal to the write data line of a memory group downstream of the memory group to which the write data signal is written is masked. The memory circuit according to claim 1.

3. A second data conversion unit integrates n first read data signals, which are sequentially read from one of the memory units in any of the plurality of memory groups via at least one memory group control unit, into a second read data signal. It comprises a second memory control unit that outputs the second read data signal integrated by the second data conversion unit, The plurality of memory group control units, if the read address signal included in the request signal received from the first memory control unit or the preceding memory group control unit indicates a corresponding memory group, sequentially read the data held in one of the memories in the corresponding memory group; if the read address signal does not indicate a corresponding memory group, forward the request signal to the subsequent memory group control unit. The memory circuit according to claim 1 or claim 2.

4. Each of the plurality of memory groups has a read data line that sequentially transfers the read data signal via the subsequent memory group control unit. The read data lines of the memory group preceding the memory group that reads the aforementioned read data signal do not transmit the aforementioned read data signal. The memory circuit according to claim 3.

5. In each of the aforementioned plurality of memory groups, The number of data terminals that receive the second write data signal is 1 / n of the number of data terminals in the first memory control unit that outputs the first write data signal. The number of data terminals that output the first read data signal is 1 / n of the number of data terminals in the second memory control unit that receive the second read data signal. The memory circuit according to claim 3.

6. Each of the aforementioned plurality of memories is m memory cells connected to multiple word lines, m pairs of bit lines are connected to each of the m rows of the memory cells arranged in a second direction that intersects the first direction in which the word line extends, m pre-charge circuits and m sense amplifiers are connected to each of the m pairs of bit lines, Each of the m sense amplifiers is sequentially connected to m reed latches and m reed switches, Each of the m bit line pairs is connected to the precharge circuit, the sense amplifier, the reed latch, and the reed switch. Furthermore, it has m / n buffers connected to each of the n reed switches. The memory circuit according to claim 3.

7. Each of the plurality of memories has a memory array control circuit, The memory array control circuit is In response to the read address signal included in the request signal, one of n column read signals is generated for selecting m / n of the read switches. The memory circuit according to claim 6.

8. The aforementioned single memory is In response to a single request signal and a read address signal, one of the plurality of word lines is selected, data is read from the m memory cells connected to the selected word line and stored in the m read latches. From the m data stored in the m read latches, m / n data points are sequentially read via the read switch in response to n column read signals, and the first read data signal containing m / n data points is output n times. The memory circuit according to claim 7.

9. Each of the aforementioned plurality of memories is m memory cells connected to multiple word lines, m pairs of bit lines are connected to each of the m rows of the memory cells arranged in a second direction that intersects the first direction in which the word line extends, m pre-charge circuits and m write buffers are connected to each of the m bit line pairs. Each of the m write buffers is sequentially connected to m write latches and m write selectors, The precharge circuit, the write buffer, the write latch, and the write selector are connected to each of the m bit line pairs BL and BLB. Furthermore, it has m / n flip-flop circuits connected to each of the n light selectors. The memory circuit according to claim 3.

10. Each of the plurality of memories has a memory array control circuit, The memory array control circuit is In accordance with the write address signal included in the request signal, one of the n column write signals for selecting m / n write selectors is generated. The memory circuit according to claim 9.

11. The aforementioned single memory is In response to a single request signal and a write address signal, m / n write selectors are sequentially selected using n column write signals, and the second write data signals containing m / n data are sequentially stored in m / n write latches. In accordance with the write address signal, one of the plurality of word lines is selected, and n second write data signals, each containing m data stored in m write latches, are written to the m memory cells connected to the selected word line. The memory circuit according to claim 10.

12. The plurality of memory groups each have a plurality of memory units, each containing the plurality of memories. Each of the aforementioned plurality of memories has a plurality of memory cells connected to a plurality of word lines, The aforementioned single memory is In accordance with the write address signal included in the request signal, one of the plurality of word lines is selected, and the n second write data signals are sequentially written to the plurality of memory cells connected to the selected word line. In accordance with the read address signal included in the request signal, one of the plurality of word lines is selected, and the n data is sequentially read from the plurality of memory cells connected to the selected word line. The memory circuit according to claim 3.

13. Each of the aforementioned plurality of memories is A plurality of bit line pairs are connected to each row of memory cells arranged in a second direction that intersects the first direction in which the word line extends, Multiple data latches connected to each of the aforementioned multiple bit line pairs, A data line through which the second write data signal or the first read data signal is transmitted, A data selection unit that connects the data line to one of the plurality of data latches according to the second write address signal or the first read address signal, The memory circuit according to claim 12.

14. Each of the plurality of memory units has a low-power mode in which it holds data but does not perform the write and read operations, and an active mode in which it can perform write or read operations. Each of the memory group control units corresponding to the plurality of memory groups sets the memory unit that performs the write operation or the read operation to active mode. The memory unit in which the write operation or read operation is not performed for a predetermined period of time is set to the low-power mode. The memory circuit according to claim 12.

15. The first memory control unit operates in synchronization with the first clock signal it receives, and outputs the first clock signal and a second clock signal obtained by multiplying the frequency of the first clock signal by n to the adjacent memory group control unit. Each of the plurality of memory group control units operates in synchronization with the first clock signal, Each of the aforementioned plurality of memory groups operates in synchronization with the second clock signal, The second memory control unit operates in synchronization with the first clock signal. The memory circuit according to claim 3.

16. The first data conversion unit receives the first write data signal from the first memory control unit in synchronization with the first clock signal, converts it into the n second write data signals in synchronization with the second clock signal, and outputs them sequentially to the adjacent memory group control units. Each of the plurality of memory group control units outputs the first clock signal received from the first memory control unit or the preceding memory group control unit to the subsequent memory group control unit or the second memory control unit, and outputs the second clock signal received from the first memory control unit or the preceding memory group control unit to the corresponding memory group and the subsequent memory group control unit. The second data conversion unit converts the n first read data signals, which are received sequentially in synchronization with the second clock signal, into second read data signals in synchronization with the first clock signal, and outputs them to the second memory control unit. The memory circuit according to claim 15.

17. The first memory control unit converts b a-bit third write data signals received sequentially from the outside into a first write data signal of a × b bits and outputs it to the first data conversion unit (where a is an integer of 1 or more, and b is an integer of 2 or more). The second memory control unit converts the a x b bit second read data signal received from the second data conversion unit into b a bit third read data signals and outputs them sequentially to the outside. The memory circuit according to claim 3.

18. The aforementioned multiple memories are SRAM. A memory circuit according to claim 1 or claim 2.

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