Wiring boards and mounting structures

The wiring board design addresses the issue of deteriorating electrical reliability by using an organic coating on the land conductor to enhance adhesion and plating, improving the connectivity and reliability of via hole conductors.

JP2026112600APending Publication Date: 2026-07-07KYOCERA CORP

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
KYOCERA CORP
Filing Date
2024-12-25
Publication Date
2026-07-07

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Abstract

The present invention provides a wiring board that improves the electrical reliability of via hole conductors without affecting the adhesion between the land conductor and the insulating layer. [Solution] The wiring board according to this disclosure includes a first insulating layer having a first surface, a conductor layer located on the first surface and including at least a land conductor, a second insulating layer located on the first surface and having a second surface on the opposite side of the first insulating layer, and including via holes penetrating from the second surface to the land conductor, and a via hole conductor located in the via hole and in contact with the land conductor. The land conductor includes a first region in contact with the via hole conductor and a second region other than the first region. An organic coating is located between the second region and the second insulating layer.
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Description

Technical Field

[0001] The present invention relates to a wiring board and a mounting structure using the same.

Background Art

[0002] As described in Patent Document 1, a wiring board has a structure in which an insulating layer and a conductor layer are alternately laminated. In order to electrically connect conductor layers located in different layers, a via hole conductor is located in a via hole provided in the insulating layer. The via hole conductor is usually connected to a land conductor included in the conductor layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Disclosure of the Invention

Problems to be Solved by the Invention

[0004] Conventionally, in order to reduce the deterioration of electrical characteristics due to the skin effect, an organic film is formed between the insulating layer and the conductor layer without roughening the wiring (or by reducing the degree of roughening) to improve the adhesion between the insulating layer and the conductor layer. Further, in the via hole portion, in order to strengthen the connection between the land conductor and the via hole conductor, a concave portion having a diameter larger than the diameter of the bottom of the via hole is provided in the land conductor, and by forming the via hole conductor, the connection between the land conductor and the via hole conductor is strengthened. The organic film formed at the bottom of the via hole is removed by the laser irradiated during the formation of the via hole. However, the organic film formed on the insulating layer protruding into the concave portion is not removed. It is difficult for plating to adhere to the organic film, and the gap around the insulating layer protruding into the concave portion is small. Therefore, the circulation of the plating solution is also poor, and it is difficult for the plating to grow. As a result, there is a problem that the electrical reliability of the via hole conductor in the wiring board deteriorates.

[0005] The object of this disclosure is to provide a wiring board that improves the electrical reliability of via hole conductors without affecting the adhesion between the land conductor and the insulating layer. [Means for solving the problem]

[0006] The wiring board according to this disclosure includes a first insulating layer having a first surface, a conductor layer located on the first surface and including at least a land conductor, a second insulating layer located on the first surface and having a second surface on the opposite side of the first insulating layer, and including via holes penetrating from the second surface to the land conductor, and a via hole conductor located in the via hole and in contact with the land conductor. The land conductor includes a first region in contact with the via hole conductor and a second region other than the first region. An organic coating is located between the second region and the second insulating layer.

[0007] The implementation structure relating to this disclosure includes the above-mentioned wiring board and electronic components connected to the wiring board. [Effects of the Invention]

[0008] The wiring board relating to this disclosure has the configuration described in the section on means for solving the problem, thereby improving the electrical reliability of via hole conductors without affecting the adhesion between the land conductor and the insulating layer. [Brief explanation of the drawing]

[0009] [Figure 1] This is an explanatory diagram illustrating a wiring board according to one embodiment of the present disclosure. [Figure 2] This is an enlarged diagram illustrating one embodiment of region X shown in Figure 1. [Figure 3] Figure 2 is an enlarged explanatory diagram illustrating one embodiment of region Y. [Modes for carrying out the invention]

[0010] A wiring board according to one embodiment of the present disclosure will be described with reference to Figures 1 to 3. Figure 1 is an explanatory diagram for illustrating a wiring board 10 according to one embodiment of the present disclosure. As shown in Figure 1, the wiring board 10 according to one embodiment includes a core insulating layer 1, a build-up insulating layer 2 (a first insulating layer 21 and a second insulating layer 22), a conductor layer 3 (a core conductor layer and a build-up conductor layer), and a solder resist 6.

[0011] The core insulating layer 1 is located approximately in the center of the wiring board 10 in the thickness direction. The core insulating layer 1 is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin, and glass. One of these insulating materials may be used, or two or more may be used in combination.

[0012] The thickness of the core insulating layer 1 is not particularly limited, and is, for example, between 40 μm and 2000 μm. The core insulating layer 1 is not an essential component, and for example, in a substrate referred to as a coreless substrate, the core insulating layer 1 is not used.

[0013] The core insulating layer 1 may contain a reinforcing material. Examples of reinforcing materials include insulating fabrics such as glass fibers, glass nonwoven fabrics, aramid nonwoven fabrics, aramid fibers, and polyester fibers. Only one type of reinforcing material may be used, or two or more types may be used in combination. Furthermore, the core insulating layer 1 may contain insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. Only one type of insulating filler may be used, or two or more types may be used in combination.

[0014] Core conductor layers are located on both sides of the core insulating layer 1. The core conductor layers are conductor layers 3 located on both sides of the core insulating layer 1. The core conductor layers are not limited as long as they are made of a conductive material. Examples of conductive materials include metals such as copper. The thickness of the core conductor layers is not limited, for example, 1 μm or more and 30 μm or less. In Figure 1, although the core conductor layers are located on both sides of the core insulating layer 1, it is sufficient for them to be located on at least one side of the core insulating layer 1.

[0015] As shown in Figure 1, the core insulating layer 1 has a through-hole conductor 3a located therein to electrically connect the upper and lower surfaces of the core insulating layer 1. The through-hole conductor 3a is located within a through-hole 11 that penetrates from the upper surface to the lower surface of the core insulating layer 1. The through-hole conductor 3a contains a metal such as copper. The through-hole conductor 3a is connected to the core conductor layer formed on both sides of the core insulating layer 1. The through-hole conductor 3a may be formed integrally with the core conductor layer. The through-hole conductor 3a may be located only on the inner wall surface of the through-hole 11, or it may be filled inside the through-hole 11.

[0016] As shown in Figure 1, build-up layers are located on both sides of the core layer, which includes the core insulating layer 1 and the core conductor layer. The build-up layer has a structure in which build-up insulating layers 2 and build-up conductor layers are alternately laminated. The build-up insulating layer 2 includes a first insulating layer 21 and a second insulating layer 22. The build-up conductor layer is a conductor layer 3 located on the surfaces of the first insulating layer 21 and the second insulating layer 22.

[0017] In Figure 1, the build-up layer has two build-up insulating layers 2. However, the build-up layer may have more than two build-up insulating layers 2. In this specification, when considering two adjacent layers of the build-up insulating layers 2, the layer closer to the core insulating layer 1 is defined as the "first insulating layer 21," and the layer further from the core insulating layer 1 is defined as the "second insulating layer 22."

[0018] The first insulating layer 21 has a first surface 2a. Among the surfaces of the first insulating layer 21, the first surface 2a is the surface farther from the core insulating layer 1. The second insulating layer 22 has a second surface 2b. Among the surfaces of the second insulating layer 22, the second surface 2b is the surface located on the opposite side of the first insulating layer 21. In the case of two adjacent layers of the core insulating layer 1 and the build-up insulating layer 2, the core insulating layer 1 may be regarded as the "first insulating layer 21".

[0019] The build-up insulating layer 2 is not particularly limited as long as it is a material having insulation properties. Examples of the material having insulation properties include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. These resins may be used alone or in combination of two or more. In FIG. 1, although the build-up layers are located on both sides of the core layer, they may be located on at least one surface of the core layer.

[0020] The build-up insulating layers 2 may be made of the same resin or different resins. The build-up insulating layer 2 and the core insulating layer 1 may be made of the same resin or different resins. The thickness of the build-up insulating layer 2 is not particularly limited, and is, for example, 10 μm or more and 100 μm or less. The build-up insulating layers 2 may have the same thickness or different thicknesses.

[0021] The build-up insulating layer 2 may contain a reinforcing material. Examples of the reinforcing material include insulating fabric materials such as glass fiber, glass non-woven fabric, aramid non-woven fabric, aramid fiber, and polyester fiber. The reinforcing material may be used alone or in combination of two or more. Further, the build-up insulating layer 2 may contain insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. The insulating fillers may be used alone or in combination of two or more.

[0022] On the surface of the build-up insulating layer 2, a build-up conductor layer is located. The build-up conductor layer is the conductor layer 3 located on the surface of the build-up insulating layer 2. The build-up conductor layer is not particularly limited as long as it is a material having conductivity. Examples of the material having conductivity include metals such as copper. The thickness of the build-up conductor layer is not limited, and is, for example, 1 μm or more and 40 μm or less.

[0023] The build-up conductor layers may be the same metal or different metals. The build-up conductor layer and the core conductor layer may be the same metal or different metals. Further, the build-up conductor layers may have the same thickness or different thicknesses.

[0024] In the build-up insulating layer 2, via hole conductors 4 for electrically connecting the upper and lower surfaces of the build-up insulating layer 2 are located. Specifically, when paying attention to two adjacent layers of the build-up insulating layer 2, the via hole conductor 4 is located in a via hole 23 that penetrates from the second surface 2b of the second insulating layer 22 to the land conductor 5 located on the first surface 2a of the first insulating layer 21. The land conductor 5 and the via hole conductor 4 are part of the conductor layer 3.

[0025] As shown in FIG. 1, a solder resist 6 may be located on the surface of the build-up layer. The solder resist 6 is formed of a resin, and examples of the resin include acrylic-modified epoxy resin. An opening is provided in the solder resist 6 for electrically connecting the conductor layer 3 and the electrode of the electronic component E via solder S. Examples of the electronic component E include semiconductor integrated circuit elements and optoelectronic elements.

[0026] As shown in Figure 2, the via-hole conductor 4 may include, for example, a first conductor layer 41 and a second conductor layer 42. Figure 2 is an enlarged explanatory diagram illustrating one embodiment of region X shown in Figure 1. The first conductor layer 41 functions, for example, as a base metal layer. The first conductor layer 41 is formed, for example, by sputtering and electroless plating. The first conductor layer 41 contains, for example, copper. The thickness of the first conductor layer 41 is not limited and may be, for example, 0.05 μm or more and 2.00 μm or less.

[0027] The second conductor layer 42 is the main part of the via-hole conductor 4. The second conductor layer 42 is formed by, for example, electroplating. The second conductor layer 42 contains, for example, copper.

[0028] As shown in Figure 2, the via hole conductor 4 is in contact with the land conductor 5. Specifically, the land conductor 5 includes a first region 51 and a second region 52 other than the first region 51. The first region 51 is the region in contact with the via hole conductor 4. The second region 52 is the region other than the first region 51, as described above, and is the region where the via hole conductor 4 is not located. In other words, the second region 52 is the region of the land conductor 5 that is not in contact with the via hole conductor 4 and the first insulating layer 21.

[0029] As shown in Figure 2, an organic coating 7 is located on the surface of the second region 52, that is, the portion where the land conductor 5 faces the second insulating layer 22. The organic coating 7 is not located in the first region 51. This structure provides excellent adhesion between the land conductor 5 and the second insulating layer 22, and makes the wiring board 10 electrically reliable between the via hole conductor 4 and the land conductor 5. The organic coating 7 is not limited. Examples of materials constituting the organic coating 7 include silane coupling agents.

[0030] Although the arithmetic mean roughness of the surface of the second region 52 is not limited, it is preferable to have a relatively small roughness from the viewpoint of electrical signal transmission. The surface of the second region 52 may have an arithmetic mean roughness of, for example, 100 nm or more and 200 nm or less.

[0031] The first region 51 of the land conductor 5 may have a recessed shape that is recessed toward the first surface 2a side of the first insulating layer 21, as shown in Figure 2. Having a recessed shape in the first region 51 is advantageous in that, for example, the contact area between the via hole conductor 4 and the land conductor 5 can be increased, thereby improving the connection strength between the two.

[0032] The conductor layer 3 may further have wiring conductors on its first surface 2a. Although the arithmetic mean roughness of the surface of the wiring conductor is not limited, it is preferable to have a relatively small roughness from the viewpoint of electrical signal transmission. The surface of the wiring conductor may have an arithmetic mean roughness of, for example, 100 nm or more and 200 nm or less.

[0033] Furthermore, the presence of the organic coating 7 improves the adhesion between the conductor layer 3 and the insulating layer. Therefore, the organic coating 7 may also be present on the surface of conductor layers 3 other than the second region 52 of the land conductor 5 (such as power supply conductors and ground conductors).

[0034] The arithmetic mean roughness of the side surface of the via hole conductor 4 is not limited. For example, the side surface of the via hole conductor 4 may have a greater arithmetic mean roughness than the surface of the second region 52. With such a configuration, the side surface of the via hole conductor 4, which is more susceptible to greater stress than the second region 52 of the land conductor 5 in the thickness direction of the wiring board 10, can adhere firmly to the second insulating layer 22. The side surface of the via hole conductor 4 may have an arithmetic mean roughness of, for example, 100 nm or more and 1000 nm or less. The roughness of the side surface of the via hole conductor 4 is measured and calculated, for example, by a white light interferometer.

[0035] As shown in Figure 2, the via hole conductor 4 may have a third region 53 at its peripheral edge on the land conductor 5 side, which is in contact with the second insulating layer 22 and located along the plane direction of the first surface 2a. If the third region 53 is present, the arithmetic mean roughness of the surface of the third region 53 is not limited. The arithmetic mean roughness of the surface of the third region 53 may be greater than, for example, the arithmetic mean roughness of the surface of the second region 52. The surface of the third region 53 refers to the surface in contact with the second insulating layer 22.

[0036] When the arithmetic mean roughness of the surface of the third region 53 is greater than the arithmetic mean roughness of the surface of the second region 52, for example, in the region including the boundary between the side surface of the via hole conductor 4 and the third region where stress tends to concentrate, the adhesion between the via hole conductor 4 and the second insulating layer 22 is further improved, and the transmission of electrical signals is improved because the arithmetic mean roughness of the surface of the second region 52, where stress does not tend to concentrate, is relatively small. As a result, a wiring board 10 with excellent adhesion between the via hole conductor 4 and the second insulating layer 22 and excellent transmission of electrical signals can be provided.

[0037] The thickness L of the organic coating 7 is not limited as long as it covers the surface of the second region 52. The organic coating 7 may have a thickness L of, for example, 10 nm or more and 100 nm or less. The organic coating 7 may have a uniform thickness L, or it may have a non-uniform thickness L as shown in Figure 3. Figure 3 is an enlarged explanatory diagram for illustrating one embodiment of region Y shown in Figure 2. The non-uniform thickness L of the organic coating 7 increases the surface area. As a result, the adhesion between the resin and the organic coating is improved. When the organic coating 7 has a non-uniform thickness L, it may have a non-uniform thickness L within the above range, and the difference between the thickest and thinnest parts may be, for example, 50 nm or less. The thickness L of the organic coating 7 can be defined, for example, on the upper surface of the land conductor 5, as the length from the land conductor 5 to the second insulating layer 22 in the thickness direction of the wiring board 10, and on the side surface of the land conductor 5, as the length from the land conductor 5 to the second insulating layer 22 in the plane direction of the first surface 2a.

[0038] As shown in Figure 3, when the second insulating layer 22 contains an insulating filler 8, some of the insulating filler 8 may be in contact with the organic coating 7. Although the insulating filler 8 does not adhere tightly to the organic coating 7, the adhesion between the organic coating 7 and the resin is excellent. Even if the insulating filler 8 and the organic coating 7 are in contact, it is only a point contact, so the adhesion between the organic coating 7 and the resin at points other than the contact point can mitigate the reduction in adhesion.

[0039] In the wiring board 10 according to one embodiment, the method for forming the land conductor 5 and via hole conductor 4 is not limited, and for example, they may be formed by the following procedure. First, a conductor layer 3 including the land conductor 5 is formed on the first surface 2a of the first insulating layer 21, for example, by a semi-additive method. The land conductor 5 and conductor layer 3 are as described above, and a detailed explanation is omitted.

[0040] Next, the surface of the land conductor 5 formed on the first surface 2a of the first insulating layer 21 is covered with an organic film 7. The organic film 7 is formed, for example, by the adsorption of a copper complex and coordination bonding with copper. As described above, a detailed explanation of the organic film 7 is omitted.

[0041] After the surface of the land conductor 5 is covered with an organic film 7, a second insulating layer 22 is formed so as to cover the surface of the first surface 2a and the organic film 7. The second insulating layer 22 is formed, for example, by arranging a resin film or the like, which is the raw material for the second insulating layer 22, under reduced pressure so as to cover the surface of the first surface 2a and the organic film 7, and then heating and pressurizing it.

[0042] Next, via holes 23 are formed in the second insulating layer 22. The method of forming the via holes 23 is not limited; for example, a laser can be used to form the via holes 23. The via holes are formed so as to penetrate from the second surface 2b of the second insulating layer 22 to the land conductor 5. By irradiating with a laser, the organic film 7 located in the first region 51 of the land conductor 5 is removed. Therefore, the land conductor 5 is exposed at the bottom of the via hole 23 instead of the organic film 7. Desmearing treatment may be performed to remove the smear generated during laser irradiation if necessary. Etching treatment may also be performed to smooth the surface of the first region 51. For example, such etching treatment creates a region at the periphery of the via hole conductor 4 on the land conductor 5 side where a third region 53 is located, which is in contact with the second insulating layer 22 and located along the plane direction of the first surface 2a. Furthermore, desmearing treatment may be performed again to remove the organic film 7 remaining on the second insulating layer 22 in the region where the third region 53 is located. The desmearing conditions at this time may be weaker than those used to remove the smear. The arithmetic mean roughness of the inner wall surface of the via hole 23 is approximately the same as the arithmetic mean roughness of the side surface of the via hole conductor 4.

[0043] Next, a first conductor layer 41 is formed on the inner wall surface of the via hole 23. The first conductor layer 41 is formed, for example, by electroless plating or sputtering. The first conductor layer 41 is as described above, and a detailed explanation is omitted.

[0044] Next, a second conductor layer 42 is formed on the surface of the first conductor layer 41. The second conductor layer 42 is formed, for example, by electroplating. The second conductor layer 42 is as described above, and a detailed explanation is omitted.

[0045] As shown in Figure 2, when forming the via hole conductor 4, the first conductor layer 41 and the second conductor layer 42 are also formed on the periphery of the opening of the via hole 23 on the second surface 2b, so that the conductor layer 3 (first conductor layer 41 and second conductor layer 42) located on the second surface 2b becomes the land conductor 5. This land conductor 5 located on the second surface 2b is considered to be the land located on the first surface 2a, and these steps are repeated a desired number of times.

[0046] Next, the mounting structure according to this disclosure will be described with reference to Figure 1. The mounting structure according to one embodiment includes a wiring board 10 according to one embodiment and an electronic component E located in the mounting area of ​​the wiring board 10.

[0047] Figure 1 shows a state in which the wiring board 10 and the electronic component E are not connected. By connecting the electronic component connection pad (part of the build-up conductor layer located on the surface of one build-up layer) exposed from an opening in the solder resist 6 located on one surface of the wiring board 10 to the electrodes of the electronic component E, for example via solder S, a mounting structure according to one embodiment can be obtained. Examples of electronic components E include semiconductor integrated circuit elements and optoelectronic elements. In the mounting structure according to one embodiment, electronic components E may also be connected via solder S to other pads exposed from openings in the solder resist 6 located on the other surface of the wiring board 10 (part of the build-up conductor layer located on the surface of the other build-up layer). Alternatively, a motherboard or the like may be connected via solder S to other pads of the wiring board 10.

[0048] The embodiments of this disclosure have been described above. However, the invention relating to this disclosure is not limited to the embodiments described above, and various modifications and improvements are possible within the scope of this disclosure as shown in (1) to (8) below.

[0049] (1) The wiring board according to the present disclosure includes a first insulating layer having a first surface, a conductor layer located on the first surface and including at least a land conductor, a second insulating layer located on the first surface and having a second surface on the opposite side of the first insulating layer, and including via holes penetrating from the second surface to the land conductor, and a via hole conductor located in the via hole and in contact with the land conductor. The land conductor includes a first region in contact with the via hole conductor and a second region other than the first region. An organic coating is located between the second region and the second insulating layer. (2) In the wiring board described in (1) above, the first region has a recessed shape that is recessed toward the first surface. (3) In the wiring board described in (1) or (2) above, the conductor layer further has a wiring conductor on the first surface, and the surface of the wiring conductor and the surface of the second region have an arithmetic mean roughness of 100 nm or more and 200 nm or less. (4) In the wiring board described in any of (1) to (3) above, the organic coating has an uneven thickness. (5) In the wiring board described in any of (1) to (4) above, the second insulating layer contains an insulating filler, and some of the insulating filler is in contact with the organic coating. (6) In the wiring board described in any of (1) to (5) above, the side surface of the via hole conductor has a greater arithmetic mean roughness than the surface of the second region. (7) In the wiring board described in any of (1) to (6) above, the via hole conductor has a third region at the peripheral edge on the land conductor side that is in contact with the second insulating layer and is located along the plane direction of the first surface, and the arithmetic mean roughness of the surface in contact with the second insulating layer of the third region is greater than the arithmetic mean roughness of the surface in contact with the organic coating of the second region. (8) The implementation structure relating to this disclosure includes a wiring board as described in any of (1) to (7) above, and an electronic component connected to the wiring board. [Explanation of Symbols]

[0050] 1. Insulating layer for core 11 Through Holes 2. Insulating layer for build-up 21 First insulating layer 22 Second insulating layer 23 Beer Hall 2a 1st page 2b 2nd side 3 Conductor layers 3a Through-hole conductor 4 via hole conductors 41. First Conductor Layer 42 Second Conductor Layer 5 Land conductor 51 First area 52 Second area 53 Third area 6 Solder Resist 7 Organic coating 8. Insulating filler 10 Wiring board S Handa E Electronic components

Claims

1. A first insulating layer having a first surface, Located on the first surface, a conductor layer including at least a land conductor, A second insulating layer located on the first surface and having a second surface on the opposite side of the first insulating layer, and including via holes penetrating from the second surface to the land conductor, A via hole conductor located in the via hole and in contact with the land conductor, Includes, The land conductor includes a first region that contacts the via hole conductor and a second region other than the first region. An organic coating is located between the second region and the second insulating layer. Wiring board.

2. The wiring board according to claim 1, wherein the first region has a recessed shape that is recessed toward the first surface side.

3. The wiring substrate according to claim 1, wherein the conductor layer further has a wiring conductor on the first surface, and the surface of the wiring conductor and the surface of the second region have an arithmetic mean roughness of 100 nm or more and 200 nm or less.

4. The wiring board according to claim 1, wherein the organic coating has a non-uniform thickness.

5. The wiring board according to claim 1, wherein the second insulating layer includes an insulating filler, and a portion of the insulating filler is in contact with the organic coating.

6. The wiring board according to claim 1, wherein the side surface of the via hole conductor has a greater arithmetic mean roughness than the surface of the second region.

7. The wiring board according to claim 1, wherein the via hole conductor has a third region at the peripheral edge on the land conductor side that is in contact with the second insulating layer and is located along the plane direction of the first surface, and the arithmetic mean roughness of the surface in contact with the second insulating layer of the third region is greater than the arithmetic mean roughness of the surface of the second region.

8. A mounting structure comprising a wiring board according to any one of claims 1 to 7 and an electronic component connected to the wiring board.