Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device that improves heat dissipation while suppressing the occurrence of cracks in the uppermost of multiple semiconductor chips. [Solution] The semiconductor device comprises a plurality of semiconductor chips and a molding resin. The plurality of semiconductor chips are stacked on top of each other. Each semiconductor chip has a bottom surface and an top surface located opposite the bottom surface. The top surface of the first semiconductor chip, which is located in the uppermost layer of the plurality of semiconductor chips, has, in a plan view, an outer peripheral region and a central region located inside the outer peripheral region. The molding resin covers at least the outer peripheral region and has through holes that expose at least partially the central region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] Japanese Patent Application Laid-Open No. 9-64236 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 includes a wiring board, an integrated circuit chip, an underfill, and an encapsulant. The wiring board has a first surface and a second surface located on the opposite side of the first surface. A plurality of terminal pads are formed on the second surface, and external terminals are formed on the terminal pads. The integrated circuit chip has a third surface and a fourth surface located on the opposite side of the third surface. The integrated circuit chip is disposed on the first surface such that the third surface faces the first surface. The fourth surface has an outer peripheral region and a central region located inside the outer peripheral region in a plan view. The underfill is filled between the wiring board and the integrated circuit chip. The encapsulant seals the wiring board and the integrated circuit chip. However, the encapsulant does not cover the central region of the fourth surface, and the external terminals are exposed from the encapsulant.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device described in Patent Document 1, when a plurality of integrated circuit chips are stacked, there is a risk that one of the integrated circuit chips located at the uppermost stage among the plurality of integrated circuit chips may crack. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0005] The semiconductor device of this disclosure comprises a plurality of semiconductor chips and a molding resin. The plurality of semiconductor chips are stacked. Each semiconductor chip has a bottom surface and an top surface located opposite the bottom surface. The top surface of the first semiconductor chip, which is located in the uppermost layer of the plurality of semiconductor chips, has, in a plan view, an outer peripheral region and a central region located inside the outer peripheral region. The molding resin has through holes that cover at least the outer peripheral region and expose at least partially the central region. [Effects of the Invention]

[0006] The semiconductor device described herein can improve heat dissipation while suppressing the occurrence of cracks in the uppermost of multiple semiconductor chips. [Brief explanation of the drawing]

[0007] [Figure 1] This is a plan view of semiconductor device DEV1. [Figure 2] This is a cross-sectional view of semiconductor device DEV1 in line II-II of Figure 1. [Figure 3] This is a plan view of a semiconductor chip (CHP). [Figure 4A] Figure 3 is a cross-sectional view of a semiconductor chip CHP in IVA-IVA. [Figure 4B] This is a magnified view of a portion of Figure 4A. [Figure 4C] This is a cross-sectional view of a semiconductor chip CHP near a through-hole via TSV. [Figure 5] This is a manufacturing process diagram for semiconductor device DEV1. [Figure 6] This is a cross-sectional view illustrating the chip stacking process S2. [Figure 7] This is a cross-sectional view illustrating the underfill filling process S3. [Figure 8] This is a cross-sectional view illustrating the resin molding process S4. [Figure 9] This is a cross-sectional view of semiconductor device DEV1A. [Figure 10]It is a cross-sectional view of the semiconductor device DEV1B. [Figure 11] It is a cross-sectional view for explaining an example of a method for forming the through-hole TH2. [Figure 12] It is a plan view of the semiconductor device DEV1 according to a modification. [Figure 13] It is a cross-sectional view of the semiconductor device DEV1 according to the modification in XIII-XIII of FIG. 12. [Figure 14] It is a cross-sectional view of the semiconductor device DEV2. [Figure 15] It is a cross-sectional view of the semiconductor device DEV3. [Figure 16] It is a cross-sectional view of the semiconductor device DEV4. [Figure 17] It is a cross-sectional view of the semiconductor device DEV5. [Figure 18] It is a bottom view of the semiconductor chip CHP in the semiconductor device DEV5. [Figure 19] It is a plan view of the semiconductor device DEV6. [Figure 20] It is a cross-sectional view of the semiconductor device DEV6 in XX-XX of FIG. 19.

Embodiments for Carrying Out the Invention

[0008] Details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First Embodiment) Hereinafter, the semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of the semiconductor device DEV1> As shown in FIGS. 1 and 2, the semiconductor device DEV1 includes a plurality of semiconductor chips CHP, an underfill UFL, and a mold resin MLD.

[0011] Multiple semiconductor chips (CHPs) are stacked along the thickness direction of the semiconductor device DEV1. The uppermost semiconductor chip CHP is designated as semiconductor chip CHP1. The lowermost semiconductor chip CHP is designated as semiconductor chip CHP2. The semiconductor chip CHP located between semiconductor chip CHP1 and semiconductor chip CHP2 is designated as semiconductor chip CHP3. In the examples shown in Figures 1 and 2, there are two semiconductor chip CHP3s, but the number of semiconductor chip CHP3s may be one or more. In a plan view, the area of ​​semiconductor chip CHP2 is larger than the area of ​​semiconductor chip CHP1 and semiconductor chip CHP2. The thickness of semiconductor chip CHP1 is larger than the thickness of semiconductor chip CHP1 and semiconductor chip CHP2.

[0012] As shown in Figures 3, 4A, and 4B, the semiconductor chip CHP has a semiconductor substrate SUB and a multilayer wiring layer MWL. Although not shown, the source and drain regions of the transistor are formed on the underside of the semiconductor substrate SUB. Also, although not shown, the gate insulating film of the transistor is formed on the channel region of the transistor located between the source and drain regions. The gate electrode of the transistor is formed on the gate insulating film. The semiconductor substrate SUB is made of, for example, single-crystal silicon.

[0013] A multilayer wiring layer (MWL) comprises multiple interlayer insulating films (ILDs), multiple wiring layers (WLs), and a passivation film (PV). The multiple interlayer insulating films (ILDs) are stacked on the underside of the semiconductor substrate (SUB). Each wiring layer (WL) is formed on one interlayer insulating film (ILD) and covered by another interlayer insulating film (ILD). However, the uppermost wiring layer (WL furthest from the semiconductor substrate (SUB)) is not covered by an interlayer insulating film (ILD). The interlayer insulating films (ILDs) are formed from materials such as silicon oxide, and the wiring layers (WLs) are formed from metallic materials such as aluminum or copper.

[0014] The uppermost wiring layer WL has pads PD1. The passivation film PV is formed on the uppermost interlayer insulating film ILD so as to cover the uppermost wiring layer WL. The passivation film PV has openings OP that partially expose the pads PD1.

[0015] The semiconductor chip CHP further has a bump BMP, which has a seed layer SD, a pillar PL, and a solder layer SLD. The seed layer SD is formed on the pad PD1 within the opening OP. The seed layer SD is also formed on the passivation film PV around the opening OP. The seed layer SD is, for example, a laminated film of a titanium layer and a copper layer formed on the titanium layer. The pillar PL is formed on the seed layer SD. The pillar PL is made of, for example, copper or a copper alloy. The solder layer SLD is formed on the pillar PL. The solder layer SLD is made of, for example, a tin alloy. However, the structure of the bump BMP is not limited to the structure shown in Figure 4B. For example, a metal layer made of nickel or the like may be interposed between the pillar PL and the solder layer SLD.

[0016] As shown in Figure 4C, through-hole vias (TSVs) are formed on the semiconductor chip CHP. However, through-hole vias (TSVs) are not formed on the semiconductor chip CHP1. A through-hole via (TSV) has a through-hole TH1, a metal layer ML1, and an insulating film IF.

[0017] The through-hole TH1 extends from the upper surface of the semiconductor substrate SUB to the multilayer wiring layer MWL. The insulating film IF is formed on the inner wall surface of the through-hole TH1. The insulating film IF is also formed on the lower surface of the semiconductor substrate SUB. Although not shown, the wiring layer WL is exposed from the through-hole TH1. The metal layer ML1 is formed inside the through-hole TH1. The metal layer ML1 is made of, for example, copper or a copper alloy. The insulating film IF is formed between the inner wall surface of the through-hole TH1 and the metal layer ML1. The insulating film IF is made of, for example, silicon oxide.

[0018] The semiconductor chip CHP further has pads PD2. Pads PD2 are formed on the upper surface of the semiconductor substrate SUB with an insulating film IF interposed therebetween. Pads PD2 are formed of, for example, copper or a copper alloy. Pads PD2 are electrically connected to through-hole vias TSV (metal layer ML1). The bumps BMP of the upper semiconductor chip CHP are connected to the pads PD2 of the lower semiconductor chip CHP, thereby stacking the two semiconductor chip CHPs.

[0019] Underfill UFL is filled between two adjacent semiconductor chips (CHPs). Additionally, underfill UFL is positioned on the top surface of semiconductor chip CHP2, covering the sides of semiconductor chip CHP1, semiconductor chip CHP2, and semiconductor chip CHP3.

[0020] The molded resin MLD covers the underfill UFL and multiple semiconductor chip CHPs. However, the underfill UFL may be exposed on the side of the semiconductor device DEV1. The upper surface of the semiconductor chip CHP1 has, in a plan view, an outer peripheral region PER and a central region CER located inside the outer peripheral region PER. The molded resin MLD covers the upper surface of the semiconductor chip CHP1. The molded resin MLD only needs to cover the outer peripheral region PER at a minimum. If the thickness of the semiconductor chip CHP1 is T, the width of the outer peripheral region PER is, for example, 1.6 × T + 0.35 mm or more.

[0021] Multiple through-holes TH2 are formed in the MLD (molding resin) portion covering the upper surface of the semiconductor chip CHP1. These through-holes TH2 penetrate the MLD, exposing the central region CER (central area). In a plan view, the multiple through-holes TH2 are arranged, for example, in a grid pattern.

[0022] Mold resin (MLD) contains fillers, which are made of materials such as silicone. Underfill (UFL), on the other hand, does not contain fillers. Therefore, the thermal expansion coefficient of mold resin (MLD) is smaller than that of underfill (UFL).

[0023] <Manufacturing method for semiconductor device DEV1> As shown in Figure 5, the manufacturing method of the semiconductor device DEV1 includes a preparation step S1, a chip stacking step S2, an underfill filling step S3, a resin molding step S4, and a piece formation step S5.

[0024] In preparation step S1, a semiconductor chip CHP is prepared. Firstly, in preparation step S1, a semiconductor wafer is prepared. The semiconductor wafer contains multiple semiconductor chip CHPs. The structure of the semiconductor chip CHPs contained in the semiconductor wafer is the same as the structure of the semiconductor chip CHPs in semiconductor device DEV1, except that they are not individualized, through-hole vias TSV are not formed, pads PD2 are not formed, and the semiconductor substrate SUB is thicker. Secondly, a glass carrier is attached to the underside of the semiconductor wafer. This protects the bump BMP and reinforces the semiconductor wafer.

[0025] Thirdly, the semiconductor substrate SUB is polished on its upper surface. This reduces the thickness of the semiconductor substrate SUB. Fourthly, a through-hole via TSV is formed. When forming the through-hole via TSV, firstly, through-holes TH1 are formed in the semiconductor substrate SUB and the multilayer wiring layer MWL by etching. Next, an insulating film IF is formed on the inner wall surface of the through-hole TH1, on the bottom surface of the through-hole TH1, and on the upper surface of the semiconductor chip CHP, for example by CVD (Chemical Vapor Deposition). Next, the insulating film IF located on the bottom surface of the through-hole TH1 is removed by anisotropic etching. This exposes the wiring layer WL from the through-hole TH1. Next, a seed layer is formed on the insulating film IF and on the wiring layer WL exposed from the through-hole TH1, for example by sputtering. Next, an electroplated layer grows on the seed layer by performing electroplating using the seed layer. Finally, the electroplated layer and seed layer that protrude from the through-hole TH1 are removed by CMP (Chemical Mechanical Polishing), for example, leaving a metal layer ML1.

[0026] Fifth, a pad PD2 is formed on the insulating film IF. When forming the pad PD2, first, a seed layer is formed on the insulating film IF. Next, a resist pattern is formed on the seed layer. Next, the pad PD2 is grown on the seed layer exposed from the resist pattern by electroplating. Next, the seed layer that was under the resist pattern is removed by etching. Sixth, the semiconductor wafer is divided into multiple semiconductor chips CHP by dicing along the boundaries of the semiconductor chip CHP. Note that when preparing semiconductor chip CHP1, the process of forming through-hole vias TSV and pad PD2 is not performed. When preparing semiconductor chip CHP2, the semiconductor wafer is not diced.

[0027] As shown in Figure 6, in the chip stacking process S2, semiconductor chips CHP1 and CHP3 are stacked on top of semiconductor chip CHP2, and the bump BMP of the upper semiconductor chip CHP is connected to the pad PD2 of the lower semiconductor chip CHP. As shown in Figure 7, in the underfill filling process S3, underfill UFL is filled between two adjacent semiconductor chips CHP. In the underfill filling process S3, firstly, uncured underfill UFL is poured between two adjacent semiconductor chips CHP. Secondly, heating is performed, causing the uncured underfill UFL to harden.

[0028] As shown in Figure 8, in the resin molding process S4, multiple semiconductor chips CHP and underfill UFL are covered with mold resin MLD, for example by the transfer molding method. Protrusions are formed on the inner surface of the mold used at this time. When the protrusions contact the upper surface of the semiconductor chip CHP1, through holes TH2 are formed in the portion of the mold resin MLD located on the upper surface of the semiconductor chip CHP1. In the dicing process S5, the semiconductor wafer containing the semiconductor chip CHP3, the underfill UFL and the mold resin MLD are diced along the boundary of the semiconductor chip CHP3. As a result, a semiconductor device DEV1 with the structure shown in Figures 1 and 2 is obtained.

[0029] <Effects of Semiconductor Device DEV1> As shown in Figure 9, in the comparative example semiconductor device DEV1A, the portion of the molded resin MLD located on the upper surface of the semiconductor chip CHP1 has been completely removed by polishing. From another perspective, this means that the outer peripheral region PER is not covered by the molded resin MLD. If the portion of the molded resin MLD located on the upper surface of the semiconductor chip CHP1 is completely removed in order to ensure the heat dissipation of semiconductor device DEV1A, stress will concentrate in the outer peripheral region PER, causing cracks to form in the outer peripheral region PER. The occurrence of such cracks caused by stress concentration becomes more pronounced as the thickness of the semiconductor chip CHP1 increases.

[0030] The thickness of the semiconductor device DEV1 is pre-standardized. If the thickness of the semiconductor device DEV1 does not reach the standardized predetermined thickness, the thickness of the semiconductor chip CHP1 is increased to adjust the thickness of the semiconductor device DEV1 to meet the standard. Therefore, it is difficult to avoid the stress concentration described above by reducing the thickness of the semiconductor chip CHP1.

[0031] As shown in Figure 10, in the comparative example semiconductor device DEV1B, the upper surface of the semiconductor chip CHP1, including the outer peripheral region PER, is completely covered by the molding resin MLD. Therefore, in semiconductor device DEV1B, stress concentration in the outer peripheral region PER is mitigated. However, in semiconductor device DEV1B, the upper surface of the semiconductor chip CHP1 is completely covered by the molding resin MLD, and because the thermal conductivity of the molding resin MLD is low, heat dissipation becomes insufficient.

[0032] On the other hand, in semiconductor device DEV1, the mold resin MLD covers the outer peripheral region PER, thus mitigating the stress concentration described above. Furthermore, in semiconductor device DEV1, through holes TH2 are formed in the mold resin MLD, allowing heat generated by semiconductor device DEV1 to dissipate easily through the through holes TH2, thus improving heat dissipation. In this way, semiconductor device DEV1 ensures heat dissipation while suppressing stress concentration on the uppermost semiconductor chip CHP (semiconductor chip CHP1), and consequently, the occurrence of cracks.

[0033] To further improve heat dissipation, a heatsink may be mounted on the top surface of the molded resin (MLD). In this case, the heat dissipation paste used to mount the heatsink enters the through-hole TH2, promoting heat transfer between the semiconductor chip CHP1 and the heatsink, so it is not necessary to completely remove the molded resin (MLD) from the top surface of the semiconductor chip CHP1.

[0034] <Variation> In the above description, an example was explained in which a through-hole TH2 is formed by providing a protrusion on the inner surface of the mold and bringing the protrusion into contact with the upper surface of the semiconductor chip CHP1. However, the through-hole TH2 may be formed by other methods. For example, the through-hole TH2 may be formed by polishing the upper surface of the mold resin MLD and then irradiating the upper surface of the mold resin MLD with laser light.

[0035] Furthermore, as shown in Figure 11, a water-soluble film WSF may be placed on the semiconductor chip CHP1 before sealing the multiple semiconductor chips CHP and underfill UFL with the mold resin MLD. Then, the inner surface of the mold is brought into contact with the water-soluble film WSF and the MLD is used for sealing, thereby forming the through-hole TH2. The water-soluble film WSF is removed by washing with water after the formation of the through-hole TH2. In this case, processing to create protrusions on the mold or introducing equipment for laser processing becomes unnecessary, and the manufacturing cost of the semiconductor device DEV1 can be reduced. As shown in Figures 12 and 13, only one through-hole TH2 is formed in the semiconductor device DEV1. Thus, the number of through-holes TH2 does not need to be multiple.

[0036] (Second Embodiment) The semiconductor device DEV2 according to the second embodiment will be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0037] As shown in Figure 14, the semiconductor device DEV2 further has a metal layer ML2. The metal layer ML2 is formed on the upper surface of the semiconductor chip CHP1 within the through hole TH2. The metal layer ML2 is formed in the same manner as the pad PD2. The metal layer ML2 is made of a material with high thermal conductivity. For example, the metal layer ML2 is made of copper or a copper alloy. In the semiconductor device DEV2, the through hole TH2 is formed by bringing the inner surface of the mold into contact with the metal layer ML2 and sealing it with the molding resin MLD.

[0038] In semiconductor device DEV2, the metal layer ML2 is positioned within the through-hole TH2, allowing heat generated in DEV2 to dissipate more easily through the through-hole TH2. Therefore, heat dissipation is further improved in semiconductor device DEV2. In addition, semiconductor device DEV2 eliminates the need for processing such as creating protrusions in the mold or introducing equipment for laser processing to form the through-hole TH2, thus reducing the manufacturing cost of semiconductor device DEV2.

[0039] (Third embodiment) The semiconductor device DEV3 according to the third embodiment will be described. Here, the differences from the semiconductor device DEV2 will be mainly explained, and redundant explanations will not be repeated.

[0040] As shown in Figure 15, in semiconductor device DEV3, through-hole via TSVs are also formed on semiconductor chip CHP1. In addition, in semiconductor device DEV3, a metal layer ML3 is formed on the upper surface of semiconductor chip CHP2. Metal layer ML3 is made of a metal material with high thermal conductivity, such as copper or a copper alloy. In a plan view, metal layers ML2 and ML3 overlap each other. Metal layers ML2 and ML3 are connected by through-hole via TSVs of semiconductor chip CHP1 and semiconductor chip CHP3.

[0041] In semiconductor device DEV3, heat generated in semiconductor chips CHP2 and CHP3 is transferred to the metal layer ML2 via through-hole vias TSV and dissipated through through-holes TH2. Therefore, heat dissipation is further improved in semiconductor device DEV3.

[0042] (Fourth Embodiment) The semiconductor device DEV4 according to the fourth embodiment will now be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0043] As shown in Figure 16, the semiconductor device DEV4 further includes a wiring board PSUB. In the semiconductor device DEV4, multiple semiconductor chips CHP are mounted on the wiring board PSUB. In the semiconductor device DEV4, underfill UFL is filled between two of the multiple semiconductor chips CHP. In addition, in the semiconductor device DEV4, underfill UFL1 is filled between the semiconductor chip CHP2 and the wiring board PSUB and is also positioned on the wiring board PSUB so as to cover the sides of the semiconductor chip CHP2. In the semiconductor device DEV4, mold resin MLD covers the underfill UFL and the multiple semiconductor chips CHP.

[0044] When multiple semiconductor chips (CHPs) are mounted on a wiring substrate (PSUB), the semiconductor device DEV4 is prone to warping due to the difference in thermal expansion coefficients between the PSUB and the CHPs. However, in the semiconductor device DEV4, an underfill UFL and a molded resin (MLD) covering the multiple CHPs are placed on the PSUB. Furthermore, the difference between the thermal expansion coefficient of the molded resin (MLD) and the PSUB is smaller than the difference between the thermal expansion coefficient of the PSUB and the CHPs. Therefore, the semiconductor device DEV4 can suppress warping caused by the difference in thermal expansion coefficients between the PSUB and the CHPs.

[0045] (Fifth embodiment) The semiconductor device DEV5 according to the fifth embodiment will be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0046] As shown in Figures 17 and 18, in semiconductor device DEV5, semiconductor chips CHP1 and CHP3, excluding semiconductor chip CHP2, have multiple dummy bump DBMPs. The structure of the dummy bump DBMPs is similar to that of the bump BMPs. However, while the bump BMPs are electrically connected to the circuits of the semiconductor chip CHPs, the dummy bump DBMPs are not electrically connected to the circuits of the semiconductor chip CHPs.

[0047] Multiple bump BMPs are arranged, for example, in a grid pattern in a plan view. Multiple dummy bump DBMPs are positioned outside of the multiple bump BMPs in a plan view. Multiple dummy bump DBMPs are arranged, for example, along the outer edge of the underside of the semiconductor chip CHP. In semiconductor device DEV4, the upper semiconductor chip CHP is connected to the lower semiconductor chip CHP by both bump BMPs and dummy bump DBMPs.

[0048] In semiconductor device DEV5, the upper semiconductor chip CHP is connected to the lower semiconductor chip CHP by both the bump BMP and the dummy bump DBMP. Therefore, the deformation of semiconductor chip CHP1 is restricted by the semiconductor chip CHP located below it. As a result, with semiconductor device DEV5, stress concentration in the outer peripheral region PER is further reduced, and consequently, cracking of semiconductor chip CHP1 can be further suppressed. In addition, in semiconductor device DEV5, heat generated in the semiconductor chip CHP located below it is transferred to semiconductor chip CHP1 via the dummy bump DBMP. Therefore, heat generated in the semiconductor chip CHP located below it is more easily dissipated through the through-hole TH2, further improving heat dissipation.

[0049] (Sixth Embodiment) The semiconductor device DEV6 according to the sixth embodiment will now be described. Here, we will mainly explain the differences from the semiconductor device DEV1, and will avoid repeating redundant explanations.

[0050] As shown in Figures 19 and 20, in the semiconductor device DEV6, the multiple through-holes TH2 include through-holes TH2a and through-holes TH2b. The opening area of ​​through-hole TH2a is different from the opening area of ​​through-hole TH2b. For example, the opening area of ​​through-hole TH2a is larger than the opening area of ​​through-hole TH2b.

[0051] One of the multiple semiconductor chips (CHP) generates more heat at the location where it overlaps with the through-hole TH2a in a plan view than at the location where it overlaps with the through-hole TH2b in a plan view. For example, semiconductor chip CHP2 has interface circuits for the CPU (Central Processing Unit) and DDR (Double Data Rate) memory at the location where it overlaps with the through-hole TH2a in a plan view, and circuits that generate less heat at the location where it overlaps with the through-hole TH2b in a plan view.

[0052] When the total opening area of ​​the through-holes TH2 is large, heat is dissipated more easily from the through-holes TH2 compared to when the total opening area of ​​the through-holes TH2 is small. On the other hand, when the total opening area of ​​the through-holes TH2 is large, cracks are more likely to occur in the semiconductor chip CHP1 compared to when the total opening area of ​​the through-holes TH2 is small. In semiconductor device DEV6, by increasing the opening area of ​​the through-holes TH2 at locations that overlap with circuits that generate a lot of heat in a plan view, and decreasing the opening area of ​​the through-holes at locations that overlap with circuits that do not generate a lot of heat in a plan view, heat dissipation can be further improved without excessively increasing the total opening area of ​​the through-holes TH2, that is, while suppressing the occurrence of cracks in the semiconductor chip CHP1.

[0053] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0054] BMP bump, CER central region, CHP semiconductor chip, CHP1, CHP2, CHP3 semiconductor chip, DBMP dummy bump, DEV1, DEV1A, DEV1B, DEV2, DEV3, DEV4, DEV5, DEV6 semiconductor device, IF insulating film, ILD interlayer insulating film, ML1, ML2, ML3 metal layer, MLD mold resin, MWL multilayer wiring layer, OP opening, PD1, PD2 pad, PER outer region, PL pillar, PSUB wiring substrate, PV passivation film, S1 preparation process, S2 chip stacking process, S3 underfill filling process, S4 resin molding process, S5 piece formation process, SD seed layer, SLD solder layer, SUB semiconductor substrate, TH1, TH2, TH2a, TH2b through-hole, TSV through-hole via, UFL, UFL1 underfill, WL wiring layer, WSF Water-soluble film.

Claims

1. Multiple semiconductor chips, Equipped with mold resin, The aforementioned multiple semiconductor chips are stacked on top of each other. Each of the aforementioned semiconductor chips has a bottom surface and an upper surface located opposite the bottom surface. The upper surface of the first semiconductor chip located at the top of the plurality of semiconductor chips has, in a plan view, an outer peripheral region and a central region located inside the outer peripheral region. A semiconductor device wherein the mold resin covers at least the outer peripheral region and has through holes that at least partially expose the central region.

2. Further comprising a first metal layer, The semiconductor device according to claim 1, wherein the first metal layer is formed on the upper surface of the first semiconductor chip within the through hole.

3. The system further comprises a second metal layer formed on the upper surface of the second semiconductor chip located at the bottom of the plurality of semiconductor chips, The semiconductor device according to claim 2, wherein each of the plurality of semiconductor chips located above the second semiconductor chip has a through-hole via formed therein to connect the first metal layer and the second metal layer.

4. The semiconductor device according to claim 1, wherein, if the thickness of the first semiconductor chip is T, the width of the outer peripheral region is 1.6 × T + 0.35 mm or more.

5. Further equipped with a wiring board, The plurality of semiconductor chips are arranged on the wiring substrate, The semiconductor device according to claim 1, wherein the molding resin is arranged on the wiring substrate so as to cover the plurality of semiconductor chips.

6. Each of the plurality of semiconductor chips located above the second semiconductor chip, which is located at the bottom of the plurality of semiconductor chips, has a plurality of bumps formed on its lower surface and a plurality of dummy bumps. Two of the aforementioned plurality of semiconductor chips are connected by the plurality of bumps and the plurality of dummy bumps, The semiconductor device according to claim 1, wherein the plurality of dummy bumps are located outward from the plurality of bumps in a plan view.

7. The mold resin has a first through hole and a second through hole as the through hole. The semiconductor device according to claim 1, wherein the opening area of ​​the first through hole is different from the opening area of ​​the second through hole.

8. The opening area of ​​the first through hole is larger than the opening area of ​​the second through hole. The semiconductor device according to claim 7, wherein one of the plurality of semiconductor chips generates more heat at a position that overlaps with the first through-hole in a plan view than at a position that overlaps with the second through-hole in a plan view.

9. The plurality of semiconductor chips further comprises underfill filling between two adjacent chips, The mold resin covers the plurality of semiconductor chips and the underfill, The semiconductor device according to claim 1, wherein the thermal expansion coefficient of the mold resin is smaller than the thermal expansion coefficient of the underfill.

10. The semiconductor device according to claim 1, wherein the molding resin contains a filler.

11. The semiconductor device according to claim 1, wherein the thickness of the first semiconductor chip is greater than the thickness of each of the plurality of semiconductor chips located below the first semiconductor chip.

12. The process of stacking multiple semiconductor chips, The process includes a step of sealing the plurality of semiconductor chips with a molding resin, The upper surface of the first semiconductor chip, which is located at the top of the plurality of semiconductor chips, has, in a plan view, an outer peripheral region and a central region located inside the outer peripheral region. A method for manufacturing a semiconductor device, wherein the mold resin has through holes that cover at least the outer peripheral region and expose at least a portion of the central region.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the through-hole is formed by bringing a plurality of protrusions formed on the inner surface of the mold into contact with the upper surface when sealing the plurality of semiconductor chips with the mold resin.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the through-holes are formed by attaching a water-soluble film to the upper surface before sealing the plurality of semiconductor chips with the molding resin, and then washing with water to remove the water-soluble film after sealing the plurality of semiconductor chips with the molding resin.

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