Electronic components

Abstract

To provide an electronic component that can suppress the effects of the wire ghosting phenomenon. [Solution] The electronic component comprises a substrate, a first semiconductor substrate disposed on the substrate and having a first region for detecting light and a second region outside the first region, a second semiconductor substrate disposed on the first semiconductor substrate and bonded to the first semiconductor substrate, an optical member that transmits light and faces the first and second semiconductor substrates via a hollow portion, a plurality of first electrodes disposed in the second region, a plurality of second electrodes disposed in a region on the substrate outside the region where the first semiconductor substrate is disposed, and a conductive wire connecting the first electrode and the second electrode, wherein the second semiconductor substrate is disposed between the first region and the first electrode, and when the maximum height from the surface of the first semiconductor substrate on which the first electrode of the conductive wire is disposed is h1 and the height of the second semiconductor substrate is h2,

Description

Technical Field

[0001] The present invention relates to electronic components.

Background Art

[0002] Patent Document 1 discloses a semiconductor device in which a second semiconductor chip is disposed on a first chip on which a photoelectric conversion unit is formed, and a flare prevention plate for blocking light is provided on the second semiconductor chip.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an electronic component including an imaging device, a semiconductor substrate including the imaging device and the substrate are electrically connected by wire bonding. In such a configuration, in the technique described in Patent Document 1, it has been difficult to suppress a wire ghost phenomenon in which light incident from the outside and hitting the wire is reflected and incident on the imaging device and appears in an image captured by the imaging device.

[0005] An object of the present invention is to provide an electronic component capable of suppressing the influence of the wire ghost phenomenon.

Means for Solving the Problems

[0006] According to one aspect of the present invention, there is provided an electronic component including a substrate, a first semiconductor substrate disposed on the substrate and having a first region for detecting light and a second region outside the first region, a second semiconductor substrate disposed on the first semiconductor substrate and joined to the first semiconductor substrate, an optical member facing the first semiconductor substrate and the second semiconductor substrate through a hollow portion and transmitting the light, a plurality of first electrodes disposed in the second region, a plurality of second electrodes disposed in a region outside the region where the first semiconductor substrate is disposed on the substrate, and a conductive wire connecting the first electrodes and the second electrodes. The second semiconductor substrate is disposed between the first region and the first electrodes. When the maximum height from the surface of the first semiconductor substrate where the first electrodes of the conductive wire are disposed is h1 and the height of the second semiconductor substrate is h2, h1 < h2.

[0007] According to another aspect of the present invention, there is provided an electronic component including a substrate, a first semiconductor substrate disposed on the substrate and having a first region for detecting light and a second region outside the first region, a second semiconductor substrate disposed on the first semiconductor substrate and joined to the first semiconductor substrate, an optical member transmitting the light, a plurality of first electrodes disposed in the second region, a plurality of second electrodes disposed in a region outside the region where the first semiconductor substrate is disposed on the substrate, and a conductive wire connecting the first electrodes and the second electrodes. The second semiconductor substrate is disposed between the first region and the first electrodes, and the optical member is joined to the second semiconductor substrate through a second joining member so as to cover at least the first region.

Advantages of the Invention

[0008] According to the present invention, the influence of the wire ghost phenomenon in the electronic component can be suppressed.

Brief Description of the Drawings

[0009] [Figure 1] It is a cross-sectional view showing an electronic component according to the first embodiment. [Figure 2] It is a plan view showing an electronic component according to the first embodiment. [Figure 3] This is a cross-sectional view illustrating the wire ghosting phenomenon. [Figure 4] This is a cross-sectional view showing an electronic component according to the first embodiment. [Figure 5] This is a cross-sectional view illustrating an electronic component and wire ghosting phenomenon according to the first embodiment. [Figure 6] A cross-sectional view illustrating an electronic component and wire ghosting phenomenon according to the first embodiment. [Figure 7] This is a plan view showing an electronic component according to the first embodiment. [Figure 8] This is a plan view showing an electronic component according to the first embodiment. [Figure 9] This is a plan view showing an electronic component according to the first embodiment. [Figure 10] This is a plan view showing an electronic component according to the second embodiment. [Figure 11] This is a cross-sectional view showing an electronic component according to the second embodiment. [Figure 12] This is an enlarged cross-sectional view showing an electronic component according to the second embodiment. [Figure 13] This is a cross-sectional view showing an electronic component according to the third embodiment. [Figure 14] This is a plan view showing an electronic component according to the third embodiment. [Figure 15] This is a cross-sectional view illustrating an electronic component and wire ghosting phenomenon according to a third embodiment. [Figure 16] This is a plan view showing an electronic component according to the third embodiment. [Figure 17] This is a plan view showing an electronic component according to the third embodiment. [Figure 18] This is a plan view showing an electronic component according to the third embodiment. [Figure 19] This is a plan view showing an electronic component according to the third embodiment. [Figure 20] This is a cross-sectional view showing an electronic component according to the third embodiment. [Figure 21] This is an enlarged cross-sectional view showing an electronic component according to the third embodiment. [Figure 22]It is a cross-sectional view showing an electronic component according to the third embodiment. [Figure 23] It is a block diagram showing a schematic configuration of a photoelectric conversion system according to the fourth embodiment. [Figure 24] It is a diagram showing a configuration example of a photoelectric conversion system and a moving body according to the fifth embodiment.

Embodiments for Carrying Out the Invention

[0010] The following embodiments are for embodying the technical idea of the present invention and do not limit the present invention. The sizes and positional relationships of the members shown in each drawing may be exaggerated for clarity of explanation. In the following description, the same configurations may be denoted by the same numbers and the description thereof may be omitted.

[0011] Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the following description, terms indicating specific directions and positions (for example, "up", "down", "right", "left", and other terms including these terms) are used as necessary. The use of these terms is for facilitating the understanding of the embodiments with reference to the drawings, and the technical scope of the present invention is not limited by the meanings of these terms.

[0012] In this specification, a plan view means viewing from a direction perpendicular to the light incident surface of a substrate such as a semiconductor substrate. Further, a cross-sectional view means viewing from a direction perpendicular to a plane parallel to the direction perpendicular to the light incident surface of the substrate. When the light incident surface of the substrate is rough when viewed microscopically, the plan view and the cross-sectional view are defined based on the light incident surface of the substrate when viewed macroscopically.

[0013] [First Embodiment] The electronic component according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 9.

[0014] In electronic components equipped with a semiconductor substrate having a detection area for detecting light, a phenomenon called wire ghosting may occur when light incident from an external source strikes a conductive wire, reflects, and then enters the detection area, appearing in the image formed by the detection area. Generally, conductive wires are made of metals such as gold, silver, aluminum, copper, or alloys thereof, and therefore tend to reflect light. The electronic component according to this embodiment achieves the suppression of such wire ghosting.

[0015] Figure 1 is a cross-sectional view showing an electronic component 100 according to this embodiment. As shown in Figure 1, the electronic component 100 according to this embodiment includes a substrate 101, a frame 102, an optical member 103, a first semiconductor substrate 104, and a second semiconductor substrate 110.

[0016] A frame 102 is bonded to the substrate 101. The substrate 101 is positioned to cover an opening on one side of the frame 102. An optical member 103 is bonded to the frame 102 to cover the opening on the other side. The external shape of the electronic component 100 is formed by the bonded substrate 101, frame 102, and optical member 103. The electronic component 100 has a hollow portion 120 surrounded by the frame 102 and the optical member 103.

[0017] In the hollow portion 120, the first semiconductor substrate 104 is placed and bonded on the substrate 101. The first semiconductor substrate 104 is electrically connected to the substrate 101 via conductive wires 109 by wire bonding.

[0018] A second semiconductor substrate 110 is placed on the first semiconductor substrate 104 in the hollow portion 120 and bonded to the first semiconductor substrate 104. The second semiconductor substrate 110 is electrically connected to the first semiconductor substrate 104 by a conductive member (not shown). The electrical connection between the first semiconductor substrate 104 and the second semiconductor substrate 110 is achieved, for example, by solder ball bonding, bump bonding, or hybrid bonding without bumps.

[0019] The substrate 101 is formed primarily from a ceramic material such as alumina or aluminum nitride. Alternatively, the substrate 101 may be formed primarily from glass epoxy. In the case of ceramic, the high thermal conductivity is advantageous for heat dissipation. In the case of glass epoxy, it is advantageous for weight reduction. A circuit (not shown) is formed on the substrate 101 and connected to the first semiconductor substrate 104 via conductive wires 109.

[0020] The frame 102 is formed from, for example, ceramics such as alumina and aluminum nitride, glass epoxy, resin materials, or metal materials, similar to the substrate 101. If the frame 102 is made of ceramic and the substrate 101 is also made of ceramic, the substrate 101 and the frame 102 can be formed as a single, integrated component with a recessed shape. If the frame 102 is made of a different material from the substrate 101, it is preferable to select appropriate materials for the substrate 101 and the frame 102, such as materials with similar coefficients of thermal expansion, from the viewpoint of bonding reliability.

[0021] The optical element 103 is translucent and transmits light detected by the detection area of ​​the first semiconductor substrate 104. The optical element 103 is made of, for example, glass, quartz, or sapphire. Optical elements 103 made of quartz or sapphire can also function as low-pass filters (LPFs). Since sapphire has higher strength than quartz, optical elements 103 made of sapphire can be made thinner. That is, optical elements 103 made of sapphire are advantageous for miniaturizing the entire electronic component 100. In addition, the coefficient of thermal expansion of sapphire is about the same as that of alumina. Therefore, when the frame 102 is made of alumina, optical elements 103 made of sapphire can improve the reliability of the bond between the frame 102 and the optical element 103. The optical element 103 may be coated with an anti-reflective coating or an infrared cut coating. In this embodiment, from the viewpoint of suppressing light reflection, it is preferable that an anti-reflective coating is applied to at least one or both surfaces of the optical member 103, specifically the surface facing the first semiconductor substrate 104 and the second semiconductor substrate 110, and the opposite surface.

[0022] The first semiconductor substrate 104 is, for example, a silicon substrate and has a detection region for detecting light in the central region 105 on the side of the optical member 103. Multiple image sensors may be formed in the detection region. The image sensors may be, for example, CMOS (Complementary Metal-Oxide Semiconductor) image sensors or avalanche diodes. If the image sensors are avalanche diodes, the avalanche diodes may be SPADs (Single Photon Avalanche Diodes).

[0023] The second semiconductor substrate 110 is, for example, a silicon substrate and may include circuits such as memory circuits. By making the second semiconductor substrate 110 electrically conductive with the first semiconductor substrate 104 over a short distance, high-speed signal transmission between the two becomes possible.

[0024] Figure 2 is a plan view showing the electronic component 100 from the side of the optical member 103 according to this embodiment. As shown in Figure 2, the substrate 101, frame 102, optical member 103, and first semiconductor substrate 104 each have a rectangular outline and are arranged so that their longitudinal and transverse directions are aligned. Here, we assume an electronic component 100 in which the longitudinal length is x and the transverse length is y, and both x and y are approximately 10 mm to 60 mm, but the size of the electronic component 100 is not limited to this.

[0025] The rectangular first semiconductor substrate 104 has a rectangular central region 105 as a first region and a peripheral region 106 as a second region arranged around the central region 105. The central region 105 is located in the center of the electronic component 100. Multiple first electrodes 107 are provided in the peripheral region 106. Multiple second electrodes 108 are provided in the region of the substrate 101 outside the region where the first semiconductor substrate is located, corresponding to the multiple first electrodes 107. The multiple first electrodes 107 and the multiple second electrodes 108 are connected by multiple conductive wires 109.

[0026] The second semiconductor substrate 110 is located in the peripheral region 106 of the first semiconductor substrate 104. More specifically, the second semiconductor substrate 110 is located between the central region 105 and the first electrode 107.

[0027] Figure 3 is a cross-sectional view illustrating the wire ghosting phenomenon. For convenience, in Figure 3, electronic components that may exhibit the wire ghosting phenomenon are indicated using the same reference numerals as the electronic component 100 in this embodiment. Figure 3(a) shows how incident light 111 entering the electronic component from above the optical member 103 strikes the conductive wire 109 and is reflected. Strictly speaking, the path of the incident light 111 passing through the optical member 103 changes slightly depending on the refractive index of the optical member 103, but for the sake of simplicity, the incident light 111 is shown as linear incident light. Figure 3(b) is a magnified cross-sectional view showing the vicinity of the conductive wire 109 in Figure 3(a).

[0028] In the electronic component shown in Figure 3, when h1 is the height of the conductive wire 109 from the surface on which the first electrode 107 is located, and h2 is the height of the second semiconductor substrate 110, then h1 > h2. The surface on which the first electrode 107 is located is the surface of the first semiconductor substrate 104 on which the second semiconductor substrate 110 is located. Furthermore, height h1 is the maximum height of the conductive wire 109 from the surface on which the first electrode 107 is located. Also, when θ is the angle between the normal to the surface on which the first electrode 107 is located and the conductive wire 109, near height h1, θ = 45°, and the conductive wire 109 is tilted outward from the first semiconductor substrate 104. Incident light 111 that strikes this region of the conductive wire 109 tilted at θ = 45° is reflected in that region and proceeds towards the optical member 103 without hitting the second semiconductor substrate 110. The incident light 111 that has traveled to the optical element 103 is reflected again by the surface of the optical element 103 facing the first semiconductor substrate 104, and incident on the first semiconductor substrate 104 inside the second semiconductor substrate 110. In other words, in the electronic component shown in Figure 3, there is a high possibility that the incident light 111 will be incident on the central region 105 of the first semiconductor substrate 104, which can cause wire ghosting.

[0029] Note that in the electronic component shown in FIG. 3, strictly speaking, there may be light that travels all the way to the opposite surface of the surface of the first semiconductor substrate 104 facing the optical member 103 and is reflected from that surface and then re-enters. However, since this re-entering light is weaker than the light reflected from the surface facing the first semiconductor substrate 104, it is not shown in FIG. 3. Also, the path of the incident light 111 can vary depending on, in addition to the above-described path, the distance d1 between the first electrode 107 and the second semiconductor substrate 110, the width d2 of the second semiconductor substrate 110, and the clearance c1 between the first semiconductor substrate 104 and the optical member 103. In any case, when h1 > h2, there is a high possibility that the incident light 111 reflected by the conductive wire 109 will enter the central region 105 of the first semiconductor substrate 104 and cause a wire ghost phenomenon.

[0030] FIG. 4 is a cross-sectional view showing the electronic component 100 according to the present embodiment. FIG. 4(a) shows a state in which the incident light 111 incident from above the optical member 103 hits the conductive wire 109 and is reflected, similar to FIG. 3(a). FIG. 4(b) is an enlarged cross-sectional view showing the vicinity of the conductive wire 109 in FIG. 4(a).

[0031] Unlike the electronic component shown in FIG. 3, in the electronic component 100 according to the present embodiment, as shown in FIG. 4(b), h1 < h2. Note that, similar to FIG. 3, in FIG. 4 as well, the angle θ formed by the normal to the surface on which the first electrode 107 is disposed and the conductive wire 109 is θ = 45° in the vicinity of the height h1. The incident light 111 that hits the region where the conductive wire 109 is inclined at θ = 45° is reflected in that region and travels toward the side of the second semiconductor substrate 110. The incident light 111 that has traveled toward the side of the second semiconductor substrate 110 is reflected again from the side surface of the second semiconductor substrate 110 facing the conductive wire 109 and travels toward the outer edge direction of the first semiconductor substrate 104. That is, in the electronic component 100 according to the present embodiment shown in FIG. 4, since it does not enter the central region 105 of the first semiconductor substrate 104, a wire ghost phenomenon does not occur.

[0032] Figures 5(a) to 6(b) are enlarged cross-sectional views showing the vicinity of the electronic component 100 and the conductive wire 109 illustrating the wire ghosting phenomenon according to this embodiment, respectively. The case described in Figures 3 and 4 will be explained in more detail below using Figures 5(a) to 6(b).

[0033] In the cases shown in Figures 5(a) to 6(b), the clearance c1 between the first semiconductor substrate 104 and the optical member 103 is 0.775 mm, and the width d2 of the second semiconductor substrate 110 is 1.0 mm, which is common to all cases.

[0034] In the case shown in Figure 5(a), h1=h2=0.3mm, θ=45° near height h1, and d1=0.2mm. In this case, incident light 111 incident on the side of the conductive wire 109 that is tilted at θ=45° and is closer to the first semiconductor substrate 104 is reflected by the side surface of the second semiconductor substrate 110 facing the conductive wire 109 and travels towards the outer edge of the first semiconductor substrate 104. However, in this case, incident light 111 incident on the side of the conductive wire 109 that is tilted at θ=45° and is farther away from the first semiconductor substrate 104 is reflected beyond the second semiconductor substrate 110 by the surface of the optical member 103 facing the first semiconductor substrate 104. This reflected incident light 111 then enters the first semiconductor substrate 104. For this reason, in the case shown in Figure 5(a), a wire ghosting phenomenon may occur.

[0035] In the case shown in Figure 5(b), h1 = 0.25 mm, and the other dimensions are the same as in the case shown in Figure 5(a). In this case, the incident light 111 incident on the region of the conductive wire 109 tilted at θ = 45° is all reflected by the side surface of the second semiconductor substrate 110 facing the conductive wire 109 and propagates towards the outer edge of the first semiconductor substrate 104. That is, in the case shown in Figure 5(b), the incident light 111 does not incident on the central region 105 of the first semiconductor substrate 104, so the wire ghosting phenomenon does not occur.

[0036] In the case shown in Fig. 5(c), h1 = 0.2 mm, h2 = 0.3 mm, d1 = 0.2 mm, and θ = 60°. In this case, although h1 < h2, the incident light 111 incident on the region where the conductive wire 109 is inclined at θ = 60° does not hit the second semiconductor substrate 110 and advances toward the side of the optical member 103 and is reflected by the surface of the optical member 103 facing the first semiconductor substrate 104. This reflected light is reflected again on the second semiconductor substrate 110. This light reflected again advances toward the side of the optical member 103 once more, is reflected by the surface of the optical member 103 facing the first semiconductor substrate 104, and is incident on the first semiconductor substrate 104. Therefore, in the case shown in Fig. 5(c), the wire ghost phenomenon may occur. However, in the case shown in Fig. 5(c), since the number of reflections is larger than that in the case shown in Fig. 5(a), the amount of light finally incident on the first semiconductor substrate 104 decreases, so the degree of influence on the image due to the wire ghost phenomenon decreases.

[0037] In the case shown in Fig. 5(d), h1 = 0.04 mm, and the other dimensions are the same as those in the case shown in Fig. 5(c). In this case, all of the incident light 111 incident on the region where the conductive wire 109 is inclined at θ = 60° is reflected by the side surface of the second semiconductor substrate 110 facing the conductive wire 109 and advances toward the outer edge direction of the first semiconductor substrate 104. That is, in the case shown in Fig. 5(d), since it does not enter the central region 105 of the first semiconductor substrate 104, the wire ghost phenomenon does not occur. However, considering that the diameter of the conductive wire 109 is about 0.015 to 0.03 mm, for example, h1 = 0.04 mm results in a clearance of about 0.01 to 0.025 mm between the first semiconductor substrate 104 and the conductive wire 109. Therefore, in the case shown in Fig. 5(d), there is a possibility that the first semiconductor substrate 104 and the conductive wire 109 may come into contact and cause a defect, including variations in the wire bonding process.

[0038] In the case shown in Figure 5(e), d1 = 0.1 mm, and the other dimensions are the same as in the case shown in Figure 5(c). In this case, most of the incident light 111 incident on the region of the conductive wire 109 tilted at θ = 60° is reflected off the side surface of the second semiconductor substrate 110 facing the conductive wire 109 and travels towards the outer edge of the first semiconductor substrate 104. Most of this incident light 111 is reflected on the side of the region of the conductive wire 109 tilted at θ = 60° that is closer to the first semiconductor substrate 104. However, some of the incident light 111 incident on the region of the conductive wire 109 tilted at θ = 60° travels along the following two paths. In the first path, the incident light 111 travels towards the optical member 103 without hitting the second semiconductor substrate 110, is reflected off the surface of the optical member 103 facing the first semiconductor substrate 104, and is reflected again on the second semiconductor substrate 110. Furthermore, in the first path, the incident light 111 travels again towards the optical element 103, is reflected by the surface of the optical element 103 facing the first semiconductor substrate 104, and enters the first semiconductor substrate 104. The second path is one in which the incident light 111 travels towards the optical element 103 without hitting the second semiconductor substrate 110, is reflected by the surface of the optical element 103 facing the first semiconductor substrate 104, passes over the second semiconductor substrate 110, and enters the first semiconductor substrate 104. In both the first and second paths, since the incident light 111 enters the first semiconductor substrate 104, a wire ghosting phenomenon may occur. Also, in this case, since the incident light 111 enters two different regions of the first semiconductor substrate 104, a wire ghosting phenomenon may occur in two regions. However, in this case, the amount of light incident on the first semiconductor substrate 104 is less than in the cases shown in Figures 5(a) and 5(c), so the impact of the wire ghosting phenomenon on the image is reduced.

[0039] As described above, in order to further suppress the wire ghost phenomenon, in addition to h1 < h2, it is preferable that the angle θ formed by the normal line of the surface on which the first electrode 107 is disposed and the conductive wire 109 is less than 45°. That is, the conductive wire 109 has a region inclined outward with respect to the first semiconductor substrate 104 at an angle θ formed by the conductive wire 109 and the normal line of the surface on which the first electrode 107 is disposed in the region up to the height h1, and it is preferable that the angle θ is less than 45°. Also, it is preferable that the region where the conductive wire 109 is inclined at θ is small. Also, the distance d1 between the first electrode 107 and the second semiconductor substrate 110 is preferably small. Also, the width d2 of the second semiconductor substrate 110 is such that the wider it is, in addition to the distance from the first electrode 107 to the central region 105 becoming farther, when there is light reflected by the optical member 103 or the second semiconductor substrate 110, the number of reflections also increases. For this reason, a wider width d2 of the second semiconductor substrate 110 is more effective in suppressing the wire ghost phenomenon. However, if the width d2 of the second semiconductor substrate 110 is wide, it may prevent miniaturization of the first semiconductor substrate 104. Therefore, the width d2 of the second semiconductor substrate 110 is preferably selected in view of overall optimization.

[0040] In the case shown in FIG. 6(a) and the case shown in FIG. 6(b), h1 = 0.15 mm, h2 = 0.3 mm, d1 = 0.2 mm, and θ = 45° respectively. The configurations in these cases are close to the configurations in the case shown in FIG. 5(a) and the case shown in FIG. 5(b), but the difference between these cases and FIGS. 5(a) and 5(b) is that the second electrode 108 is at the same height as the first electrode 107. In such a case, in the conductive wire 109, the region parallel to the surface of the first semiconductor substrate 104 becomes long. The second electrode 108 may be provided on the convex portion of the substrate 101 and at the same height as the first electrode 107, or may be provided on a semiconductor substrate different from the first semiconductor substrate 104 provided on the substrate 101 and at the same height as the first electrode 107.

[0041] In the case shown in Figure 6(a), the conductive wire 109 has a sloped region that slopes at θ=45° near height h1, and a parallel region on the side of the second electrode 108 that is perfectly parallel to the first semiconductor substrate 104 relative to the sloped region. Therefore, incident light 111 that enters the parallel region of the conductive wire 109 is reflected by that parallel region and propagates towards the outer edge of the first semiconductor substrate 104.

[0042] In the case shown in Figure 6(b), the conductive wire 109 has a sloped region that slopes at θ=45° near height h1, and a non-parallel region on the side of the second electrode 108 that is not perfectly parallel to the first semiconductor substrate 104 but has a slight angle to it. Incident light 111 that enters this non-parallel region of the conductive wire 109 is reflected by that non-parallel region and proceeds toward the optical member 103. The incident light 111 that proceeds toward the optical member 103 is reflected multiple times by the surface of the optical member 103 facing the first semiconductor substrate 104 and by the second semiconductor substrate 110 before entering the first semiconductor substrate 104. For this reason, in the case shown in Figure 6(b), a wire ghosting phenomenon may occur. In an actual wire bonding process, the shape of the conductive wire 109 may be such that it has the non-parallel region shown in Figure 6(b).

[0043] Therefore, from the viewpoint of further suppressing the effects of the wire ghosting phenomenon, it is preferable that the height of the second electrode 108 be lower than the upper surface of the first semiconductor substrate 104. It is also preferable that there be a larger area in which the conductive wire 109 and the first semiconductor substrate 104 are parallel.

[0044] Figures 7, 8, and 9 are plan views showing modified examples of the electronic component 100 according to this embodiment, and each shows a plan view of the electronic component 100 from the side of the optical member 103. As shown in Figures 7, 8, and 9, the arrangement of the second semiconductor substrate 110 and the arrangement of the conductive wires 109 can be changed as appropriate.

[0045] In the arrangement shown in Figure 7, two second semiconductor substrates 110 are arranged such that a central region 105 is sandwiched between two peripheral regions 106 along the short side of the first semiconductor substrate 104. Furthermore, no conductive wires 109 are arranged on the side of the central region 105 along the longitudinal direction of the first semiconductor substrate 104. This arrangement shown in Figure 7 is suitable when the number of conductive wires 109 is small.

[0046] In the arrangement shown in Figure 8, eight second semiconductor substrates 110 are arranged in total, two each in the peripheral region 106 along the short and long sides of the first semiconductor substrate 104. The eight second semiconductor substrates 110 are arranged to surround the central region 105. On each side, there is a clearance between two adjacent second semiconductor substrates 110 that are not separated by the central region 105. Conductive wires 109 are not placed in the region facing the clearance. This arrangement shown in Figure 8 is suitable when many functions are to be placed on the second semiconductor substrate 110 or when there are many conductive wires 109. Note that the eight second semiconductor substrates 110 are arranged to surround the central region 105. The number of second semiconductor substrates 110 arranged in the peripheral region 106 along each side of the first semiconductor substrate 104 is not limited to two; multiple second semiconductor substrates 110 other than a total of eight may be arranged to surround the central region 105.

[0047] As shown in Figures 7 and 8, the conductive wire 109 may not be placed in the region facing the peripheral region 106 where the second semiconductor substrate 110 is not located. In other words, the conductive wire 109 does not need to be placed in the region between the outer edge of the first semiconductor substrate 104 and the central region 105 where the second semiconductor substrate 110 is not located.

[0048] In the configuration shown in Figure 9, the rectangular annular second semiconductor substrate 110 is arranged in the peripheral region 106 such that it completely encloses the central region 105. In this case, conductive wires 109 can be placed in all regions facing the peripheral region 106. However, since the rectangular annular second semiconductor substrate 110 has low versatility, the configuration shown in Figure 9 may be selected considering the overall optimization.

[0049] Thus, according to this embodiment, the effect of the wire ghost phenomenon in the electronic component 100 can be suppressed.

[0050] [Second Embodiment] An electronic component according to a second embodiment of the present invention will be described with reference to Figures 10 to 12. Components similar to those in the electronic component according to the first embodiment will be denoted by the same reference numerals, and their descriptions will be omitted or simplified.

[0051] Figure 10 is a plan view of the electronic component 100 according to this embodiment, showing a plan view of the electronic component 100 from the side of the optical member 103. Figure 11 is a cross-sectional view along line AA' in Figure 10.

[0052] The arrangement of the second semiconductor substrate 110 in the electronic component 100 according to this embodiment is the same as the arrangement shown in Figure 8 in the first embodiment, as shown in Figure 10.

[0053] The electronic component 100 according to this embodiment differs from the electronic component 100 according to the first embodiment in the following two points. Specifically, as shown in Figures 10 and 11, the first bonding member 112 is arranged in the clearance region between the first semiconductor substrate 104 and the second semiconductor substrate 110, and between the two second semiconductor substrates 110. The two second semiconductor substrates 110, each with the first bonding member 112 in its clearance region, are arranged adjacent to each other without passing through the central region 105. The second point is that conductive wires 109 are also arranged in the region facing the clearance region where the first bonding member 112 is provided. Note that the first bonding member 112 only needs to be arranged in at least one of the clearance regions between the first semiconductor substrate 104 and the second semiconductor substrate 110, and between the two second semiconductor substrates 110.

[0054] The first bonding member 112 has insulation properties, such as resin, and specifically, it is an underfill material or the like. The first bonding member 112 may be colored, such as black, to suppress light reflection, or may have a shape, such as an uneven shape, that can suppress light reflection onto the first semiconductor substrate 104. By arranging the first bonding member 112 in the clearance region between the second semiconductor substrates 110, it is possible to suppress the incident light 111 incident on the conductive wire 109 in the region facing the clearance region from being reflected and incident on the central region 105 of the first semiconductor substrate 104. Thereby, the influence of the wire ghost phenomenon can be further suppressed.

[0055] FIG. 12(a) and FIG. 12(b) are cross-sectional views showing an enlarged structure within the dashed frame in FIG. 11. In the case shown in FIG. 12(a), the first bonding member 112 is arranged to a position lower than the second semiconductor substrate 110. In the case shown in FIG. 12(b), the first bonding member 112 is arranged to the same height as the height h2 of the second semiconductor substrate 110. Even in such an embodiment, by setting the height h1 of the conductive wire 109 < h2, the influence of the wire ghost phenomenon can be suppressed in the same manner as in the first embodiment. Note that the first bonding member 112 may be arranged at a height equal to or higher than the height h2 of the second semiconductor substrate 110.

[0056] [Third Embodiment] The electronic component according to the third embodiment of the present invention will be described with reference to FIGS. 13 to 22. Components similar to those of the electronic component according to the first and second embodiments are denoted by the same reference numerals, and the description thereof is omitted or simplified.

[0057] FIG. 13 is a cross-sectional view showing the electronic component 100 according to this embodiment. FIG. 14 is a plan view showing the electronic component 100 according to this embodiment, showing a plan view from the side of the optical member 103 of the electronic component 100.

[0058] The difference between the electronic component 100 according to this embodiment and the electronic component 100 according to the first and second embodiments is that the frame 102 is not provided, and the optical member 103 and the second semiconductor substrate 110 are joined via the second bonding member 113. The optical member 103 is joined to the second semiconductor substrate 110 via the second bonding member 113 so as to cover at least the central region 105 of the first semiconductor substrate 104. The positional relationship between the first semiconductor substrate 104, the second semiconductor substrate 110 and the conductive wire 109 in the electronic component 100 according to this embodiment is the same as in the first and second embodiments.

[0059] Figures 15(a) and 15(b) are enlarged cross-sectional views showing the vicinity of the electronic component 100 and the conductive wire 109 illustrating the wire ghosting phenomenon according to this embodiment.

[0060] In the case shown in Figure 15(a), the height h1 of the conductive wire 109 is equal to the height h2 of the second semiconductor substrate 110. Also, the angle of θ near height h1 is 45°. The configuration of the conductive wire 109 and the second semiconductor substrate 110 in the case shown in Figure 15(a) is the same as the configuration shown in Figure 5(a) in the first embodiment. On the other hand, the configuration in the case shown in Figure 15(a) differs from the configuration shown in Figure 5(a) in the first embodiment in that the optical member 103 is joined to the second semiconductor substrate 110 via the second bonding member 113. In the case shown in Figure 15(a), the optical member 103 is joined to the second semiconductor substrate 110. Therefore, the incident light 111 incident on the conductive wire 109 is reflected off the sides of the second semiconductor substrate 110, the second bonding member 113, and the optical member 103, and travels towards the outer edge of the first semiconductor substrate 104. In other words, as shown in Figure 15(a), the incident light 111 does not enter the central region 105 of the first semiconductor substrate 104, thus suppressing the wire ghosting phenomenon.

[0061] In the case shown in Figure 15(b), h1 > h2. In this case, the incident light 111 incident on the conductive wire 109 is reflected off the side surface of the optical member 103 and propagates towards the outer edge of the first semiconductor substrate 104. That is, in the case shown in Figure 15(b), the incident light 111 does not incident on the central region 105 of the first semiconductor substrate 104, so the wire ghosting phenomenon can be suppressed.

[0062] In the first embodiment, the degree of influence of the wire ghosting phenomenon could change depending on the height relationship between the conductive wire 109 and the second semiconductor substrate 110, and the angle of the conductive wire 109. In contrast, in this embodiment, the wire ghosting phenomenon can be suppressed regardless of the height or angle of the conductive wire 109, thus increasing the degree of freedom regarding the shape of the conductive wire 109.

[0063] For the second joining member 113, for example, an ultraviolet-curing adhesive or a thermosetting adhesive can be used. Furthermore, in order to suppress the light that passes through it, it is preferable to use a colored material such as black rather than a transparent material with high light transmittance for the second joining member 113.

[0064] Figures 16(a) and 16(b) are enlarged cross-sectional views showing the vicinity of the conductive wire 109 of the electronic component 100 according to this embodiment, respectively. Figures 16(a) and 16(b) show examples of structures including the optical member 103, the outer edge of the second bonding member 113, and the outer edge of the second semiconductor substrate 110.

[0065] As shown in Figure 16(a), the outer edge of the optical element 103 may be located inward from the outer edge of the second semiconductor substrate 110. The outer edge of the second semiconductor substrate 110 referred to here is the outer edge of the second semiconductor substrate 110 that is opposite to the central region 105 of the first semiconductor substrate 104. In this case, the second bonding member 113 may be arranged to cover at least a portion of the outer edge of the optical element 103. At least a portion of the outer edge of the optical element 103 covered by the second bonding member 113 includes a portion of the side surface of the optical element 103.

[0066] Furthermore, as shown in Figure 16(b), the outer edge of the optical element 103 may be located outside the outer edge of the second semiconductor substrate 110. The outer edge of the second semiconductor substrate 110 referred to here is the outer edge of the second semiconductor substrate 110 that is opposite to the central region 105 of the first semiconductor substrate 104. In this case, the second bonding member 113 may be arranged along the optical element 103 to the outside of the outer edge of the second semiconductor substrate 110. The second bonding member 113, which is arranged to the outside of the outer edge of the second semiconductor substrate 110, covers the portion of the back surface of the optical element 103 that is the side of the optical element 103 facing the first semiconductor substrate 104, that is outside the outer edge of the second semiconductor substrate 110.

[0067] The amount of light that enters from the sides or back of the optical element 103 and reaches the central region 105 is inherently small. However, as shown in Figures 16(a) and 16(b), the second bonding member 113 covers the sides and back of the optical element 103, which further enhances the suppression effect of the wire ghosting phenomenon.

[0068] Figures 17 and 18 are plan views showing modified examples of the electronic component 100 according to this embodiment, and show a plan view of the electronic component 100 from the side of the optical member 103. Figures 17 and 18 show the case in which the conductive wire 109 is arranged in the same way as shown in Figures 7 and 8 of the first embodiment. In this embodiment as well, the conductive wire 109 may not be arranged in the area facing the peripheral area 106 where the second semiconductor substrate 110 is not arranged. By arranging the conductive wire 109 in this way, the effect of the wire ghost phenomenon can be suppressed.

[0069] Furthermore, in this embodiment as well, the first joining member 112 can be arranged in the same manner as in the second embodiment. Figure 19 is a plan view showing the electronic component 100 according to this embodiment with the first joining member 112 arranged, and shows a plan view of the electronic component 100 from the side of the optical member 103. Figure 20 is a cross-sectional view along line AA' in Figure 19.

[0070] As shown in Figures 19 and 20, in this embodiment as well, similar to the case shown in Figures 10 and 11 of the second embodiment, the first bonding member 112 may be placed in the clearance region between the first semiconductor substrate 104 and the second semiconductor substrate 110 and between the second semiconductor substrates 110 themselves. In this embodiment as well, the placement of the first bonding member 112 makes it possible to suppress the reflection of incident light 111 incident on the conductive wire 109 in the region facing the clearance region and incident on the central region 105 of the first semiconductor substrate 104. The first bonding member 112 and the second bonding member 113 may be colored, such as black, in order to suppress light reflection, or they may have a shape that can suppress the reflection of light to the first semiconductor substrate 104, such as an uneven shape.

[0071] Figures 21(a) and 21(b) are enlarged cross-sectional views showing the structure within the dashed frame in Figure 20, respectively. As shown in Figures 21(a) and 21(b), two second semiconductor substrates 110 are arranged adjacent to each other without passing through the central region 105 of the first semiconductor substrate 104. In the clearance region between these two second semiconductor substrates 110, the space between the first semiconductor substrate 104 and the optical member 103 is covered by both the first bonding member 112 and the second bonding member 113. In these cases, the space between the first semiconductor substrate 104 and the optical member 103 may be covered by either the first bonding member 112 or the second bonding member 113.

[0072] In the case shown in Figure 21(a), there is a clearance between the first bonding member 112 and the second bonding member 113 in the clearance region between the second semiconductor substrates 110. In the case shown in Figure 21(b), the first bonding member 112 and the second bonding member 113 are arranged in contact with each other so that there is no clearance between them in the clearance region between the second semiconductor substrates 110. In this case, even in the region where the second semiconductor substrate 110 is not arranged, the light reflected from the conductive wire 109 by the first bonding member 112 and the second bonding member 113 does not directly enter the first semiconductor substrate 104, thus further suppressing the effect of the wire ghosting phenomenon.

[0073] Furthermore, in the configuration shown in Figures 13 to 21, since there is no frame 102 and no clearance between the optical member 103 and the second semiconductor substrate 110, the effect of miniaturizing the electronic component 100 can also be obtained.

[0074] Furthermore, in order to protect the central region 105, which is the detection area of ​​the first semiconductor substrate 104, and the conductive wires 109 from the external environment, the peripheral region 106 of the first semiconductor substrate 104 and the conductive wires 109 may be covered with an sealing material (not shown) or the like, as necessary. Protection from the external environment includes preventing the intrusion of foreign matter and moisture.

[0075] Furthermore, the electronic component 100 according to this embodiment may also be provided with a frame 102. Figure 22 is a cross-sectional view showing a configuration in which the electronic component 100 according to this embodiment is further provided with a frame 102. The difference between the configuration shown in Figure 22 and the configuration shown in Figure 13 is that, in addition to the provision of a frame 102 and the bonding of the second semiconductor substrate 110 and the optical member 103 via a second bonding member 113, the frame 102 and the optical member 103 are bonded via a third bonding member 114.

[0076] As shown in Figure 22, the frame 102 is bonded to one side of the substrate 101 so as to surround the area on the substrate 101 where the first semiconductor substrate 104 and conductive wire 109 are arranged. The optical member 103 is bonded to the upper surface of the second semiconductor substrate 110 via the second bonding member 113. The optical member 103 is also bonded to the frame side of the frame 102 opposite to the substrate 101 via the third bonding member 114.

[0077] In the configuration shown in Figure 22, the effect of suppressing the wire ghosting phenomenon is equivalent to that of the configurations shown in Figures 13 to 21, but the frame 102 can easily protect the central region 105 of the first semiconductor substrate 104 and the conductive wires 109 from the external environment.

[0078] Furthermore, the second bonding member 113 between the second semiconductor substrate 110 and the optical element 103, and the third bonding member 114 between the frame 102 and the optical element 103, may be the same material or they may be different materials.

[0079] Furthermore, in the configuration shown in Figure 22, since the optical member 103 is bonded to multiple second semiconductor substrates 110 and frame 102, it may be affected by variations in the height of each component. For this reason, in the configuration shown in Figure 22, in order to bond the optical member 103 accurately without tilting, the thickness, material, etc. of the second bonding member 113 may be changed for each component to accommodate variations in height.

[0080] [Fourth Embodiment] A photoelectric conversion system according to a fourth embodiment of the present invention will be described with reference to Figure 23. Figure 23 is a block diagram showing the schematic configuration of the photoelectric conversion system according to this embodiment.

[0081] The electronic components 100 described in the first to third embodiments above are applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in photoelectric conversion systems. Figure 23 shows a block diagram of a digital still camera as an example of these.

[0082] The photoelectric conversion system 200 illustrated in Figure 23 includes an imaging device 201, a lens 202 for forming an optical image of a subject onto the imaging device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light onto the imaging device 201. The imaging device 201 is an electronic component 100 described in any of the first to third embodiments, which converts the optical image formed by the lens 202 into image data.

[0083] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes the output signal output from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data. The imaging device 201 may include an AD conversion unit that generates the digital signal processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or it may be formed on a semiconductor layer different from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. Alternatively, the signal processing unit 208 may be formed on the same semiconductor layer as the imaging device 201.

[0084] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200 or it may be detachable.

[0085] Furthermore, the photoelectric conversion system 200 includes an overall control and calculation unit 218 that controls various calculations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system 200 only needs to include at least an imaging device 201 and a signal processing unit 208 that processes the output signals output from the imaging device 201.

[0086] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0087] Thus, according to this embodiment, a photoelectric conversion system can be realized by applying the electronic components 100 according to the first to third embodiments.

[0088] [Fifth Embodiment] A fifth embodiment of the present invention, consisting of a photoelectric conversion system and a mobile unit, will be described with reference to Figure 24. Figure 24 is a diagram showing the configuration of the photoelectric conversion system and mobile unit according to this embodiment.

[0089] Figure 24(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the electronic component 100 described in any of the first to third embodiments above. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging device 310. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0090] The photoelectric conversion system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0091] In this embodiment, the photoelectric conversion system 300 images the area around the vehicle, for example, the front or rear. Figure 24(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0092] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically drive to prevent vehicles from straying from their lanes. Furthermore, the photoelectric conversion system can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to mobile objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0093] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0094] In this specification, expressions such as “A or B,” “at least one of A and B,” “at least one of A and / or B,” and “one or more of A and / or B” can include all possible combinations of the enumerated items unless otherwise explicitly defined. That is, the above expressions are understood to disclose all cases of including at least one A, including at least one B, and including both at least one A and at least one B. This also applies to combinations of three or more elements.

[0095] The embodiments described above can be modified as appropriate without departing from the technical concept. Furthermore, the disclosures in this specification include not only what is described herein, but also all matters that can be understood from this specification and the drawings attached thereto. The disclosures in this specification also include the complement of the concepts described herein. That is, if this specification states, for example, "A is greater than B," then even if the statement "A is not greater than B" is omitted, this specification can be said to disclose that "A is not greater than B." This is because the statement "A is greater than B" presupposes that the case where "A is not greater than B" is being considered.

[0096] The above-disclosed embodiment includes the following configuration. (Composition 1) circuit board and A first semiconductor substrate is disposed on the substrate and has a first region for detecting light and a second region outside the first region, A second semiconductor substrate is placed on the first semiconductor substrate and bonded to the first semiconductor substrate, An optical member that transmits light and faces the first semiconductor substrate and the second semiconductor substrate via a hollow portion, Multiple first electrodes arranged in the second region, A plurality of second electrodes are arranged in the substrate in a region outside the region where the first semiconductor substrate is arranged, It includes a conductive wire connecting the first electrode and the second electrode, The second semiconductor substrate is disposed between the first region and the first electrode, where, when the maximum height from the surface of the first semiconductor substrate on which the first electrode of the conductive wire is disposed is h1 and the height of the second semiconductor substrate is h2, h1 < h2. An electronic component characterized by this. (Configuration 2) A substrate, A first semiconductor substrate disposed on the substrate, having a first region for detecting light and a second region outside the first region, A second semiconductor substrate disposed on the first semiconductor substrate and joined to the first semiconductor substrate, An optical member that transmits the light, A plurality of first electrodes disposed in the second region, A plurality of second electrodes disposed in a region outside the region of the substrate where the first semiconductor substrate is disposed, A conductive wire connecting the first electrode and the second electrode, and having, The second semiconductor substrate is disposed between the first region and the first electrode, The optical member is joined to the second semiconductor substrate via a second joining member so as to cover at least the first region. An electronic component characterized by this. (Configuration 3) Two or more of the second semiconductor substrates are provided. The electronic component according to Configuration 1 or 2, characterized by this. (Configuration 4) In a region between the outer edge of the first semiconductor substrate and the first region where the second semiconductor substrate is not disposed, no conductive wire is disposed. The electronic component according to any one of Configurations 1 to 3, characterized by this. (Configuration 5) An insulating first joining member is disposed between the first semiconductor substrate and the second semiconductor substrate. The electronic component according to any one of Configurations 1 to 4, characterized by this. (Configuration 6) The second semiconductor substrate includes two second semiconductor substrates disposed adjacent to each other without passing through the first region, The electronic component according to configuration 5, characterized in that the first bonding member is also disposed between the two second semiconductor substrates. (Composition 7) The electronic component according to configuration 6, characterized in that the first bonding member is positioned at or above the height of the second semiconductor substrate. (Composition 8) The electronic component according to any one of configurations 5 to 7, characterized in that the first joining member is colored. (Composition 9) The electronic component according to any one of configurations 1 to 8, characterized in that the second semiconductor substrate is arranged to surround the periphery of the first region. (Composition 10) The conductive wire has a region inclined outward with respect to the first semiconductor substrate at an angle θ between the conductive wire and the normal to the surface on which the first electrode is arranged, up to the height h1. An electronic component according to any one of configurations 1 to 9, characterized in that the angle θ is less than 45°. (Composition 11) The electronic component according to configuration 2, characterized in that the optical member is bonded to the second semiconductor substrate via a second bonding member. (Composition 12) The electronic component according to configuration 11, characterized in that the outer edge of the optical member is located inward from the outer edge of the second semiconductor substrate opposite to the central region of the first semiconductor substrate. (Composition 13) The electronic component according to configuration 12, characterized in that the second bonding member is arranged so as to cover at least a portion of the outer edge of the optical member. (Composition 14) The electronic component according to configuration 11, characterized in that the outer edge of the optical member is located outside the outer edge of the second semiconductor substrate on the side opposite to the first semiconductor substrate. (Composition 15) The electronic component according to configuration 14, characterized in that the second bonding member is disposed on at least a portion of the surface facing the first semiconductor substrate in the region of the second semiconductor substrate of the optical member that is outside the outer edge. (Composition 16) The second semiconductor substrate includes two second semiconductor substrates arranged adjacent to each other without the first region in between. An insulating first bonding member is placed between the two second semiconductor substrates. The electronic component according to any one of the configurations 11 to 15, characterized in that, in the region between the two second semiconductor substrates, the space between the first semiconductor substrate and the optical member is covered by either or both of the first bonding member and the second bonding member. (Composition 17) The electronic component according to configuration 16, characterized in that there is a clearance between the first bonding member and the second bonding member in the region between the two second semiconductor substrates. (Composition 18) The electronic component according to configuration 16, characterized in that the first bonding member and the second bonding member are in contact with each other in the region between the two second semiconductor substrates. (Composition 19) The first semiconductor substrate and the conductive wires are arranged in a frame that surrounds the region, The electronic component according to any one of configurations 11 to 18, characterized in that the optical member is joined to the frame via a third joining member. (Composition 20) The electronic components described in any one of items 1 to 19, A signal processing device that processes the signal output from the aforementioned electronic component and A photoelectric conversion system characterized by having the following features. (Composition 21) It is a mobile object, The electronic components described in any one of items 1 to 19, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned electronic component, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features. [Explanation of Symbols]

[0097] 100 Electronic Components 101 circuit board 102 Frame 103 Optical components 104 First Semiconductor Substrate 109 Conductive wire 110 Second Semiconductor Substrate 112 First Joining Member 113 Second Joining Member 114 Third Joining Member 120 Hollow part

Claims

1. circuit board and A first semiconductor substrate is disposed on the substrate and has a first region for detecting light and a second region outside the first region, A second semiconductor substrate is placed on the first semiconductor substrate and bonded to the first semiconductor substrate, An optical member that transmits light and faces the first semiconductor substrate and the second semiconductor substrate via a hollow portion, A plurality of first electrodes arranged in the second region, A plurality of second electrodes are arranged in the substrate in a region outside the region where the first semiconductor substrate is arranged, It includes a conductive wire connecting the first electrode and the second electrode, The second semiconductor substrate is disposed between the first region and the first electrode. An electronic component characterized in that, when the maximum height from the surface of the first semiconductor substrate on which the first electrode of the conductive wire is arranged is h1, and the height of the second semiconductor substrate is h2, h1 < h2.

2. circuit board and A first semiconductor substrate is disposed on the substrate and has a first region for detecting light and a second region outside the first region, A second semiconductor substrate is placed on the first semiconductor substrate and bonded to the first semiconductor substrate, The optical member that transmits the aforementioned light, Multiple first electrodes arranged in the second region, A plurality of second electrodes are arranged in the substrate in a region outside the region where the first semiconductor substrate is arranged, It includes a conductive wire connecting the first electrode and the second electrode, The second semiconductor substrate is disposed between the first region and the first electrode. The electronic component is characterized in that the optical member is bonded to the second semiconductor substrate via a second bonding member so as to cover at least the first region.

3. The electronic component according to claim 1 or 2, characterized in that two or more of the second semiconductor substrates are arranged.

4. The electronic component according to claim 1 or 2, characterized in that the conductive wire is not disposed in the region between the outer edge of the first semiconductor substrate and the first region where the second semiconductor substrate is not disposed.

5. The electronic component according to claim 1 or 2, characterized in that an insulating first bonding member is disposed between the first semiconductor substrate and the second semiconductor substrate.

6. The second semiconductor substrate includes two second semiconductor substrates arranged adjacent to each other without the first region in between. The electronic component according to claim 5, characterized in that the first bonding member is also disposed between the two second semiconductor substrates.

7. The electronic component according to claim 6, characterized in that the first bonding member is positioned at a height greater than or equal to the height of the second semiconductor substrate.

8. The electronic component according to claim 5, characterized in that the first joining member is colored.

9. The electronic component according to claim 1 or 2, characterized in that the second semiconductor substrate is arranged to surround the periphery of the first region.

10. The conductive wire has a region inclined outward with respect to the first semiconductor substrate at an angle θ between the conductive wire and the normal to the surface on which the first electrode is arranged, up to the height h1. The electronic component according to claim 1 or 2, characterized in that the angle θ is less than 45°.

11. The electronic component according to claim 2, characterized in that the optical member is bonded to the second semiconductor substrate via a second bonding member.

12. The electronic component according to claim 11, characterized in that the outer edge of the optical member is located inward from the outer edge of the second semiconductor substrate that is opposite to the central region of the first semiconductor substrate.

13. The electronic component according to claim 12, characterized in that the second bonding member is arranged to cover at least a portion of the outer edge of the optical member.

14. The electronic component according to claim 11, characterized in that the outer edge of the optical member is located outside the outer edge of the second semiconductor substrate on the side opposite to the first semiconductor substrate.

15. The electronic component according to claim 14, characterized in that the second bonding member is disposed on at least a portion of the surface facing the first semiconductor substrate in the region of the second semiconductor substrate of the optical member that is outside the outer edge.

16. The second semiconductor substrate includes two second semiconductor substrates arranged adjacent to each other without the first region in between. An insulating first bonding member is placed between the two second semiconductor substrates. The electronic component according to claim 11, characterized in that, in the region between the two second semiconductor substrates, the space between the first semiconductor substrate and the optical member is covered by either the first bonding member or the second bonding member or both.

17. The electronic component according to claim 16, characterized in that there is a clearance between the first bonding member and the second bonding member in the region between the two second semiconductor substrates.

18. The electronic component according to claim 16, characterized in that the first bonding member and the second bonding member are in contact with each other in the region between the two second semiconductor substrates.

19. The first semiconductor substrate and the conductive wires are arranged in a frame that surrounds the region, The electronic component according to claim 11, characterized in that the optical member is joined to the frame via a third joining member.

20. The electronic component according to claim 1 or 2, A signal processing device that processes the signal output from the aforementioned electronic component and A photoelectric conversion system characterized by having the following features.

21. It is a mobile object, The electronic component according to claim 1 or 2, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned electronic component, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

Images