Semiconductor equipment

Abstract

The objective is to provide a semiconductor device that can improve moisture resistance or acid resistance. [Solution] The semiconductor device disclosed comprises a semiconductor substrate, wiring provided on the semiconductor substrate, and a protective film covering at least a portion of the wiring, wherein the wiring has a first metal layer and a second metal layer provided on the first metal layer and containing a metal having higher moisture resistance or acid resistance than the first metal layer, and in the wiring, the contact portion between the first metal layer and the second metal layer is not exposed to a member provided on the protective film.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device capable of enhancing insulation reliability. This semiconductor device includes a semiconductor substrate including a drift layer of a first conductivity type and a terminal well region formed on the surface layer of the drift layer and having a second conductivity type different from the first conductivity type. On the surface of the semiconductor substrate, a surface electrode mainly composed of aluminum is formed by electrically connecting with its outer peripheral end face positioned on and contacting the terminal well region. An insulating protective film covers the surface electrode end portion of the surface electrode and the terminal well region and extends to the outer peripheral side of the semiconductor substrate. An electrode protective film made of titanium is provided between the surface electrode and the insulating protective film. The electrode protective film and the insulating protective film have an opening through which the surface electrode is exposed corresponding to the electrode formation region of the surface electrode.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Power devices, or semiconductor devices for power applications, are used as switching elements to control power supply to motor loads and other applications. Insulated-gate semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are widely used as power semiconductor devices. Power devices are increasingly capable of handling high currents, high voltages, and low losses, and are used in a variety of fields. Power devices are often used in harsh environments such as high altitudes, high temperatures, and high humidity, requiring high reliability against temperature cycling and humidity.

[0005] In the configuration of Patent Document 1, the ends of the surface electrodes where the electric field is strongest in the Schottky barrier diode are covered with a protective film made of Ti or a similar material with high corrosion resistance. This prevents corrosion of the surface electrodes, which are made of aluminum, a wiring material that is prone to corrosion. However, in the configuration of Patent Document 1, since multiple metal materials are in contact, corrosion of the electrodes due to the local galvanic effect may occur in the presence of moisture.

[0006] This disclosure was made to solve the above-mentioned problems and aims to provide a semiconductor device that can improve moisture resistance or acid resistance. [Means for solving the problem]

[0007] The semiconductor device according to the first disclosure comprises a semiconductor substrate, wiring provided on the semiconductor substrate, and a protective film covering at least a portion of the wiring, wherein the wiring has a first metal layer and a second metal layer provided on the first metal layer and containing a metal having higher moisture resistance or acid resistance than the first metal layer, and in the wiring, the contact portion between the first metal layer and the second metal layer is not exposed to a member provided on the protective film.

[0008] The semiconductor device according to the second disclosure comprises a semiconductor substrate having an active region, a wiring region outside the active region, and a termination region outside the wiring region; wiring provided on the wiring region; and a protective film covering at least a portion of the wiring, wherein the wiring has a first metal layer and a second metal layer provided on the first metal layer and containing a metal having higher moisture resistance or acid resistance than the first metal layer, and the protective film is provided from the upper surface of the second metal layer to the sides on both sides of the first metal layer.

[0009] The semiconductor device according to the third disclosure comprises a semiconductor substrate, a pad electrode provided on the semiconductor substrate, and a protective film provided on the pad electrode, wherein the pad electrode has a first metal layer and a second metal layer provided on the first metal layer and containing a metal that has higher moisture resistance or acid resistance than the first metal layer, the pad electrode has a pad opening formed in which the first metal layer is exposed from the second metal layer, and the contact portion between the first metal layer and the second metal layer facing the pad opening is covered with the protective film. [Effects of the Invention]

[0010] In the semiconductor device according to the first disclosure, the contact area between the first metal layer and the second metal layer is not exposed to the component provided on the protective film. Therefore, moisture resistance or acid resistance can be improved. In the semiconductor device according to the second disclosure, a protective film is provided extending from the upper surface of the second metal layer to both sides of the first metal layer. Therefore, moisture resistance or acid resistance can be improved. In the semiconductor device according to the third disclosure, the contact area between the first metal layer and the second metal layer facing the pad opening is covered with a protective film. Therefore, moisture resistance or acid resistance can be improved. [Brief explanation of the drawing]

[0011] [Figure 1] This is a plan view of the semiconductor device according to Embodiment 1. [Figure 2] This is an enlarged view of the active region according to Embodiment 1. [Figure 3]It is a cross-sectional view obtained by cutting Fig. 2 along the straight line A-B. [Figure 4] It is an enlarged view of the region at the end of the active region according to Embodiment 1. [Figure 5] It is a cross-sectional view obtained by cutting Fig. 4 along the straight line C-D. [Figure 6] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 7] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 8] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 9] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 10] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 11] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 12] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 13] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 14] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 15] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 16] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 17] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 18] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 19] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 20] It is a cross-sectional view for explaining the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 21] It is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to Embodiment 1. [Figure 22] It is an enlarged view of a region at an end of an active region according to Embodiment 2. [Figure 23] It is a cross-sectional view obtained by cutting Fig. 22 along the straight line C-D. [Figure 24] It is an enlarged view of a region at an end of an active region according to Embodiment 3. [Figure 25] It is a cross-sectional view obtained by cutting Fig. 24 along the straight line C-D. [Figure 26] It is an enlarged view of a region at an end of an active region according to Embodiment 4. [Figure 27] It is a cross-sectional view obtained by cutting Fig. 26 along the straight line C-D. [Figure 28] It is a plan view of a semiconductor device according to Embodiment 5. [Figure 29] It is an enlarged view of a region at an end of an active region according to Embodiment 5. [Figure 30] It is a cross-sectional view obtained by cutting Fig. 29 along the straight line E-F.

Embodiments for Carrying Out the Invention

[0012] The semiconductor devices according to the respective embodiments will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and the repeated description may be omitted.

[0013] Embodiment 1. Fig. 1 is a plan view of a semiconductor device 100 according to Embodiment 1. The semiconductor substrate of the semiconductor device 100 has an active region 101, a gate wiring region 102 outside the active region 101, and a termination region 104 outside the gate wiring. A main electrode of the semiconductor device 100 is formed on the upper surface of the active region 101. The main electrode is, for example, a source electrode. The main electrode corresponds to a pad electrode 41 described later.

[0014] A gate wiring region 102 surrounding the active region 101 is provided with gate wiring 42 that is electrically connected to the gate electrode, which is a control electrode. The gate wiring 42 is connected to the gate pad 103. A termination region 104 for voltage resistance is formed to surround the active region 101, the gate wiring region 102, and the gate pad 103. A dicing line region 105, corresponding to the dicing line when cutting out the chip, is provided surrounding the termination region 104.

[0015] Figure 2 is an enlarged view of the active region 101 according to Embodiment 1. Figure 2 is an enlarged view of region 106 in Figure 1. Figure 3 is a cross-sectional view obtained by cutting Figure 2 along the line AB. As shown in Figure 3, the semiconductor device 100 includes an n+ type semiconductor substrate 1. An n+ type buffer layer 2 is formed on the semiconductor substrate 1. An n- type drift layer 3 is formed on the upper side of the buffer layer 2. A p-type well layer 4 is selectively formed on the upper side of the drift layer 3. An n+ type source layer 5 and a p+ type contact layer 6 are formed on the upper side of the well layer 4. An n-type JFET doped layer 7 is formed between the well layers 4.

[0016] A gate insulating film 8 is provided on the upper surface of the semiconductor substrate 1, above the well layer 4, the source layer 5, and the JFET doped layer 7. A gate electrode layer 9 is provided on the gate insulating film 8. The gate electrode layer 9 is made of, for example, polysilicon. An interlayer insulating film 10 is formed on the gate electrode layer 9. A Ni silicide layer 11 is formed on the upper surface of the semiconductor substrate 1, above the source layer 5 and the contact layer 6. A barrier metal layer 12 is provided on the Ni silicide layer 11 and the interlayer insulating film 10. The barrier metal layer 12 is made of, for example, Ti / TiN. A metal layer 13 is formed on the barrier metal layer 12. The metal layer 13 is, for example, an Al electrode. The Ni silicide layer 11, the barrier metal layer 12, and the metal layer 13 may be collectively called the source electrode or pad electrode 41.

[0017] A Ni silicide layer 14 is formed on the back surface of the semiconductor substrate 1. An Al electrode 15 is formed on the back surface of the Ni silicide layer 14. The Ni silicide layer 14 and the Al electrode 15 can be collectively referred to as the drain electrode.

[0018] Figure 4 is an enlarged view of the end region 107 of the active region 101 according to Embodiment 1. Figure 5 is a cross-sectional view obtained by cutting Figure 4 along the CD line. As shown in Figure 5, a p-type FLR (Field Limiting Ring) layer 16 and an n+-type channel stopper layer 17 are formed on the upper surface side of the drift layer 3 in the terminal region 104. In this way, a pressure-resistant holding structure called an FLR structure is formed in the terminal region 104. In the terminal region 104, a field insulating film 18 is formed on the upper surface of the semiconductor substrate 1. A protective film 19, such as a nitride film, is formed on the field insulating film 18. A protective film 20, such as a polyimide film, is formed on the protective film 19. The protective film 19 is, for example, an inorganic protective film with excellent moisture resistance and a moisture permeability prevention function. The protective film 20 is, for example, an organic protective film with a stress relaxation function.

[0019] In the gate wiring region 102, a gate electrode 21 is formed on the field insulating film 18. The gate electrode 21 is a wiring layer connected to the gate electrode layer 9. The gate electrode 21 is made of polysilicon. A barrier metal layer 22 is formed on the gate electrode 21. The barrier metal layer 22 is made of, for example, Ti silicide / TiN. A metal layer 23 is formed on the barrier metal layer 22. The metal layer 23 is made of, for example, Al. In the active region 101, a metal layer 24 is formed on the field insulating film 18 via the barrier metal layer 22. The metal layer 24 is made of, for example, Al.

[0020] A metal layer 25, which is an electrode protective film, is formed on the metal layers 23 and 24. The metal layer 25 is made of, for example, Ti. The barrier metal layer 22, the metal layer 23, and the metal layer 25 provided on the metal layer 23 constitute the gate wiring 42. The barrier metal layer 22, the metal layer 24, and the metal layer 25 provided on the metal layer 24 constitute the pad electrode 41. Protective films 19 and 20 are formed on the metal layer 25. The protective films 19 and 20 cover the entire gate wiring 42 and the ends of the pad electrode 41.

[0021] In the semiconductor device 100, the source electrode is formed on the upper surface of the semiconductor substrate 1, and the drain electrode is formed on the back surface of the semiconductor substrate 1. As a result, the main current flows in the vertical direction of the semiconductor substrate 1. In a MOSFET composed of a source layer 5, a well layer 4, a drift layer 3, a gate insulating film 8, and a gate electrode layer 9, the main current is controlled by the gate.

[0022] As shown in Figure 2, the unit cell is formed in a stripe pattern. Multiple gate electrode layers 9 are also formed in a stripe pattern. The gate electrode layer 9 is connected to the gate electrode 21 of the gate wiring region 102 adjacent to the edge of the active region 101. In the contact hole 30 enclosed by X shown in Figure 4, the gate electrode 21 is connected to the gate wiring 42. Also, in the contact hole 29 enclosed by X shown in Figures 2 and 4, the semiconductor substrate 1 and the pad electrode 41 are in contact. This grounds the source.

[0023] Next, a method for manufacturing the semiconductor device 100 will be described. Figures 6 to 21 are cross-sectional views illustrating the manufacturing method of the semiconductor device 100 according to Embodiment 1. Figures 6 and 7 are cross-sectional views of the active region 101 (AB) and the outer peripheral region (CD), respectively, after the process of forming the diffusion layer, MOS gate, interlayer film, and wiring has been completed. The steps up to this point can be formed using general semiconductor processes, so their explanation will be omitted.

[0024] Next, a Ti film 26 is formed on the metal layers 13 and 24 using sputtering technology or the like. Figures 8 and 9 are cross-sectional views AB and CD, respectively, of the Ti film 26 after it has been formed. Next, resist patterning is performed using general photoengraving technology. Figures 10 and 11 are cross-sectional views AB and CD, respectively, of the resist 27 after it has been patterned.

[0025] Next, the Ti film 26 is etched using the resist 27 as a mask. This forms a metal layer 25 at a predetermined position. Figures 12 and 13 are cross-sectional views AB and CD, respectively, of the state after the metal layer 25 has been formed. At this time, the dimensions and position of the resist 27 are adjusted as needed so that the metal layer 25 can cover the metal layers 23 and 24.

[0026] Next, after removing the resist 27, a nitride film 28 is formed using a method such as deposition. Figures 14 and 15 are cross-sectional views AB and CD, respectively, of the film after the nitride film 28 has been formed. Furthermore, resist patterning is performed using general photoengraving techniques. Figures 16 and 17 are cross-sectional views AB and CD, respectively, of the film after the resist 27 has been formed.

[0027] Next, the nitride film 28 is etched using the resist 27 as a mask to form a protective film 19 at a predetermined position. Figures 18 and 19 are cross-sectional views AB and CD, respectively, of the state after the protective film 19 has been formed. At this time, the dimensions and position of the resist 27 are adjusted so that all parts where the metal layer 23 or metal layer 24 and metal layer 25 are in contact are covered by the protective film 19.

[0028] Next, the resist 27 is removed. Figures 20 and 21 are cross-sectional views AB and CD, respectively, after the resist 27 has been removed. Subsequent steps can be performed using general semiconductor processes, so their explanation is omitted.

[0029] Next, the operation of the semiconductor device 100 will be described. When the positive voltage applied to the gate pad 103 exceeds the threshold voltage of the MOSFET, the MOSFET turns on. This causes the drain voltage to drop, the main current to flow between the source and drain, and the semiconductor device 100 enters the ON state. Conversely, when the negative voltage applied to the gate pad 103 falls below the threshold voltage while the device is ON, the MOSFET turns off. This interrupts the current between the source and drain, the drain voltage rises, and the semiconductor device 100 enters the OFF state.

[0030] In the off state, a depletion layer extends laterally from the active region 101 towards the end of the termination region 104. At this time, the FLR layer 16 and the channel stopper layer 17 are set so that the electric field strength is below a predetermined value. For this reason, the gate wiring 42 formed in the region closest to the termination region 104 at the end of the active region 101 is more susceptible to the effects of the drain voltage than the active region 101.

[0031] Furthermore, under high temperature and high humidity conditions, moisture can penetrate from the outside while being ionized. In particular, in transfer-molded products, moisture may penetrate from the tip edge through the resin interface, etc. Thus, especially at the outer periphery of the tip, the metal layer 23 formed of Al in the gate wiring 42 is more susceptible to corrosion than other parts due to the effects of temperature, humidity, and electric field.

[0032] In contrast, in this embodiment, the metal layer 23 made of Al is covered with a metal layer 25 which is a Ti electrode with excellent corrosion resistance. Therefore, moisture resistance or acid resistance can be improved, and THB (Temperature Humidity Bias) resistance can be improved.

[0033] Furthermore, in the gate wiring 42, the entire upper surface and both sides of the metal layer 23 are covered by the metal layer 25. In other words, the contact area between the metal layer 23 and the metal layer 25 is not exposed to the component provided on the protective film 19. This prevents the contact area between the two types of metals, such as Al and Ti, from being exposed to moisture by the protective film 20, sealing resin, etc. Therefore, corrosion of the metal due to the localized galvanic effect can be suppressed, and moisture resistance or acid resistance can be further improved.

[0034] Furthermore, the gate wiring 42 is covered with a protective film 19. This further suppresses the intrusion of moisture and improves moisture resistance or acid resistance. In particular, covering the entire top surface and both sides of the gate wiring 42 with the protective film 19 further improves moisture resistance or acid resistance.

[0035] Furthermore, a portion of the active region 101 needs to be joined to the package electrode by methods such as wire bonding or soldering. For this reason, a portion of the metal layers 13 and 24 is exposed. In other words, the pad electrode 41 has a pad opening 41a in which the metal layer 24 is exposed from the metal layer 25. At the pad opening 41a, the metal layer 24 is not covered by the metal layer 25. Therefore, there is a risk that the contact portion of the metal layers 24 and 25, i.e., the edge of the metal layer 25, may be exposed at the position facing the pad opening 41a.

[0036] In contrast, in this embodiment, the contact area between the metal layer 24 and the metal layer 25 facing the pad opening 41a is covered with a protective film 19. In other words, in the pad electrode 41, the contact area between the metal layer 24 and the metal layer 25 is not exposed to the member provided on the protective film 19. Therefore, galvanic corrosion and localized galvanic effects can be prevented, and moisture resistance or acid resistance can be further improved.

[0037] Furthermore, in this embodiment, a protective film 20, which is a polyimide film, is provided on top of the protective film 19. This allows for stress relief, especially in molded products. The protective film 20 also covers the corners of the gate wiring 42 and pad electrodes 41. This allows for stress relief in areas prone to stress, such as stepped sections of the wiring.

[0038] In this embodiment, the metal layer 25 is formed of Ti. The thickness of this Ti film is preferably set to a thickness that does not cause pinholes, and is preferably around 200 to 3000 Å, taking into account the effects on etching and wafer warping. Alternatively, the metal layer 25 may be formed of a material containing Ti, Au, or Pt, which has excellent moisture resistance. The metal layer 25 should contain a metal with higher moisture resistance or acid resistance than metal layers 23 and 24.

[0039] Furthermore, in this embodiment, the metal layers 23 and 24 are formed of Al. However, the metal layers 23 and 24 may also contain Al or Cu. The metal layers 23 and 24 are not limited to pure Al, but may also be AlSi or AlSiCu, or even wiring with Cu as the main material.

[0040] The thickness of the nitride film as the protective film 19 should preferably be such that cracks do not occur in the film under the operating temperature conditions, and a thickness of approximately 5000 to 30000 Å is desirable considering the effects on etching and wafer warping. The protective film 19 may also be an oxide film. The protective film 19 may also be a glass coating such as a plasma nitride film or a plasma oxide film.

[0041] In this embodiment, in the gate wiring 42 located furthest towards the termination region 104 within the gate wiring region 102, the contact portion between the metal layer 23 and the metal layer 24 is not exposed to the member provided on the protective film 19. However, this is not limited to this, and it is sufficient that in any wiring provided in the wiring region between the active region 101 and the termination region 104, the contact portion between the metal layer 23 and the metal layer 24 is not exposed to the member provided on the protective film 19.

[0042] This configuration, in which the contact points of different metal layers are not exposed, can be applied to any wiring on the semiconductor substrate 1. As mentioned above, this configuration, in which the contact points of different metal layers are not exposed, is particularly effective when applied to wiring on the outer edge of the chip, but the effect of improving moisture resistance and acid resistance can be obtained regardless of which wiring it is applied to.

[0043] For example, the pad electrode 41 may be configured such that the contact portion between metal layer 24 and metal layer 25 is not exposed, and the above configuration may not be applied to the gate wiring 42. Similarly, the gate wiring 42 may be configured such that the contact portion between metal layer 23 and metal layer 25 is not exposed, and the above configuration may not be applied to the pad electrode 41. Note that "the contact portion between different metal layers is not exposed to the member provided on the protective film" means that the edges of the contact surfaces between different metal layers are not exposed to the member provided on the protective film 19.

[0044] Furthermore, in the example shown in Figure 5, the entire top and both sides of the gate wiring 42 are covered with the protective film 19. However, the protective film 19 only needs to cover at least a portion of the gate wiring 42. For example, the protective film 19 may be provided so as to cover only a portion of the gate wiring 42, extending from the top surface of the metal layer 25 to both sides of the metal layer 23. This configuration also allows the metal layer 25 and the protective film 19 to improve moisture resistance or acid resistance. It is preferable that the contact areas of the metal layers 23 and 25 and the contact areas of the metal layers 24 and 25 are not exposed, but they may be partially exposed within an acceptable range.

[0045] The semiconductor substrate 1 may be a silicon substrate, or it may be formed from a wide-bandgap semiconductor. The wide-bandgap semiconductor may be silicon carbide, gallium nitride-based material, or diamond. Furthermore, the semiconductor device 100 is not limited to a MOSFET, but may be other devices such as an IGBT.

[0046] The modifications described above can be appropriately applied to the semiconductor device according to the following embodiments. Since the semiconductor device according to the following embodiments has many similarities with Embodiment 1, the explanation will focus on the differences from Embodiment 1.

[0047] Embodiment 2. Figure 22 is an enlarged view of the end region 107 of the active region 101 according to Embodiment 2. Figure 23 is a cross-sectional view obtained by cutting Figure 22 along the CD line. This embodiment differs from Embodiment 1 in that the metal layer 25 is provided only on the upper surface of metal layer 23 and the upper surface of metal layer 24. In other words, the side surfaces of metal layer 23 and metal layer 24 are exposed from metal layer 25. The other configurations are the same as those of Embodiment 1.

[0048] In this embodiment, the metal layer 25 partially covers the metal layers 23 and 24 to improve moisture resistance. In addition, in the gate wiring 42, the protective film 19 is provided from the upper surface of the metal layer 25 to both sides of the metal layer 23. Therefore, even when the metal layer 25 is provided only on the upper surface of the metal layer 23, the edges of the contact surface between the metal layer 23 and the metal layer 25 can be covered with the protective film 19. Furthermore, the edges of the contact surface between the metal layer 24 and the metal layer 25 are also covered with the protective film 19. Thus, moisture resistance or acid resistance can be improved.

[0049] Similar to Embodiment 1, the protective film 19 does not need to cover the entire gate wiring 42. The protective film 19 may be provided from the top surface of the metal layer 25 to both sides of the metal layer 23. Alternatively, the protective film 19 may be provided from the top surface of the metal layer 25 to the sides of the metal layer 24. This allows the edges of the metal layer 25 to be covered with the protective film 19.

[0050] Embodiment 3. Figure 24 is an enlarged view of the edge region 107 of the active region 101 according to Embodiment 3. Figure 25 is a cross-sectional view obtained by cutting Figure 24 along the CD line. In this embodiment, the pad electrode 41 differs from Embodiment 1 in that the metal layer 24 is entirely covered by the metal layer 25. The other configurations are the same as those of Embodiment 1.

[0051] In this embodiment, the top and side surfaces of the metal layers 23 and 24, which are Al electrodes, are all covered by the metal layer 25, which is a Ti electrode. As a result, the contact area between the metal layer 23 or metal layer 24 and the metal layer 25 is not exposed, improving moisture resistance or acid resistance. Furthermore, by covering a portion of the gate wiring 42 and pad electrode 41 with the protective film 19, moisture resistance or acid resistance can be further improved.

[0052] Embodiment 4. Figure 26 is an enlarged view of the end region 107 of the active region 101 according to Embodiment 4. Figure 27 is a cross-sectional view obtained by cutting Figure 26 along the CD line. In this embodiment, the contact portion of the metal layer 24 and the metal layer 25 in the pad electrode 41 is exposed from the protective film 19, which is a difference from Embodiment 1. The other configurations are the same as those of Embodiment 1. In this embodiment, the moisture resistance of the pad electrode 41 is reduced compared to Embodiment 1. However, in the gate wiring 42, the contact portion of the metal layer 23 and the metal layer 25 is not exposed to the member provided on the protective film 19. Therefore, moisture resistance or acid resistance can be improved in areas that are susceptible to the effects of temperature, humidity, and electric fields.

[0053] Embodiment 5. Figure 28 is a plan view of the semiconductor device 100 according to Embodiment 5. Figure 29 is an enlarged view of the edge region 107 of the active region 101 according to Embodiment 5. Figure 30 is a cross-sectional view obtained by cutting Figure 29 along the EF line. In this embodiment, a source liner wiring region 108 is provided between the gate wiring region 102 and the termination region 104. The source liner wiring region 108 is the region of the semiconductor substrate 1 in which source liner wiring 48 is provided.

[0054] In the source liner wiring region 108, a metal layer 32, which is an Al electrode, is formed on the barrier metal layer 22. A metal layer 25 made of Ti is formed on the metal layer 32. The barrier metal layer 22, the metal layer 32, and the metal layer 25 provided on the metal layer 32 constitute the source liner wiring 48. The source liner wiring 48 is connected to the well layer 4 and the contact layer 6 in the contact hole 31. The source liner wiring 48 is connected to the source electrode of the active region 101.

[0055] In this embodiment, the entire upper surface and both sides of the metal layer 32 of the source liner wiring 48 are covered by the metal layer 25. Therefore, the contact area between the metal layer 32 and the metal layer 25 is not exposed to the member provided on the protective film 19. Furthermore, the entire upper surface and both sides of the source liner wiring 48 are covered by the protective film 19. This improves moisture resistance or acid resistance.

[0056] In this embodiment, the source liner wiring 48 is the wiring located closest to the termination region 104. Therefore, considering the path of moisture intrusion and the electric field distribution in the termination region 104, the source liner wiring 48 is also protected by the metal layer 25 and the protective film 19, in addition to the gate wiring 42.

[0057] Furthermore, only one of the gate wiring 42 or the source liner wiring 48 may be protected. Also, although this embodiment shows an example in which source wiring is provided in the wiring area, if the semiconductor device 100 is an IGBT, emitter wiring may also be provided.

[0058] The technical features described in each embodiment may be used in combination as appropriate.

[0059] The various aspects of this disclosure are summarized below as an appendix. (Note 1) Semiconductor substrate and Wiring provided on the semiconductor substrate, A protective film covering at least a portion of the aforementioned wiring, Equipped with, The wiring comprises a first metal layer and a second metal layer provided on the first metal layer and containing a metal that has higher moisture resistance or acid resistance than the first metal layer. A semiconductor device characterized in that, in the wiring, the contact portion between the first metal layer and the second metal layer is not exposed to the member provided on the protective film. (Note 2) The semiconductor substrate has an active region, a wiring region outside the active region, and a termination region outside the wiring region. The semiconductor device according to Appendix 1, characterized in that the aforementioned wiring is provided in the aforementioned wiring region. (Note 3) A semiconductor substrate having an active region, a wiring region outside the active region, and a termination region outside the wiring region, Wiring provided on the aforementioned wiring area, A protective film covering at least a portion of the aforementioned wiring, Equipped with, The wiring comprises a first metal layer and a second metal layer provided on the first metal layer and containing a metal that has higher moisture resistance or acid resistance than the first metal layer. The semiconductor device is characterized in that the protective film is provided extending from the upper surface of the second metal layer to the side surfaces on both sides of the first metal layer. (Note 4) The semiconductor device according to Appendix 3, characterized in that, in the wiring, the contact portion between the first metal layer and the second metal layer is not exposed to the member provided on the protective film. (Note 5) The semiconductor device according to any one of the appendices 2 to 4, characterized in that the aforementioned wiring is the wiring located furthest towards the termination region within the wiring region. (Note 6) A semiconductor device according to any one of appendices 1 to 5, characterized in that the entire upper surface and both sides of the first metal layer are covered by the second metal layer. (Note 7) The pad electrode comprises a third metal layer provided on the active region, and a fourth metal layer provided on the third metal layer, the fourth metal layer containing a metal that has higher moisture resistance or acid resistance than the third metal layer. The pad electrode has a pad opening formed in which the third metal layer is exposed from the fourth metal layer. The semiconductor device according to any one of appendices 2 to 5, characterized in that the contact portion between the third metal layer and the fourth metal layer facing the pad opening is covered with the protective film. (Note 8) The semiconductor device according to any one of the appendices 1 to 7, characterized in that the aforementioned wiring is gate wiring. (Note 9) The semiconductor device according to any one of the appendices 1 to 7, characterized in that the aforementioned wiring is either source wiring or emitter wiring. (Note 10) The semiconductor device according to any one of the appendices 1 to 9, characterized in that the second metal layer contains Ti, Au, or Pt. (Note 11) The semiconductor device according to any one of appendices 1 to 10, characterized in that the first metal layer contains Al or Cu. (Note 12) A semiconductor device according to any one of appendices 1 to 11, characterized by comprising a polyimide film provided on the protective film. (Note 13) The semiconductor device according to Appendix 12, characterized in that the polyimide film covers the corners of the wiring. (Note 14) The semiconductor device according to any one of the appendices 1 to 13, characterized in that the protective film is a nitride film or an oxide film. (Note 15) The semiconductor device according to any one of appendices 1 to 14, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor. (Note 16) The semiconductor device according to Appendix 15, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond. (Note 17) Semiconductor substrate and A pad electrode provided on the semiconductor substrate, A protective film provided on the pad electrode, Equipped with, The pad electrode comprises a first metal layer and a second metal layer provided on the first metal layer and containing a metal that has higher moisture resistance or acid resistance than the first metal layer. The pad electrode has a pad opening formed in which the first metal layer is exposed from the second metal layer. A semiconductor device characterized in that the contact portion between the first metal layer and the second metal layer facing the pad opening is covered with the protective film. [Explanation of Symbols]

[0060] 1 Semiconductor substrate, 2 Buffer layer, 3 Drift layer, 4 Well layer, 5 Source layer, 6 Contact layer, 7 JFET doped layer, 8 Gate insulating film, 9 Gate electrode layer, 10 Interlayer insulating film, 11 Ni silicide layer, 12 Barrier metal layer, 13 Metal layer, 14 Ni silicide layer, 15 Al electrode, 16 FLR layer, 17 Channel stopper layer, 18 Field insulating film, 19 Protective film, 20 Protective film, 21 Gate electrode, 22 Barrier metal layer, 23 Metal layer, 24 Metal layer, 25 Metal layer, 26 Ti film, 27 Resist, 28 Nitride film, 29, 30, 31 Contact hole, 32 Metal layer, 41 Pad electrode, 41a Pad opening, 42 Gate wiring, 48 Source liner wiring, 100 Semiconductor device, 101 Active region, 102 Gate wiring region, 103 Gate pad, 104 Termination area, 105 dicing line area, 108 source liner wiring area

Claims

1. Semiconductor substrate and Wiring provided on the semiconductor substrate, A protective film covering at least a portion of the aforementioned wiring, Equipped with, The wiring comprises a first metal layer and a second metal layer provided on the first metal layer and containing a metal that has higher moisture resistance or acid resistance than the first metal layer. A semiconductor device characterized in that, in the wiring, the contact portion between the first metal layer and the second metal layer is not exposed to the member provided on the protective film.

2. The semiconductor substrate has an active region, a wiring region outside the active region, and a termination region outside the wiring region. The semiconductor device according to claim 1, characterized in that the wiring is provided in the wiring region.

3. A semiconductor substrate having an active region, a wiring region outside the active region, and a termination region outside the wiring region, Wiring provided on the aforementioned wiring area, A protective film covering at least a portion of the aforementioned wiring, Equipped with, The wiring comprises a first metal layer and a second metal layer provided on the first metal layer and containing a metal that has higher moisture resistance or acid resistance than the first metal layer. The semiconductor device is characterized in that the protective film is provided extending from the upper surface of the second metal layer to the side surfaces on both sides of the first metal layer.

4. The semiconductor device according to claim 3, characterized in that, in the wiring, the contact portion between the first metal layer and the second metal layer is not exposed to the member provided on the protective film.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that the aforementioned wiring is the wiring located furthest towards the termination region within the wiring region.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that the entire upper surface and both sides of the first metal layer are covered by the second metal layer.

7. The pad electrode comprises a third metal layer provided on the active region, and a fourth metal layer provided on the third metal layer, the fourth metal layer containing a metal having higher moisture resistance or acid resistance than the third metal layer. The pad electrode has a pad opening formed in which the third metal layer is exposed from the fourth metal layer. The semiconductor device according to any one of claims 2 to 4, characterized in that the contact portion between the third metal layer and the fourth metal layer facing the pad opening is covered with the protective film.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that the aforementioned wiring is gate wiring.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that the aforementioned wiring is source wiring or emitter wiring.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that the second metal layer includes Ti, Au, or Pt.

11. The semiconductor device according to any one of claims 1 to 4, characterized in that the first metal layer comprises Al or Cu.

12. The semiconductor device according to any one of claims 1 to 4, characterized by comprising a polyimide film provided on the protective film.

13. The semiconductor device according to claim 12, characterized in that the polyimide film covers the corners of the wiring.

14. The semiconductor device according to any one of claims 1 to 4, characterized in that the protective film is a nitride film or an oxide film.

15. The semiconductor device according to any one of claims 1 to 4, characterized in that the semiconductor substrate is formed of a wide-bandgap semiconductor.

16. The semiconductor device according to claim 15, characterized in that the wide-bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

17. Semiconductor substrate and A pad electrode provided on the semiconductor substrate, A protective film provided on the pad electrode, Equipped with, The pad electrode comprises a first metal layer and a second metal layer provided on the first metal layer and containing a metal that has higher moisture resistance or acid resistance than the first metal layer. The pad electrode has a pad opening formed in which the first metal layer is exposed from the second metal layer. A semiconductor device characterized in that the contact portion between the first metal layer and the second metal layer facing the pad opening is covered with the protective film.

Images