Semiconductor device and memory access method

Abstract

The CPU can deliver performance tailored to its specific application when accessing memory. [Solution] A semiconductor device comprising a CPU, a cache memory, and a plurality of memories, wherein each of the plurality of memories can be switched between being connected to the CPU via the cache memory or being connected to the CPU without going through the cache memory.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a memory access method.

Background Art

[0002] There is known a semiconductor device such as a microcomputer in which a memory such as an internal memory is connected to a CPU (Central Processing Unit) via a cache memory (see, for example, Patent Document 1).

[0003] In such a semiconductor device, by temporarily storing a copy of the data stored in the memory in the cache memory, the data can be placed near the CPU, enabling high-speed access to the data.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

[0005] [Summary] In the above semiconductor device, data having a size larger than the unit of access from the CPU is copied to the cache memory. Therefore, when a copy is not pre-stored in the cache memory, access is made to the memory of the copy source to read the data, resulting in a longer access time and a situation where the processing speed of the CPU may become longer than expected. Therefore, when using the semiconductor device for an application with a predetermined processing speed, problems may occur.

[0006] The technology of the present disclosure has been made in view of the above points, and provides a semiconductor device and a memory access method that can exhibit performance according to the application for access between the CPU and the memory.

[0007] The semiconductor device of this disclosure comprises a CPU, a cache memory, and a plurality of memories, each of which is switchable between being connected to the CPU via the cache memory or being connected to the CPU without the cache memory. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a diagram illustrating an example of an access path from the CPU in a semiconductor device according to an embodiment. [Figure 3] Figure 3 is a block diagram showing an example of a conventional semiconductor device configuration. [Detailed explanation]

[0009] An example of an embodiment of the disclosed technology will be described below with reference to the drawings. Note that the dimensional ratios in the drawings are exaggerated for illustrative purposes and may differ from actual ratios.

[0010] Figure 1 shows a block diagram illustrating an example of the configuration of the semiconductor device 10 of this embodiment. The semiconductor device 10 of this embodiment includes a CPU (Central Processing Unit) 12, a cache memory 14, a DMAC (Direct Memory Access Controller) 16, an AHB (Advanced High-performance Bus)-SRAM (Static Read Only Memory) bridge 18, 20, a flash ROM (Read Only Memory) 22, an external memory 24, a MUX (Multiplexer) 26, a boot control circuit 30, and SRAMs 1 to 4.

[0011] The CPU 12 and the AHB-SRAM bridge 18 are connected via the AHB 13. The AHB-SRAM bridge 18 and SRAMs 1-4 are connected via the MUX 26. In other words, each of SRAMs 1-4 can be connected to the CPU 12 via the AHB-SRAM bridge 18.

[0012] Furthermore, the CPU 12 and the cache memory 14 are connected via the AHB 13. The cache memory 14 temporarily stores copies of the data stored in SRAM 1-4, thereby keeping the data close to the CPU 12. By keeping the data close to the CPU 12 in this way, access to the data from the CPU 12 can be made faster.

[0013] The cache memory 14, DMAC 16, AHB-SRAM bridge 20, flash ROM 22, and external memory 24 are connected via AHB 19. That is, the flash ROM 22 and external memory 24 are each connected to the CPU 12 via the cache memory 14.

[0014] Furthermore, the AHB-SRAM bridge 20 and SRAMs 1-4 are connected via the MUX 26. In other words, each of SRAMs 1-4 can be connected to the CPU 12 via the cache memory 14 through the AHB-SRAM bridge 20.

[0015] The flash ROM 22 stores the connection destination settings for SRAM 1 to 4 in advance, according to the application of the semiconductor device 10. For example, if the connection is via the cache memory 14, the setting value is set to "0", and if the connection is not via the cache memory 14, the setting value is set to "1". The flash ROM 22 in this embodiment is an example of the setting unit of this disclosure. In this case, for example, if "0001" is set in the flash ROM 22, as shown in Figure 2, SRAM 1 will be connected to the CPU 12 without going through the cache memory 14, and each of SRAM 2 to 4 will be connected to the CPU 12 via the cache memory 14. In Figure 2, the access path from the CPU 12 to SRAM 1 to 4 is shown by a dotted line.

[0016] The boot control circuit 30, when the semiconductor device 10 is started up, i.e., during boot-up, refers to the setting value set in the flash ROM 22 and sets the connection destination for each of the SRAMs 1 to 4 in the MUX 26. In the example shown in Figure 2, the operating unit 230 refers to the setting value "0001" set in the flash ROM 22 and sets SRAM 1 to be connected directly to the CPU 12 without going through the cache memory 14, specifically to be connected to the AHB-SRAM bridge 18. The boot control circuit 30 also sets each of the SRAMs 2 to 4 to be connected to the CPU 12 via the cache memory 14, specifically to be connected to the AHB-SRAM bridge 20.

[0017] The MUX26 switches whether each of the SRAMs 1 to 4 is connected to the CPU 12 via the cache memory 14 or connected to the CPU 12 without going through the cache memory 14, according to the settings of the boot control circuit 30. The MUX26 in this embodiment is an example of the switching unit of this disclosure.

[0018] In the example shown in Figure 2, depending on the switching of MUX26, SRAM1, which is connected to the CPU12 without going through the cache memory 14, becomes accessible from the CPU12 regardless of the state of the cache memory 14. Specifically, the processing speed is determined not by the access unit of the cache memory 14 (e.g., 16 bytes or 32 bytes or more), but by the access unit from the CPU12 (e.g., 1 to 4 bytes). Therefore, when the CPU12 accesses SRAM1, it is possible to access it at a constant speed. The CPU12 is able to execute programs at a constant speed.

[0019] Therefore, when the semiconductor device 10 is used for motor control, or in other applications where the amount of processing performed by the CPU 12 within a certain period of time is predetermined, one or more of the SRAMs 1 to 4 required for that application should be configured in the flash ROM 22 so that they are connected to the CPU 12 without going through the cache memory 14.

[0020] As described above, the semiconductor device 10 of this embodiment includes a CPU 12, a cache memory 14, and SRAMs 1 to 4. Each of the SRAMs 1 to 4 of the semiconductor device 10 can be switched between being connected to the CPU 12 via the cache memory 14 or being connected to the CPU 12 without going through the cache memory 14.

[0021] However, in the conventional semiconductor device 100 shown in Figure 3, each of the SRAMs 1 to 4 is connected to the CPU 12 only via the cache memory 14. Therefore, unlike the semiconductor device 10 of this embodiment, it may not be able to handle applications where the amount of processing performed by the CPU 12 within a certain period of time is predetermined. On the other hand, in the semiconductor device 10 of this embodiment, depending on the application, it is possible to switch whether each of the SRAMs 1 to 4 is connected to the CPU 12 via the cache memory 14 or connected to the CPU 12 without going through the cache memory 14. Therefore, according to the semiconductor device 10 of this embodiment, the CPU 12 can access the SRAMs 1 to 4 and achieve performance according to the application.

[0022] In the above embodiment, the semiconductor device 10 has been described as including four SRAMs. However, the number of SRAMs included in the semiconductor device 10 is not limited to four. It may be three or less, or five or more. Further, not only SRAMs but other memories may be used.

[0023] Also, each of the above embodiments is merely an example, and any modification or improvement can be applied.

[0024] One or more elements included in one of the above multiple embodiments can be combined with one or more elements included in other embodiments among the above multiple embodiments.

[0025] (Additional clause) (Additional clause 1) A CPU, a cache memory, and a plurality of memories, and each of the plurality of memories can be switched between being connected to the CPU via the cache memory or being connected to the CPU without passing through the cache memory. A semiconductor device.

[0026] (Additional clause 2) For each of the plurality of memories, a setting unit that sets a connection destination, and a switching unit that switches, for each of the plurality of memories according to the setting of the setting unit, between being connected to the CPU via the cache memory and being connected to the CPU without passing through the cache memory. The semiconductor device according to claim 1, further comprising the above.

[0027] (Additional clause 3) Each of the plurality of memories is an SRAM. The semiconductor device according to claim 1 or claim 2.

[0028] (Claim 4) The switching unit, Depending on the settings, it switches whether each of the multiple memory modules is connected to the CPU via cache memory or directly to the CPU without going through the cache memory. Memory access method. [Explanation of Symbols]

[0029] 1-4 SRAM 10 Semiconductor Devices 12 CPU 13, 19 AHB 16 DMAC 18, 20 AHB-SRAM Bridge 14 Cache memory 22 Flash ROM 24 External memory 26 MUX 30 Boot-time control circuit

Claims

1. CPU and, Cache memory and Equipped with multiple memory modules, Each of the aforementioned plurality of memories can be switched between being connected to the CPU via the cache memory or being connected to the CPU without going through the cache memory. Semiconductor equipment.

2. Each of the aforementioned multiple memories includes a setting unit for setting the connection destination, and a switching unit that, according to the settings of the setting unit, switches whether each of the plurality of memories is connected to the CPU via the cache memory or connected to the CPU without going through the cache memory, The semiconductor device according to claim 1, further comprising:

3. Each of the aforementioned multiple memories is SRAM. The semiconductor device according to claim 1.

4. The switching part is Depending on the settings, it switches whether each of the multiple memory modules is connected to the CPU via cache memory or directly to the CPU without going through the cache memory. Memory access method.

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