Semiconductor equipment

Abstract

To provide semiconductor devices that can contribute to Sustainable Development Goals (SDGs) 7, 8, 9, 11, and 12. [Solution] A semiconductor device comprising a package and an integrated circuit chip mounted on an internal substrate of the package, wherein the integrated circuit chip has a plurality of terminals, a control unit, and a plurality of functional circuits, the internal substrate is provided with a first wire connected to a first terminal among the plurality of terminals and a second wire connected to a second terminal among the plurality of terminals, and the control unit determines the type of package based on the potential of the first terminal and the potential of the second terminal, and controls the operation of the plurality of functional circuits according to the type of package.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Semiconductor devices are used in almost all current electronic products. Due to their use in countless electronic products, there is an increasing demand for miniaturization, multifunctionality, and cost reduction of semiconductor devices. Furthermore, recently, in order for humanity to continue living stably on Earth, consideration for human society and the global environment with respect to electronic products is also required. On September 25, 2015, at the United Nations Summit held at the United Nations Headquarters in New York, the "2030 Agenda for Sustainable Development" centered on the "Sustainable Development Goals (SDGs)" was adopted, and since then, various efforts have been made by governments and enterprises around the world to achieve the goals.

[0003] For example, Patent Document 1 describes a semiconductor device in which semiconductor elements are mounted on a substrate for a semiconductor device, and by simplifying the structures of the mounting pad main body and the external electrode main body, and providing a substrate for a semiconductor device having a mounting pad main body and an external electrode main body that are not sensitive to magnetism at a lower cost, it is expected to contribute to the achievement of Goals 9 and 12 of the Sustainable Development Goals (SDGs) proposed by the United Nations.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The structural innovations and production of semiconductor devices are related to SDGs Goals 7, 8, 9, 11, and 12. Specifically, they are related to the following goals: Goal 7: Ensure everyone has access to affordable, stable, and modern energy. Goal 8: Enable the world to use resources more efficiently in consumption and production. Goal 9: Make infrastructure and industries sustainable by using resources more efficiently and adopting more environmentally friendly technologies and production methods. Goal 11: Reduce the per capita environmental impact of urban dwellers, particularly by paying special attention to air quality and waste management. Goal 12: Manage natural resources sustainably and use them efficiently.

[0006] Thus, modern semiconductor devices are required not only to be miniaturized, multifunctional, and low-cost, but also to contribute to the SDGs through structural innovations and production methods. There is a need for semiconductor devices that can solve the various challenges mentioned above. [Means for solving the problem]

[0007] One aspect of the semiconductor device according to the present invention is The package and The package comprises an integrated circuit chip mounted on an internal substrate of the package, The aforementioned integrated circuit chip has a plurality of terminals, a control unit, and a plurality of functional circuits. The internal circuit board is provided with a first wire connected to a first terminal among the plurality of terminals, and a second wire connected to a second terminal among the plurality of terminals. The control unit, based on the potential of the first terminal and the potential of the second terminal, the package The type of package is determined, and the operation of the multiple functional circuits is controlled according to the type of package. [Brief explanation of the drawing]

[0008] [Figure 1]This is a perspective view of the external appearance of an electronic device. [Figure 2] This is a diagram showing an example of the functional configuration of an electronic device. [Figure 3] This is a cross-sectional view showing the structure of a semiconductor device. [Figure 4] This is a transparent view of the terminal mounting side of package 330a. [Figure 5] This is a transparent view of the terminal mounting side of package 330b. [Figure 6] This is a functional block diagram of an integrated circuit chip. [Figure 7] This figure shows an example of the correspondence between the potential of the terminals of an integrated circuit chip and the package. [Figure 8] This is a plan view of a portion of the printed circuit board 400A. [Figure 9] This is a plan view of a portion of the printed circuit board 400B. [Figure 10] This figure shows a semiconductor device mounted on a printed circuit board 400A. [Figure 11] This figure shows a semiconductor device mounted on a printed circuit board 400B. [Figure 12] This figure shows an example of the correspondence between the mode of the control unit and the signal propagating to the terminals of the semiconductor device. [Modes for carrying out the invention]

[0009] Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for illustrative purposes only. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are essential components of the present invention.

[0010] In the following, the electronic device of this embodiment will be described using a multifunction printer equipped with printing and scanning functions as an example of the electronic device according to the present invention.

[0011] 1. Structure of electronic devices FIG. 1 is an external perspective view of the electronic device 1. In the following description, the X direction, Y direction, and Z direction perpendicular to each other will be used. Also, the starting side of the arrow indicating the X direction is referred to as the -X side, the tip side is referred to as the +X side, the starting side of the arrow indicating the Y direction is referred to as the -Y side, the tip side is referred to as the +Y side, and the starting side of the arrow indicating the Z direction may be referred to as the -Z side and the tip side as the +Z side.

[0012] The electronic device 1 includes a device main body 12 having a substantially rectangular parallelepiped shape as a whole. The device main body 12 includes a recording device 13 that records on paper, and an image reading device 10 that is provided on the recording device 13 and reads information such as pictures, characters, and photographs formed on the placed original manuscript to generate an image. For example, the image generated by the image reading device 10 is printed on paper by the recording device 13.

[0013] The image reading device 10 includes an ADF (Auto Document Feeder) 27 that is an automatic document feeder. The ADF 27 is provided rotatably with the back side of the device main body 12, which is the -Y side, as the fulcrum of the rotation axis J, and also functions as a top plate that can be opened and closed with respect to the upper part of the device main body 12.

[0014] The ADF 27 includes a document conveyance unit 28 having a drive mechanism for conveying documents, a document placement surface 40, and a document discharge surface 42. The document placed on the document placement surface 40 is fed into the image reading device 10 by the document conveyance unit 28, read, and then discharged and placed on the document discharge surface 42.

[0015] On the upper part of the front side, which is the +Y side of the device main body 12, an operation unit 16 is provided, and the operation unit 16 is configured to include a power button, a print setting button, a display panel, etc. for operating the electronic device 1.

[0016] On the back side, which is the -Y side of the device main body 12, a back side tray 24 on which paper is placed is provided. The paper placed on the back side tray 24 is fed to the recording device 13 and recorded.

[0017] The bottom side of the front tray 22, which is the -Z side, is provided with a paper storage section 26 that can accommodate multiple sheets of paper. The paper storage section 26 is slidably mounted in the Y direction at the bottom of the device body 12 and is configured to be detachable from the device body 12. Paper placed in the paper storage section 26 is fed to the recording device 13 and recorded.

[0018] The front side of the main body 12 of the device is provided with a drawer unit 20 that is attached to the front tray 22 and slides in the Y direction. Paper that has been fed from the rear tray 24 or the paper storage unit 26 to the recording device 13 and recorded is discharged from an opening 18 provided on the front side of the main body 12 of the device and placed on the front tray 22 and the drawer unit 20 when it is pulled out from the front tray 22.

[0019] 2. Functional configuration of electronic devices Figure 2 shows an example of the functional configuration of electronic device 1. As shown in Figure 2, electronic device 1 has a main board 50, a sub-board 51, and a sub-board 52. The main board 50 and the sub-boards 51 and 52 are, for example, multilayer printed circuit boards.

[0020] The main board 50 is equipped with a semiconductor device 100 having an integrated circuit chip 200, a motor driver 110, a head drive IC 120, a serial flash memory 130, DDR 140, a power supply circuit 190, and a reset IC 192. DDR is an abbreviation for Double-Data-Rate SDRAM. The main board 50 is also provided with connectors 151, 152, 153, and 154.

[0021] The sub-board 51 has an LCD control IC 160 mounted on it. The sub-board 51 is connected to the main board 50 by a cable 71.

[0022] The sub-board 52 has an SD control IC 170 mounted on it, and a connector 181 is also provided. The sub-board 52 is connected to the main board 50 by a cable 72.

[0023] Furthermore, the electronic device 1 includes various motors 61, a print head 62, a scanner module 63, a wireless LAN module 64, and an LCD 65. LAN stands for Local Area Network. LCD stands for Liquid Crystal Display.

[0024] The motor 61 is connected to the main board 50 via a connector 151 and is driven by a motor driver 110.

[0025] The print head 62 is provided in the recording device 13 and is connected to the main board 50 via a connector 152, and is driven by the head drive IC 120.

[0026] The scanner module 63 is provided in the image reading device 10, connected to the main board 50 via a connector 153, and controlled by the integrated circuit chip 200. The scanner module 63 also scans the original document and transmits the generated scan data to the integrated circuit chip 200.

[0027] The wireless LAN module 64 is a module that performs wireless data communication with an external device of the electronic device 1. The wireless LAN module 64 is connected to the main board 50 via cable 73 and is controlled by the integrated circuit chip 200. The wireless LAN module 64 also communicates with the integrated circuit chip 200 via USB.

[0028] The LCD65 is a display panel included in the operation unit 16 that displays various information. The LCD65 is connected to the sub-board 51 via cable 74 and is controlled by the LCD control IC 160.

[0029] The LCD control IC 160 is connected to the LCD 65 via cable 74 and is a circuit that controls the display of various information on the LCD 65. The LCD control IC 160 is controlled by the integrated circuit chip 200.

[0030] The SD control IC 170 is a circuit that controls the writing and reading of data to and from the SD card 3 inserted into the connector 181. The SD control IC 170 is controlled by the integrated circuit chip 200. The SD control IC 170 also communicates with the integrated circuit chip 200 via USB.

[0031] The motor driver 110 is connected to the motor 61 via a connector 151 and is the circuit that drives the motor 61. The motor driver 110 is controlled by an integrated circuit chip 200.

[0032] The head drive IC 120 is connected to the print head 62 via connector 152 and is the circuit that drives the print head 62. The head drive IC 120 is controlled by the integrated circuit chip 200.

[0033] The serial flash memory 130 and DDR140 are storage devices that store various types of data, and the writing and reading of data are controlled by the integrated circuit chip 200.

[0034] The power supply circuit 190 supplies power to the semiconductor device 100, motor driver 110, head drive IC 120, serial flash memory 130, and DDR140. For example, the power supply circuit 190 generates a power supply voltage of several volts and supplies it to the semiconductor device 100, motor driver 110, head drive IC 120, serial flash memory 130, and DDR140. The power supply circuit 190 also generates a power supply voltage of several tens of volts to drive the motor 61 and print head 62 and supplies it to the motor driver 110 and head drive IC 120. The power supply circuit 190 is controlled by the integrated circuit chip 200.

[0035] The reset IC 192 monitors the power supply voltage and other parameters of the semiconductor device 100 and resets the semiconductor device 100 if it detects an abnormality. The reset IC 192 is controlled by the integrated circuit chip 200.

[0036] Thus, the integrated circuit chip 200 is an SoC that controls the motor driver 110, head drive IC 120, serial flash memory 130, DDR 140, scanner module 63, wireless LAN module 64, LCD control IC 160, SD control IC 170, power supply circuit 190, and reset IC 192. SoC is an abbreviation for System On Chip.

[0037] Furthermore, the integrated circuit chip 200 is connected to an external PC 2 of the electronic device 1 via a connector 154, and communicates data with the PC 2. The connector 154 is, for example, a USB It is a connector.

[0038] 3. Structure of a semiconductor device Figure 3 is a cross-sectional view showing the structure of the semiconductor device 100. In the following explanation, we will use the x, y, and z directions, which are independent of the X, Y, and Z directions shown in Figure 1 and are mutually orthogonal. Furthermore, the starting point of the arrow indicating the x direction may be referred to as the -x side and the tip as the +y side; the starting point of the arrow indicating the y direction may be referred to as the -y side and the tip as the +y side; and the starting point of the arrow indicating the z direction may be referred to as the -z side and the tip as the +z side.

[0039] As shown in Figure 3, the semiconductor device 100 comprises a base substrate 300, an integrated circuit chip 200, and a housing 350.

[0040] The housing 350 is located on the +z side of the integrated circuit chip 200 and is bonded to the base substrate 300 so as to cover the integrated circuit chip 200. The housing 350 contains epoxy resin or the like to protect the integrated circuit chip 200.

[0041] A base substrate 300 is located on the -z side of the integrated circuit chip 200. The integrated circuit chip 200 is mounted on the base substrate 300 by a bonding material 370 such as an adhesive. The base substrate 300 and the integrated circuit chip 200 are electrically connected via bonding wires 380.

[0042] The base substrate 300 is provided with multiple wiring patterns and multiple electrodes (not shown). The bonding wire 380 is electrically connected to electrodes (not shown) formed on the +z side of the base substrate 300. Multiple electrodes (not shown) are also provided on the -z side of the base substrate 300. Solder balls 310 are attached to each of the electrodes on the -z side of the base substrate 300. In other words, the base substrate 300 is provided with multiple solder balls 310, which are ball-shaped terminals. The printed circuit board 400, which is the main board 50 in Figure 2, is provided with multiple pads 410 and multiple wirings (not shown), and each of the multiple solder balls 310 is joined to each of the multiple pads 410. The base substrate 300 is electrically connected to the printed circuit board 400 by the multiple solder balls 310. The multiple solder balls 310 constitute a so-called ball grid array that electrically and mechanically connects the base substrate 300 and the printed circuit board 400. In the following explanation, the -z side of the base board 300 to which multiple solder balls 310 are attached will be referred to as the terminal mounting surface 301.

[0043] The package 330 is composed of a base substrate 300, a housing 350, and a ball grid array consisting of multiple solder balls 310. The integrated circuit chip 200 is mounted on the base substrate 300, which is the internal substrate of the package 330.

[0044] In the semiconductor device 100 configured as described above, signals input to the semiconductor device 100 via a plurality of solder balls 310 provided on the terminal mounting surface 301 propagate through electrodes and wiring patterns provided on the base substrate 300 and bonding wires 380, and are input to the integrated circuit chip 200. Furthermore, signals output from the integrated circuit chip 200 are input to a plurality of pads 410 on the printed circuit board 400 via the bonding wires 380, electrodes and wiring patterns provided on the base substrate 300 and the plurality of solder balls 310.

[0045] In this embodiment, the integrated circuit chip 200 can be mounted in multiple types of packages 330. Hereinafter, the integrated circuit chip 200 will be described as being mounted in one of four types of packages: packages 330a, 330b, 330c, and 330d. The types of package 330 on which the path chip 200 is mounted are not limited to four types. In the following, when package 330 is described as one of packages 330a, 330b, 330c, or 330d, the designations "a", "b", "c", or "d" will also be added to the symbols of its components.

[0046] Figure 4 shows a transparent view of the terminal mounting surface 301a of the base substrate 300a of package 330a, viewed from the +z side. Figure 5 shows a transparent view of the terminal mounting surface 301d of the base substrate 300d of package 330d, viewed from the +z side. Package 330a is a small package; for example, the terminal mounting surface 301a is 12mm x 12mm in size. Package 330d is a large package; for example, the terminal mounting surface 301d is 16mm x 16mm in size.

[0047] As shown in Figure 4, the base substrate 300a of the package 330a has a side 302a extending in the x direction, a side 303a extending in the x direction and opposite to side 302a, a side 304a extending in the y direction, and a side 305a extending in the y direction and opposite to side 304a. Each of sides 304a and 305a intersects with sides 302a and 303a. In other words, the base substrate 300a is roughly rectangular in shape with sides 302a, 303a, 304a, and 305a as its outer periphery.

[0048] As shown in Figure 4, on the terminal mounting surface 301a of the base board 300a, multiple solder balls 310a are distributed in a grid pattern in 23 rows in the y direction, with a maximum of 23 solder balls 310a in each row. Solder balls 310a connected to the motor driver 110, head drive IC 120, serial flash memory 130, DDR 140, and connectors 151, 152, 153, 154, etc., are located at or near the outermost edge of the terminal mounting surface 301a. The multiple solder balls 310a located at the outermost edge are spaced further apart to ensure space for wiring connected to the solder balls 310a inside them. In addition, power supply voltage is supplied to the multiple solder balls 310a located in the central area enclosed by the dashed line on the terminal mounting surface 301a.

[0049] As shown in Figure 5, the base substrate 300d of the package 330d has a side 302d extending in the x direction, a side 303d extending in the x direction and opposite to side 302d, a side 304d extending in the y direction, and a side 305d extending in the y direction and opposite to side 304d. Sides 304d and 305d intersect with sides 302d and 303d, respectively. That is, the base substrate 300d is roughly rectangular in shape with sides 302d, 303d, 304d, and 305d as its outer periphery.

[0050] As shown in Figure 5, on the terminal mounting surface 301d of the base board 300d, multiple solder balls 310d are distributed in a staggered pattern in 25 rows in the y direction, with a maximum of 15 solder balls 310d in each row. Solder balls 310d connected to the motor driver 110, head drive IC 120, serial flash memory 130, DDR 140, and connectors 151, 152, 153, 154, etc., are located at or near the outermost edge of the terminal mounting surface 301d. In addition, power supply voltage is supplied to multiple solder balls 310d located in the central area enclosed by the dashed line on the terminal mounting surface 301d.

[0051] 4. Functional configuration of an integrated circuit chip Figure 6 is a functional block diagram of the integrated circuit chip 200. As shown in Figure 6, the integrated circuit chip 200 includes a control unit 210, USB interface circuits 221, 222, 223, memory interface circuits 231, 232, n GPIOs 241-1 to 241-n, a clock signal generation circuit 250, and a storage unit 260. GPIO is an abbreviation for General-Purpose Input / Output. Note that the integrated circuit chip 200 includes some of the components shown in Figure 6. The configuration may be modified by omitting or changing components, or by adding other components.

[0052] The clock signal generation circuit 250 generates and outputs clock signals CKU1, CKU2, CKU3, CKM1, CKM2, and CK. For example, the clock signal generation circuit 250 may generate clock signals CKU1, CKU2, CKU3, CKM1, CKM2, and CK by dividing or multiplying the source oscillation signal obtained by oscillating a crystal oscillator (not shown) mounted on the base board 300. Clock signals CKU1, CKU2, and CKU3 are supplied to USB interface circuits 221, 222, and 223, respectively. Clock signals CKM1 and CKM2 are supplied to memory interface circuits 231 and 232, respectively. Clock signal CK is supplied to the control unit 210.

[0053] USB interface circuit 221 is connected to terminal group T1G, which includes multiple terminals of the integrated circuit chip 200. USB interface circuit 222 is connected to terminal group T2G, which includes multiple terminals of the integrated circuit chip 200. USB interface circuit 223 is connected to terminal group T3G, which includes multiple terminals of the integrated circuit chip 200. Memory interface circuit 231 is connected to terminal group T4G, which includes multiple terminals of the integrated circuit chip 200. Memory interface circuit 232 is connected to terminal group T5G, which includes multiple terminals of the integrated circuit chip 200. Control unit 210 is connected to terminal group T6G, which includes multiple terminals of the integrated circuit chip 200.

[0054] The terminal groups T1G to T6G of the integrated circuit chip 200 are connected to the terminal groups S1G to S6G of the semiconductor device 100, respectively. Each terminal included in the terminal groups S1G to S6G of the semiconductor device 100 is a solder ball 310 provided on the terminal mounting surface 301. Terminal group S1G of the semiconductor device 100 is connected to PC2 via connector 154. Terminal group S2G of the semiconductor device 100 is connected to SD control IC 170 via cable 72. Terminal group S3G of the semiconductor device 100 is connected to wireless LAN module 64 via cable 73. Terminal group S4G of the semiconductor device 100 is connected to serial flash memory 130. Terminal group S5G of the semiconductor device 100 is connected to DDR140. Terminal group S6G of the semiconductor device 100 is connected to LCD control IC 160.

[0055] GPIO241-1 to 241-n are connected to terminals T1 to Tn of the integrated circuit chip 200, respectively. Terminals T1 to Tn of the integrated circuit chip 200 are connected to terminals S1 to Sn of the semiconductor device 100, respectively. Terminals S1 to Sn of the semiconductor device 100 are solder balls 310 provided on the terminal mounting surface 301. Terminals Tp and Tq of the integrated circuit chip 200 are connected to wirings 321 and 322 provided on the base substrate 300 of the package 330, respectively. On the base substrate 300, wiring 321 is fixed to the power supply potential or ground potential, and wiring 322 is fixed to the power supply potential or ground potential. In Figure 6, wiring 321 is fixed to the power supply potential and wiring 322 is fixed to ground potential.

[0056] The memory unit 260 includes a ROM 261, a RAM 262, and a register 263. ROM stands for Read Only Memory, and RAM stands for Random Access Memory. ROM 261 stores various programs and predetermined data. RAM 262 is used as a workspace for the control unit 210 and stores programs and data read from ROM 261, as well as data temporarily generated by the control unit 210. Register 263 stores various setting data, etc.

[0057] The control unit 210 performs various control and image processing functions. In this embodiment, the control unit 210 is a processor such as a CPU, and performs various control and image processing functions by executing a program (not shown) stored in the ROM 261. However, some of the processing of the control unit 210 may be implemented in hardware.

[0058] Specifically, the control unit 210 performs various controls on the motor driver 110, the head drive IC 120, the scanner module 63, and the LCD control IC 160.

[0059] Furthermore, the control unit 210 communicates with PC2 via USB by controlling the USB interface circuit 221. The control unit 210 also communicates with SD control IC 170 via USB by controlling the USB interface circuit 222. Additionally, the control unit 210 communicates with the wireless LAN module 64 via USB by controlling the USB interface circuit 223. Finally, the control unit 210 transmits image data to the LCD control IC 160.

[0060] Furthermore, the control unit 210 controls the memory interface circuit 231 to write and read data to and from the serial flash memory 130. The control unit 210 also controls the memory interface circuit 232 to write and read data to and from the DDR140.

[0061] For example, the control unit 210 receives image data for printing from PC2 via USB interface circuit 221 and writes it to serial flash memory 130 or DDR140. Also, for example, the control unit 210 receives image data stored on SD card 3 from SD control IC 170 via USB interface circuit 222 and writes it to serial flash memory 130 or DDR140. Also, for example, the control unit 210 receives image data from wireless LAN module 64 via USB interface circuit 223 and writes it to serial flash memory 130 or DDR140. Also, for example, the control unit 210 acquires scan data from scanner module 63, performs image processing on the scan data to generate image data, and writes it to serial flash memory 130 or DDR140.

[0062] Furthermore, for example, the control unit 210 writes the image data generated by performing image processing on the scan data to the serial flash memory 130 or DDR140.

[0063] Furthermore, for example, the control unit 210 reads image data for printing from the serial flash memory 130 or DDR140, performs image processing for printing to generate print data, and outputs it to the head drive IC 120. Also, for example, the control unit 210 reads image data from the serial flash memory 130 or DDR140 and transmits it to the PC2 via the USB interface circuit 221. Also, for example, the control unit 210 reads image data from the serial flash memory 130 or DDR140 and transmits it to the SD control IC 170 via the USB interface circuit 222. Also, for example, the control unit 210 reads image data from the serial flash memory 130 or DDR140 and transmits it to the wireless LAN module 64 via the USB interface circuit 223.

[0064] Furthermore, the control unit 210 controls the input and output of each of the GPIO241-1 to 241-n. Specifically, the control unit 210 controls each of the GPIO241-1 to 241-n to function as either an input / output circuit, an input circuit, or an output circuit. For example, the control unit 210 may control GPIO241-k and Tl of the GPIO241-1 to 241-n to function as output circuits, and output control signals from terminals Tk and Tl to the power supply circuit 190 and the reset IC 192, respectively.

[0065] Furthermore, in this embodiment, the control unit 210 is supplied with the potentials of terminals Tp and Tq. Based on the potentials of terminals Tp and Tq, the control unit 210 determines the type of package 330 on which the integrated circuit chip 200 is mounted. That is, the control unit 210 determines the potentials of terminals Tp and Tq. Based on the potential of q, it is determined whether package 330 is package 330a, 330b, 330c, or 330d.

[0066] Figure 7 shows an example of the correspondence between the potentials of terminals Tp and Tq and packages 330a, 330b, 330c, and 330d. In the example in Figure 7, the control unit 210 determines that package 330 is package 330a when the potentials of terminals Tp and Tq are both at a low level. Package 330a is a small package, and the electronic device 1 on which the semiconductor device 100 is mounted belongs to group 1 of models with significant functional limitations.

[0067] Furthermore, the control unit 210 determines that package 330 is package 330b when the potential of terminal Tp is low and the potential of terminal Tq is high. Package 330b is a medium-sized package, and the electronic device 1 on which the semiconductor device 100 is mounted belongs to group 2 of models with moderate functional limitations.

[0068] Furthermore, the control unit 210 determines that package 330 is package 330c when the potential of terminal Tp is high and the potential of terminal Tq is low. Package 330c is a medium-sized package, and the electronic device 1 on which the semiconductor device 100 is mounted belongs to group 3 of models with minimal functional limitations.

[0069] Furthermore, the control unit 210 determines that package 330 is package 330d when the potentials of terminals Tp and Tq are both at a high level. Package 330d is a large package, and the electronic device 1 on which the semiconductor device 100 is mounted belongs to group 4 of models with no functional limitations.

[0070] Thus, the package sizes increase in the order of 330d, 330c, 330b, and 330a, and the functional limitations of the electronic device 1 on which the semiconductor device 100 is mounted increase in the order of 330a, 330b, 330c, and 330d. Therefore, the control unit 210 controls the operation of each functional circuit, such as the USB interface circuits 221, 222, and 223, the memory interface circuits 231 and 232, and the GPIOs 241-1 to 241-n, according to the type of package 330.

[0071] For example, the control unit 210 may determine, depending on the type of package 330, whether a predetermined terminal Ti of the integrated circuit chip 200 is used as both a CMOS terminal and an LVDS terminal. CMOS is an abbreviation for Complementary Metal Oxide Semiconductor. LVDS is an abbreviation for Low Voltage Differential Signaling. For example, if the package 330 is package 330a, the control unit 210 determines that terminal Ti is dedicated to being either a CMOS terminal or an LVDS terminal, and if the package 330 is package 330d, it determines that terminal Ti is used as both a CMOS terminal and an LVDS terminal.

[0072] Furthermore, depending on the type of package 330, the control unit 210 may fix the potential of each unused terminal Tj of the multiple terminals of the integrated circuit chip 200 to a low level. For example, if terminal T2 is not used, the control unit 210 controls GPIO241-2 to become an output circuit and controls terminal T2 to have a low potential. In this way, the risk of each unused terminal Tj becoming an intermediate potential and causing through-current to flow through elements such as MOSFETs inside the integrated circuit chip 200, thereby damaging them, is reduced, as is the risk of the integrated circuit chip 200 malfunctioning due to noise. In addition, the risk of each terminal Sj of the semiconductor device 100 connected to each unused terminal Tj becoming an intermediate potential is reduced, and the risk of external devices connected to each terminal Sj malfunctioning is reduced.

[0073] Furthermore, the control unit 210, depending on the type of package 330, redirects unused functional circuits to The supply of the clock signal may be stopped. For example, if the control unit 210 determines that package 330 is package 330a, and the functions of the SD card 3 and wireless LAN module 64 are not needed, it controls the clock signal generation circuit 250 to stop supplying clock signals CKU2 and CKU3 to the USB interface circuits 222 and 223. In this way, power consumption is reduced, the rise in internal temperature of the small package 330a, which has poor heat dissipation, is suppressed, and the risk of malfunction of the semiconductor device 100 is reduced.

[0074] Furthermore, the control unit 210 may stop supplying power to unused functional circuits depending on the type of package 330. For example, if the control unit 210 determines that package 330 is package 330a, and the functions of the SD card 3 and wireless LAN module 64 are not needed, it will stop supplying power to the USB interface circuits 222 and 223. In this way, power consumption is reduced, the rise in internal temperature of the small package 330a with poor heat dissipation is suppressed, and the risk of the semiconductor device 100 malfunctioning is reduced.

[0075] Furthermore, the control unit 210 may, depending on the type of package 330, stop supplying clock signals to unused functional circuits and also stop supplying power.

[0076] Furthermore, the control unit 210 does not need to perform initial setup on unused functional circuits depending on the type of package 330. For example, if the control unit 210 determines that package 330 is package 330a, and the functions of the SD card 3 and wireless LAN module 64 are not needed, it will not perform initial setup on the USB interface circuits 222 and 223. In this way, unnecessary initial setup is eliminated, and the startup time of the semiconductor device 100 is shortened.

[0077] Furthermore, the control unit 210 may change the frequency of the clock signal CK depending on the type of package 330. For example, if the control unit 210 determines that package 330 is package 330d, it controls the clock signal generation circuit 250 so that the frequency of the clock signal CK falls within a first frequency range. If the control unit 210 determines that package 330 is package 330c, it controls the clock signal generation circuit 250 so that the frequency of the clock signal CK falls within a second frequency range lower than the first frequency range. If the control unit 210 determines that package 330 is package 330b, it controls the clock signal generation circuit 250 so that the frequency of the clock signal CK falls within a third frequency range lower than the second frequency range. If the control unit 210 determines that package 330 is package 330a, it controls the clock signal generation circuit 250 so that the frequency of the clock signal CK falls within a fourth frequency range lower than the third frequency range. In this way, the larger the package 330, the better the heat dissipation, allowing the control unit 210 to increase the frequency range of the clock signal CK and improve the performance of the semiconductor device 100. Conversely, the smaller the package 330, the worse the heat dissipation, allowing the control unit 210 to lower the maximum frequency of the clock signal CK and reduce power consumption. As a result, the rise in the internal temperature of the package 330 is suppressed, and the risk of malfunction of the semiconductor device 100 is reduced.

[0078] 5. Switching the terminal functions of semiconductor devices In this embodiment, the semiconductor device 100 can be mounted on multiple types of printed circuit boards 400. In the following description, the semiconductor device 100 will be described as being mountable on either of two types of printed circuit boards 400A or 400B, but the types of printed circuit boards 400 on which the semiconductor device 100 is mounted are not limited to these two types. Printed circuit boards 400A and 400B correspond to the main board 50 shown in Figure 2.

[0079] Figure 8 is a plan view of a portion of the printed circuit board 400A, viewed from the +z side. The printed circuit board 400A is provided with a plurality of pads 410, and as shown in Figure 8, the plurality of pads 410 include pads P1A, P2A, P3A, P4A, P5A, P6A, P7A, P11A, P12A, P13A, P14A, P15A, P16A, and P17A. Each of the plurality of pads 410 is provided at a position corresponding to each of the plurality of solder balls 310, which are the plurality of terminals of the semiconductor device 100, and the semiconductor device 100 is mounted on the printed circuit board 400A by bonding each solder ball 310 to each pad 410. Note that in Figure 8, the edge 302 of the terminal mounting surface 301 is shown as a dashed line. That is, each of pads P2A and P12A is bonded to the outermost solder ball 310 provided on the terminal mounting surface 301.

[0080] Then, when the semiconductor device 100 is mounted on the printed circuit board 400A, each of the multiple pads 410 provided on the printed circuit board 400A is electrically connected to one of the terminals of the semiconductor device 100 and one of the terminals of the integrated circuit chip 200.

[0081] Printed circuit board 400A has multiple wirings, including wirings W1A, W2A, W3A, W4A, W5A, W6A, W7A, W11A, W12A, W13A, W14A, W15A, W16A, and W17A. Furthermore, printed circuit board 400A is a multilayer board and has multiple through-holes, including through-holes TH1A, TH2A, TH11A, and TH12A.

[0082] Wires W1A, W2A, W3A, W4A, W5A, W6A, and W7A are connected to pads P1A, P2A, P3A, P4A, P5A, P6A, and P7A, respectively. Wires W11A, W12A, W13A, W14A, W15A, W16A, and W17A are connected to pads P11A, P12A, P13A, P14A, P15A, P16A, and P17A, respectively. Wire W6A is connected to unshown wiring in another layer via through-hole TH1A. Wire W7A is connected to unshown wiring in another layer via through-hole TH2A. Wire W16A is connected to unshown wiring in another layer via through-hole TH11A. Wiring W17A is connected to wiring (not shown) located on another layer through through-hole TH12A.

[0083] Wiring W5A extends in the y-direction from pad P5A. Wiring W1A extends in the y-direction from pad P1A, passing between pads P5A and P3A. Wiring W4A extends in the y-direction from pad P4A, passing between pads P3A and P15A. Wiring W2A extends in the y-direction from pad P2A, passing between wires W1A and W3A. Wiring W3A extends in the y-direction from pad P3A, passing between wires W2A and W4A. In other words, wires W2A and W3A are located between wires W1A and W4A.

[0084] Wiring W15A extends in the y-direction from pad P15A, passing between wiring W4A and wiring W11A. Wiring W11A extends in the y-direction from pad P11A, passing between pads P15A and pad P13A. Wiring W14A extends in the y-direction from pad P14A. Wiring W12A extends in the y-direction from pad P12A, passing between wiring W11A and wiring W13A. Wiring W13A extends in the y-direction from pad P13A, passing between wiring W12A and wiring W14A. In other words, wirings W12A and W13A are located between wiring W11A and wiring W14A.

[0085] Figure 9 is a plan view of a portion of the printed circuit board 400B as seen from the +z side. As shown in Figure 9, the multiple pads 410 provided on the printed circuit board 400B include pads P1B, P2B, P3B, P4B, P5B, P6B, P7B, P11B, P12B, P13B, P14B, P15B, P16B, and P17B. Each of the multiple pads 410 is a semiconductor The solder balls 310 are positioned at locations corresponding to each of the multiple solder balls 310, which are the multiple terminals of the device 100. Each solder ball 310 is joined to each pad 410, thereby mounting the semiconductor device 100 onto the printed circuit board 400B. In Figure 9, the edge 302 of the terminal mounting surface 301 is shown as a dashed line. That is, each of the pads P2B and P12B is joined to the outermost solder ball 310 provided on the terminal mounting surface 301.

[0086] Then, when the semiconductor device 100 is mounted on the printed circuit board 400B, each of the multiple pads 410 provided on the printed circuit board 400B is electrically connected to one of the terminals of the semiconductor device 100 and one of the terminals of the integrated circuit chip 200.

[0087] Printed circuit board 400B has multiple wirings, including wirings W1B, W2B, W3B, W4B, W5B, W6B, W7B, W11B, W12B, W13B, W14B, W15B, W16B, W17B, W21B, W22B, W23B, and W24B. Furthermore, printed circuit board 400B is a multilayer board and has multiple through-holes, including through-holes TH1B, TH2B, TH11B, and TH12B.

[0088] Wires W1B, W2B, W3B, W4B, W5B, W6B, and W7B are connected to pads P1B, P2B, P3B, P4B, P5B, P6B, and P7B, respectively. Wires W11B, W12B, W13B, W14B, W15B, W16B, and W17B are connected to pads P11B, P12B, P13B, P14B, P15B, P16B, and P17B, respectively. Wire W7B is connected to unshown wiring in another layer via through-hole TH2B. Wire W16B is connected to unshown wiring in another layer via through-hole TH11B. Wire W17B is connected to unshown wiring in another layer via through-hole TH12B.

[0089] Wiring W21B is connected to pads P1B and P4B. Wiring W22B is connected to pads P4B and P11B. Wiring W23B is connected to pads P11B and P14B. Wiring W24B is connected to pad P4B and further connected through through-hole TH1B to an unshown ground pattern in another layer. Therefore, wires W1B, W4B, W11B, W14B, W21B, W22B, W23B, and W24B are at ground potential.

[0090] Wiring W5B extends in the y-direction from pad P5B. Wiring W1B extends in the y-direction from pad P1B, passing between pads P5B and P3B. Wiring W4B extends in the y-direction from pad P4B, passing between pads P3B and P15B. Wiring W2B extends in the y-direction from pad P2B, passing between wires W1B and W3B. Wiring W3B extends in the y-direction from pad P3B, passing between wires W2B and W4B. In other words, wires W2B and W3B are located between the ground potential wires W1B and W4B. Therefore, in the x-direction, the crosstalk between signals propagating through wires W5B and W15B is reduced by the ground potential wires W1B and W4B. Therefore, signals propagating through wiring W2B and W3B are protected from noise caused by signals propagating through wiring W5B and W15B, and signals propagating through wiring W5B and W15B are protected from noise caused by signals propagating through wiring W2B and W3B.

[0091] Furthermore, since there is a ground-potential wire W21B between wires W2B, W3B and wire W6B, the crosstalk between signals propagating through wires W2B, W3B and the signal propagating through wire W6B is reduced in the y-direction by the ground-potential wire W21B. Therefore, the signals propagating through wires W2B, W3B are protected from noise caused by the signal propagating through wire W6B, and the signals propagating through wire W6B are protected from noise caused by the signals propagating through wires W2B, W3B. It is protected from noise.

[0092] In this way, the ground potential wirings W1B, W4B, and W21B protect the wirings W2B, W3B, W5B, W6B, and W15B from noise, thus reducing the risk of unwanted pulses superimposed on any of these wirings causing the semiconductor device 100 to malfunction.

[0093] Wiring W15B extends in the y-direction from pad P15B through wiring W4B and wiring W11B. Wiring W11B extends in the y-direction from pad P11B through pad P15B and pad P13B. Wiring W14B extends in the y-direction from pad P14B. Wiring W12B extends in the y-direction from pad P12B through wiring W11B and wiring W13B. Wiring W13B extends in the y-direction from pad P13B through wiring W12B and wiring W14B. In other words, wirings W12B and W13B are located between wiring W11B and wiring W14B, which are at ground potential. Therefore, in the x-direction, the crosstalk between signals propagating through wiring W12B and W13B and signals propagating through wiring W15B is reduced by the ground potential wirings W11B and W14B. Therefore, signals propagating through wiring W12B and W13B are protected from noise caused by signals propagating through wiring W15B, and signals propagating through wiring W15B are protected from noise caused by signals propagating through wiring W12B and W13B.

[0094] Furthermore, since there is a ground-potential wire W23B between wires W12B, W13B and wire W16B, the crosstalk between signals propagating through wires W12B, W13B and signals propagating through wire W16B is reduced in the y direction by the ground-potential wire W23B. Therefore, signals propagating through wires W12B, W13B are protected from noise caused by signals propagating through wire W16B, and signals propagating through wire W16B are protected from noise caused by signals propagating through wires W12B, W13B.

[0095] In this way, the ground potential wirings W11B, W14B, and W23B protect the wirings W12B, W13B, W15B, and W16B from noise, thus reducing the risk of unwanted pulses superimposed on any of these wirings causing the semiconductor device 100 to malfunction.

[0096] In this embodiment, the integrated circuit chip 200 is mounted on either printed circuit board 400A or printed circuit board 400B. The integrated circuit chip 200 operates in mode A when the semiconductor device 100 is mounted on printed circuit board 400A, and in mode B when the semiconductor device 100 is mounted on printed circuit board 400B. The control unit 210 determines whether the printed circuit board 400 on which the semiconductor device 100 is mounted is printed circuit board 400A or printed circuit board 400B, for example, based on the potential of terminal S1 of the semiconductor device 100, i.e., the potential of terminal T1 of the integrated circuit chip 200. For example, when the potential of terminal T1 is low, the control unit 210 determines that the printed circuit board 400 is printed circuit board 400A and operates in mode A, and when the potential of terminal T1 is high, it determines that the printed circuit board 400 is printed circuit board 400B and operates in mode B.

[0097] In this embodiment, the wiring W7A provided on the printed circuit board 400A is at ground potential, and the wiring W7B provided on the printed circuit board 400B is at power potential. Furthermore, when the semiconductor device 100 is mounted on the printed circuit board 400A, pad P7A is connected to terminal S1 of the semiconductor device 100, and when the semiconductor device 100 is mounted on the printed circuit board 400B, pad P7B is connected to terminal S1 of the semiconductor device 100. Therefore, when the semiconductor device 100 is mounted on the printed circuit board 400A, pad P7A and terminal S1 of the semiconductor device 100 are connected, and as shown in Figure 10, the potential of terminal T1 of the integrated circuit chip 200 becomes ground potential. On the other hand, when the semiconductor device 100 is mounted on the printed circuit board 400B, pad P7B and terminal S1 of the semiconductor device 100 are connected, and as shown in Figure 11, The potential of terminal T1 of the integrated circuit chip 200 is the power supply potential. Therefore, when the potential of terminal T1 is low, the control unit 210 can determine that the printed circuit board 400 on which the semiconductor device 100 is mounted is printed circuit board 400A and operate in mode A, and when the potential of terminal T1 is high, it can determine that the printed circuit board 400 is printed circuit board 400B and operate in mode B.

[0098] For example, when the semiconductor device 100 is mounted on a printed circuit board 400A, pads P1A, P2A, P3A, and P4A are connected to predetermined terminals Sa, Sb, Sc, and Sd of the semiconductor device 100, respectively. When the semiconductor device 100 is mounted on a printed circuit board 400B, pads P1B, P2B, P3B, and P4B are connected to terminals Sa, Sb, Sc, and Sd of the semiconductor device 100, respectively. In mode A and mode B, for example, the signals propagated to terminals Sa, Sb, Sc, and Sd of the semiconductor device 100 are different.

[0099] Figure 12 shows an example of the correspondence between modes A and B and the signals propagating to terminals Sa, Sb, Sc, and Sd. In the example in Figure 12, in mode A, low-speed signals propagate to terminals Sa, Sb, Sc, and Sd. That is, low-speed signals propagate to wiring W1A, W2A, W3A, and W4A provided on printed circuit board 400A. Thus, when the control unit 210 determines that the printed circuit board 400 on which the semiconductor device 100 is mounted is printed circuit board 400A, it sets terminals Sa, Sb, Sc, and Sd to terminals on which low-speed signals propagate. The low-speed signal has a frequency of less than 20 MHz. For example, the low-speed signal may be a CMOS signal such as 3.3V.

[0100] On the other hand, in mode B, high-speed signals propagate through both terminals Sb and Sc, while terminals Sa and Sd are connected to wiring W1A and W4A, and are therefore at ground potential. In other words, high-speed signals propagate through wiring W2A and W3A on printed circuit board 400A, and are protected from noise by ground potential wiring W1B, W4B, and W21B. Thus, when the control unit 210 determines that the printed circuit board 400 on which the semiconductor device 100 is mounted is printed circuit board 400B, it sets terminals Sb and Sc to be terminals through which high-speed signals propagate. High-speed signals have a frequency of 20 MHz or higher.

[0101] For example, the high-speed signal may be a USB communication signal for operating in USB 2.0 High-Speed ​​mode (480MHz). For instance, the signal used by the semiconductor device 100 to communicate with PC2, SD control IC 170, wireless LAN module, etc., is a USB communication signal. Furthermore, the high-speed signal in this case may be a high-speed differential signal consisting of two signals paired together.

[0102] Furthermore, the high-speed signal may also be an LVDS signal. For example, print data output from the semiconductor device 100 to the head drive IC 120, scan data input from the scanner module 63 to the semiconductor device 100, and image data output from the semiconductor device 100 to the LCD control IC 160 may all be LVDS signals. In the electronic device 1 on which the printed circuit board 400B is mounted, the LCD 65 is large and animations are displayed on the LCD 65, so the control unit 210 operates in mode B and transmits high-speed signal image data to the LCD control IC 160 via the terminal group S6G. On the other hand, in the electronic device 1 on which the printed circuit board 400A is mounted, the LCD 65 is small and animations are not displayed on the LCD 65, so the control unit 210 operates in mode A and transmits low-speed signal image data to the LCD control IC 160 via the terminal group S6G.

[0103] Furthermore, for example, when the semiconductor device 100 is mounted on the printed circuit board 400A, pads P11A, P12A, P13A, and P14A are connected to predetermined terminals Se, Sf, Sg, and Sh of the semiconductor device 100, respectively, and when the semiconductor device 100 is mounted on the printed circuit board 400B, pads P11B, P12B, P13B, and P14B are connected to terminals of the semiconductor device 100, respectively. Assuming that Se, Sf, Sg, and Sh are connected, the signals propagated to terminals Se, Sf, Sg, and Sh of the semiconductor device 100 will be different in mode A and mode B.

[0104] Although not shown in the diagram, in mode A, low-speed signals propagate to terminals Se, Sf, Sg, and Sh, and low-speed signals propagate to wiring W11A, W12A, W13A, and W14A provided on printed circuit board 400A. Thus, when the control unit 210 determines that the printed circuit board 400 on which the semiconductor device 100 is mounted is printed circuit board 400A, it sets terminals Se, Sf, Sg, and Sh to terminals on which low-speed signals propagate.

[0105] On the other hand, in mode B, high-speed signals propagate through both terminals Sf and Sg, while terminals Se and Sh are connected to wiring W11A and W14A and are therefore at ground potential. In other words, high-speed signals propagate through wiring W12A and W13A on printed circuit board 400A, and are protected from noise by ground potential wiring W11B, W14B, and W23B. Thus, when the control unit 210 determines that the printed circuit board 400 on which the semiconductor device 100 is mounted is printed circuit board 400B, it sets terminals Sb and Sc to terminals on which high-speed signals propagate.

[0106] Note that terminal Tp of the integrated circuit chip 200 is an example of a "first terminal," and wiring 321 of the base board 300 is an example of a "first wiring." Terminal Tq of the integrated circuit chip 200 is an example of a "second terminal," and wiring 322 of the base board 300 is an example of a "second wiring." In addition, a predetermined terminal Ti of the integrated circuit chip 200 is an example of a "third terminal."

[0107] 6. Effects As described above, according to the electronic device 1 of this embodiment, in the semiconductor device 100, one integrated circuit chip 200 can be mounted in multiple types of packages 330, so there is no need to design and produce integrated circuit chips with different functions for each type of package 330. Therefore, the production line and production equipment for the integrated circuit chip 200 can be kept to a minimum, minimizing production costs and man-hours, and the management man-hours for the integrated circuit chip 200 can also be kept to a minimum, thus achieving cost reduction. Furthermore, by limiting the functions of the integrated circuit chip 200 according to the functions of the electronic device 1, the integrated circuit chip 200 can be mounted in a package 330 of the minimum size required according to its functions, thus achieving miniaturization of the semiconductor device 100. In addition, since the integrated circuit chip 200 can be mounted in a package 330 of the minimum size required according to its functions, the amount of material required for the production of the package 330 can be reduced, and the production equipment for the integrated circuit chip 200 can be kept to a minimum, so resources such as materials and personnel required for production can be used without waste. Furthermore, since the production equipment for the integrated circuit chip 200 can be kept to a minimum, the amount of compressed air and electricity used at the production plant can be reduced, thereby reducing CO2 emissions.

[0108] Furthermore, according to the electronic device 1 of this embodiment, in the semiconductor device 100, when the integrated circuit chip 200 is mounted on package 330b, terminal Ti is used as both a CMOS terminal and an LVDS terminal, thus reducing the number of terminals on the integrated circuit chip 200 and the number of wirings on the printed circuit board 400 on which the semiconductor device 100 is mounted. In addition, by dedicating terminal Ti to being a CMOS terminal or an LVDS terminal and limiting the function of the integrated circuit chip 200, the integrated circuit chip 200 can be mounted on a package 330 of the minimum size necessary according to its function.

[0109] Furthermore, when the functions of the integrated circuit chip 200 are restricted according to the functions of the electronic device 1 on which the semiconductor device 100 is mounted, fixing the potential of the unused terminals of the integrated circuit chip 200 to a low level reduces the risk that the potential of the unused terminals will become an intermediate potential, and electricity The risk of sub-device 1 malfunctioning is reduced.

[0110] Furthermore, according to the electronic device 1 of this embodiment, the supply of unnecessary clock signals and power to unused functional circuits is stopped in the integrated circuit chip 200, thus reducing power consumption and achieving power savings. Also, according to the electronic device 1 of this embodiment, by not performing initial setup of unused functional circuits in the integrated circuit chip 200, the power consumption required for unnecessary initial setup is reduced and the startup time is shortened, thus achieving power savings. In addition, according to the electronic device 1 of this embodiment, by changing the frequency of the clock signal according to the package 330 on which the integrated circuit chip 200 is mounted, the performance of the integrated circuit chip 200 can be increased within a range where the temperature inside the package 330 does not become excessively high. As a result, stable energy consumption is achieved at low cost, contributing to a reduction in the amount of power generated by power plants and being environmentally friendly.

[0111] Furthermore, according to the electronic device 1 of this embodiment, the functions of terminals Sa, Sb, Sc, Sd and terminals Se, Sf, Sg, Sf of the semiconductor device 100 are switched depending on the printed circuit board 400 on which the semiconductor device 100 is mounted. As a result, these terminals are used interchangeably, minimizing the number of terminals and wiring required, and enabling miniaturization of the semiconductor device 100. In addition, the production line and production equipment for the semiconductor device 100 can also be minimized, reducing the production cost of the semiconductor device 100 and achieving lower costs. Moreover, when the semiconductor device 100 is mounted on the printed circuit board 400B, the wiring through which high-speed signals propagate is sandwiched by ground wiring, reducing crosstalk caused by high-speed signals and minimizing the risk of malfunction. Furthermore, according to the electronic device 1 of this embodiment, since the terminals of the semiconductor device 100 are shared, the number of terminals and wires required can be minimized, thereby reducing the amount of material needed to produce the semiconductor device 100 and printed circuit board 400, and also minimizing the production equipment for the semiconductor device 100 and printed circuit board 400. This allows for the efficient use of resources such as materials and personnel required for production. In addition, since the production equipment for the semiconductor device 100 and printed circuit board 400 can be minimized, the amount of compressed air and electricity used in the production plant can be reduced, and the amount of CO2 emissions can be reduced.

[0112] Furthermore, according to the electronic device 1 of this embodiment, the printed circuit board 400 on which the semiconductor device 100 is mounted can be identified based on the potential of terminal S1 of the semiconductor device 100, thereby enabling miniaturization and cost reduction of the semiconductor device 100.

[0113] Based on the above, the electronic device 1 according to this embodiment can contribute to SDGs Goals 7, 8, 9, 11, and 12.

[0114] The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0115] For example, in this embodiment, the package 330 of the semiconductor device 100 was described as a BGA (Ball Grid Array), but the package 330 may be a surface mount package other than BGA, such as a SiP (System-in-Package), LGA (Land Grid Array), or WPP (Wafer Process Packaging). For example, if the package 330 is an LGA, the terminals of the semiconductor device 100 are lands provided on the package 330, and the lands, which are the terminals of the semiconductor device 100, are connected to the pads 410 provided on the printed circuit board 400 by solder balls 310.

[0116] Although embodiments have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its spirit. For example, the above embodiments can be combined as appropriate.

[0117] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0118] The following conclusions can be drawn from the embodiments described above.

[0119] One aspect of a semiconductor device is: The package and The package comprises an integrated circuit chip mounted on an internal substrate of the package, The aforementioned integrated circuit chip has a plurality of terminals, a control unit, and a plurality of functional circuits. The internal circuit board is provided with a first wire connected to a first terminal among the plurality of terminals, and a second wire connected to a second terminal among the plurality of terminals. The control unit determines the type of package based on the potential of the first terminal and the potential of the second terminal, and controls the operation of the plurality of functional circuits according to the type of package.

[0120] This semiconductor device allows a single integrated circuit chip to be mounted in multiple types of packages, eliminating the need to design and produce separate integrated circuit chips with different functions for each package type. Therefore, production costs and labor are minimized by reducing the production lines and equipment required for integrated circuit chips, and management costs are also reduced, resulting in lower costs. Furthermore, by limiting the functionality of the integrated circuit chip according to the function of the electronic device it will be mounted in, it can be mounted in the smallest possible package size, enabling miniaturization. Additionally, because the integrated circuit chip can be mounted in the smallest possible package size according to its function, the amount of materials needed for package production is reduced, and the production equipment for the integrated circuit chip can be minimized, allowing for efficient use of resources such as materials and personnel. Moreover, because the production equipment for the integrated circuit chip can be minimized, the amount of compressed air and electricity used in the production plant is reduced, thereby reducing CO2 emissions. Therefore, this semiconductor device contributes to SDGs Goals 7, 8, 9, 11, and 12.

[0121] In one embodiment of the semiconductor device, The control unit may determine, depending on the type of package, whether the third terminal among the plurality of terminals is used as both a CMOS terminal and an LVDS terminal.

[0122] This semiconductor device can reduce the number of terminals on an integrated circuit chip and the number of connections on the printed circuit board on which the semiconductor device is mounted. Furthermore, by limiting the functionality of the integrated circuit chip according to the function of the electronic device it is mounted in, it is possible to mount the integrated circuit chip in the smallest possible package size according to its function. Therefore, this semiconductor device can contribute to SDGs Goals 7, 8, 9, 11, and 12.

[0123] In one embodiment of the semiconductor device, Depending on the type of package, the control unit may fix the potential of the unused terminals among the plurality of terminals to a low level.

[0124] According to this semiconductor device, the functions of the integrated circuit chip depend on the function of the electronic device it is installed in. When restricted, the risk of unused terminals reaching an intermediate potential is reduced, thereby reducing the risk of malfunction in electronic devices that incorporate the semiconductor device. Therefore, this semiconductor device can contribute to SDGs Goals 7, 8, 9, 11, and 12.

[0125] In one embodiment of the semiconductor device, The control unit may, depending on the type of package, stop supplying clock signals to unused functional circuits among the plurality of functional circuits.

[0126] This semiconductor device reduces power consumption and achieves energy savings by stopping the supply of unnecessary clock signals. Therefore, it enables stable energy consumption at low cost, contributes to reducing power generation at power plants, and is environmentally friendly. Consequently, this semiconductor device can contribute to SDGs Goals 7, 8, 9, 11, and 12.

[0127] In one embodiment of the semiconductor device, The control unit may, depending on the type of package, stop supplying power to unused functional circuits among the plurality of functional circuits.

[0128] This semiconductor device eliminates the supply of unnecessary power, thereby reducing power consumption and achieving energy savings. Therefore, it enables stable energy consumption at low cost, contributes to reducing power plant output, and is environmentally friendly. Consequently, this semiconductor device can contribute to SDGs Goals 7, 8, 9, 11, and 12.

[0129] In one embodiment of the semiconductor device, The control unit does not need to perform initial setup of unused functional circuits among the plurality of functional circuits, depending on the type of package.

[0130] This semiconductor device reduces power consumption required for unnecessary initial setup and shortens startup time, resulting in energy savings. Therefore, it enables stable energy consumption at low cost, contributes to reducing power plant output, and is environmentally friendly. Consequently, this semiconductor device can contribute to SDGs Goals 7, 8, 9, 11, and 12.

[0131] In one embodiment of the semiconductor device, The control unit may change the frequency of the clock signal depending on the package.

[0132] This semiconductor device allows for performance enhancement within a range that prevents excessive temperature buildup inside the package, depending on the package type. Therefore, it enables stable energy consumption at low cost, contributes to reducing power plant output, and is environmentally friendly. Consequently, this semiconductor device can contribute to SDGs Goals 7, 8, 9, 11, and 12. [Explanation of Symbols]

[0133] 1...Electronic device, 2...PC, 3...SD card, 10...Image reader, 12...Main unit, 13...Recording device, 16...Operation unit, 18...Opening, 20...Drawer unit, 22...Front tray, 24...Rear tray, 26...Paper storage unit, 27...ADF, 28...Document transport unit, 40...Document placement surface, 42...Document output surface, 44...Cover, 50...Main board, 51...Sub-board, 52...Sub-board, 61...Motor, 62...Print head, 63...Scanner module, 64 ...Wireless LAN module, 65...LCD, 71, 72, 73...Cable, 100...Semiconductor equipment, 110...Motor driver, 120...Head drive IC, 130...Serial flash memory, 140...DDR, 151, 152, 153, 154...Connector, 160...LCD control IC, 170...SD control IC, 181...Connector, 190...Power supply circuit, 192...Reset IC, 200...Integrated circuit chip, 210...Control unit, 221, 222, 22 3…USB interface circuit, 231,232…Memory interface circuit, 241,241-1~241-n…GPIO, 250…Clock signal generation circuit, 260…Storage unit, 261…ROM, 262…RAM, 263…Register, 300,300a,300d…Base board, 301,301a,301d…Terminal mounting side, 302a,303a,304a 305a…Edges of the base board, 302d, 303d, 304d, 305d…Edges of the base board, 310, 310a, 310d…Solder balls, 321, 322…Wiring, 330, 330a, 330b, 330c, 330d…Package, 350…Enclosure, 370…Bonding material, 380…Bonding wire, 400, 400A, 400B…Printed circuit board, 410…Pad

Claims

1. The package and The package comprises an integrated circuit chip mounted on an internal substrate of the package, The aforementioned integrated circuit chip has a plurality of terminals, a control unit, and a plurality of functional circuits. The internal circuit board is provided with a first wire connected to a first terminal among the plurality of terminals, and a second wire connected to a second terminal among the plurality of terminals. The control unit determines the type of package based on the potential of the first terminal and the potential of the second terminal, and controls the operation of the plurality of functional circuits according to the type of package. A semiconductor device characterized by the following features.

2. The control unit determines, depending on the type of package, whether the third terminal among the plurality of terminals is used as both a CMOS terminal and an LVDS terminal. The semiconductor device according to feature 1.

3. The control unit fixes the potential of the unused terminals among the plurality of terminals to a low level, depending on the type of package. The semiconductor device according to feature 1.

4. The control unit stops supplying clock signals to unused functional circuits among the plurality of functional circuits, depending on the type of package. The semiconductor device according to feature 1.

5. The control unit, depending on the type of package, stops supplying power to unused functional circuits among the plurality of functional circuits. The semiconductor device according to feature 1.

6. The control unit, depending on the type of package, does not perform initial setup of unused functional circuits among the plurality of functional circuits. The semiconductor device according to feature 1.

7. The control unit changes the frequency of the clock signal according to the package. The semiconductor device according to feature 1.

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