Semiconductor memory device and method for manufacturing the same

Abstract

This invention provides a memory that can suppress the collapse of the laminate when replacing the sacrificial layer with a conductive material. [Solution] The memory comprises a first laminate in which electrode films and a first insulating film are alternately stacked in a first direction. A second laminate is provided adjacent to the first laminate, and in which the first insulating film and the second insulating film are alternately stacked in the first direction. A third laminate extends in a second direction from the end of the first laminate in a first plane perpendicular to the first direction, and in which electrode films and the first insulating film are alternately stacked in the first direction. A first columnar body includes a semiconductor layer provided penetrating the first laminate in the first direction. The first columnar body constitutes a plurality of memory cells at the intersection with the electrode films, with the electrode films serving as gate electrodes. Contacts extend in the first direction within the second laminate or within the third insulating film, and are provided to the depth of each of the plurality of electrode films of the third laminate. A connect layer electrically connects the plurality of contacts and the plurality of electrode films corresponding to each of them.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same.

Background Art

[0002] A semiconductor memory device such as a NAND type flash memory may have a memory cell array in which a plurality of memory cells are three-dimensionally arranged. Such a memory cell array includes an electrode film that functions as a plurality of word lines and a plurality of insulating films. The electrode film and the insulating layer are alternately laminated. The electrode film is formed by replacing the sacrificial film with a conductive material from a laminate of a plurality of sacrificial films and a plurality of insulating films. When the sacrificial film is removed in such a replacement process, the laminate may bend due to its own weight.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Summary of the Invention

[0004] The present invention provides a semiconductor memory device and a method for manufacturing the same that can suppress indentation of a laminate when replacing the sacrificial films with a conductive material in a laminate of multiple sacrificial films and multiple insulating films. [Means for solving the problem]

[0005] The semiconductor memory device according to this embodiment comprises a first laminate in which electrode films and a first insulating film are alternately stacked in a first direction. A second laminate is provided adjacent to the first laminate and is constructed by alternately stacking a first insulating film and a second insulating film in a first direction. A third laminate extends in a second direction from the end of the first laminate in a first plane perpendicular to the first direction and is constructed by alternately stacking electrode films and a first insulating film in a first direction. A first columnar body includes a semiconductor layer provided penetrating the first laminate in a first direction. The first columnar body constitutes a plurality of memory cells at the intersection with a plurality of electrode films, with the plurality of electrode films serving as gate electrodes. A plurality of contacts extend in a first direction within the second laminate or within a third insulating film provided above the second laminate and are provided to the respective depths of the plurality of electrode films in the third laminate. A plurality of connect layers electrically connect the plurality of contacts to the plurality of electrode films corresponding to each of the plurality of contacts. [Brief explanation of the drawing]

[0006] [Figure 1] A cross-sectional view showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 2] An enlarged cross-sectional view showing an example of the configuration of a memory cell array according to the first embodiment. [Figure 3] A cross-sectional view showing the manufacturing process from bonding the array wafer and circuit wafer to the completion of the semiconductor memory device. [Figure 4] A cross-sectional view showing the manufacturing process, following Figure 3. [Figure 5] A cross-sectional view showing the manufacturing process, following Figure 4. [Figure 6]Cross-sectional view showing the manufacturing process, following FIG. 5. [Figure 7] Plan view showing a configuration example of a memory cell array according to the first embodiment. [Figure 8] Cross-sectional view showing a configuration example of a memory cell array according to the first embodiment. [Figure 9] Plan view showing an example of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 10] Cross-sectional view showing an example of a manufacturing method of a semiconductor memory device according to the first embodiment. [Figure 11] Cross-sectional view showing an example of the manufacturing method, following FIG. 10. [Figure 12] Cross-sectional view showing an example of the manufacturing method, following FIG. 11. [Figure 13] Plan view showing an example of the manufacturing method, following FIG. 12. [Figure 14] Cross-sectional view showing an example of the manufacturing method, following FIG. 12. [Figure 15] Cross-sectional view showing an example of the manufacturing method, following FIG. 14. [Figure 16] Cross-sectional view showing an example of the manufacturing method, following FIG. 15. [Figure 17] Cross-sectional view showing an example of the manufacturing method, following FIG. 16. [Figure 18] Plan view showing an example of the manufacturing method, following FIG. 17. [Figure 19] Cross-sectional view showing an example of the manufacturing method, following FIG. 17. [Figure 20] Plan view showing an example of the manufacturing method, following FIG. 18. [Figure 21] Cross-sectional view showing an example of the manufacturing method, following FIG. 19. [Figure 22] Cross-sectional view showing an example of the manufacturing method, following FIG. 21. [Figure 23] Plan view showing an example of the manufacturing method, following FIG. 22. [Figure 24] Cross-sectional view showing an example of the manufacturing method, following FIG. 22. [Figure 25] Plan view showing an example of the manufacturing method, following FIG. 23. [Figure 26] Cross-sectional view showing an example of the manufacturing method, following FIG. 24. [Figure 27] A plan view showing an example of the manufacturing method, following Figure 25. [Figure 28] A cross-sectional view showing an example of the manufacturing method, following Figure 26. [Figure 29] A cross-sectional view showing an example of the manufacturing method, following Figure 28. [Figure 30] A cross-sectional view showing an example of the manufacturing method, following Figure 29. [Figure 31] Figure 30 is followed by a cross-sectional view showing an example of the manufacturing method. [Figure 32] A plan view showing an example of the configuration of a memory cell array according to the second embodiment. [Figure 33] A plan view showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 34] A plan view showing an example of the manufacturing method, following Figure 33. [Figure 35] A plan view showing an example of the manufacturing method, following Figure 34. [Figure 36] A plan view showing an example of the manufacturing method, following Figure 35. [Figure 37] A plan view showing an example of the manufacturing method, following Figure 36. [Figure 38] A plan view showing an example of the manufacturing method, following Figure 37. [Figure 39] A plan view showing an example of the manufacturing method, following Figure 38. [Figure 40] A plan view showing an example configuration of a semiconductor memory device according to the third embodiment. [Figure 41] Cross-sectional view along line AA in Figure 40. [Figure 42] Cross-sectional view along line BB in Figure 40. [Figure 43] A plan view showing an example configuration of a semiconductor memory device according to the fourth embodiment. [Figure 44] A plan view showing an example configuration of a semiconductor memory device according to the fourth embodiment. [Figure 45] Cross-sectional view along line AA in Figure 44. [Figure 46] Cross-sectional view along line BB in Figure 44. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual. The same elements are denoted by the same reference numerals in the specification and the drawings.

[0008] (First Embodiment) Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to the first embodiment.

[0009] The semiconductor memory device of this embodiment is, for example, a NAND flash memory having a memory cell array in which memory cells are arranged in three dimensions. The semiconductor memory device of this embodiment is manufactured by bonding an array wafer containing an array chip 1 and a circuit wafer containing a circuit chip 2 on a bonding surface S.

[0010] The array chip 1 comprises a memory cell array 11 containing multiple memory cells and an interlayer insulating film 12 beneath the memory cell array 11. The interlayer insulating film 12 is, for example, a laminate containing a silicon oxide film (e.g., an SiO2 film) containing silicon and oxygen and other insulating films.

[0011] Circuit chip 2 is located beneath array chip 1. Circuit chip 2 comprises an interlayer insulating film 13 beneath an interlayer insulating film 12, and a substrate 14 beneath the interlayer insulating film 13. The interlayer insulating film 13 is, for example, a laminate containing a silicon oxide film (e.g., an SiO2 film) containing silicon and oxygen, and other insulating films. The substrate 14 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Substrate 14 is an example of a second substrate.

[0012] Figure 1 shows the X and Y directions, which are parallel to and perpendicular to the surface of the substrate 14, and the Z direction, which is perpendicular to the surface of the substrate 14. The X, Y, and Z directions intersect each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity. The Z direction is an example of the first direction. The X direction is an example of the second direction. The Y direction is an example of the third direction.

[0013] The array chip 1 comprises multiple word lines WL, a source-side selection line SGS, and a drain-side selection line SGD as multiple electrode films within the memory cell array 11. The source-side selection line SGS is positioned above these word lines WL, and the drain-side selection line SGD is positioned below these word lines WL. The array chip 1 includes a cell region Rmc on which the memory cell array 11 is provided, and a word line hookup region (hereinafter also referred to as the WLHU region) Rwlhu on which word line contacts 23 are provided.

[0014] Each of the multiple word lines WL is connected to each of the multiple word line contacts 23, and is electrically connected to each of the multiple word line wirings 24 via the multiple word line contacts 23 (hereinafter also referred to as word line contacts WLC).

[0015] Multiple columnar bodies CL, which penetrate multiple word lines WL, source-side selection line SGS, and drain-side selection line SGD, are electrically connected to bit lines BL via via plugs 25 and also electrically connected to source lines SL. The columnar bodies CL are provided penetrating the stack of memory cell array 11 in the Z direction and constitute multiple memory cells MC at their intersections with the multiple word lines WL. The source lines SL are provided above the source-side selection line SGS, and the bit lines BL are provided below the drain-side selection line SGD.

[0016] Furthermore, while only the uppermost electrode film in Figure 1 may have a source-side selectivity of SGS, multiple electrode films on the uppermost side may also have source-side selectivity of SGS. The number of electrode films with source-side selectivity of SGS can be arbitrary. Similarly, while only the lowest electrode film may have a drain-side selectivity of SGD, multiple electrode films on the lowermost side may also have drain-side selectivity of SGD. The number of electrode films with drain-side selectivity of SGD can be arbitrary.

[0017] The array chip 1 further comprises metal pads 41, 47, via plugs 42, 45, 46, wiring layers 43, 44, and a passivation insulating film 48.

[0018] The metal pad 41 is bonded to the metal pad 37 of the circuit chip 2. The metal pad 41 is, for example, a metal layer containing Cu (copper). The CMOS of the circuit chip 2 C complementary M etal O xide S The EMIconductor circuit is electrically connected to the memory cell array 11 via metal pads 41, 37, etc., and controls the operation of the memory cell array 11. Via plugs 42 are provided on metal pads 41. Wiring layer 43 is provided on via plug 42 and includes multiple wires. Wiring layer 44 is provided on wiring layer 43 and includes multiple wires. Bit lines BL are formed on the same layer as wiring layer 44. Via plug 45 is provided on wiring layer 44. Via plug 46 is provided on via plug 45.

[0019] The metal pad 47 is provided on the via plug 46 and the interlayer insulating film 12. The metal pad 47 is, for example, a metal layer containing Al (aluminum) and functions as an external connection pad (e.g., a bonding pad). The passivation insulating film 48 is provided on the metal pad 47 and the interlayer insulating film 12. The passivation insulating film 48 is, for example, a laminate containing a silicon oxide film (e.g., an SiO2 film) containing silicon and oxygen and a silicon nitride film (e.g., a SiN film) containing silicon and nitrogen, and exposes a portion of the upper surface of the metal pad 47. The metal pad 47 can be connected to a mounting substrate or other devices by bonding wires, solder balls, metal bumps, etc.

[0020] The circuit chip 2 comprises a transistor 31, a contact plug 32, a wiring layer 33, a wiring layer 34, a wiring layer 35, a via plug 36, and a metal pad 37.

[0021] The transistor 31 includes a gate insulating film 31a provided on the substrate 14, a gate electrode 31b provided on the gate insulating film 31a, a source region (not shown) provided on the substrate 14, and a drain region (not shown) provided on the substrate 14.

[0022] The contact plug 32 is provided on the gate electrode 31b, source region, and drain region of the transistor 31. The wiring layer 33 is provided on the contact plug 32 and includes multiple wirings. The wiring layer 34 is provided on the wiring layer 33 and includes multiple wirings. The wiring layer 35 is provided on the wiring layer 34 and includes multiple wirings. The via plug 36 is provided on the wiring layer 35. The metal pad 37 is provided on the via plug 36. The metal pad 37 is, for example, a metal layer including a Cu layer. The circuit chip 2 has a CMOS circuit that controls the operation of the array chip 1. This CMOS circuit is composed of transistors 31 and the like and is electrically connected to the array chip 1 via the metal pad 37.

[0023] Figure 2 is an enlarged cross-sectional view showing an example configuration of a memory cell array according to the first embodiment. Figure 2 shows one columnar body CL.

[0024] The memory cell array 11 comprises a laminate 51 including electrode films 51a and insulating films 51b that are alternately stacked in the Z direction. The electrode films 51a function, for example, as word lines WL, source-side selection lines SGS, or drain-side selection lines SGD. In Figure 2, the uppermost electrode film 51a is the source-side selection line SGS, the lowermost electrode film 51a is the drain-side selection line SGD, and the other electrode films 51a are word lines WL. The word lines WL function as gate electrodes of the memory cell MC. The electrode films 51a are, for example, metal layers containing W (tungsten, molybdenum). The insulating films 51b are, for example, silicon oxide films (e.g., SiO2 films) containing silicon and oxygen. The insulating film 51b is an example of a first insulating film.

[0025] The columnar body CL is provided penetrating the laminate 51 in the Z direction and has a columnar shape. The columnar body CL is provided within the memory hole MH that penetrates the laminate 51 in the Z direction. The columnar body CL includes a block insulating film 52 provided on the inner surface of the memory hole MH, a charge storage layer 53 provided on the inner surface of the block insulating film 52, a tunnel insulating film 54 provided on the inner surface of the charge storage layer 53, a channel semiconductor layer 55 provided on the inner surface of the tunnel insulating film 54, and a core insulating film 56 provided on the inner surface of the channel semiconductor layer 55. The columnar body CL constitutes a memory cell MC at its intersection with the word line WL, a source-side selection transistor at its intersection with the source-side selection line SGS, and a drain-side selection transistor at its intersection with the drain-side selection line SGD. The memory cell MC is also called a cell transistor.

[0026] The block insulating film 52 is, for example, a silicon oxide film containing silicon and oxygen (e.g., an SiO2 film). The charge storage layer 53 is capable of storing charge according to the logic of the data. The charge storage layer 53 is, for example, an insulating film such as a silicon nitride film containing silicon and nitrogen (e.g., a SiN film). The tunnel insulating film 54 is, for example, a silicon oxide film containing silicon and oxygen (e.g., an SiO2 film) or a silicon nitride film containing silicon and nitrogen (e.g., an O1 film). The channel semiconductor layer 55 functions as the channel of the memory cell MC. The channel semiconductor layer 55 is, for example, a film containing silicon (e.g., a polysilicon layer). The core insulating film 56 is, for example, a silicon oxide film containing silicon and oxygen (e.g., an SiO2 film). The channel semiconductor layer 55 is an example of a semiconductor layer.

[0027] Figures 3 to 6 are cross-sectional views showing the manufacturing process from bonding the array wafer W1 and the circuit wafer W2 to the completion of the semiconductor memory device.

[0028] Figure 3 shows an array wafer W1 containing multiple array chips 1 and a circuit wafer W2 containing multiple circuit chips 2. In Figure 3, the Z-direction orientation of the array wafer W1 is opposite to the Z-direction orientation of the array chips 1 in Figure 1. The array wafer W1 and the circuit wafer W2 are bonded together to electrically connect the array chips 1 and the circuit chips 2. Figure 3 shows the array wafer W1 before its orientation is reversed for bonding.

[0029] In this embodiment, as shown in Figure 3, a memory cell array 11, an interlayer insulating film 12a, a metal pad 41, a via plug 45, etc., are formed on the substrate 15 of the array wafer W1. Separately, a transistor 31, an interlayer insulating film 13, a metal pad 37, etc., are formed on the substrate 14 of the circuit wafer W2. Substrates 14 and 15 are semiconductor substrates such as silicon substrates.

[0030] Next, as shown in Figure 4, the array wafer W1 and the circuit wafer W2 are bonded together such that the upper surface S1 of the array wafer W1 and the upper surface S2 of the circuit wafer W2 face each other. This causes the interlayer insulating film 12a and the interlayer insulating film 13 to adhere to each other at the bonding surface S.

[0031] Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pad 41 and the metal pad 37. In this way, the array wafer W1 and the circuit wafer W2 are bonded together with the interlayer insulating films 12a and 13 in between.

[0032] Next, as shown in Figure 5, the substrate 15 is CMP( C hemical M echanical P The material is removed by olishing or wet etching. This exposes the interlayer insulating film 12a, columnar body CL, via plug 45, etc.

[0033] Next, as shown in Figure 6, a source wire SL is formed on the interlayer insulating film 12a and the columnar body CL, and the interlayer insulating film 12b is formed on the interlayer insulating film 12a via the source wire SL.

[0034] Next, a via plug 46 is formed on the via plug 45, penetrating the interlayer insulating film 12b, and a metal pad 47 is formed on the interlayer insulating film 12b and the via plug 46.

[0035] Next, a passivation insulating film 48 is formed on the interlayer insulating film 12b and the metal pad 47, and the passivation insulating film 48 is processed to expose a portion of the metal pad 47.

[0036] Subsequently, the array wafer W1 and circuit wafer W2 are cut into multiple chips. In this way, the semiconductor memory device shown in Figure 1 is manufactured.

[0037] Figure 1 shows the interface between the interlayer insulating film 12 and the interlayer insulating film 13, and the interface (bonding surface S) between the metal pad 41 and the metal pad 37. However, after the annealing described above, these interfaces are generally no longer visible. Nevertheless, the locations where these interfaces once existed can be identified, for example, by the inclination of the side surfaces of the metal pad 41 and the metal pad 37, or by the misalignment between the side surfaces of the metal pad 41 and the metal pad 37.

[0038] Figure 7 is a plan view showing an example configuration of the memory cell array 11 according to the first embodiment. Figure 8 is a cross-sectional view showing an example configuration of the memory cell array 11 according to the first embodiment. Figure 7 shows the end of the memory cell array 11. AA in Figure 8 shows a cross-section along line AA in Figure 7. BB in Figure 8 shows a cross-section along line BB in Figure 7. CC in Figure 8 shows a cross-section along line CC in Figure 7. DD in Figure 8 shows a cross-section along line DD in Figure 7. EE in Figure 8 shows a cross-section along line EE in Figure 7. FF in Figure 8 shows a cross-section along line FF in Figure 7. GG in Figure 8 shows a cross-section along line GG in Figure 7.

[0039] As shown in Figure 7, the memory cell array 11 has a cell region Rmc and a WLHU region Rwlhu.

[0040] In the laminate 51, the cell region Rmc is provided with a first laminate 51_1. As shown in Figure 8, the first laminate 51_1 is constructed by alternately stacking electrode films 51a and insulating films 51b in the Z direction. As shown in Figure 7, the first laminate 51_1 is provided with a plurality of columnar bodies CL. The first laminate 51_1 is also provided with a plurality of slits ST_CELL.

[0041] The slit ST_CELL is provided so as to penetrate the first laminate 51_1 in the Z direction as shown in Figure 8 and extend in the X direction as shown in Figure 7. The slit ST_CELL divides the first laminate 51_1 into multiple block BLKs. The portion of the first laminate 51_1 sandwiched between two slit ST_CELLs is called a block BLK. A block BLK constitutes, for example, a unit for data erasure. The slit ST_CELL electrically isolates the first laminate 51_1 for each block BLK.

[0042] The inner wall of the slit ST_CELL is covered with an insulating film such as a silicon oxide film, and a conductive material is embedded inside the insulating film. The conductive material is connected to the source wire SL and can function as a source wire. When not used as a source wire, the slit ST_CELL may be filled with an insulating film such as a silicon oxide film (e.g., an SiO2 film) containing silicon and oxygen.

[0043] Of the laminate 51, the WLHU region Rwlhu is provided adjacent to the cell region Rmc. The WLHU region Rwlhu is provided with the second laminate 51_2 and the third laminate 51_3.

[0044] As shown in Figure 8, the second laminate 51_2 has insulating films 51b (e.g., silicon oxide film) and insulating films 51c (e.g., silicon nitride film) stacked alternately in the Z direction. As shown in Figure 7, the second laminate 51_2 is adjacent to the first laminate 51_1 with a slit ST_WLC in between. The second laminate 51_2 is also adjacent to the third laminate 51_3. Multiple word line contact WLCs are provided in the second laminate 51_2.

[0045] As shown in Figure 8, the slit ST_WLC penetrates the first or second laminate 51_1, 51_2 in the Z direction between the first laminate 51_1 and the second laminate 51_2. As shown in Figure 7, the slit ST_WLC is intermittently extended in the Y direction within the XY plane. The slit ST_WLC is filled with an insulating film (e.g., silicon oxide film). This physically separates the first laminate 51_1 and the second laminate 51_2, preventing the insulating film 51c of the second laminate 51_2 in the WLHU region Rwlhu from being replaced by the conductive material of the electrode film 51a. On the other hand, each block BLK of the slit ST_WLC has an opening OP that connects a portion of the first laminate 51_1 in the cell region Rmc to the third laminate 51_3 in the WLHU region Rwlhu.

[0046] As shown in Figure 8, the third stack 51_3 has electrode films 51a (e.g., tungsten, molybdenum) and insulating films 51b (e.g., silicon oxide films) stacked alternately in the Z direction. As shown in Figure 7, the third stack 51_3 is connected to the first stack 51_1 from its end via an opening OP, and extends in the +X direction from the end of the first stack 51_1 in the XY plane. The electrode films 51a and insulating films 51b of the third stack 51_3 are continuously connected to those of the first stack 51_1 in each layer. Furthermore, a dummy columnar body DMC is provided at the end of the third stack 51_3 on the cell region Rmc side. The dummy columnar body DMC is formed simultaneously with the CL in the first stack, but does not function as a memory cell. The dummy columnar DMC is provided to suppress the bending of the insulating film 51b at the connection between the first laminate 51_1 and the third laminate 51_3 due to its own weight when replacing the insulating film 51c of the first and third laminates 51_1 and 51_3 with the conductive material of the electrode film 51a. Furthermore, the third laminate 51_3 is provided with a slit ST_LWI. The dummy columnar DMC may also be placed around the slit ST_LWI to prevent bending.

[0047] As shown in Figure 8, the slit ST_LWI penetrates the third laminate 51_3 in the Z direction within the third laminate 51_3. As shown in Figure 7, the slit ST_LWI extends in the X direction along the stretching direction of the third laminate 51_3 in the XY plane. The inner wall of the slit ST_LWI is covered with an insulating film such as a silicon oxide film, and a conductive material is further embedded inside the insulating film. Thus, the slit ST_LWI can be formed simultaneously with the slit ST_CELL. However, the conductive material does not need to be connected to the source wire SL. Therefore, alternatively, the slit ST_LWI may be filled with an insulating film such as a silicon oxide film.

[0048] As shown in Figure 7, multiple word line contact WLCs are provided extending in the Z direction within the second laminate 51_2. As shown in Figure 8, the multiple word line contact WLCs are provided to the respective depths of multiple electrode films 51a (i.e., word lines WL).

[0049] The word line contact WLC is embedded inside a spacer 26 (e.g., a silicon oxide film) provided on the inner wall of the contact hole. For example, tungsten is used for the word line contact WLC.

[0050] For example, in a cross-section along the DD line in Figure 7, as shown in Figure 8, the word line contact WLCd extends to the second electrode film 51a from the bottom of the first or third laminate 51_1, 51_3, and is not provided below that (in the -Z direction). The word line contact WLCd is electrically connected to the second electrode film 51a from the bottom via the connect layer 27d. The word line contact WLCd is electrically insulated from electrode films 51a other than the second electrode film 51a from the bottom by the spacer 26 and the insulating film 51c.

[0051] In the cross-section along the EE line in Figure 7, as shown in Figure 8, the word line contact WLCe extends to the third electrode film 51a from the bottom of the first or third laminate 51_1, 51_3, and is not provided below that (in the -Z direction). The word line contact WLCe is electrically connected to the third electrode film 51a from the bottom via the connect layer 27e. The word line contact WLCe is electrically insulated from electrode films 51a other than the third electrode film 51a from the bottom by the spacer 26 and the insulating film 51c.

[0052] In the cross-section along the FF line in Figure 7, as shown in Figure 8, the word line contact WLCf extends to the fourth electrode film 51a from the bottom of the first or third laminate 51_1, 51_3, and is not provided below that (in the -Z direction). The word line contact WLCf is electrically connected to the fourth electrode film 51a from the bottom via the connect layer 27f. The word line contact WLCf is electrically insulated from electrode films 51a other than the fourth electrode film 51a from the bottom by the spacer 26 and the insulating film 51c.

[0053] In the cross-section along the GG line in Figure 7, as shown in Figure 8, the word line contact WLCg extends to the fifth electrode film 51a from the bottom of the first or third laminate 51_1, 51_3, and is not provided below that (in the -Z direction). The word line contact WLCg is electrically connected to the fifth electrode film 51a from the bottom via the connect layer 27g. The word line contact WLCg is electrically insulated from electrode films 51a other than the fifth electrode film 51a from the bottom by the spacer 26 and the insulating film 51c.

[0054] Although not shown in the diagram, other word line contacts (WLCs) are also provided in the other electrode films 51a to their respective depths and are electrically connected to the corresponding electrode films 51a.

[0055] Thus, each word line contact WLC is electrically connected to the corresponding electrode film 51a via a single connect layer 27.

[0056] Multiple connect layers 27 are provided between multiple word line contacts WLCs and multiple corresponding electrode films 51a, electrically connecting them. The connect layers 27 are formed by isotropically etching the second insulating film 51c from the bottom of each word line contact WLC. Therefore, the connect layers 27 spread substantially evenly from the bottom of each word line contact WLC to its periphery. Conductive materials such as tungsten and molybdenum are used for the connect layers 27.

[0057] For example, the connect layer 27d is provided between the word line contact WLCd and the second-to-last electrode film 51a of the first or third laminate 51_1, 51_3, electrically connecting them. The connect layer 27d is not provided in any layer other than this second-to-last electrode film 51a.

[0058] The connect layer 27e is provided between the word line contact WLCe and the third electrode film 51a from the bottom of the first or third laminate 51_1, 51_3, and electrically connects them. The connect layer 27e is not provided in any layer other than this third electrode film 51a from the bottom.

[0059] The connect layer 27f is provided between the word line contact WLCf and the fourth electrode film 51a from the bottom of the first or third laminate 51_1, 51_3, electrically connecting them. The connect layer 27f is not provided in any layer other than this fourth electrode film 51a from the bottom.

[0060] The connect layer 27g is provided between the word line contact WLCg and the fifth electrode film 51a from the bottom of the first or third laminate 51_1, 51_3, electrically connecting them. The connect layer 27g is not provided in any layer other than this fifth electrode film 51a from the bottom.

[0061] As shown in Figure 8, interlayer insulating films 57 and 58 are provided on the first to third laminates 51_1 to 51_3. For example, insulating films (e.g., silicon oxide films) are used for the interlayer insulating films 57 and 58. The slits ST_CELL, ST_WLC, ST_LWI, and word line contact WLC extend in the Z direction, penetrating the interlayer insulating films 57 and 58.

[0062] Thus, according to the first embodiment, multiple word line contacts (WLCs) are provided in the second laminate 51_2 to the respective depths of the multiple electrode films 51a, and are electrically connected to the corresponding electrode films 51a of the third laminate 51_3 via the connect layer 27.

[0063] Multiple electrode films 51a of the first laminate 51_1 each correspond to multiple electrode films 51a of the third laminate 51_3 and are electrically connected. Furthermore, multiple insulating films 51b of the first laminate 51_1 each correspond to multiple insulating films 51b of the third laminate 51_3, electrically isolating adjacent electrode films 51a in the Z direction. This allows multiple word line contacts (WLCs) to be electrically connected to the multiple electrode films 51a of the first and third laminates 51_1 and 51_3, respectively, while maintaining their electrical insulation from one another.

[0064] On the other hand, the second laminate 51_2 is provided with first and second insulating films 51b and 51c. The multiple first insulating films 51b of the second laminate 51_2 correspond to the multiple first insulating films 51b of the first and third laminates 51_1 and 51_3, respectively. The multiple second insulating films 51c of the second laminate 51_2 correspond to the multiple electrode films 51a of the first and third laminates 51_1 and 51_3, respectively. Therefore, in the WLHU region Rwlhu, the multiple word line contacts WLC are electrically isolated from the electrode films 51a and connect layer 27 other than the corresponding electrode films 51a and connect layer 27.

[0065] This allows voltage to be applied separately from each word line contact WLC to each electrode film 51a (each word line WL).

[0066] Furthermore, in the manufacturing process described later, when the second insulating film 51c of the first and third laminates 51_1 and 51_3 is replaced with the electrode film 51a, the second insulating film 51c of the second laminate 51_2 is left in place without being replaced. This makes it possible to prevent the first insulating film 51b from bending or collapsing due to its own weight in the WLHU region Rwlhu without the need to provide support columns.

[0067] In Figure 7, one block BLK is provided with one opening OP and one slit ST_LWI. However, one block BLK may be provided with multiple openings OP and multiple slits ST_LWI. In this case, word line contacts WLC may be provided around each slit ST_LWI.

[0068] Next, a method for manufacturing a semiconductor memory device according to this embodiment will be described.

[0069] Figures 9 to 31 show an example of a semiconductor memory device manufacturing method according to the first embodiment. Figures 9, 13, 18, 20, 23, 25, and 27 show a plan view of the memory cell array 11. Figures 10 to 12, 14 to 17, 19, 21, 22, 24, 26, and 28 to 31 show a cross-section of the memory cell array 11.

[0070] Furthermore, the cross-sections along lines AA, BB, CC, and DD in the plan view of Figure 9, etc., are shown as AA, BB, CC, and DD in the cross-sectional view of Figure 10, etc., respectively. The structures corresponding to the cross-sections along lines EE, FF, and GG in Figure 7 are omitted from the illustration in Figure 10, etc.

[0071] As shown in Figure 10, a laminate 51 is formed on a substrate 15 by alternately stacking a first insulating film 51b (e.g., a silicon oxide film) and a second insulating film 51c (e.g., a silicon nitride film) in the Z direction. Furthermore, an interlayer insulating film 57 (e.g., a silicon oxide film) is deposited on the laminate 51.

[0072] Next, lithography and etching techniques are used to form the slit holes (trenches) H_ST_WLC of the slit ST_WLC and the contact holes H_WLC of the word line contact WLC. The slit holes H_ST_WLC are located between the cell region Rmc and the WLHU region Rwlhu. As shown in Figure 9, the slit holes H_ST_WLC have openings OP that separate the cell region Rmc and the WLHU region Rwlhu while connecting a portion of the cell region Rmc to the WLHU region Rwlhu. As shown in Figure 10, the contact holes H_WLC are formed in the WLHU region Rwlhu up to the second insulating film 51c, which corresponds to the depth of the electrically connected electrode film 51a. Multiple contact holes H_WLC are formed up to the second insulating film 51c, each with a different depth. The first laminate 51_1 and the third laminate 51_3 are still composed of laminates containing multiple first insulating films 51b and multiple second insulating films 51c.

[0073] Next, as shown in Figure 11, spacers 26 (e.g., silicon oxide film) are formed on the inner walls of the slit hole H_ST_WLC and contact hole H_WLC. Then, a sacrificial film SAC1 is embedded inside the spacers 26 within the slit hole H_ST_WLC and contact hole H_WLC. The sacrificial film SAC1 is made of a material (e.g., polysilicon, carbon) that can be etched against the spacers 26 and the laminate 51. Next, the upper ends of the slit hole H_ST_WLC and contact hole H_WLC are covered with a silicon oxide film 57 on the laminate 51 so that they are not exposed to the outside.

[0074] Next, using lithography and etching techniques, the interlayer insulating film 57 on the slit hole H_ST_WLC is removed, the sacrificial film SAC1 within the slit hole H_ST_WLC is selectively removed, and an insulating film (e.g., silicon oxide film) is embedded within the slit hole H_ST_WLC. This forms the slit ST_WLC as shown in Figure 12.

[0075] Next, as shown in Figure 13, multiple memory holes MH are formed in the cell region Rmc of the laminate 51, penetrating the laminate 51 in the Z direction. Then, the block insulating film 52, charge storage layer 53, tunnel insulating film 54, channel semiconductor layer 55, and core insulating film 56 shown in Figure 2 are formed on the inner wall of the memory holes MH in this order. As a result, columnar bodies CL are formed within the memory holes MH.

[0076] Simultaneously with the formation of the memory hole MH, a dummy hole DMH is formed near the opening OP of the WLHU region Rwlhu. The dummy hole DMH also penetrates the stacked body 51 in the Z direction. Furthermore, simultaneously with the formation of the columnar body CL, a block insulating film 52, a charge storage layer 53, a tunnel insulating film 54, a channel semiconductor layer 55, and a core insulating film 56 are formed on the inner wall of the dummy hole DMH in this order. As a result, a dummy columnar body DMC is formed within the dummy hole DMH. The dummy columnar body DMC is a columnar body having the same configuration as the columnar body CL, but it does not function as a memory cell. The dummy columnar body DMC is provided to support the first insulating film 51b near the opening OP in the replacement process described later.

[0077] Next, as shown in Figures 13 and 14, slit holes H_ST_CELL for slit ST_CELL and slit holes H_ST_LWI for slit ST_LWI are formed using lithography and etching techniques. Slit hole H_ST_CELL penetrates the cell region Rmc of the laminate 51 in the Z direction and extends in the X direction in the XY plane. Slit hole H_ST_LWI penetrates the WLHU region Rwlhu of the laminate 51 in the Z direction and extends in the X direction in the XY plane.

[0078] Next, the insulating film 58 is deposited on the insulating film 57 under poor coverage conditions using a method such as plasma CVD (Chemical Vapor Deposition). As shown in Figure 15, the insulating film 58 is formed so as to close the openings of the slit holes H_ST_CELL and H_ST_WLI without filling them.

[0079] Next, lithography and etching techniques are used to remove the insulating films 57 and 58 on the contact hole H_WLC, exposing the surface of the sacrificial film SAC1.

[0080] Next, as shown in Figure 16, the sacrificial film SAC1 in the contact hole H_WLC is selectively removed using a wet etching method or an ashing method, and then the spacer 26 at the bottom of the contact hole H_WLC is removed by anisotropic etching. This removes the spacer 26 at the bottom while leaving the spacer 26 on the side walls of each contact hole H_WLC, exposing the second insulating film 51c at the bottom.

[0081] Next, using lithography and etching techniques, the insulating film 58 on the slit hole H_ST_LWI is removed, as shown in Figure 17.

[0082] Next, as shown in Figures 18 and 19, the second insulating film 51c of the laminate 51 in the WLHU region Rwlhu is isotropically etched through the contact hole H_WLC and the slit hole H_ST_LWI using wet etching or the CDE (Chemical Dry Etching) method. This causes the second insulating film 51c to be recessed in the XY plane. As shown by the arrow in Figure 18, each second insulating film 51c of the laminate 51 is recessed through the slit hole H_ST_LWI, forming a recess region RCS. At this time, the second insulating film 51c exposed at the bottom of the contact hole H_WLC is etched from both the contact hole H_WLC side and the slit hole H_ST_LWI side. That is, as shown by arrow A27 in Figure 19, the second insulating film 51c exposed at the bottom of the contact hole H_WLC is etched from both the contact hole H_WLC side and the slit hole H_ST_LWI side. As a result, the contact hole H_WLC and the slit hole H_ST_LWI are connected via the cavity H27.

[0083] The inner walls of the contact hole H_WLC, except for the bottom, are protected by the spacer 26. Therefore, the second insulating film 51c is not exposed or etched on the inner walls of the contact hole H_WLC. Thus, the contact hole H_WLC and the slit hole H_ST_LWI communicate in the layer of the second insulating film 51c exposed at the bottom of the contact hole H_WLC, but not in the other layers of the second insulating film 51c.

[0084] In Figure 19, although not shown, the same applies to the other contact holes H_WLC. For example, in Figure 18, for convenience, the four contact holes are denoted as H_WLCd to H_WLCg, and the four corresponding cavities are denoted as H27d to H27g. Contact hole H_WLCd communicates with slit hole H_ST_LWI via cavity H27d in the second insulating film 51c, the second layer from the bottom of the laminate 51. Contact hole H_WLCe communicates with slit hole H_ST_LWI via cavity H27e in the second insulating film 51c, the third layer from the bottom of the laminate 51. Contact hole H_WLCf communicates with slit hole H_ST_LWI via cavity H27f in the second insulating film 51c, the fourth layer from the bottom of the laminate 51. The contact hole H_WLCg communicates with the slit hole H_ST_LWI via a cavity H27g in the second insulating film 51c, which is the fifth layer from the bottom of the laminate 51.

[0085] Thus, the contact holes H_WLC and the slit holes H_ST_LWI communicate in the second insulating film 51c of different depths exposed at the bottom of each contact hole H_WLC, but not in the second insulating film 51c of other layers. As a result, multiple contact holes H_WLC communicate with the slit holes H_ST_LWI via cavities H27 in the second insulating film 51c of different layers.

[0086] Next, as shown in Figures 20 and 21, a sacrificial film SAC2 is formed in the contact hole H_WLC and the slit hole H_ST_LWI. The sacrificial film SAC2 is composed of a material (e.g., polysilicon, carbon) that can be selectively etched against the spacer 26 and the laminate 51.

[0087] Next, using lithography and etching techniques, the interlayer insulating film 58 on the slit hole H_ST_CELL is removed, as shown in Figure 22.

[0088] Next, as shown in Figures 23 and 24, the second insulating film 51c of the laminate 51 in the cell region Rmc is isotropically etched through the slit hole H_ST_CELL using wet etching or the CDE method. As a result, as shown in Figure 23, multiple second insulating films 51c within the cell region Rmc are removed in the XY plane through the slit hole H_ST_CELL. In the cell region Rmc, the second insulating film 51c around the columnar body CL is removed.

[0089] Etching of the second insulating film 51c stops at slit ST_WLC. However, etching of the second insulating film 51c proceeds from the opening OP toward the WLHU region Rwlhu and reaches the slit hole H_ST_LWI. As a result, as shown in Figure 23, the slit hole H_ST_CELL communicates with the slit hole H_ST_LWI and the contact hole H_WLC through the opening OP. At this time, the slit hole H_ST_LWI and the contact hole H_WLC are filled with the sacrificial film SAC2.

[0090] As shown in Figure 24, a space SP is formed where the second insulating film 51c was present. In this case, in the cell region Rmc, the columnar body CL supports the first insulating film 51b, so bending or collapse of the first insulating film 51b can be suppressed. In the WLHU region Rwlhu, no support columns are provided except for the dummy columnar body DMC. However, in the WLHU region Rwlhu, except near the slit hole H_ST_LWI and the contact hole H_WLC, the second insulating film 51c remains, and no space SP is formed. Therefore, in the WLHU region Rwlhu, bending or collapse of the laminate 51 can be suppressed even without support columns.

[0091] Next, as shown in Figures 25 and 26, the sacrificial film SAC2 is selectively removed using a wet etching method or an ashing method. As a result, the slit hole H_ST_CELL communicates with the slit hole H_ST_LWI through the spaces SP in each layer formed by the removal of multiple second insulating films 51c.

[0092] Next, a thin block insulating film (e.g., an aluminum oxide film) is formed on the inner wall of the space SP formed between the first insulating films 51b via the contact hole H_WLC, slit hole H_ST_CELL, and slit hole H_ST_LWI. Furthermore, a titanium nitride film (e.g., an aluminum oxide film) is formed inside the block insulating film, and a conductive material is embedded further inside. Examples of conductive materials include tungsten and molybdenum. This forms an electrode film 51a between adjacent first insulating films 51b in the Z direction. The first and third laminates 51_1 and 51_3 become laminates containing multiple first insulating films 51b and multiple electrode films 51a. The second laminate 51_2 becomes a laminate containing multiple first insulating films 51b and multiple second insulating films 51c. In this way, in the first and third laminates 51_1 and 51_3, the second insulating film 51c is replaced with an electrode film 51a (replacement step).

[0093] Next, by using a wet etching method, the material of the electrode film 51a formed on the inner walls of the contact hole H_WLC, slit hole H_ST_CELL, and slit hole H_ST_LWI is etched to remove the short-circuit paths between adjacent electrode films 51a in the Z direction, thereby obtaining the structures shown in Figures 27 and 28.

[0094] Next, a sacrificial film SAC3, such as polysilicon or carbon, is filled into the contact hole H_WLC, slit hole H_ST_CELL, and slit hole H_ST_LWI. Then, the upper part of the sacrificial film SAC3 is removed using CMP or RIE etching, and an interlayer insulating film 58 is deposited on the surface. Subsequently, the interlayer insulating film 58 on the slit holes H_ST_CELL and H_ST_LWI is removed using lithography techniques, and the sacrificial film SAC3 in the slit holes H_ST_CELL and H_ST_LWI is selectively removed using wet etching or ashing. At this time, the sacrificial film SAC3 is left in the contact hole H_WLC. This results in the structure shown in Figure 29.

[0095] Next, as shown in Figure 30, spacers 26 are formed on the inner walls of the slit holes H_ST_CELL and H_ST_LWI.

[0096] Next, the interlayer insulating film 58 on the contact hole H_WLC is removed using lithography and etching techniques to expose the sacrificial film SAC3. Then, the sacrificial film SAC3 is removed using a wet etching method or ashing method, as shown in Figure 31.

[0097] Next, conductive material is embedded in the contact hole H_WLC, the slit hole H_ST_CELL, and the slit hole H_ST_LWI. This results in the structures shown in Figures 7 and 8.

[0098] Subsequently, multilayer wiring layers and the like (not shown) are formed on the interlayer insulating film 58, and the semiconductor memory device according to this embodiment is completed through the process described with reference to Figures 3 to 6.

[0099] According to the manufacturing method of this embodiment, when the second insulating film 51c of the first and third laminates 51_1 and 51_3 is replaced with the electrode film 51a, the second insulating film 51c of the second laminate 51_2 is left in place without being replaced. This makes it possible to prevent the first insulating film 51b from bending or collapsing due to its own weight in the WLHU region Rwlhu without the need to provide support columns.

[0100] (Second Embodiment) Figure 32 is a plan view showing an example of the configuration of a memory cell array 11 according to the second embodiment. In the second embodiment, the slits ST_CELL, ST_WLC, and ST_LWI are formed using a plurality of holes H_ST_CELL, H_ST_WLC, and H_ST_LWI arranged in the X direction. Therefore, the slits ST_CELL, ST_WLC, and ST_LWI each extend in the direction of the arrangement of the plurality of holes (H_ST_CELL, H_ST_WLC, H_ST_LWI). The slits ST_CELL and ST_WLC are formed by connecting the plurality of holes (H_ST_CELL, H_ST_WLC) with an insulating film, such as a silicon oxide film, by filling the area around the plurality of holes (H_ST_CELL, H_ST_WLC). The slit ST_LWI is formed by connecting the plurality of holes (H_ST_LWI) with a conductive material, such as tungsten, by filling the area around the plurality of holes (H_ST_LWI).

[0101] For example, a slit ST_CELL contains a plurality of holes H_ST_CELL that penetrate the first laminate 51_1 in the Z direction and are arranged in the X direction. A slit ST_CELL is formed by selectively removing the second insulating film 51c between adjacent first insulating films 51b in the Z direction via the plurality of holes H_ST_CELL, and filling the space with an insulating film such as a silicon oxide film. As a result, the slit ST_CELL is formed so that adjacent holes H_ST_CELL in the X direction are connected by their insulating films. Therefore, the slit ST_CELL extends in the X direction where the plurality of holes H_ST_CELL are arranged, electrically isolating the first laminate 51_1 for each block BLK.

[0102] Furthermore, the slit ST_CELL extends from between adjacent blocks BLK in the X direction to the second laminate 51_2 of the WLHU region Rwlhu, separating adjacent word line contacts WLC in the Y direction.

[0103] A slit ST_WLC contains multiple holes H_ST_WLC that penetrate multiple first insulating films 51b between the first laminate 51_1 and the second laminate 51_2 in the Z direction and are arranged in the Y direction. The slit ST_WLC fills the spaces between adjacent first insulating films 51b in the Z direction via the multiple holes H_ST_WLC with an insulating film, such as a silicon oxide film. As a result, the slit ST_WLC is formed so that adjacent holes H_ST_WLC in the Y direction are connected by their insulating films. Therefore, the slit ST_WLC extends in the Y direction where the multiple holes H_ST_WLC are arranged, separating the cell region Rmc from the WLHU region Rwlhu.

[0104] Furthermore, the slit ST_WLC has an opening OP, similar to the first embodiment, and the cell region Rmc and the WLHU region Rwlhu are connected at the opening OP.

[0105] The slit ST_LWI contains a plurality of holes H_ST_LWI that penetrate the third laminate 51_3 in the Z direction and are arranged in the X direction. The slit ST_LWI is formed by selectively removing the second insulating film 51c between adjacent first insulating films 51b in the Z direction via the plurality of holes H_ST_LWI, and filling it with a conductive material such as tungsten. As a result, the slit ST_LWI is formed so that adjacent holes H_ST_LWI in the X direction are connected by the conductive material. Therefore, the slit ST_LWI extends in the X direction where the plurality of holes H_ST_LWI are arranged, and electrically connects the electrode film 51a of the first laminate 51_1 to the word line contact WLC. The electrode film 51a of the slit ST_LWI functions as a path leading to the word line contact WLC via the opening OP.

[0106] Furthermore, spacers 26 are provided on the inner walls of multiple holes H_ST_LWI, and the holes H_ST_LWI themselves are electrically insulated from the third laminate 51_3. Therefore, electrode films 51a adjacent to each other in the Z direction of the third laminate 51_3 are electrically isolated.

[0107] Furthermore, in the second embodiment, a slit ST_WLC2 is provided. The slit ST_WLC2 extends in the Y direction from the slit ST_CELL toward the slit ST_LWI between a plurality of word line contact WLCs adjacent to each other in the X direction. The slit ST_WLC2 penetrates the second laminate 51_2 in the Z direction and includes a plurality of holes H_ST_WLC2 arranged in the Y direction. The slit ST_WLC2 is formed by selectively removing the second insulating film 51c between the first insulating film 51b via the plurality of holes H_ST_WLC2 and filling it with an insulating film such as a silicon oxide film. As a result, the slit ST_WLC2 is formed so as to connect adjacent holes H_ST_WLC2 in the Y direction with an insulating film. Therefore, the slit ST_WLC2 extends in the Y direction where the plurality of holes H_ST_WLC2 are arranged and separates adjacent word line contact WLCs in the X direction.

[0108] Multiple holes H_REP are provided on both sides of the slit ST_CELL in the cell region Rmc and are arranged in the X direction. At the boundary between the slit ST_CELL and the first laminate 51_1, the holes H_REP penetrate the slit ST_CELL or the first laminate 51_1 in the Z direction. A spacer 26 is provided on the inner wall of the hole H_REP, and a conductive material is provided inside the spacer 26. The holes H_REP are used when replacing the second insulating film 51c of the first laminate 51_1 with the electrode film 51a.

[0109] Multiple dummy columnar DMCs are provided on both sides of the third stack 51_3 in the WLHU region Rwlhu and are arranged in the X direction. The dummy columnar DMCs penetrate either the second stack 51_2 or the third stack 51_3 in the Z direction at the boundary between the second stack 51_2 and the third stack 51_3. The dummy columnar DMCs have the same configuration as columnar CLs but do not function as memory cells MCs. The dummy columnar DMCs are used as supports for the first insulating film 51b of the third stack 51_3 when replacing the second insulating film 51c of the third stack 51_3 with the electrode film 51a. Note that the dummy columnar DMCs are not necessarily required to be provided.

[0110] Multiple word line contacts (WLCs) are provided by extending the second laminate 51_2 in the Z direction and reaching the respective depths of the multiple electrode films 51a (i.e., word lines WL). Each word line contact WLC is electrically connected to one of the electrode films 51a of the third laminate 51_3 via a connect layer 27 provided at its bottom. The third laminate 51_3 has multiple electrode films 51a extending the WLHU region Rwlhu in the X direction and is electrically connected to the multiple electrode films 51a of the first laminate 51_1 at the opening OP. Therefore, the voltage of each word line WL can be controlled via each word line contact WLC.

[0111] The other configurations of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0112] Next, a method for manufacturing a semiconductor memory device according to the second embodiment will be described.

[0113] Figures 33 to 39 are plan views showing an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Similar to the first embodiment, a laminate 51 is formed by stacking a plurality of first insulating films 51b (e.g., silicon oxide films) and a plurality of second insulating films 51c (e.g., silicon nitride films).

[0114] Next, as shown in Figure 33, the word line contact WLC contact holes H_WLC are formed in the laminate 51. Multiple contact holes H_WLC are formed at different depths in the WLHU region Rwlhu so as to reach each of the multiple second insulating films 51c of the laminate 51. Next, the contact holes H_WLC are filled with a sacrificial film SAC1 (e.g., polysilicon or carbon).

[0115] Next, as shown in Figure 34, multiple memory holes MH are formed in the cell region Rmc. The memory holes MH are formed to penetrate the stack 51. At the same time, holes H_REP, H_ST_CELL, H_ST_WLC, H_ST_WLC2, and DMH are also formed to penetrate the stack 51. The sacrificial film SAC1 is also filled into the memory holes MH and holes H_REP, H_ST_CELL, H_ST_WLC, H_ST_WLC2, and DMH.

[0116] Next, a silicon oxide film 58 is deposited on the surface of the laminate 51, and the silicon oxide film 58 on the holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2 is removed using lithography and etching techniques, and the sacrificial film SAC1 is selectively removed using a wet etching method or an ashing method.

[0117] Next, using a wet etching method, portions of each of the multiple second insulating films 51c of the laminate 51 are isotropically etched through the holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2. As a result, the holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2 communicate in the space after the second insulating film 51c has been removed.

[0118] Next, a fourth insulating film is embedded in the space remaining after the second insulating film 51c is removed through the holes H_ST_CELL, H_ST_WLC, and H_ST_WLC2. For the fourth insulating film, an insulating material such as a silicon oxide film is used. As a result, as shown in Figure 35, the slits ST_CELL, ST_WLC, and ST_WLC2 are composed of a laminate of the first insulating film 51b and the fourth insulating film.

[0119] Next, an interlayer insulating film 58 is deposited on the surface of the laminate 51, and the interlayer insulating film 58 on the memory holes MH and dummy holes DMH is removed using lithography and etching techniques, and the internal sacrificial film SAC1 is selectively removed using a wet etching method or an ashing method.

[0120] Next, as shown in Figure 36, a columnar body CL is formed in the memory hole MH, and a dummy columnar body DMC is formed in the dummy hole DMH. The columnar body CL and the dummy columnar body DMC have the same configuration as those in the first embodiment and are formed in the same process.

[0121] Next, an interlayer insulating film 58 is deposited on the surface of the laminate 51, and the interlayer insulating film 58 on the holes H_REP is removed using lithography and etching techniques, and the internal sacrificial film SAC1 is selectively removed using wet etching or ashing.

[0122] Next, the second insulating film 51c of the cell region Rmc is isotropically etched through the hole H_REP using a wet etching method. As a result, as shown in Figure 37, the second insulating film 51c around the columnar body CL in the cell region Rmc is removed, and a space SP is formed between the first insulating films 51b. The space SP extends to the vicinity of the opening OP. The second insulating film 51c of the WLHU region Rwlhu remains.

[0123] Next, an interlayer insulating film 58 is deposited on the surface of the laminate 51, and the interlayer insulating film 58 on the contact hole H_WLC is removed using lithography and etching techniques, and the internal sacrificial film SAC1 is selectively removed using a wet etching method or an ashing method.

[0124] Next, a spacer 26 (for example, a silicon oxide film) is formed on the inner wall of the contact hole H_WLC. Then, the spacer 26 at the bottom of the contact hole H_WLC is anisotropically etched and removed. This removes the spacer 26 at the bottom of the contact hole H_WLC while leaving the spacer 26 on the side walls, exposing the second insulating film 51c at the bottom.

[0125] Using wet etching or the CDE method, the second insulating film 51c of the laminate 51 in the WLHU region Rwlhu is isotropically etched from the bottom of the contact hole H_WLC through the contact hole H_WLC. As a result, as shown in Figure 38, the second insulating film 51c is etched in the XY plane from the bottom of the contact hole H_WLC toward the slits ST_CELL, ST_WLC, and ST_WLC2. Spaces SP are formed where the second insulating film 51c has been etched. The slits ST_CELL, ST_WLC, and ST_WLC2 function as etching stoppers.

[0126] Here, multiple contact holes H_WLC are formed at different depths in the WLHU region Rwlhu, reaching each of the multiple second insulating films 51c of the laminate 51. Therefore, each of the multiple contact holes H_WLC forms a space SP in multiple layers of different heights. The second insulating film 51c, except for the bottom of the contact hole H_WLC, is not etched because it is covered by the spacer 26. Figure 38 shows only one space SP formed at the bottom of one contact hole H_WL.

[0127] Next, an interlayer insulating film 58 is deposited on the surface of the laminate 51, and the interlayer insulating film 58 on multiple holes H_ST_LWI is removed using lithography and etching techniques, and the internal sacrificial film SAC1 is selectively removed using a wet etching method or an ashing method.

[0128] Next, the second insulating film 51c of the laminate 51 in the WLHU region Rwlhu is isotropically etched through multiple holes H_ST_LWI using wet etching or the CDE method. The multiple holes H_ST_LWI communicate in the X direction in the space SP after the second insulating film 51c has been removed. As a result, as shown in Figure 39, the space SP is continuously connected from the opening OP in the direction of the arrangement of the multiple holes H_ST_LWI (X direction). Furthermore, the space SP from the holes H_ST_LWI communicates with the space SP from each contact hole H_WLC. Note that the space SP from the holes H_ST_LWI is formed by etching the second insulating film 51c of each layer of the laminate 51. At this time, the dummy columnar body DMC functions as a support column to prevent the first insulating film 51b between the contact hole H_WLC and the hole H_ST_LWI from bending.

[0129] Spatial SP communicates with hole H_ST_LWI in WLHU region Rwlhu via opening OP from cell region Rmc. Furthermore, spatial SP communicates with the corresponding contact hole H_WLC in each layer via spatial SP from hole H_ST_LWI.

[0130] Next, a thin block insulating film (e.g., an aluminum oxide film) is formed on the inner wall of the space SP formed between the first insulating films 51b via holes H_REP, H_ST_LWI, and contact hole H_WLC. Furthermore, a titanium nitride film (e.g., an aluminum oxide film) is formed inside the block insulating film, and a conductive material is embedded further inside. Examples of conductive materials include tungsten and molybdenum. This forms an electrode film 51a between adjacent first insulating films 51b in the Z direction. The first and third laminates 51_1 and 51_3 become laminates containing multiple first insulating films 51b and multiple electrode films 51a. The second laminate 51_2 remains a laminate containing multiple first insulating films 51b and multiple second insulating films 51c. In this way, in the first and third laminates 51_1 and 51_3, the second insulating films 51c are replaced with electrode films 51a (replacement process).

[0131] Next, the material of the electrode film 51a formed on the inner walls of hole H_REP, hole H_ST_LWI, and contact hole H_WLC is etched by a wet etching method to remove short-circuit paths between adjacent electrode films 51a in the Z direction.

[0132] Next, a sacrificial film SAC3 (e.g., polysilicon or carbon) is filled into holes H_REP, H_ST_LWI, and contact hole H_WLC. Then, the upper part of the sacrificial film SAC3 is removed using CMP or RIE etching, and an interlayer insulating film 58 is deposited on the surface. Subsequently, the interlayer insulating film 58 on holes H_REP and H_ST_LWI is removed using lithography, and the sacrificial film SAC3 inside holes H_REP and H_ST_LWI is selectively removed using wet etching or ashing. At this time, the sacrificial film SAC3 is left in the contact hole H_WLC. Next, a spacer 26 (e.g., silicon oxide film) is formed on the inner walls of holes H_REP and H_ST_LWI. Then, a conductive material is embedded inside the spacer 26. This results in the structure shown in Figure 32.

[0133] Subsequently, a multilayer wiring layer (not shown) is formed, and the semiconductor memory device according to the second embodiment is completed through the process described with reference to Figures 3 to 6.

[0134] According to the second embodiment, slits ST_CELL, ST_LWI, ST_WLC, and ST_WLC2 are formed in the direction of the arrangement of holes H_ST_CELL, H_ST_LWI, H_ST_WLC, and H_ST_WLC2. As a result, the area in the WLHU region Rwlhu where the second insulating film 51c is replaced by the electrode film 51a is limited, so that the first insulating film 51b is less likely to bend during the replacement process. Therefore, it is not necessary to provide support columns in the WLHU region Rwlhu. In other words, the second embodiment can obtain the same effects as the first embodiment.

[0135] According to the second embodiment, the hole H_ST_CELL used to form the slit ST_CELL is provided separately from the hole H_REP used in the replacement process. Therefore, the slit ST_CELL can be formed not only in the cell region Rmc but also in the WLHU region Rwlhu. This makes the first insulating film 51b even less prone to bending during the replacement process.

[0136] According to the second embodiment, in the WLHU region Rwlhu, a slit ST_WLC2 is provided between adjacent word line contact WLCs in the X direction. This makes the first insulating film 51b less prone to bending during the replacement process, and limits the amount of the second insulating film 51c etched through each contact hole H_WLC, thereby suppressing short circuits between adjacent word line contact WLCs.

[0137] In addition, one block BLK is provided with one opening OP and one slit ST_LWI. However, one block BLK may be provided with multiple openings OP and multiple slits ST_LWI. In this case, a word line contact WLC may be provided around each slit ST_LWI.

[0138] (Third embodiment) Figure 40 is a plan view showing an example configuration of a semiconductor memory device according to the third embodiment. Figure 41 is a cross-sectional view along line A41-A41 in Figure 40. Figure 42 is a cross-sectional view along line B42-B42 in Figure 40. Figure 40 shows a plane at the height level indicated by the dashed lines in Figures 41 and 42.

[0139] In the third embodiment, the second laminate 51_2 is processed in a stepped manner in the WLHU region Rwlhu. For example, the second laminate 51_2 has steps STP1 to STP8, as shown in Figure 40. Steps STP1 to STP8 descend sequentially in the -Z direction. Above steps STP1 to STP8 of the second laminate 51_2, an interlayer insulating film 57 is provided, as shown in Figures 41 and 42. Multiple word line contacts (WLCs) penetrate the interlayer insulating film 57 provided on the second laminate 51_2 in the Z direction to the depth of their respective corresponding electrode films 51a. Each of the multiple word line contacts (WLCs) corresponds to each of the steps STP1 to STP8 and is electrically connected to each of the multiple electrode films 51a directly below steps STP1 to STP8 via a connect layer 27. Therefore, each of the multiple word line contacts (WLCs) extends within the interlayer insulating film 57 to a different depth.

[0140] The second laminate 51_2 is processed in a stepped manner in both the X and Y directions. Therefore, the second laminate 51_2 descends in steps STP1, STP3, STP5, and STP7 in the X direction, and also descends in steps STP2, STP4, STP6, and STP8. Furthermore, the second laminate 51_2 descends in steps STP1 and STP2 in the Y direction, descends in steps STP3 and STP4, descends in steps STP5 and STP6, and also descends in steps STP7 and STP8.

[0141] The slit ST_LWI includes a plurality of holes H_ST_LWI that penetrate the third laminate 51_3 in the Z direction and are arranged in the X direction. The slit ST_LWI is formed by filling the spaces between adjacent first insulating films 51b in the Z direction with a conductive material, such as tungsten, via the plurality of holes H_ST_LWI. Thus, the slit ST_LWI is formed so that adjacent holes H_ST_LWI in the X direction are connected by a conductive material. Therefore, the slit ST_LWI extends in the X direction where the plurality of holes H_ST_LWI are arranged, and electrically connects the electrode film 51a of the first laminate 51_1 to the word line contact WLC. The electrode film 51a of the slit ST_LWI functions as a path leading to the word line contact WLC via the opening OP. That is, the slit ST_LWI (electrode film 51a of the third laminate 51_3) can function similarly to that of the second embodiment. Furthermore, the third laminate 51_3 can be formed using the hole H_ST_LWI in the same manner as in the second embodiment.

[0142] Multiple word line contacts (WLCs) are connected to a connect layer 27 provided at the bottom of each, and are electrically connected to the corresponding electrode film 51a of the third laminate 51_3 via the connect layer 27. The configuration and formation method of the word line contacts WLCs and the connect layer 27 may be the same as those of the second embodiment. However, the holes H_ST_LWI are provided penetrating the third laminate 51_3 below the interlayer insulating film 57, but are not provided in the interlayer insulating film 57. On the other hand, the word line contacts WLCs penetrate the interlayer insulating film 57 and are provided to the depth of the connect layer 27, but are not formed inside the second laminate 51_2.

[0143] For example, as shown in Figures 41 and 42, the word line contact WLCa penetrates the interlayer insulating film 57 and is formed up to the connect layer 27 corresponding to step STP5. The connect layer 27 corresponding to the word line contact WLCa is connected to the electrode film 51a (i.e., the word line WL) which is provided at the same height. This allows the word line contact WLCa to control the voltage of the corresponding word line WL.

[0144] In Figure 41, the word line contact WLCb penetrates the interlayer insulating film 57 and is formed down to the connect layer 27, which corresponds to step STP6, one step below the word line contact WLCa. The connect layer 27 corresponding to the word line contact WLCb is connected to the electrode film 51a, which is provided at the same height. As a result, the word line contact WLCb can control the voltage of the corresponding word line WL.

[0145] In Figure 42, the word line contact WLCc penetrates the interlayer insulating film 57 and is formed down to the connect layer 27, which corresponds to step STP7, one step below the word line contact WLCb. The connect layer 27 corresponding to the word line contact WLCc is connected to the electrode film 51a, which is provided at the same height. As a result, the word line contact WLCc can control the voltage of the corresponding word line WL.

[0146] Similarly, for the other steps STP1 to STP4 and STP8, the word line contacts WLC are electrically connected to their respective word lines WL. This allows multiple word line contacts WLC to control the voltage of their respective word lines WL.

[0147] The third embodiment differs from the second embodiment in that the second laminate 51_2 is processed in a stepped manner in the WLHU region Rwlhu, and an interlayer insulating film 57 is provided on top of it. However, the configuration of the third embodiment is substantially the same as that of the second embodiment. Therefore, the third embodiment does not require support columns in the WLHU region Rwlhu, and the same effects as the second embodiment can be obtained. Furthermore, the manufacturing method of the third embodiment can be understood by referring to the manufacturing method of the second embodiment. Therefore, the explanation of the manufacturing method of the third embodiment is omitted here.

[0148] In addition, one block BLK is provided with one opening OP and one slit ST_LWI. However, one block BLK may be provided with multiple openings OP and multiple slits ST_LWI. In this case, a word line contact WLC may be provided around each slit ST_LWI.

[0149] (Fourth Embodiment) Figures 43 and 44 are plan views showing an example configuration of a semiconductor memory device according to the fourth embodiment. Figure 44 shows an enlarged plan view of a part of the configuration in Figure 43. Figure 45 is a cross-sectional view along line A45-A45 in Figure 44. Figure 46 is a cross-sectional view along line B46-B46 in Figure 44. Figure 44 shows a plan view at the height level indicated by the dashed lines in Figures 45 and 46.

[0150] As shown in Figure 43, in the fourth embodiment, the WLHU region Rwlhu is provided between a plurality of adjacent cell regions Rmc in the X direction and is shared by these memory cell arrays 11.

[0151] In the fourth embodiment, the WLHU region Rwlhu includes a step portion STP and a bridge portion BRG. The step portion STP is a second laminate 51_2 that is processed in a step-like manner so as to descend from the center of the WLHU region Rwlhu toward the cell regions Rmc on both sides. The bridge portion BRG is not processed in a step-like manner and remains in place until the uppermost layer, and is a second laminate 51_2 that connects multiple adjacent cell regions Rmc.

[0152] In the fourth embodiment, the word line contact WLC is connected to a slit ST_LWI provided in the bridge section BRG via a slit ST_LWI provided in the step section STP. The slit ST_LWI is also provided in the bridge section BRG and branches in the ±X direction in the bridge section BRG to connect to a plurality of adjacent memory cell arrays 11. The slit ST_LWI includes a hole H_ST_LWI and a third stack 51_3 provided around it. The word line contact WLC is electrically connected to the electrode film 51a (word line WL) of the cell region Rmc via the electrode film 51a of the third stack 51_3.

[0153] For example, as shown in Figure 44, the second laminate 51_2 has steps STP1 to STP6. Steps STP1 to STP6 descend sequentially in the -Z direction. Above steps STP1 to STP6 of the second laminate 51_2, an interlayer insulating film 57 is provided, as shown in Figures 45 and 46. Multiple word line contacts (WLCs) penetrate the interlayer insulating film 57 provided on the second laminate 51_2 in the Z direction to the depth of their respective corresponding electrode films 51a. Each of the multiple word line contacts (WLCs) corresponds to each of the steps STP1 to STP6 and is electrically connected to each of the multiple electrode films 51a directly below steps STP1 to STP6 via a connect layer 27. Thus, each of the multiple word line contacts (WLCs) extends within the interlayer insulating film 57 to a different depth.

[0154] The second laminate 51_2 is processed in a stepped manner in both the X and Y directions. Therefore, the second laminate 51_2 descends in steps STP1, STP3, and STP5 in the X direction, and also descends in steps STP2, STP4, and STP6. Furthermore, the second laminate 51_2 descends in steps STP1 and STP2 in the Y direction, descends in steps STP3 and STP4, and also descends in steps STP5 and STP6.

[0155] The slit ST_LWI has the same configuration as that of the third embodiment. The slit ST_LWI extends in the X direction, with a plurality of holes H_ST_LWI arranged therein, and electrically connects the electrode film 51a of the first laminate 51_1 to the word line contact WLC. The electrode film 51a of the slit ST_LWI functions as a path leading to the word line contact WLC through the opening OP.

[0156] In the fourth embodiment, the slit ST_LWI is provided across the step section STP, the second laminate 51_2 in the center of the WLHU region Rwlhu, and the second laminate 51_2 of the bridge section BRG. Furthermore, the slit ST_LWI branches out in the bridge section BRG toward a plurality of adjacent cell regions Rmc in the X direction, and is connected to the first laminate 51_1 of both at the opening OP of these cell regions Rmc. As a result, the word line contact WLC is electrically connected in common to the corresponding word line WL in each of the adjacent cell regions Rmc.

[0157] Multiple word line contacts (WLCs) are connected to a connect layer 27 provided at the bottom of each, and are electrically connected to the corresponding electrode film 51a of the third laminate 51_3 via the connect layer 27. The configuration and formation method of the word line contacts WLCs and the connect layer 27 may be the same as those of the second embodiment. However, the holes H_ST_LWI are provided penetrating the third laminate 51_3 below the interlayer insulating film 57, but are not provided in the interlayer insulating film 57. On the other hand, the word line contacts WLCs penetrate the interlayer insulating film 57 and are provided to the depth of the connect layer 27, but are not formed inside the second laminate 51_2.

[0158] For example, as shown in Figures 45 and 46, the word line contact WLCa penetrates the interlayer insulating film 57 and is formed up to the connect layer 27 corresponding to step STP3. The connect layer 27 corresponding to the word line contact WLCa is connected to the electrode film 51a (i.e., the word line WL) which is provided at the same height. This allows the word line contact WLCa to control the voltage of the corresponding word line WL.

[0159] In Figure 45, the word line contact WLCb penetrates the interlayer insulating film 57 and is formed down to the connect layer 27, which corresponds to step STP4, one step below the word line contact WLCa. The connect layer 27 corresponding to the word line contact WLCb is connected to the electrode film 51a, which is provided at the same height. As a result, the word line contact WLCb can control the voltage of the corresponding word line WL.

[0160] In Figure 46, the word line contact WLCc penetrates the interlayer insulating film 57 and is formed down to the connect layer 27, which corresponds to step STP5, one step below the word line contact WLCb. The connect layer 27 corresponding to the word line contact WLCc is connected to the electrode film 51a, which is provided at the same height. As a result, the word line contact WLCc can control the voltage of the corresponding word line WL.

[0161] Similarly, in the other steps STP1, STP2, and STP6, the word line contacts WLC are electrically connected to their respective corresponding word lines WL. That is, the multiple connect layers 27 electrically connect the multiple word line contacts WLC to the multiple electrode films 51a in the adjacent memory cell array 11. This allows the multiple word line contacts WLC to independently control the voltage of their respective corresponding word lines WL.

[0162] The fourth embodiment differs from the third embodiment in the arrangement of the WLHU region Rwlhu, the configuration of the step section STP, and the configuration of the bridge section BRG. Therefore, the fourth embodiment differs from the third embodiment in the path of the slit ST_LWI that electrically connects the word line contact WLC and the word line WL. However, the other configurations of the fourth embodiment correspond to the configuration of the third embodiment. Thus, the fourth embodiment also does not require support columns in the WLHU region Rwlhu, and the same effects as the second embodiment can be obtained. Furthermore, the manufacturing method of the fourth embodiment can be understood by referring to the manufacturing method of the second embodiment, just as with the third embodiment. Therefore, the description of the manufacturing method of the fourth embodiment is omitted here.

[0163] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0164] 11 memory cell array BLK Block MC memory cell DMC Dummy Columnar Body WL Word Line Rwlhu, WLHU area Rmc cell area 51_1 First Laminate 51_2 Second Laminate 51_3 Third Layer ST_WLC, ST_LWI, ST_CELL slits WLC Word Line Contacts 26 Spacers 27 Connect Layer 51a Electrode membrane 51b, 51c First and second insulating films 57, 58 Interlayer insulating film

Claims

1. A first laminate in which electrode films and first insulating films are alternately stacked in a first direction, A second laminate is provided adjacent to the first laminate, wherein the first insulating film and the second insulating film are alternately laminated in the first direction, A third laminate is formed in which the electrode film and the first insulating film are alternately laminated in the first direction, extending in a second direction from the end of the first laminate within a first plane perpendicular to the first direction, A first columnar body comprising a semiconductor layer provided penetrating the first laminate in a first direction, wherein the intersection portion with the plurality of electrode films constitutes a plurality of memory cells with the plurality of electrode films as gate electrodes, A plurality of contacts extending in the first direction within the second laminate or within a third insulating film provided above the second laminate, and provided to the depth of each of the plurality of electrode films of the third laminate, A plurality of connect layers that electrically connect the plurality of contacts and the plurality of electrode films corresponding to each of the plurality of contacts, A semiconductor memory device equipped with the following features.

2. The semiconductor memory device according to claim 1, further comprising a plurality of first slits that penetrate the first laminate in a first direction and extend in a second direction, dividing the first laminate into a plurality of blocks.

3. The semiconductor memory device according to claim 2, further comprising a second slit between the first laminate and the second laminate, which penetrates the first or second laminate in a first direction, extends intermittently in a third direction perpendicular to the second direction within the first plane, and has an opening that connects a portion of the plurality of blocks to the third laminate.

4. The semiconductor memory device according to claim 3, further comprising a third slit extending in the second direction within the third laminate and penetrating the third laminate in the first direction.

5. Each of the plurality of electrode films of the first laminate is electrically connected to the plurality of electrode films of the third laminate. The semiconductor memory device according to claim 1, wherein in the first and third laminates, the plurality of electrode films adjacent in the first direction are electrically isolated by the first insulating film.

6. The plurality of first insulating films in the first and third laminates correspond to the plurality of first insulating films in the second laminate, The semiconductor memory device according to claim 1, wherein the plurality of electrode films of the first and third laminates each correspond to the plurality of second insulating films of the second laminate.

7. The semiconductor memory device according to claim 1, wherein one of the plurality of contacts is electrically connected to the corresponding electrode film via one of the connect layers.

8. The semiconductor memory device according to claim 2, wherein the first slit includes a plurality of first holes that penetrate the plurality of first insulating films of the first laminate in a first direction and are arranged in a second direction.

9. A laminate is formed by alternately stacking the first insulating film and the second insulating film in the first direction. Between the first region of the laminate and the second region of the laminate adjacent to the first region, a second slit hole is formed having an opening that connects a part of the first region to the second region while separating the first region and the second region, and in the second region of the laminate, a plurality of contact holes are formed to the depth of each of the plurality of second insulating films. A plurality of first slit holes are formed in the first region of the laminate that penetrate in the first direction and extend in the second direction within a first plane perpendicular to the first direction, and a plurality of third slit holes are formed in the second region of the laminate that penetrate in the first direction and extend in the second direction. By removing a portion of the second insulating film on the bottom surface of each of the plurality of contact holes, and by removing a portion of the plurality of second insulating films in the second region through the plurality of third slit holes, the plurality of contact holes and the plurality of third slit holes are connected. The plurality of second insulating films in the first region are removed through the plurality of first slit holes, and the plurality of first slit holes are connected to the plurality of third slit holes through the opening. A method for manufacturing a semiconductor memory device, comprising: filling a conductive material into the space formed between the first insulating films by removing the second insulating film through the plurality of contact holes, the plurality of first slit holes, and the plurality of third slit holes, thereby forming an electrode film.

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