Capacitor structure and method for manufacturing the same

Abstract

The present invention provides a capacitor structure and a method for manufacturing the same that can improve defects in the lower electrode and increase capacitance. [Solution] The capacitor structure includes a substrate, a first support layer, and a capacitor. The first support layer is located on the substrate. The capacitor is located on the substrate. The capacitor includes a lower electrode, an upper electrode, and a dielectric layer. The lower electrode includes a first portion and a second portion. The first portion is located on a plurality of capacitor holes penetrating the first support layer. The second portion is electrically connected to the first portion and covers the bottom surface of the first support layer. The upper electrode is located on the lower electrode. The dielectric layer is located between the lower electrode and the upper electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly, to a capacitor structure having a columnar capacitor and a method for manufacturing the same.

Background Art

[0002] Columnar capacitors are semiconductor components widely applied in electronic products. However, as the dimensions of columnar capacitors are miniaturized, further improving the capacitance and yield of columnar capacitors has become a goal to be pursued. For example, in well-known columnar capacitors, since the lower electrodes of a plurality of columnar capacitors are separated from each other, a defect that the lower electrodes are peeled off easily occurs, thereby reducing the yield and also becoming a bottleneck in improving the capacitance.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a capacitor structure and a method for manufacturing the same that can improve the defects of the lower electrodes described above and eliminate the bottleneck in capacitance improvement.

Means for Solving the Problems

[0004] The present invention provides a capacitor structure including a substrate, a first support layer, and a capacitor. The first support layer is located on the substrate. The capacitor is located on the substrate. The capacitor includes a lower electrode, an upper electrode, and a dielectric layer. The lower electrode includes a first portion and a second portion. The first portion is located on a plurality of capacitor holes penetrating the first support layer. The second portion is electrically connected to the first portion and covers the bottom surface of the first support layer. The upper electrode is located on the lower electrode. The dielectric layer is located between the lower electrode and the upper electrode.

[0005] The present invention provides a method for manufacturing a capacitor structure, comprising the following steps: 1. Forming a first support layer on a substrate. 2. Forming the lower electrode of a capacitor. The lower electrode includes a first portion and a second portion. The first portion is formed on a plurality of capacitor holes penetrating the first support layer. The second portion is electrically connected to the first portion and covers the bottom surface of the first support layer. 3. Forming a dielectric layer of the capacitor on the lower electrode. 4. Forming the upper electrode of the capacitor on the dielectric layer. [Effects of the Invention]

[0006] As described above, in the capacitor structure provided by the present invention, the lower electrode includes a first portion and a second portion, the second portion covering the bottom surface of the first support layer and further formed within the cavity. In this way, the second portion of the lower electrode can provide an additional bonding area, thereby effectively improving the capacitance of the capacitor structure and allowing for a larger yield margin. Furthermore, the second portion of the lower electrode can effectively improve the structural strength of the capacitor structure, thereby improving the quality of the capacitor structure. [Brief explanation of the drawing]

[0007] [Figure 1A] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1B] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1C] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1D] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1E] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1F] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1G]This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1H] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1I] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1J] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1K] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1L] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 1M] This is a top view of the manufacturing process of a capacitor structure according to several embodiments of the present invention. [Figure 2A] This is a cross-sectional view along the I-I' section in Figure 1A. [Figure 2B] This is a cross-sectional view along the line I-I' in Figure 1B. [Figure 2C] This is a cross-sectional view along the line I-I' in Figure 1C. [Figure 2D] This is a cross-sectional view along the line I-I' in Figure 1D. [Figure 2E] This is a cross-sectional view along the line I-I' in Figure 1E. [Figure 2F] This is a cross-sectional view along the line I-I' in Figure 1F. [Figure 2G] This is a cross-sectional view along the line I-I' in Figure 1G. [Figure 2H] This is a cross-sectional view along the line I-I' in Figure 1H. [Figure 2I] This is a cross-sectional view along the line I-I' in Figure 1I. [Figure 2J] This is a cross-sectional view along the I-I' section in Figure 1J. [Figure 2K] This is a cross-sectional view along the line I-I' in Figure 1K. [Figure 2L] This is a cross-sectional view along the line I-I' in Figure 1L. [Figure 2M] It is a cross-sectional view taken along the I-I' cross-section line of FIG. 1M. [Figure 3A] It is a top view of the manufacturing process of the capacitor structure according to some other embodiments of the present invention. [Figure 3B] It is a top view of the manufacturing process of the capacitor structure according to some other embodiments of the present invention. [Figure 4A] It is a cross-sectional view taken along the I-I' cross-section line of FIG. 3A. [Figure 4B] It is a cross-sectional view taken along the I-I' cross-section line of FIG. 3B. [Figure 5] It is a cross-sectional view of the capacitor structure according to some other embodiments of the present invention. [Figure 6] It is a top view of the electrode layer 118a and the support layer 114 of FIG. 5. [Figure 7] It is a cross-sectional view of the capacitor structure according to some other embodiments of the present invention. [Figure 8] It is a top view of the electrode layer 118a and the support layer 114 of FIG. 7.

Mode for Carrying Out the Invention

[0008] Hereinafter, examples will be given for detailed description. For ease of understanding, in the following description, the same components will be denoted by the same reference numerals. FIGS. 1A to 1M are top views of the manufacturing process of the capacitor structure according to some embodiments of the present invention. FIGS. 2A to 2M are cross-sectional views taken along the I-I' cross-section line of FIGS. 1A to 1M.

[0009] Referring to Figures 1A and 2A, a dielectric layer 104 can be formed on the substrate 100, and a conductive plate 102 can be formed within the dielectric layer 104. Next, a termination layer 106, a sacrificial layer 108, a support layer 110, a sacrificial layer 112, and a support layer 114 can be formed sequentially on the conductive plate 102 and the dielectric layer 104. The substrate 100 may be a semiconductor substrate, for example, a silicon substrate. In some other embodiments, the substrate 100 may be a silicon-on-insulator (SOI). The material of the conductive plate 102 may be a metal, for example, tungsten or copper. In another embodiment, the conductive plate 102 may be a doped region (not shown) formed in the active region of the substrate 100. The material of the termination layer 106 may be a suitable etch-stop dielectric material. The materials of the support layers 110 and 114 may be a suitable support dielectric material. In this embodiment, the materials for the terminal layer 106, the support layer 110, and the support layer 114 are, for example, nitrides (e.g., silicon nitride). The materials for the sacrificial layer 108 and the sacrificial layer 112 may be insulating materials having an etching selectivity ratio with the support layers 110 and 114, such as oxides (e.g., silicon oxide).

[0010] Referring to Figures 1B and 2B, a patterned photoresist layer 116 can be formed on the support layer 114. Referring to Figures 1C and 2C, the patterned photoresist layer 116 can be used as a mask to pattern the support layer 114, sacrificial layer 112, support layer 110, sacrificial layer 108, and termination layer 106, thereby forming multiple capacitor holes OP1 within the support layer 114, sacrificial layer 112, support layer 110, sacrificial layer 108, and termination layer 106. In other words, the capacitor holes OP1 can penetrate the support layer 114, support layer 110, and termination layer 106, exposing the conductive plate 102. The patterned photoresist layer 116 can then be removed.

[0011] Referring to Figures 1D and 2D, the electrode material layer 118 can be conformally formed on the support layer 114 and within the capacitor hole OP1.

[0012] Referring to Figures 1E and 2E, a packing layer 120 can be formed on the electrode material layer 118 and within the capacitor hole OP1. The material of the packing layer 120 is, for example, an oxide (e.g., silicon oxide). Next, a hard mask layer 122 can be formed on the packing layer 120. The hard mask layer 122 may be a single-layer structure or a multi-layer structure. The material of the hard mask layer 122 is, for example, carbon, silicon nitride, or a combination thereof. Subsequently, a patterned photoresist layer 124 can be formed on the hard mask layer 122.

[0013] Referring to Figures 1F and 2F, first, a patterned photoresist layer 124 can be used as a mask to pattern a hard mask layer 122, thereby forming a patterned hard mask layer 122. Next, the patterned photoresist layer 124 can be removed. Then, using the patterned hard mask layer 122 as a mask, the packing layer 120, electrode material layer 118, and support layer 114 can be patterned to form an electrode layer 118a with the patterned electrode material layer 118. This allows for the formation of multiple openings OP2 that penetrate the support layer 114 and expose parts of the sacrificial layer 112, electrode layer 118a, and packing layer 120. Each opening OP2 is connected to a plurality of capacitor holes OP1 in which the electrode layer 118a has already been formed. The patterned hard mask layer 122 may be consumed during the process described above and may be removed afterward.

[0014] Referring to Figures 1G and 2G, for example, the packed layer 120 and sacrificial layer 112 can be removed using a wet etching method. Referring to Figures 1H and 2H, for example, a portion of the support layer 110 can be removed using a dry etching method, exposing a portion of the sacrificial layer 108. Next, referring to Figures 1I and 2I, for example, the sacrificial layer 108 can be removed using a wet etching method, forming an opening OP2 located between a plurality of electrode layers 118a and exposing the terminal layer 106. As shown in Figure 2I, the electrode layer 118a can be connected to the support layer 114, support layer 110, and terminal layer 106, and will not collapse because it is supported by the support layer 114 and support layer 110.

[0015] Referring to Figures 1J and 2J, an electrode material layer 126 can be formed that covers the electrode layer 118a, support layer 114, support layer 110, and terminal layer 106.

[0016] Referring to Figures 1K and 2K, a dielectric material layer 128 and an electrode material layer 130 can be formed sequentially on the electrode material layer 126. The material of the dielectric material layer 128 is, for example, a high dielectric constant material.

[0017] Referring to Figures 1L and 2L, electrode material layers 132 and 134 can be formed sequentially on electrode material layer 130. The material for electrode material layer 132 is, for example, doped silicon germanium, such as boron-doped silicon germanium (B-doped SiGe). The material for electrode material layer 134 is, for example, a conductive material such as tungsten.

[0018] In this embodiment, the terminal layer 106, sacrificial layer 108, support layer 110, sacrificial layer 112, support layer 114, electrode material layers 118, 126, 130, 134, and dielectric material layer 128 can each be formed by chemical vapor deposition, but the present invention is not limited thereto. The materials of the electrode material layers 118, 126, and 130 are conductive materials such as titanium nitride (TiN), but the present invention is not limited thereto.

[0019] Referring to Figures 1M and 2M, the electrode material layers 134, 132, 130, 128, and 126 can be patterned to form electrode layers 134a, 132a, 130a, 128a, and 126a, respectively, and the terminal layer 106 located in the peripheral region can be exposed.

[0020] The capacitor structure 10 of this embodiment will be described below with reference to Figures 1M and 2M. While the method for forming the capacitor structure 10 was described as an example, the present invention is not limited thereto. For clarity, the components related to the lower electrode E1 are shown in Figure 2J.

[0021] Referring to Figures 1M, 2J, and 2M, the capacitor structure 10 includes a substrate 100, a support layer 114, and a capacitor C1. The support layer 114 is located on the substrate 100. The capacitor C1 is located on the substrate 100. The capacitor C1 includes a lower electrode E1, an upper electrode E2, and a dielectric layer 128a. The lower electrode E1 includes a first portion E11 and a second portion E12. The first portion E11 of the lower electrode E1 is located on a plurality of capacitor holes OP1 that penetrate the support layer 114. The first portion E11 of the lower electrode E1 connects these capacitor holes OP1 to each other. In this embodiment, the first portion E11 of the lower electrode E1 can also cover the upper surface S1 and the first side wall S3 of the support layer 114. In this embodiment, the first portion E11 of the lower electrode E1 includes electrode layers 118a and 126a and has a first thickness T1. The second portion E12 of the lower electrode E1 is electrically connected to the first portion E11 of the lower electrode E1 and covers the bottom surface 114b of the support layer 114. In this embodiment, the second portion E12 of the lower electrode E1 includes the electrode layer 126a and may have a second thickness T2 (shown in Figure 2J) that is smaller than the first thickness T1. In this embodiment, the second portion E12 of the lower electrode E1 further covers the second side wall S4 of the support layer 114, and the first side wall S3 and the second side wall S4 face each other. The second portion E12 of the lower electrode E1 connects these capacitor holes OP1 to each other. A portion of the second portion E12 of the lower electrode E1 may be located within the cavity 112H defined by the first portion E11 of the lower electrode E1, the support layer 114, and the support layer 110. This can improve the capacitance and structural strength of the capacitor structure 10.

[0022] Furthermore, in this embodiment, as shown in Figures 1G and 2G, the electrode layer 118a may include a plurality of U-shaped cross-sectional structures 118U formed in these capacitor holes OP1 and planar structures EC1 connecting these U-shaped cross-sectional structures 118U to each other, but the present invention is not limited thereto. The planar structures EC1 of the electrode layer 118a may be located on the upper surface S1 of the support layer 114. By the step of forming the opening OP2 described above, the electrode layer 118a may have a plurality of upper surfaces S2 (shown in Figure 2M) located at different heights, thereby advantageous for the removal of sacrificial layers 108, 112 and the formation of the electrode material layer 126 and the dielectric material layer 128. As shown in Figures 1J, 2J, and 2M, the electrode layer 126a includes a plurality of U-shaped cross-sectional structures 126U formed in these capacitor holes OP1 and opening OP2 and planar structures EC2 connecting these U-shaped cross-sectional structures to each other. The electrode layer 126a covers the support layer 114 and the electrode layer 118a, and the electrode layer 126a is electrically connected to the electrode layer 118a. This effectively improves the capacitance and structural strength of the capacitor structure 10. Referring to Figure 2M, the upper electrode E2 is located on the lower electrode E1, and the dielectric layer 128a is located between the lower electrode E1 and the upper electrode E2. In this embodiment, the upper electrode E2 located on the dielectric layer 128a may include electrode layers 130a, 132a, and 134a in order.

[0023] The capacitor structure 10 may further include a conductive plate 102 and a dielectric layer 104. The conductive plate 102 is located below the first portion E11 of the lower electrode E1 and is electrically connected to the lower electrode E1. In this embodiment, the conductive plate 102 can be directly connected to the electrode layer 118a.

[0024] The capacitor structure 10 may further include a support layer 110 located between the support layer 114 and the substrate 100. Capacitor holes OP1 and opening OP2 penetrate the support layer 110. The second portion E12 of the lower electrode E1 may cover the upper surface 110a and the bottom surface 110b of the support layer 110. In this embodiment, the second portion E12 of the lower electrode E1 is located within a cavity 108H defined by the first portion E11, the support layer 110, and the termination layer 106.

[0025] The capacitor structure 10 may further include a termination layer 106. The capacitor hole OP1 penetrates the termination layer 106, while the opening OP2 does not penetrate the termination layer 106. The second portion E12 of the lower electrode E1 further covers the upper surface 106a of the termination layer 106. The termination layer 106 is located between the conductive plate 102 and the second portion E12 of the lower electrode E1. The electrode layer 118a can be connected to the termination layer 106. The electrode layer 126a can cover part of the termination layer 106.

[0026] Furthermore, the details of each component of the capacitor structure 10 (for example, materials and formation methods) have been explained in detail in the embodiments described above, so they will not be explained again here.

[0027] Based on the embodiment described above, the lower electrode E1 of the capacitor structure 10 includes a first portion E11 and a second portion E12, the second portion E12 covering the bottom surface 114b of the support layer 114 and further formed within the cavities 112H and 108H. Compared with well-known capacitor structures in which the lower electrode does not cover the bottom surface of the support layer and is not formed within the cavities, the capacitor structure 10 of this embodiment can provide additional bonding area, thereby effectively improving the capacitance of the capacitor structure 10 and allowing for a larger yield margin. Furthermore, the capacitor structure 10 of this embodiment can effectively improve the structural strength of the lower electrode E1 via the planar structure EC2 connecting these U-shaped cross-sectional structures 126U and / or the planar structure EC1 connecting these U-shaped cross-sectional structures 118U to each other, thereby improving the quality of the capacitor structure 10.

[0028] Other modifications of the present invention are described below. Here, the same or similar components may be denoted by the same reference numerals, the same description may be omitted, and only the differences may be described.

[0029] Figures 3A and 3B are top views of the manufacturing process of a capacitor structure according to another embodiment of the present invention. Figures 4A and 4B are cross-sectional views along the I-I' section in Figures 3A and 3B.

[0030] Referring to Figures 3A and 4A, the structures of Figures 3A and 4A can be obtained by performing steps similar to those in Figures 1E and 2E. The difference is that the pattern of the patterned photoresist layer 124 in Figures 3A and 4A is different from the pattern of the patterned photoresist layer 124 in Figures 1E and 2E.

[0031] Next, by performing the same steps as in Figures 1F to 1M and Figures 2F to 2M, the capacitor structure 20 shown in Figures 3B and 4B can be obtained. The difference between the capacitor structure 20 and the capacitor structure 10 is as follows: In the capacitor structure 20, all upper surfaces S2 of the electrode layer 118a can have the same height. In other words, the capacitor structure 20 does not have the step of forming the opening OP2.

[0032] Figure 5 is a cross-sectional view of a capacitor structure according to another embodiment of the present invention. Figure 6 is a top view of the electrode layer 118a and support layer 114 of Figure 5.

[0033] Referring to Figures 2M and 5, the differences in the manufacturing method and structure between capacitor structure 30 and capacitor structure 10 are as follows. In the manufacturing method of capacitor structure 30, after forming the electrode layer 118a, a portion of the electrode layer 118a on the upper surface S1 of the support layer 114 can be removed. As a result, in capacitor structure 30, the electrode layer 118a is not located on the upper surface S1 of the support layer 114, and the electrode layer 118a does not include a planar structure EC1 as shown in Figure 2M. As shown in Figure 6, in capacitor structure 30, the electrode layer 118a can form a plurality of mutually separated circular structures 118O with a U-shaped cross-section.

[0034] Figure 7 is a cross-sectional view of a capacitor structure according to another embodiment of the present invention. Figure 8 is a top view of the electrode layer 118a and support layer 114 of Figure 7.

[0035] Referring to Figures 4B and 7, the differences in manufacturing methods and structures between capacitor structure 40 and capacitor structure 20 are as follows. In the manufacturing method of capacitor structure 40, after forming the electrode layer 118a, a portion of the electrode layer 118a on the upper surface S1 of the support layer 114 can be removed. As a result, in capacitor structure 40, the electrode layer 118a is not located on the upper surface S1 of the support layer 114, and the electrode layer 118a does not include a planar structure EC1 as shown in Figure 4B. As shown in Figure 8, in capacitor structure 40, the electrode layer 118a can form a plurality of mutually separated circular structures 118O with a U-shaped cross-section.

[0036] Based on embodiments of the present invention, it is possible to improve the structural strength and capacitance of the capacitor structure, which is advantageous for improving yield. Furthermore, the present invention can be applied to the manufacture of miniaturized capacitor structures, and the total number of crystal grains on the wafer can be increased. Thus, the present invention can reduce the manufacturing cost and energy consumption of individual ICs and the subsequent production energy consumption of packaging, thereby reducing carbon emissions in the semiconductor structure production process. For this reason, the present invention provides an environmentally friendly semiconductor technology. [Industrial applicability]

[0037] The capacitor structure provided in the present invention can be used in fields such as electronic products, decoupling capacitors, high-bandwidth memory, smart mobile devices, wearable terminal devices, high-speed, high-capacity communication equipment, industrial equipment, and automotive equipment.

[0038] Although the present invention has been disclosed by the embodiments described above, these do not limit the invention, and any person with ordinary skill in the art may make some changes or modifications without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims described below. [Explanation of Symbols]

[0039] 10 Capacitor Structure 100 circuit boards 102 Conductive plate 104, 112, 128a Dielectric layer 106 Termination layer 106a, 110a, S1, S2 top surface 108 layers of victims 110, 114 supporter group 110b, 114b bottom 108H, 112H Cavity 116, 124 patterned photoresist layers 118 Electrode material layer 118a, 126a, 130a, 132a, 134a electrode layer 118O circular structure 118U, 126U U-shaped cross-section structure 120 Filled bed 122 Hard mask layer 126, 130, 132, 134 Electrode material layer 128 Dielectric material layer C1 Capacitor E1 lower electrode E2 upper electrode E11 Part 1 E12 Part 2 EC1, EC2 planar structure OP1, OP2 opening S3 1st side wall S4 2nd side wall T1 First Thread T2 Second thickness

Claims

1. circuit board and A first support layer located on the substrate, Located on the aforementioned substrate, A first portion located on a plurality of capacitor holes penetrating the first support layer, A second portion is electrically connected to the first portion and covers the bottom surface of the first support layer, A lower electrode including, An upper electrode located on the lower electrode, A dielectric layer located between the lower electrode and the upper electrode, A capacitor including, A capacitor structure including this.

2. The capacitor structure according to claim 1, wherein the first portion of the lower electrode has a first thickness, and the second portion has a second thickness smaller than the first thickness.

3. The capacitor structure according to claim 1, wherein a portion of the second portion of the lower electrode is located within a cavity defined by the first portion and the first support layer.

4. The capacitor structure according to claim 1, wherein the first portion of the lower electrode covers the upper surface and first side wall of the first support layer, the second portion of the lower electrode further covers the second side wall of the first support layer, and the first side wall and the second side wall face each other.

5. The capacitor structure according to claim 1, wherein the first portion of the lower electrode covers the upper surface, first side wall, and second side wall of the first support layer, and the first side wall and the second side wall face each other.

6. The capacitor structure according to claim 1, further comprising a second support layer located between the first support layer and the substrate, wherein a plurality of capacitor holes penetrate the second support layer, and the second portion of the lower electrode covers the upper and bottom surfaces of the second support layer.

7. The capacitor structure according to claim 6, wherein the second portion of the lower electrode is located within a cavity defined by the first portion, the first support layer, and the second support layer.

8. The capacitor structure according to claim 1, wherein the first portion of the lower electrode connects a plurality of capacitor holes to each other.

9. The capacitor structure according to claim 1, wherein the second portion of the lower electrode connects a plurality of capacitor holes to one another.

10. A conductive plate is electrically connected to the lower electrode and is located below the first portion of the lower electrode, Terminal layer, The capacitor structure according to claim 1, further comprising a plurality of capacitor holes penetrating the termination layer, the second portion of the lower electrode further covering the upper surface of the termination layer, and the termination layer being located between the conductive plate and the second portion of the lower electrode.

11. The capacitor structure according to claim 10, wherein a portion of the second portion of the lower electrode is located within a cavity defined by the first portion, the second support layer, and the termination layer.

12. The capacitor structure according to claim 2, wherein the second portion of the lower electrode further covers the second side wall of the first support layer, and the first side wall and the second side wall face each other.

13. The steps include forming a first support layer on a substrate, The lower electrode of the capacitor is formed, and the lower electrode is A first portion formed on a plurality of capacitor holes penetrating the first support layer, A second portion is electrically connected to the first portion and covers the bottom surface of the first support layer, Steps including, The steps include forming the dielectric layer of the capacitor on the lower electrode, The steps include forming the upper electrode of the capacitor on the dielectric layer, A method for manufacturing a capacitor structure that includes [a specific component].

14. The step of forming the lower electrode of the capacitor is The steps include forming a first electrode layer in a plurality of capacitor holes, The steps include forming a second electrode layer on the first electrode layer and the first support layer, A method for manufacturing a capacitor structure according to claim 13, wherein the first portion of the lower electrode has a first thickness and the second portion has a second thickness smaller than the first thickness.

15. The method for manufacturing a capacitor structure according to claim 13, further comprising the step of forming a second support layer between the first support layer and the substrate, wherein a plurality of the capacitor holes penetrate the second support layer, and the second portion of the lower electrode covers the upper and bottom surfaces of the second support layer.

16. The method for manufacturing a capacitor structure according to claim 15, wherein a portion of the second portion of the lower electrode is located within a cavity defined by the first portion, the first support layer, and the second support layer.

17. The method for manufacturing a capacitor structure according to claim 13, wherein the first portion of the lower electrode connects a plurality of capacitor holes to one another.

18. The method for manufacturing a capacitor structure according to claim 13, wherein the second portion of the lower electrode connects a plurality of capacitor holes to one another.

19. The steps include forming a conductive plate before forming the first support layer, wherein the conductive plate is electrically connected to the lower electrode and is located below the first portion of the lower electrode, The steps include forming a termination layer on the conductive plate, having a plurality of capacitor holes penetrate the termination layer, and the second portion of the lower electrode further covering the upper surface of the termination layer, A method for manufacturing a capacitor structure according to claim 13, further comprising:

20. The method for manufacturing a capacitor structure according to claim 19, wherein a portion of the second portion of the lower electrode is located within a cavity defined by the first portion, the second support layer, and the termination layer.

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