Pixel circuit

Abstract

This improves the falling edge sluggishness in the pulse waveform of the drive current when driving a light-emitting element using PWM. [Solution] The pixel circuit includes a constant current control circuit that controls the current flowing through the light-emitting element, and a pulse width modulation circuit that outputs a control signal for a first thin-film transistor based on an input grayscale data voltage and a ramp signal. The constant current control circuit includes a first thin-film transistor, which controls the current flowing through the light-emitting element, and the pulse width modulation circuit includes a pulse width modulation driving thin-film transistor and a second thin-film transistor positioned between the pulse width modulation driving thin-film transistor and the output node of the control signal, to which a constant voltage is input to the gate.

Description

Technical Field

[0001] This disclosure relates to a pixel circuit.

Background Art

[0002] In a display device using micro LEDs (Light Emitting Diodes), a PWM (Pulse Width Modulation) driving method that modulates the emission time to display intermediate tones is used. Among PWM driving methods, an analog PWM driving method that analogously changes the emission pulse width according to gradation data has been becoming widespread in recent years.

[0003] A pixel circuit for analog PWM driving includes a CCG (Constant Current generation) unit, a PWM unit, and a switch. The CCG unit generates a constant current, the PWM unit compares a gradation data voltage representing gradation data with a ramp signal and converts it into a pulse signal, and the switch cuts off the current generated by the CCG unit when this pulse signal changes according to the width of the pulse signal from the PWM unit.

[0004] In analog PWM driving, the driving current is ideally required to be a rectangular pulse, but in a real circuit, the fall of the current is sluggish, and due to the finite fall transition time, particularly in the low gradation display area, the image quality is poor, which is a problem.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0006] In PWM driving of light-emitting elements, there is a need for a technology that can improve the falling edge sluggishness in the pulse waveform of the drive current. [Means for solving the problem]

[0007] One aspect of the present disclosure is a pixel circuit for controlling an element-emitting element, comprising a first thin-film transistor, a constant current control circuit for controlling the current flowing through the element-emitting element, and a pulse width modulation circuit for outputting a control signal for the first thin-film transistor based on an input grayscale data voltage and a ramp signal. The first thin-film transistor controls the current flowing through the element-emitting element. The pulse width modulation circuit comprises a pulse width modulation drive thin-film transistor and a second thin-film transistor positioned between the pulse width modulation drive thin-film transistor and the output node of the control signal, to which a constant voltage is input to the gate. [Effects of the Invention]

[0008] According to one aspect of this disclosure, the falling edge sluggishness in the pulse waveform of the drive current can be improved when driving a light-emitting element with PWM. [Brief explanation of the drawing]

[0009] [Figure 1] A schematic diagram shows the configuration of a pixel circuit according to one embodiment of this disclosure. [Figure 2] This shows the time variation of the input signal voltages VRAMP and VDATA of the PWM circuit, the control signal voltage VOUT, and the drive current ILED of the micro LED. [Figure 3A] Figure 2 shows the state of the pixel circuit at time T1. [Figure 3B] Figure 2 shows the state of the pixel circuit at time T2. [Figure 3C]Shows the state of the pixel circuit at time T3 shown in FIG. 2. [Figure 3D] Shows the state of the pixel circuit at time T4 shown in FIG. 2. [Figure 3E] Shows the state of the pixel circuit at time T5 shown in FIG. 2. [Figure 4] Schematically shows the waveform of the lamp signal VRAMP and the LED current ILED with different gradation data voltages. [Figure 5] Shows the pixel circuit of the related art excluding the additional thin film transistor from the pixel circuit shown in FIG. 1. [Figure 6] Shows the characteristics of the pixel circuit of the related art. [Figure 7] Shows a detailed configuration example of the pixel circuit of the embodiment. [Figure 8A] It is a sequence diagram showing the time change of the signal of the pixel circuit within one frame. [Figure 8B] Shows the time change of the signal group in the period indicated by the broken line circle in one graph of FIG. 8A and the signal group in the period indicated by the broken line circle in another graph. [Figure 9] Shows a simplified circuit configuration of the pixel circuit shown in FIG. 7. [Figure 10A] It is a diagram for explaining the function of the additional thin film transistor. [Figure 10B] Shows the simulation results of the Id-Vd characteristics in the pixel circuit without the additional thin film transistor and the pixel circuit with the additional thin film transistor. [Figure 11] It is a diagram for explaining the operation and effect of the pixel circuit of an embodiment of the present disclosure. [Figure 12] Shows the voltage simulation waveforms of the gate, source, and drain of the additional thin film transistor of the embodiment. [Figure 13A] In Embodiment 2, shows the simulation results of the relationship between the constant voltage VREF and the LED current ILED when a power supply voltage VH2 of 9V is applied to the PWM circuit in the pixel circuit. [Figure 13B]The simulation results of the relationship between the constant voltage VREF and the LED current ILED when a power supply voltage VH2 of 5V is applied to the PWM circuit in the pixel circuit are shown. [Figure 13C] The simulation results of the relationship between the constant voltage VREF and the LED current ILED when a power supply voltage VH2 of 1V is applied to the PWM circuit in the pixel circuit are shown. [Figure 14] A configuration example of the pixel circuit when the positive power supply voltage VH2 of the PWM circuit is 9V is shown. [Figure 15] A configuration example of the pixel circuit when the positive power supply voltage VH2 of the PWM circuit is 1V is shown. [Figure 16] In Embodiment 3, the simulation results of the relationship between the capacitance C of the capacitor and the fall time are shown. [Figure 17] The simulation results of the LED current ILED at different capacitances C in the pixel circuit of this embodiment including an additional thin film transistor are shown. [Figure 18] In Embodiment 4, an example in which a P-type thin film transistor is replaced with an N-type thin film transistor in the simplified pixel circuit shown in FIG. 9 is shown. [Figure 19] In Embodiment 5, the simulation results of the relationship between the channel length of the PWM driving thin film transistor and the fall time of the LED current are shown. [Figure 20] The configuration of the PWM driving thin film transistor having a double gate structure in the circuit diagram is shown. [Figure 21] It is a plan view showing a configuration example of the micro LED display device. [Figure 22] The configuration of the pixel circuit according to an embodiment of the present disclosure is schematically shown. [Figure 23] In the pixel circuit shown in FIG. 22, the time changes of the LED current, the drain voltage of the PWM driving thin film transistor, and the gate voltage of the constant current driving thin film transistor are shown. [Figure 24] The configuration of the pixel circuit according to an embodiment of the present disclosure is schematically shown. [Figure 25] The configuration of the pixel circuit according to an embodiment of the present disclosure is schematically shown. [Figure 26] Figure 25 shows the time evolution of the LED current, the drain voltage of the PWM-driven thin-film transistor, and the gate voltage of the constant-current-driven thin-film transistor M in the pixel circuit shown. [Figure 27] Figure 25 shows the simulation results of the relationship between the fall time of the LED current and the constant voltage DVIH in the pixel circuit shown. [Figure 28A] The simulation results for the pixel circuit shown in Figure 22 are presented. [Figure 28B] The simulation results for the pixel circuit shown in Figure 25 are presented. [Figure 29A] The simulation results for the pixel circuit shown in Figure 22 are presented. [Figure 29B] The simulation results for the pixel circuit shown in Figure 25 are presented. [Figure 30] A schematic diagram shows the configuration of a pixel circuit according to one embodiment of this disclosure. [Modes for carrying out the invention]

[0010] One aspect of this disclosure describes the control of light emission of a micro-LED (Light Emitting Diode). The pixel circuit that controls the light emission of the micro-LED emits light for a duration corresponding to the grayscale data within one frame period, and then stops the light emission of the micro-LED. A longer emission period indicates higher brightness. One frame period is the display period for one frame in video data (including moving images and still images) input from outside the display device.

[0011] One embodiment of this disclosure controls the light emission period (brightness) of a microLED by PWM (Pulse Width Modulation) according to grayscale data. The PWM-controlled method for driving a microLED (PWM driving) involves supplying a pulse drive current (also called light emission current or LED current) having a pulse width according to grayscale data to the microLED, thereby causing the microLED to emit light.

[0012] The pulse width is the period between the midpoint of the rising and falling edges of the pulse drive current; a longer pulse width means a longer emission period, i.e., higher brightness. In the low-gradation range, the drive current may consist of a steep rising waveform and a gentler falling waveform without reaching its maximum value at higher gradations.

[0013] In analog PWM driving, the waveform of the drive current is ideally required to be rectangular. However, in real circuits, there is a slowdown in the falling edge of the current, and a finite falling transition period (transition region) exists during which the drive current value gradually decreases. During this falling transition period, the drive current gradually decreases.

[0014] The emission wavelength of a micro-LED shifts to shorter wavelengths as the drive current density increases, and then shifts to longer wavelengths as the drive current density increases further. Furthermore, the external quantum efficiency (EQE) of a micro-LED decreases significantly at low drive current densities. This negative impact on micro-LED emission is particularly pronounced when the drive current supply period consists solely of the falling transition period at low grayscale levels. Therefore, the length of this falling transition period is one of the important challenges in PWM driving of micro-LEDs.

[0015] Embodiments of this disclosure include an additional thin-film transistor between the output node of the PWM circuit and the driving thin-film transistor. A constant voltage is applied to the gate of the additional thin-film transistor for one frame period. The additional thin-film transistor can shorten the fall time of the driving current of the micro-LED.

[0016] In a circuit, two circuit elements may be connected directly without any intervening circuit elements (excluding wiring), or they may be connected via other circuit elements. To clarify whether two circuit elements are directly connected or connected via other circuit elements, they are sometimes referred to as circuit-connected or electrically connected. To clarify a connection that does not involve other circuit elements, it is sometimes referred to as directly connected or physically connected.

[0017] For example, as shown in Figure 7, PWM_EM is connected to the gate of M15. When PWM_EM is low, the gate-source voltage of M15 is sufficiently large, and M15 turns on completely. Also, the current flowing from the power supply line of the positive power supply voltage VH2 of the PWM circuit 12 to VOUT is a tiny current, at most 20nA, and the absolute value of the voltage drop (Vds) across M15 at this time is about 0.5mV, which is negligibly small compared to the absolute value of the voltage from VH2 to VOUT of the PWM circuit 12, which is 13V. In the following, unless otherwise specified, connections within the circuit refer to electrical or circuit connections. <Embodiment 1>

[0018] Figure 1 schematically shows the configuration of a pixel circuit according to one embodiment of the present disclosure. Note that the pixel circuit of the present disclosure may include other components in addition to those shown in Figure 1, and some components may be omitted. Circuit elements directly connected in Figure 1 may be electrically or electrically connected.

[0019] The display area of ​​the display device includes micro(μ)LEDs 11 arranged in a predetermined manner, for example, in a matrix. The microLEDs 11 are light-emitting elements or pixels. The features of this disclosure may be applied to light-emitting elements of a different type than microLEDs. The display device includes a pixel circuit 10 that controls each of the microLEDs 11. The pixel circuit 10 includes a constant current circuit 14, a PWM circuit 12, and a current control switch 16 (example of a first thin-film transistor). The constant current control circuit 13 includes the constant current circuit 14 and the current control switch 16.

[0020] All micro-LEDs 11 may share the same color, but the display area can contain micro-LEDs 11 of different colors, such as red, blue, and green. Here, one micro-LED 11 constitutes one pixel.

[0021] The micro-LED 11 includes an anode and a cathode. A constant power supply voltage PVEE is applied to the cathode of the micro-LED 11. The internal configuration of the constant current circuit 14 is arbitrary. The constant current circuit 14 generates a constant current. A current control switch 16 is located between the micro-LED 11 and the constant current circuit 14. The current control switch 16 is a thin-film transistor (also simply called a transistor), and in the configuration example in Figure 1, it is a P-type thin-film transistor. The active layer of the P-type thin-film transistor can be formed using, for example, low-temperature polysilicon.

[0022] In the configuration example shown in Figure 1, the source of the current control switch 16 is connected to the constant current circuit 14, and the drain is connected to the anode of the micro LED 11. The current control switch 16 is positioned on the path of the current flowing from the constant current circuit 14 through the micro LED 11 to the power supply line that provides the power supply voltage PVEE, and switches that path ON / OFF.

[0023] The current control switch 16 may be placed between the micro LED 11 and the power line supplying the power supply voltage PVEE. The conductivity type of the current control switch 16 may be N-type. The active layer of the N-type thin-film transistor can be formed using, for example, an oxide semiconductor or low-temperature polysilicon.

[0024] The PWM circuit 12 includes a PWM driving thin-film transistor 121, an additional thin-film transistor 122 (an example of a second thin-film transistor), capacitors 123 and 124, a switch thin-film transistor 122, and switch thin-film transistors 125 and 126. The PWM driving thin-film transistor 121 constitutes a comparator.

[0025] One of the source / drain terminals of the switch thin-film transistor 126 and one end of the capacitor 123 are connected to the gate of the PWM-driven thin-film transistor 121. Note that the source and drain of the thin-film transistor switch depending on the direction of the current, so either one can be referred to as the source / drain.

[0026] One source / drain of switch thin-film transistor 125 and one end of capacitor 124 are connected to the gate of current-controlled switch 16. A control signal S2 is input to the gate of switch thin-film transistor 126, and a control signal SET is input to the gate of switch thin-film transistor 125. Switch thin-film transistors 126 and 125 are controlled by control signals S2 and SET, as described with reference to Figure 3A-3E.

[0027] The gate of the PWM-driven thin-film transistor 121 corresponds to the inverting input of the comparator, and the input signal voltage VIN is applied to it. A constant voltage VH2 (high voltage) is applied to the source of the thin-film transistor 121.

[0028] The drain of the PWM-driven thin-film transistor 121 is connected to the source of the additional thin-film transistor 122. The drain of the additional thin-film transistor 122 is connected to the gate of the current control switch 16. The PWM-driven thin-film transistor 121 outputs a control signal voltage VOUT, which controls the ON / OFF state of the current control switch 16, via the additional thin-film transistor 122.

[0029] Figure 1 shows that all thin-film transistors constituting the pixel circuit 10 are P-type thin-film transistors, but some or all of the thin-film transistors may be N-type thin-film transistors. In this way, manufacturing costs can be reduced by making all thin-film transistors unipolar in the backplane. Furthermore, the pixel circuit 10 may include other components such as thin-film transistors and capacitors in addition to the components shown in Figure 1, and some components may be omitted. The same applies to the control signals of the pixel circuit 10; other types of control signals may be added or some signals may be omitted.

[0030] The PWM-driven thin-film transistor 121 compares the input signal voltage VIN to its gate with the constant voltage VH2 to its source, and outputs an output signal voltage VOUT representing the comparison result via an additional thin-film transistor 122. A constant voltage VREF is applied to the gate of the additional thin-film transistor 122. The output signal voltage VOUT is applied to the gate of the current control switch 16 and is a control signal voltage that controls its ON / OFF state.

[0031] Switch thin-film transistor 126 switches the path between the transmission line of the grayscale data voltage VDATA and the gate of PWM-driven thin-film transistor 121 ON / OFF. A ramp signal VRAMP is input to the other end of capacitor 123. The ramp signal VRAMP is a voltage that increases or decreases linearly over time, and the grayscale data voltage VDATA is a voltage value corresponding to the grayscale of the pixels in the video frame. Below, we will mainly describe an example of a ramp signal that decreases in voltage, but it is also possible to use an increasing ramp signal. If the polarity of the transistor is P-type, the state of the transistor changes from off to on as the ramp signal decreases.

[0032] Capacitor 124 is configured between the gate of the current control switch 16 and the wiring (power line) that provides a constant voltage VSET. The constant voltage VSET is lower than the constant voltage VH2. One end of capacitor 124 is connected to the node between the gate of the current control switch 16 and the source / drain (comparator output) of the additional thin-film transistor 122, and the other end is connected to the wiring that provides the constant voltage VSET.

[0033] Switch thin-film transistor 125 switches the path between the gate of the current control switch 16 and the wiring that provides a constant voltage VSET on and off. One end of switch thin-film transistor 125 is connected to the node between the gate of the current control switch 16 and the output of the PWM circuit 12, and the other end is connected to the wiring that provides a constant voltage VSET. VSET (low) is written to VOUT, turning on the current control switch 16.

[0034] The PWM circuit 12 controls and outputs the width of the control signal voltage VOUT from the grayscale data voltage VDATA. The signal voltage input to the PWM circuit 12 includes the grayscale data voltage VDATA and the change in the ramp signal ΔVRAMP. The PWM circuit 12 compares the grayscale data voltage VDATA, which represents the grayscale data, with the change in the ramp signal ΔVRAMP, and when the PWM-driven thin-film transistor 121 is turned on, the control signal voltage VOUT changes.

[0035] The PWM circuit 12 shown in Figure 1 uses a PWM-driven thin-film transistor 121 to compare the sum of the grayscale data voltage VDATA and the change in the ramp signal ΔVRAMP with a constant voltage VH2, and outputs a control signal voltage VOUT via an additional thin-film transistor 122 according to the magnitude relationship between them. This corresponds to the comparison between the grayscale data voltage VDATA and the change in the ramp signal ΔVRAMP. The PWM circuit 12 outputs a high-level voltage VH2 using the PWM-driven thin-film transistor 121 and the additional thin-film transistor 122, and stops the supply of current to the micro LED 11 by turning off the current control switch 16.

[0036] Figure 2 shows the time variation of the input signal voltages VRAMP and VDATA and the control signal voltage VOUT of the PWM circuit 12, as well as the drive current ILED of the micro LED 11. The input signal voltage VIN to the PWM drive thin-film transistor 121 is the sum of the grayscale data voltage VDATA and the change in the ramp signal ΔVRAMP.

[0037] Figures 3A-3E show the state of the pixel circuit 10 at times T1-T5, as shown in Figure 2. The circuit operation of the pixel circuit 10 will be explained below with reference to Figures 2 and 3A-3E.

[0038] Referring to Figure 3A, at time T1, the micro LED 11 is not emitting light. Time T1 is included in the non-emitting period. Switch thin-film transistors 126 and 125 are OFF. Referring to Figure 2, at time T1, the control signal voltage VOUT of the PWM circuit 12 is at the H level VH2. The current control switch 16 is OFF, and the drive current ILED for the micro LED 11 is interrupted.

[0039] Referring to Figure 3B, at time T2, switch thin-film transistors 126 and 125 are turned ON. Referring to Figure 2, at time T2, the grayscale data voltage VDATA corresponding to the grayscale level of the video frame data is written to the PWM circuit 12. Time T2 to T3 is the period for writing the grayscale data voltage. Meanwhile, since switch thin-film transistor 125 is ON, the control signal voltage VOUT of the PWM circuit 12 is a low level VSET. Therefore, the current control switch 16 is ON, the drive current ILED is supplied to the micro LED 11, and the micro LED 11 lights up. Note that the timing at which switch thin-film transistors 125 and 126 turn ON may differ during the period T2 to T3.

[0040] Referring to Figure 3C, at time T3, switch thin-film transistors 126 and 125 are turned OFF. Referring to Figure 2, at time T3, the input of the ramp signal VRAMP is started. The sum of the grayscale data voltage VDATA and the change in the ramp signal ΔVRAMP is higher than the voltage VH2. The control signal voltage VOUT of the PWM circuit 12 is maintained at the L level, VSET. The current control switch 16 remains ON, and the micro LED 11 continues to emit light.

[0041] Referring to Figure 3D, at time T4, switch thin-film transistors 126 and 125 remain OFF. Referring to Figure 2, the sum of the grayscale data voltage VDATA and the change in the ramp signal ΔVRAMP is higher than the voltage VH2. The control signal voltage VOUT of the PWM circuit 12 is maintained at the L level VSET. The current control switch 16 remains ON, and the micro LED 11 continues to emit light.

[0042] Referring to Figure 3E, at time T5, switch thin-film transistors 126 and 125 remain OFF. Referring to Figure 2, the sum of the grayscale data voltage VDATA and the change in the ramp signal ΔVRAMP has decreased to voltage VH2. Here, for simplicity, the threshold voltage of the PWM drive thin-film transistor 121 is set to 0V, but when the PWM drive thin-film transistor 121 turns ON, the control signal voltage VOUT of the PWM circuit 12 changes from a low level (VSET) to a high level (VH2). In response to the change in the control signal voltage VOUT, the current control switch 16 is turned OFF, and the light emission of the micro LED 11 stops.

[0043] As described above, the pulse width of the drive current for the micro-LED 11 depends on the grayscale data voltage VDATA. In other words, the illumination period of the micro-LED 11 is controlled by the grayscale data voltage VDATA.

[0044] In Figure 2, the drive current ILED of the micro LED 11 falls sharply at time T5. This waveform is an ideal waveform; in reality, the fall of the drive current ILED may be gentler. Note that the rise of the drive current ILED, unlike the fall, has a steep slope close to ideal. This can be achieved, for example, by placing a switch thin-film transistor (not shown in Figure 1) in the LED current path. The control signal voltage to the gate of this switch thin-film transistor is a signal output from the gate driver, and can be changed sharply from high to low in about sub-microseconds. Therefore, the rise of the drive current ILED can have a steep slope close to ideal.

[0045] In conventional configurations, the drive current ILED gradually decreases from its maximum value over time, eventually reaching zero. In conventional constant-current PWM driving, there is a period during which the drive current ILED is not instantaneously cut off and does not remain constant, thus preventing the realization of ideal constant-current PWM driving. In PWM of the micro LED 11, if the fall time of the drive current ILED is long, variations in luminous efficiency and chromaticity become large, especially in the low-gradation region, which can degrade image quality. This is because the LED current density is low during the fall time.

[0046] Figure 4 schematically shows the waveforms of the ramp signal VRAMP and the LED current ILED for different grayscale data voltages. Waveform 201 shows the drive current waveform for high grayscale levels, waveform 202 shows the drive current waveform for intermediate grayscale levels, and waveform 203 shows the drive current waveform for low grayscale levels. For example, the maximum grayscale level is 255 and the minimum grayscale level is 0.

[0047] Waveforms 201 and 202, representing high-gradation and intermediate-gradation levels, have pulse widths longer than their fall time, and share the same peak value (maximum current value). Waveforms 201 and 202 have periods where the current value is constant (maximum value). In waveforms 201 and 202, the drive current rises, reaches its maximum value, maintains that value, and then falls. Here, the pulse width is the time width (half-power width) at the midpoint of the waveform (half of the maximum value) during the rising and falling phases. The rising phase can be considered virtually vertical.

[0048] The drive current waveform 203 at low grayscale levels has a pulse width shorter than its fall time, and its peak value (maximum current value) is smaller than that of the other drive current waveforms 201 and 202. Furthermore, the drive current waveform 203 begins to decrease immediately from its maximum value and does not have a fixed period of decrease. Thus, when the pulse width is shorter than the fall time of the drive current, the peak value of the drive current decreases. In other words, in the low grayscale range, the current density flowing through the LED is low, and therefore the brightness and chromaticity are prone to variation due to the influence of the current density dependence of the LED characteristics. In short, a long fall time of the LED current waveform has a greater impact on light emission in the low grayscale range.

[0049] The fall time of the drive current ILED depends on the response time (rise time) of the control signal voltage VOUT output from the PWM circuit 12. Therefore, it is important to shorten the response time of the control signal voltage VOUT output from the PWM circuit 12.

[0050] In their research on constant-current PWM driving of micro-LEDs, the inventors found that the response of the PWM circuit 12, i.e., the falling edge of the LED current ILED, correlates with the drain current of the driving thin-film transistor 121 of the PWM circuit 12. Specifically, they found that an unwanted drain current Id when the absolute value |Vgs| of the gate-source voltage of the PWM driving thin-film transistor 121 is small is one of the causes of the slow falling edge (long falling time) of the LED current ILED.

[0051] Figure 5 shows the pixel circuit 101 of the related technology, which is obtained by removing the additional thin-film transistor 122 from the pixel circuit 10 shown in Figure 1. In Figure 5, some components shown in Figure 1 are omitted. Figure 6 shows the characteristics of the pixel circuit 101 of the related technology. Figure 6 also shows graphs illustrating the characteristics of the PWM-driven thin-film transistor 121 and the LED current waveform. In each graph, the solid line shows the simulation results of the pixel circuit of the related technology, and the dashed line shows the ideal value.

[0052] Graph 251 shows the time variation of the gate-source voltage Vgs of the PWM-driven thin-film transistor 121. The gate voltage Vg of the PWM-driven thin-film transistor 121 is the same as VIN shown in Figure 2. Graph 252 shows the time variation of the drain current Id of the PWM-driven thin-film transistor 121.

[0053] Graph 253 shows the time variation of the drain voltage Vd of the PWM-driven thin-film transistor 121. The drain voltage Vd matches the control signal voltage VOUT in the pixel circuit of the related technology in which the additional thin-film transistor 122 is omitted. Graph 254 shows the time variation of the LED current ILED. Note that the reference potential of the voltage when the reference is not explicitly stated is the system ground (0V in this case).

[0054] The drain current Id of the PWM-driven thin-film transistor 121 increases with increasing absolute value of the gate-source voltage of the PWM-driven thin-film transistor 121. The charge Q(t) charged to the capacitor 124 by the drain current Id is expressed by the following equation. Q(t)=∫Id(t)dt=C×(Vd(t)-Vd(0)) C is a capacitance of 124, and Vd(0) is a constant voltage VSET.

[0055] Differentiating both sides of the above equation with respect to t yields the following relationship. Id(t) = C × dVd(t) / dt

[0056] Once the capacitor 124 is fully charged, the drain-source voltage Vds of the PWM-driven thin-film transistor 121 becomes 0, the drain current Id rapidly approaches zero, and the current stops. Since the charge Q of capacitor 124 is CV, the waveform of the drain current Id is important for the rising edge of the control signal voltage VOUT of the PWM circuit 12, i.e., the falling edge of the LED current.

[0057] As shown in Graph 252 of Figure 6, in the pixel circuit 101 of the related technology, at the beginning of the ramp signal's decline, the gate voltage Vg is higher than the source voltage VH2 of the PWM-driven thin-film transistor 121. That is, the absolute value of the gate-source voltage |Vgs| is small and the absolute value of the drain voltage |Vd| is large, resulting in an unwanted large drain current Id due to the Kink effect. Due to this unwanted drain current Id, the capacitor 124 is gradually charged, and as shown in Graph 253, the drain voltage Vd, i.e., the control signal voltage VOUT, slowly rises from around time 13ms. As a result, as shown in Graph 254, the LED current ILED cannot maintain a large current (peak value) and begins to slowly fall.

[0058] A pixel circuit in one embodiment of the present disclosure includes an additional thin-film transistor 122 between the drain of the driving thin-film transistor 121 of the PWM circuit 12 and a capacitor 124, as shown in Figure 1. A constant voltage VREF is applied to the gate of the additional thin-film transistor 122. As will be described later, the additional thin-film transistor 122 functions to keep the drain current Id of the PWM driving thin-film transistor 121 constant, thereby reducing unwanted current when the absolute value |Vgs| of the gate-source voltage of the PWM driving thin-film transistor 121 is small.

[0059] Here, a detailed configuration example of a pixel circuit 10 according to one embodiment of the present disclosure will be described. Figure 7 shows a detailed configuration example of the pixel circuit 10. Other circuit elements may be added between the directly connected circuit elements in Figure 7, and some circuit elements may be omitted.

[0060] In the example configuration shown in Figure 7, the PWM circuit 12 consists of eight thin-film transistors and two capacitive elements. The constant current circuit 14 consists of five thin-film transistors and one capacitive element. The number of transistors and capacitances in each of the two circuits 12 and 14 are arbitrary and may be common or different between the two circuits 12 and 14. Furthermore, these may also include other types of circuit elements, such as resistors.

[0061] In Figure 7, the PWM circuit 12 includes thin-film transistors 121, 122, and 125, as described with reference to Figure 1, as well as transistors M11-M15. Thin-film transistor 126 is omitted. The PWM circuit 12 also includes capacitors 123 and 124, as described with reference to Figure 1. Transistors M11-M15 are P-type switch thin-film transistors.

[0062] In the following, source / drain refers to either the source or the drain. For some thin-film transistors, the source and drain are reversed depending on the direction of the current flowing. For some thin-film transistors, the source and drain are constant, but for ease of explanation, the source / drain notation may be used.

[0063] The source of thin-film transistor M11 is supplied with the power supply voltage VH2, and its drain is connected to the source of the driving thin-film transistor 121 and to either the source or drain of transistor M12. The gate of thin-film transistor M11 is input with the control signal PWM_EM.

[0064] The scan signal PWM_S2 is input to the gate of thin-film transistor M12. One of the source / drain is connected to the drain of thin-film transistor M11 and the source of thin-film transistor 121, while the other is input to the grayscale data voltage PWM_DATA. The grayscale data voltage PWM_DATA corresponds to the grayscale data voltage VDATA in Figure 1.

[0065] The gate of the PWM-driven thin-film transistor 121 is connected to one end of capacitor 123 and to the source / drain of thin-film transistors M13 and M14. The other end of capacitor 123 is input to a ramp signal (ramp voltage) VRAMP. The source of the PWM-driven thin-film transistor 121 is connected to the drain of transistor M11 and the source / drain of transistor M12, and the drain of the PWM-driven thin-film transistor 121 is connected to the source / drain of thin-film transistor M13 and the source of thin-film transistor M15.

[0066] The gate of thin-film transistor M13 is input with the scanning signal PWM_S2. One of the source / drain of thin-film transistor M13 is connected to the drain of thin-film transistor 121 and the source of thin-film transistor M15, while the other is connected to the gate of thin-film transistor 121 and the source / drain of thin-film transistor M14.

[0067] The gate of thin-film transistor M14 is input with scan signal PWM_S1. Scan signal PWM_S1 is a scan signal that is one horizontal period faster than scan signal PWM_S2. The source of thin-film transistor M14 is connected to the gate of thin-film transistor 121 and the source / drain of thin-film transistor M13, and the drain is input with an initialization voltage VINI3, which has a constant voltage.

[0068] The gate of thin-film transistor M15 is input with the control signal PWM_EM. The source of thin-film transistor M15 is connected to the drain of thin-film transistor 121 and the source / drain of thin-film transistor M13, and the drain of thin-film transistor M15 is connected to the source of additional thin-film transistor 122.

[0069] The gate of the additional thin-film transistor 122 is input to a constant voltage VREF. Its source is connected to the drain of thin-film transistor M15, and the drain of the additional thin-film transistor 122 is connected to the source of thin-film transistor 125. The control signal voltage VOUT is output from node N1 between the drain of thin-film transistor 122 and the source of thin-film transistor 125.

[0070] The gate of thin-film transistor 125 is input with the control signal PWM_SE. The source of thin-film transistor 125 is connected to the gate of thin-film transistor 16, and the drain of thin-film transistor 125 is input with the constant voltage VSET. Capacitor 124 is connected to the source and drain of thin-film transistor 125.

[0071] The grayscale data voltage PWM_DATA is written to capacitor 123 via thin-film transistors M12, 121, and M13. Subsequently, the change in the ramp signal VRAMP is superimposed on capacitor 123.

[0072] The constant current control circuit 13 includes a constant current circuit 14, a current control switch 16, thin-film transistors M31 and M32. The constant current circuit 14 includes thin-film transistors M21-M25 and capacitor C21. Thin-film transistors M21-M25 are P-type thin-film transistors, and thin-film transistor M23 is a driving transistor that determines the magnitude of the constant current. The constant current circuit 14 controls the constant current by pulse amplitude modulation (PAM) (PAM control).

[0073] The gate of thin-film transistor M21 is input with the control signal PAM_EM. The source of thin-film transistor M21 is input with the constant power supply voltage PVDD, and its drain is connected to the source / drain of thin-film transistor M22 and the source of thin-film transistor M23.

[0074] The gate of thin-film transistor M22 is input with the scan signal PAM_S2. One of the source / drain terminals of thin-film transistor M22 is input with the data voltage PAM_DATA which controls the constant current, and the other is connected to the drain of thin-film transistor M21 and the source of thin-film transistor M23.

[0075] The gate of thin-film transistor M23 is connected to the source / drain of capacitor C21 and thin-film transistors M24 and M25. The source of thin-film transistor M23 is connected to the drain of thin-film transistor M21 and the source / drain of M22, and the drain of thin-film transistor M23 is connected to the output node N2 of the constant current circuit 14.

[0076] The scan signal PAM_S2 is input to the gate of thin-film transistor M24. One source / drain of thin-film transistor M24 is connected to the output node N2 of the constant current circuit 14, and the other is connected to the gate of thin-film transistor M23, capacitor C21, and the source / drain of transistor M25.

[0077] The scan signal PAM_S1 is input to the gate of thin-film transistor M25. Scan signal PAM_S1 is a scan signal that is one horizontal period earlier than scan signal PAM_S2. One source / drain of thin-film transistor M25 is input to the constant voltage VINI2, and the other is connected to the gate of thin-film transistor M23, the capacitor C21, and the source / drain of thin-film transistor M24.

[0078] The current value data PAM_DATA is written to capacitor C21 via thin-film transistors M22, M23, and M24. Thin-film transistor M23 outputs a current to output node N2 corresponding to the voltage of capacitor C21.

[0079] The current control switch 16 is a P-type thin-film transistor, with its source connected to the output node N2 of the constant current circuit 14 and its drain connected to the source of the thin-film transistor M31. The gate of the current control switch 16 is input to the control signal voltage VOUT from the PWM circuit 12.

[0080] A P-type thin-film transistor M31 is connected between the anode of the micro-LED 11 and the current control switch 16. Transistor M31 is a switch, and the control signal PAM_EM is input to its gate. The source of transistor M31 is connected to the drain of the current control switch 16, and this drain is connected to the anode of the micro-LED 11.

[0081] Thin-film transistor M32 is a switch, and the scan signal PAM_S2 is input to its gate. Thin-film transistor M32 is a P-type thin-film transistor. The source of thin-film transistor M32 is connected to the anode of micro LED11, and the constant power supply voltage VINI1 is supplied to its drain.

[0082] Figure 8A is a sequence diagram showing the time variation of the signal of the pixel circuit 10 within one frame. In graphs 51-54, the horizontal axis represents time and the vertical axis represents voltage. In graph 55, the horizontal axis represents time and the vertical axis represents current. Graph 51 shows the time variation of the control signal group (CC) of the constant current circuit 14. Graph 52 shows the time variation of the control signal group (PWM) of the PWM circuit 12. In Figure 8A, graphs 51 and 52 schematically show the time variation of multiple control signals, respectively. Details of the signal groups during the period indicated by the dashed circle 510 in graph 51 and the period indicated by the dashed circle 520 in graph 52 are shown in Figure 8B.

[0083] Graph 53 shows the time variation of the lamp signal VRAMP input to the PWM circuit 12. Graph 54 shows the time variation of the control signal VOUT output from the PWM circuit 12. Graph 55 shows the time variation of the drive current ILED of the micro LED 11.

[0084] Figure 8B shows the time evolution of the signal group during the period indicated by the dashed circle 510 in Graph 51 and the signal group during the period indicated by the dashed circle 520 in Graph 52. In Graphs 510 and 520, the horizontal axis represents time, and the vertical axis represents the voltage of the signal.

[0085] Graph 510 shows the time variation of the control signal group (CC) of the constant current circuit 14. In graph 510, line 511 shows the time variation of signal PAM_S1, line 512 shows the time variation of signal PAM_S2, and line 513 shows the time variation of signal PAM_EM.

[0086] Signal PAM_S1 (line 511) is a pulse signal that transitions from a high level to a low level at time t1 and changes from a low level to a high level at time t2. Signal PAM_S2 (line 512) is a pulse signal that transitions from a high level to a low level at time t2 and returns from a low level to a high level at time t3. Signal PAM_EM (line 513) is a pulse signal that transitions from a high level to a low level at time t9 and changes from a low level to a high level at a predetermined time during one frame period (not shown). In one example, the pulse width of signals PAM_S1 and PAM_S2 is one horizontal period.

[0087] Graph 520 shows the time variation of the control signal group (PWM) of the PWM circuit 12. In graph 520, line 521 shows the time variation of signal PWM_S1, line 522 shows the time variation of signal PWM_S2, line 523 shows the time variation of signal PWM_SE, and line 524 shows the time variation of signal PWM_EM.

[0088] Signal PWM_S1 (line 521) is a pulse signal that transitions from a high level to a low level at time t4 and changes from a low level to a high level at time t5. Signal PWM_S2 (line 522) is a pulse signal that transitions from a high level to a low level at time t5 and returns from a low level to a high level at time t6. Signal PWM_SE (line 523) is a pulse signal that transitions from a high level to a low level at time t6 and returns from a low level to a high level at time t7. Signal PWM_EM (line 524) is a pulse signal that transitions from a high level to a low level at time t8 and changes from a low level to a high level at a predetermined time during one frame period (not shown). In this example, the pulse width of signals PWM_S1, PWM_S2, and PWM_SE is 1 horizontal period.

[0089] Figure 9 shows a simplified circuit configuration of the pixel circuit 10 shown in Figure 7. Figure 9 shows only the important thin-film transistors that are in a conducting state during the period when a large current flows through the micro LED 11 and it is emitting light. During the light emission period, thin-film transistors M21, M23, 16, M31, M11, 121, M15, and 122 are in a conducting (non-blocking) state. Among these, thin-film transistors M21, M31, M11, and M15 can be considered to be in a short-circuit state. Switch thin-film transistors in the blocked state and the power supply voltages connected to them are also omitted.

[0090] In Figure 9, the light emission control switch thin-film transistor M15 between the PWM circuit 12's driving thin-film transistor 121 and the additional thin-film transistor 122 is omitted. The light emission control switch thin-film transistor M15 may or may not be present. In either configuration, the drain of the PWM driving thin-film transistor 121 and the source of the additional thin-film transistor 122 are electrically or circuit-connected.

[0091] Figure 9 further shows the gate voltage Vg of the PWM-driven thin-film transistor 121, the drain current Id and drain voltage Vd of the additional thin-film transistor 122, the intermediate node N22 of thin-film transistors 121 and 122, and the LED current ILED.

[0092] Figure 10A is a diagram illustrating the function of the additional thin-film transistor 122. Section 531 shows an example of ON-state characteristic values ​​of the driving thin-film transistor 121 of the PWM circuit 12 in a pixel circuit of related technology that does not include the additional thin-film transistor 122. Section 532 shows an example of ON-state characteristic values ​​in a series circuit of the PWM driving thin-film transistor 121 and the additional thin-film transistor 122.

[0093] In Section 531, which describes related technologies, the gate voltage Vg of the PWM-driven thin-film transistor 121 is assumed to be -1.4V, and the source voltage Vs is assumed to be a constant 0V. The maximum absolute value of the drain-source voltage Vds |Vds| is assumed to be 11.5V. The drain current Id of the PWM-driven thin-film transistor 121 increases with increasing |Vds| due to the Kink effect. This unwanted drain current Id gradually increases the control signal voltage VOUT, and as a result, increases the rise time of the control signal voltage VOUT.

[0094] In Section 532, which illustrates one embodiment of the present disclosure, the gate voltage Vg of the PWM-driven thin-film transistor 121 is assumed to be -1.4V, the source voltage Vs is constant at 0V, and the gate voltage Vg of the additional thin-film transistor 122 is assumed to be -4V. The absolute value |Vds| of the drain-source voltage Vds of the PWM-driven thin-film transistor 121 is maintained at approximately 2.7V. This point will be explained below.

[0095] In this embodiment, the drain voltage is divided by two thin-film transistors 121 and 122. Due to the charging of capacitor 124, even if the drain voltage Vd of the series circuit (additional thin-film transistor 122) rises, the intermediate potential of the two thin-film transistors 121 and 122 is automatically adjusted so that the drain current Id remains constant.

[0096] Because the |Vds| of the PWM-driven thin-film transistor 121 can be kept small (~2.7V), the drain current Id does not change due to the load connected to the drain of the PWM-driven thin-film transistor 121, and unnecessary Id can be reduced. In other words, the PWM-driven thin-film transistor 121 functions as a current source. A constant current flows through the additional thin-film transistor 122, and since the gate potential of the additional thin-film transistor 122 is fixed, the source potential of the additional thin-film transistor 122 changes automatically.

[0097] The drain voltage Vd of the additional thin-film transistor 122 increases over time. Even if |Vds| of the additional thin-film transistor 122 decreases, Vs of the additional thin-film transistor 122 increases slightly. In other words, the drain current Id is kept constant as |Vgs| of the additional thin-film transistor 122 increases.

[0098] In other words, instead of decreasing |Vds| of the additional thin-film transistor 122 so that the drain current Id does not change, |Vgs| of the additional thin-film transistor 122 increases. Even if the threshold voltage Vth of the additional thin-film transistor 122 shifts, the Vgs of the additional thin-film transistor 122 is automatically adjusted so that the drain current of the additional thin-film transistor 122 matches the drain current of the PWM-driven thin-film transistor 121. By keeping the drain current Id constant, unnecessary drain current Id when |Vgs| of the PWM-driven thin-film transistor 121 is small is suppressed, and the rise of the control signal voltage VOUT of the PWM circuit 12 due to the large current at a large |Vgs| can be made steeper.

[0099] Figure 10B shows the simulation results of the Id-Vd characteristics for a pixel circuit without the additional thin-film transistor 122 and for a pixel circuit with the additional thin-film transistor 122. In the graph in Figure 10B, the horizontal axis represents the drain voltage Vd and the vertical axis represents the drain current Id. Line 641 shows the simulation results for the pixel circuit with the additional thin-film transistor 122. Line 642 shows the simulation results for the pixel circuit without the additional thin-film transistor 122.

[0100] As shown by line 642 in Figure 10B, in the pixel circuit without the additional thin-film transistor 122, an increase in drain current Id due to the Kink effect is observed in the range of large absolute values ​​of the drain voltage |Vd|. On the other hand, as shown by line 641, in the pixel circuit including the additional thin-film transistor 122, the drain current Id is kept constant. In other words, at |Vds|=11.5V, the unnecessary Id is small in line 641.

[0101] Figure 11 is a diagram illustrating the effects of a pixel circuit 10 in one embodiment of the present disclosure. Graphs 551-554 show simulation results for a pixel circuit of related technology without the additional thin-film transistor 122 and for a pixel circuit of one embodiment of the present disclosure including the additional thin-film transistor 122.

[0102] Graph 551 shows the time variation of the gate voltage Vg of the PWM-driven thin-film transistor 121 in the related technology and in this embodiment. Graph 552 shows the time variation of the drain current Id of the PWM-driven thin-film transistor 121 in the related technology and the series circuit (additional thin-film transistor 122) in this embodiment. In graph 552, line 561 shows the drain current Id of the related technology, and line 562 shows the drain current Id of this embodiment. The areas under the two waveforms are equal. This is because it is the time integral of Id, and the charge held by capacitance 124 is determined only by capacitance, VH2, and VSET. For understanding the waveforms, two indicator lines are shown showing two points on line 562. The waveform of line 561 in the related technology is identical to the solid line waveform in graph 252 in Figure 6.

[0103] Graph 553 shows the time variation of the drain voltage Vd of the PWM-driven thin-film transistor 121 of the related technology and the drain voltage Vd of the series circuit (additional thin-film transistor 122) of this embodiment. Line 565 shows the drain voltage Vd of the related technology, and line 566 shows the drain voltage Vd of this embodiment. Graph 554 shows the time variation of the LED current ILED. Line 567 shows the LED current ILED of the related technology, and line 568 shows the LED current ILED of this embodiment.

[0104] In both the related technology and this embodiment, as the gate voltage Vg of the PWM-driven thin-film transistor 121 decreases, that is, as the absolute value of its gate-source voltage |Vgs| increases over time, the drain current Id increases. In the related technology shown in Figure 6, due to the unnecessary drain current Id when |Vgs| of the PWM-driven thin-film transistor 121 is small, the capacitor 124 is gradually charged, and the LED current ILED begins to fall slowly.

[0105] In the series circuit of this embodiment, the waveform of the drain current Id is skewed to the right and has a higher peak value compared to the current waveform of related technologies. In this embodiment, initially, a small drain current Id is maintained, and the capacitor 124 is charged in a short time while waiting for |Vgs| to reach a value that allows a large drain current Id to flow. As a result, the falling edge of the LED current is steep.

[0106] According to the simulation results, the pixel circuit 10 of this embodiment, which includes the additional thin-film transistor 122, can reduce the fall time of the LED current by an average of 31% across the entire grayscale range compared to a pixel circuit of related technology that does not include the additional thin-film transistor 122.

[0107] Figure 12 shows the gate, source, and drain voltage simulation waveforms of the additional thin-film transistor 122 in the embodiment. Figure 12 shows the waveforms over a 2-frame period. Graph 581 shows the time variation of the input voltage Vg to the gate of the PWM-driven thin-film transistor 121. Graph 582 shows the input voltage VREF to the gate of the additional thin-film transistor 122.

[0108] Graph 583 shows the time variation of the potential at the intermediate node N22 (source of the additional thin-film transistor 122) of the two thin-film transistors 121 and 122 shown in Figure 9. Graph 584 shows the time variation of the control signal voltage VOUT of the PWM circuit 12. This is the drain voltage of the additional thin-film transistor 122. Graph 585 shows the time variation of the LED current ILED.

[0109] As shown in Graph 582, the input voltage VREF to the gate of the additional thin-film transistor 122 remains constant during each frame period. <Embodiment 2>

[0110] Embodiment 2 describes the control voltage VREF of the additional thin-film transistor 122 described in Embodiment 1. As described in Embodiment 1, an additional thin-film transistor 122 given a constant control voltage VREF to its gate can shorten the fall time of the LED current ILED. Our research has shown that there is a more appropriate range for the gate voltage VREF of the additional TFT in order to shorten the fall time more effectively.

[0111] Specifically, it was found that VREF has the effect of shortening the fall time of the LED current ILED at a voltage at least equal to or greater than the negative power supply voltage (minimum voltage) VGL supplied to the PWM circuit 12. Furthermore, it was found that as the positive power supply voltage VH2 of the PWM circuit 12 decreases, the upper limit of the constant gate voltage VREF also decreases. The gate voltage VREF can more effectively shorten the fall time of the LED current ILED within the following range. VGL <VREF≦VH2-1.5

[0112] Figures 13A, 13B, and 13C show the simulation results of the relationship between the constant voltage VREF and the fall time of the LED current when different power supply voltages VH2 are applied to the PWM circuit 12 in the pixel circuit according to the embodiment of this disclosure. Figure 13A shows the simulation results when the power supply voltage VH2 is 9V. Figure 13B shows the simulation results when the power supply voltage VH2 is 5V. Figure 13C shows the simulation results when the power supply voltage VH2 is 1V.

[0113] Referring to Figure 13A, when the constant voltage VREF exceeds 7.5V, the fall time increases sharply. Referring to Figure 13B, when the constant voltage VREF exceeds 3.5V, the fall time increases sharply. Referring to Figure 13C, when the constant voltage VREF exceeds -0.5V, the fall time increases sharply.

[0114] As shown in the simulation results in Figures 13A, 13B, and 13C, the fall time increases sharply when the gate voltage VREF is greater than 1.5V lower than the positive power supply voltage VH2 of the PWM circuit 12 (VH2-1.5). Similar results were obtained for other values ​​of the positive power supply voltage VH2. Regarding the lower limit, a particularly large reduction in fall time was obtained in the range where the gate voltage VREF is -5V or higher. When the gate voltage VREF was made smaller than VGL, the fall time became similar to that of conventional technology. This is because the additional thin-film transistor 122 turns on completely, and the additional thin-film transistor 122 simply functions as a short circuit.

[0115] An example of a constant voltage value applied to the pixel circuit 10 shown in Figure 7 is described below. An example of a negative power supply voltage VGL is -12V. The output voltage VOUT of the PWM circuit 12, VSET at the start of light emission, may be equal to the negative power supply voltage VGL. An example of a negative power supply voltage PVEE to the cathode of the micro LED 11 is -8V. An example of a positive power supply voltage VH2 for the PWM circuit 12 is 1V. An example of a positive power supply voltage PVDD for the constant current circuit 14 is 0V. Examples of initialization voltages VINI1, VINI2, and VINI3 are each -3V.

[0116] One embodiment of this disclosure shares a power line that supplies the gate voltage to the additional thin-film transistor 122 with another power supply voltage (constant voltage). By sharing an existing power line instead of adding a new one, the circuit layout area (footprint) can be reduced.

[0117] Figure 14 shows an example where the positive power supply voltage VH2 of the PWM circuit 12 is 9V. The gate of the additional thin-film transistor 122 is supplied with the positive power supply voltage PVDD = 4.6V from the constant current circuit 14. The power line of the positive power supply voltage PVDD is connected to the gate of the additional thin-film transistor 122, supplying the positive power supply voltage PVDD and the gate voltage VREF.

[0118] Figure 15 shows an example where the positive power supply voltage VH2 of the PWM circuit 12 is 1V. The gate of the additional thin-film transistor 122 is supplied with the initialization power supply voltage VINI3 = -3V of the PWM circuit 12. The power line of the initialization power supply voltage VINI3 is connected to the gate of the additional thin-film transistor 122, supplying the initialization power supply voltage VINI3 and the gate voltage VREF. <Embodiment 3>

[0119] Capacitor 124 plays a role in maintaining the output voltage VOUT of the PWM circuit 12 at a low level. The negative power supply voltage VSET is written to VOUT, turning on the thin-film transistor 16, allowing the LED current to flow and start emitting light. According to the inventors' research, it has been found that in a pixel circuit including an additional thin-film transistor 122, there is a more appropriate range for the capacitance C of capacitor 124 in order to more effectively shorten the fall time of the LED current. Specifically, the fall time of the LED current can be more effectively shortened when the capacitance C of capacitor 124 satisfies the following conditions. 10fF ≤ C ≤ 300fF

[0120] Figure 16 shows the simulation results of the relationship between the capacitance C of capacitor 124 and the fall time. Line 601 shows the simulation results for the pixel circuit 10 of the embodiment of this disclosure, which includes the additional thin-film transistor 122. Line 602 shows the simulation results for the pixel circuit of the related technology, which does not include the additional thin-film transistor 122. As can be seen by referring to Figure 16, in the related technology, the fall time remains almost constant even when the value of the capacitance C of capacitor 124 is changed.

[0121] On the other hand, in the pixel circuit 10 of this embodiment, as the capacitance C of capacitance 124 decreases, the fall time of the LED current becomes shorter. On the other hand, when the capacitance C is 0 fF, the waveform of the LED current ILED becomes distorted.

[0122] Figure 17 shows the simulation results of the LED current ILED at different capacitances C in the pixel circuit 10 of this embodiment, which includes an additional thin-film transistor 122. The horizontal axis represents time, and the vertical axis represents the amount of LED current ILED. Line 611 shows the LED current ILED at capacitance C = 300 fF. Line 612 shows the LED current ILED at capacitance C = 10 fF. Line 613 shows the LED current ILED at capacitance C = 0 fF.

[0123] As the simulation results in Figure 17 show, the LED current waveform breaks down in the initial range when capacitance C = 0 fF. A certain capacitance is required to maintain the gate potential of the current control switch 16. The simulation results in Figure 17 show that a capacitance of 10 fF C can achieve a normal LED current waveform. When transistor 125 turns on and writes the negative power supply voltage VSET to VOUT, parasitic capacitances such as the gate-source capacitance of transistor 125 have an effect. If the capacitance of capacitor 124 is insufficient, VOUT cannot be lowered sufficiently. Therefore, the thin-film transistor 16 does not turn on completely, and the peak value is low when the LED current waveform rises. For this reason, capacitor 124 needs to have a certain capacitance. <Embodiment 4>

[0124] Embodiments 1, 2, and 3 describe pixel circuits using P-type thin-film transistors. Embodiment 4 describes a pixel circuit using N-type thin-film transistors. For example, all thin-film transistors in the pixel circuit 10 shown in Figure 7 may be N-type thin-film transistors, or only some of the thin-film transistors may be N-type thin-film transistors. This is the same for all embodiments.

[0125] Figure 18 shows an example in which the P-type thin-film transistors are replaced with N-type thin-film transistors in the simplified pixel circuit 10 shown in Figure 9. In Figure 18, the driving thin-film transistor 221 and the additional thin-film transistor 222 of the PWM circuit 12 are N-type thin-film transistors. Furthermore, the current control switch 26 is also composed of an N-type thin-film transistor.

[0126] The source of the drive thin-film transistor 221 is supplied with a negative power supply voltage VL2 instead of the positive power supply voltage VH2 shown in Figure 9. The power supply voltage VSET is the positive power supply voltage. By writing a positive voltage to VOUT, the thin-film transistor 26 is turned on, and the LED drive current (light-emitting current) flows, causing the LED to start emitting light. The fall time of the LED current can be more effectively shortened by ensuring the gate voltage of the additional thin-film transistor 222 satisfies the following conditions. VL2 + 1.5 ≤ VREF <VGH

[0127] VGH represents the high voltage of the control signal (pulse signal), for example, 8V. The power supply voltage VSET may be VGH, and VL2 may be -12V. <Embodiment 5>

[0128] Embodiment 5 describes the configuration of the driving thin-film transistor 121 of the PWM circuit 12. In Embodiment 5, the additional thin-film transistor 122 from the pixel circuit 10 may be omitted or may be retained.

[0129] The inventors found that the structure of the PWM-driven thin-film transistor 121 affects the fall time of the LED current. Specifically, they found that a certain range of channel length L of the PWM-driven thin-film transistor 121 can more effectively shorten the fall time of the LED current.

[0130] Figure 19 shows the simulation results of the relationship between the channel length of the PWM-driven thin-film transistor 121 and the fall time of the LED current. In the graph in Figure 19, the horizontal axis represents the channel length, and the vertical axis represents the fall time of the LED current. The simulation was performed on a pixel circuit that does not include the additional thin-film transistor 122.

[0131] Referring to Figure 19, the fall time decreases monotonically as the channel length L increases from 0, reaches a local minimum at a channel length L of 25 μm, and then increases monotonically. Conversely, the fall time decreases monotonically as the channel length L decreases from 100 μm, reaches a local minimum, and then increases monotonically.

[0132] The increased fall time in the range of small channel lengths is presumed to be partly due to the charging of capacitor 124 by unwanted current due to the Kink effect. On the other hand, the increase in fall time from a minimum value as the channel length L of the PWM-driven thin-film transistor 121 increases is presumed to be partly due to the increase in its S value as the channel length L increases. As the S value increases, that is, as the Id-Vg characteristic becomes smoother below the threshold voltage, the change in VOUT becomes smoother.

[0133] The graph in Figure 19 shows that the fall time increases sharply as the channel length L decreases from 8.5 μm. Furthermore, at a channel length L of 70 μm, the fall time is equivalent to that at a channel length L of 8.5 μm. The channel length L of the PWM-driven thin-film transistor 121 can be selected from the following range. The following range includes the channel length L value that exhibits the minimum (best) fall time. 8.5 μm <L≦70μm

[0134] Another perspective on the structure of the PWM-driven thin-film transistor 121 is that it can be constructed as a double-gate thin-film transistor. The double-gate structure includes two separate gate electrodes, and the same gate potential is applied to both gate electrodes. Both gate electrodes are positioned above or below the channel with respect to the substrate. In the description above, it has been assumed that thin-film transistors, including the PWM-driven thin-film transistor 121, have a single-gate structure.

[0135] Figure 20 shows the configuration of a PWM-driven thin-film transistor 121 having a double-gate structure in the circuit diagram. In the circuit diagram, the PWM-driven thin-film transistor 121 is composed of two thin-film transistors 128A and 128B connected in series, and a common gate voltage Vg is applied to their gates. The device structure includes, for example, two separated gate electrodes facing a single high-resistance semiconductor region, and these gate electrodes are connected to a common gate wiring. It should be noted that thin-film transistors other than the PWM-driven thin-film transistor 121 may also have a double-gate structure.

[0136] The following describes an example configuration of a micro-LED display device. The following description can be applied to all of the embodiments described above. Figure 21 is a plan view showing an example configuration of a micro-LED display device. The micro-LED display device includes a display area composed of a pixel circuit 10 and an array of micro-LEDs 11, a signal circuit 31 and a scanning circuit 32.

[0137] Each of the signal circuit 31 and the scanning circuit 32, and their combinations, are drive circuits (sometimes called control circuits) that drive and control the pixel circuit 10. The signal circuit 31 and the scanning circuit 32 supply control signals and power supply voltages for controlling the pixel circuit 10. For example, the signal circuit 31 supplies various power supply voltages (constant voltages) as well as the data voltages PWM_DATA and PAM_DATA of the PWM circuit 12 and constant current circuit 14 to the pixel circuit 10.

[0138] The scanning circuit 32 outputs scanning signals that include, for example, selection signals and light emission control signals for the PWM circuit 12 and the constant current circuit 14. These include PWM_S1, PWM_S2, PWM_EM, PWM_SE, PAM_S1, PAM_S2, and PAM_EM. The type of output signal from the drive circuit depends on the configuration of the pixel circuit.

[0139] The pixel circuit 10 controls the micro LED 11. The components of the pixel circuit 10 are formed on a TFT (thin-film transistor) substrate. The micro LED 11 is connected to connection pads 111 and 112 on the TFT substrate and is electrically connected to the pixel circuit 10 via the connection pads 111 and 112. <Embodiment 6>

[0140] Figure 22 schematically shows the configuration of a pixel circuit according to one embodiment of the present disclosure. Note that the pixel circuit of the present disclosure may include other components in addition to those shown in Figure 22, and some components may be omitted. Circuit elements directly connected in Figure 22 may be electrically or electrically connected.

[0141] This section primarily explains the differences from the pixel circuit configuration example shown in Figure 1. Compared to the pixel circuit shown in Figure 1, the additional thin-film transistor 122 in the PWM circuit 12 is omitted, and the thin-film transistor M41 that controls the constant current circuit 14 is added. Compared to the pixel circuit configuration shown in Figure 1, the constant current control switch 16 is omitted from the constant current control circuit 13.

[0142] The constant current circuit 14 includes thin-film transistors M21 and M23, and capacitor C21, as shown in the circuit configuration in Figure 7. Thin-film transistor M23 is a constant current drive transistor that determines the magnitude of the constant current. The gate of thin-film transistor M23 is connected to one end of capacitor C21, and the other end of capacitor C21 is connected to the power supply line of constant voltage PVDD.

[0143] The constant current control circuit 13 includes a thin-film transistor M31 as shown in Figure 7. The source of thin-film transistor M31 is connected to the drain of thin-film transistor M23, and the drain of thin-film transistor M31 is connected to the anode of micro LED 11.

[0144] In the pixel circuit shown in Figure 22, the gate of thin-film transistor M41 is conductive to one of its source / drain. The source / drain conductive to the gate of thin-film transistor M41 is connected to the gate of thin-film transistor M23, which is the driving transistor of the constant current circuit 14. The other source / drain of thin-film transistor M41 is connected to the drain of PWM-driven thin-film transistor 121. Here, as the drain potential of PWM-driven thin-film transistor 121 changes, the high-potential side switches to the source and the low-potential side switches to the drain for the P-type thin-film transistor M41, according to the high-low relationship with the gate potential of thin-film transistor M23.

[0145] The drain of the PWM-driven thin-film transistor 121 is connected to the source of the switch thin-film transistor 125 and one end of the capacitor 124. A constant voltage VSET is applied to the drain of the switch thin-film transistor 125 and the other end of the capacitor 124. The gate control of the PWM-driven thin-film transistor 121 is the same as that of the pixel circuit shown in Figure 1.

[0146] One of the features of the pixel circuit in this embodiment is that the thin-film transistor M41 is inserted between the drain of the PWM-driven thin-film transistor 121 and the gate of the constant-current-driven thin-film transistor M23, and its gate is connected to the gate of the constant-current-driven thin-film transistor M23.

[0147] When thin-film transistor M41 changes from off to on, the drain of PWM-driven thin-film transistor 121 and the gate of constant-current-driven thin-film transistor M23 are electrically connected. In other words, constant-current-driven thin-film transistor M23 controls not only the magnitude of the LED current but also the on / off control of the LED current. Therefore, a thin-film transistor dedicated to on / off control of the LED current, such as the current control switch 16 in the pixel circuit of Figure 1 or 7, is not required.

[0148] FIG. 23 shows the time variations of the LED current, the drain voltage (PWM-D voltage) of the PWM driving thin film transistor 121, and the gate voltage (PAM-G voltage) of the constant current driving thin film transistor M23 in the pixel circuit shown in FIG. 22. Graph 700 shows the time variation of the LED current. Graph 710 shows the time variations of the PWM-D voltage and the PAM-G voltage. The horizontal axis and the vertical axis of Graph 700 represent time and the LED current, respectively.

[0149] The horizontal axis and the vertical axis of Graph 710 represent time and the node voltage, respectively. In Graph 710, line 711 and line 712 represent the PAM-G voltage and the PWM-D voltage, respectively. During period T1, the gate potential (VOUT) of transistor M23 is maintained higher than the drain potential of transistor 121. VOUT is the source potential of M41, and since the gate and the source of M41 are connected, the gate-source voltage therebetween is 0V. Therefore, the thin film transistor M41 is off, and in period T2 following period T1, the constant current circuit control thin film transistor M41 is on.

[0150] First, although the PWM-D voltage 712 rises gently, it is blocked by the thin film transistor M41 and does not affect the PAM-G voltage 711.

[0151] Thereafter, when the PWM-D voltage 712 further rises and becomes larger than the PAM-G voltage 711, the drain and the source of the thin film transistor M41 are interchanged. That is, the drain of the PWM driving thin film transistor 121 becomes the source of the thin film transistor M41. When the gate-source voltage of M41 exceeds the threshold voltage (Vgs<Vth), the constant current circuit control thin film transistor M41 turns on, and the charge held in the capacitor 124 moves to the capacitor C21, whereby the PAM-G voltage 711 rises. That is, even when the PWM-D voltage 712 starts to rise, the LED current can be maintained high for a while. Therefore, the fall time of the LED current becomes shorter and steeper.

[0152] As described above, the constant current circuit-controlled thin-film transistor M41 eliminates the need for the current control switch 16, which is a constant current control switch. According to the inventors' research, the current control switch 16 is located in the path of the LED current, and its Vds (voltage drop) is large, which can be a contributing factor to power consumption by the pixel circuit. The pixel circuit of this embodiment can eliminate power consumption by the constant current control switch. Furthermore, the operation of the thin-film transistor M41 as described above makes the falling edge of the LED current waveform steeper.

[0153] Figure 24 schematically shows the configuration of a pixel circuit according to one embodiment of the present disclosure. The differences from the pixel circuit shown in Figure 22 will be explained. The pixel circuit of Figure 24 includes the thin-film transistor 122 shown in the pixel circuit of Figure 1, in addition to the pixel circuit of Figure 22. The operation of the thin-film transistor 122 is the same as that of the pixel circuit of Figure 1, and the pixel circuit of Figure 24, which includes the thin-film transistor M41 (third thin-film transistor), particularly improves the steepness of the falling edge of the LED current waveform when displaying low grayscale.

[0154] Figure 25 schematically shows the configuration of a pixel circuit according to one embodiment of the present disclosure. The differences from the pixel circuit shown in Figure 22 will be explained. In the pixel circuit shown in Figure 25, a thin-film transistor M51 (an example of a second thin-film transistor) is placed in place of the thin-film transistor M41, and a constant voltage (power supply voltage) DIVH is applied to its gate. The other configurations are the same as those of the constant-current circuit-controlled thin-film transistor M41, and the constant-current circuit-controlled thin-film transistor M51 controls the gate voltage of the constant-current drive thin-film transistor M23 (an example of a first thin-film transistor). Note that a thin-film transistor 122 can be added to the pixel circuit shown in Figure 25, as shown in Figure 24.

[0155] One embodiment of this disclosure defines the constant voltage DIVH within the following range. PAM-G voltage ≤ DIVH ≤ VH2 + Vth Here, we define PAM-G voltage = PAM_DATA + Vth. PAM_DATA is the current value data explained with reference to Figure 7, and Vth is the threshold voltage of the constant current driven thin-film transistor M23.

[0156] For example, when VH2 = +1V, Vth = -1.5V, and PAM_DATA = -4V, the constant voltage DIVH is within the following range. -5.5V ≤ DIVH ≤ -0.5V

[0157] FIG. 26 shows the time variations of the LED current, the drain voltage (PWM-D voltage) of the PWM driving thin film transistor 121, and the gate voltage (PAM-G voltage) of the constant current driving thin film transistor M23 in the pixel circuit shown in FIG. 25. The constant voltage DIVH is assumed to be -3V. Graph 760 shows the time variation of the LED current. Graph 770 shows the time variations of the PWM-D voltage and the PAM-G voltage. The horizontal axis and the vertical axis of graph 760 represent time and the LED current, respectively. The horizontal axis and the vertical axis of graph 770 represent time and the node voltage, respectively. In graph 770, line 771 and line 772 represent the PAM-G voltage and the PWM-D voltage, respectively.

[0158] First, although the PWM-D voltage 772 rises gently, it is blocked by the constant current circuit control thin film transistor M51 and does not affect the PAM-G voltage 771. After that, when the PWM-D voltage 772 rises further and becomes larger than the PAM-G voltage, the PWM-D voltage 712 switches from the source to the drain for M51. When the gate-source voltage exceeds the threshold voltage (Vgs < Vth), the thin film transistor M51 turns on, and the charge held in the capacitor 124 moves to the capacitor C21, causing the PAM-G voltage 771 to rise.

[0159] Compared with the pixel circuit shown in FIG. 22, by increasing the gate voltage of the constant current circuit control thin film transistor M51, the PWM-D voltage at which the constant current circuit control thin film transistor M51 turns off can be increased. After the PWM-D voltage reaches a voltage that completely turns off the constant current driving thin film transistor M23, the charge can be moved from the capacitor 124 to the capacitor C21, further shortening the fall time of the LED current.

[0160] Figure 27 shows the simulation results of the relationship between the fall time of the LED current and the constant voltage DVIH. In the graph of Figure 27, the horizontal axis represents the constant voltage DVIH, and the vertical axis represents the fall time of the LED current. The value of the positive power supply voltage VH2 of the PWM circuit 12 is assumed to be +1V. The area enclosed by the dashed line satisfies the conditions under which the fall time of the LED current can be further shortened.

[0161] The inventors further performed simulations of the pixel circuits shown in Figures 22 and 25. The results of these simulations are described below. Figure 28A shows the simulation results of the LED current waveform at different threshold voltages of the thin-film transistor M41 in the pixel circuit of Figure 22. The horizontal axis represents time, and the vertical axis represents the LED current. The simulation calculated the LED current waveform when the threshold voltage of thin-film transistor M41 was set to a reference value, and when the threshold voltage of thin-film transistor M41 was shifted by ±0.3V from the reference value. As shown in Figure 28A, the effect of threshold voltage fluctuations of thin-film transistor M41 on the LED current waveform is extremely small.

[0162] Figure 28B shows the simulation results of the LED current waveform at different threshold voltages of the thin-film transistor M51 in the pixel circuit of Figure 25. The horizontal axis represents time, and the vertical axis represents the LED current. The simulation calculated the LED current waveform when the threshold voltage of the thin-film transistor M51 was set to the reference value, and the LED current waveform when the threshold voltage of the thin-film transistor M51 was shifted by ±0.3V from the reference value. As shown in Figure 28B, the effect of the threshold voltage fluctuation of the thin-film transistor M51 on the LED current waveform is extremely small.

[0163] Figure 29A shows the simulation results of the effect on the average LED current due to threshold voltage shifts of different thin-film transistors in the pixel circuit shown in Figure 22. The vertical axis represents the error rate of the average LED current. The graph in Figure 29A shows the error rate of the average LED current due to the individual threshold voltage shifts of thin-film transistors 121, M23, and M41. The graph in Figure 29A further shows the error rate of the average LED current due to the threshold voltage shifts of all thin-film transistors other than those mentioned above ("OTHERS"), and the error rate of the average LED current due to the threshold voltage shifts of all thin-film transistors ("ALL").

[0164] Referring to the graph in Figure 29A, the error rate of the average LED current due to the threshold voltage shift of all thin-film transistors is positive. On the other hand, the error rate of the average LED current due to the threshold voltage shift of thin-film transistor M41 alone is negative, partially offsetting the effect of the threshold voltage shifts of the other thin-film transistors.

[0165] Figure 29B shows the simulation results of the effect on the average LED current due to threshold voltage shifts of different thin-film transistors in the pixel circuit shown in Figure 25. The vertical axis shows the rate of change of the average LED current. The graph in Figure 29B shows the error rate of the average LED current due to the individual threshold voltage shifts of thin-film transistors 121, M23, and M51. The graph in Figure 29B further shows the rate of change of the average LED current due to threshold voltage shifts of all thin-film transistors other than those mentioned above ("OTHERS"), and the error rate of the average LED current due to threshold voltage shifts of all thin-film transistors ("ALL").

[0166] Referring to the graph in Figure 29B, the rate of change in the average LED current due to the threshold voltage shift of all thin-film transistors is positive. On the other hand, the error rate of the average LED current due to the threshold voltage shift of thin-film transistor M51 alone is negative, partially offsetting the effect of the threshold voltage shifts of the other thin-film transistors.

[0167] Figure 30 schematically shows the configuration of a pixel circuit according to one embodiment of the present disclosure. The pixel circuit shown in Figure 30 is constructed by replacing the P-type thin-film transistor in the pixel circuit shown in Figure 25 with an N-type thin-film transistor. Due to the change in the type of thin-film transistor, the positive and negative signs of the power supply voltages VSET and VH2 are changed.

[0168] The thin-film transistors N121, N125, N126, N51, N21, N23, and N31 in the pixel circuit of Figure 30 correspond to the thin-film transistors 121, 125, 126, M51, M21, M23, and M31 in the pixel circuit of Figure 25, respectively. Also, the capacitors N123, N124, and NC21 in the pixel circuit of Figure 30 correspond to the capacitors 123, 124, and C21 in the pixel circuit of Figure 25, respectively. The H and L levels of the control signals for the switch transistors in the pixel circuit of Figure 30 are the opposite of those in the pixel circuit of Figure 25.

[0169] In the pixel circuit of Figure 30, the drain of the PWM-driven thin-film transistor N121 is connected to the capacitor N124. The gate of the constant-current-driven thin-film transistor N23 is connected to the capacitor NC21. The thin-film transistor N51 is inserted between the drain of the PWM-driven thin-film transistor N121 and the gate of the constant-current-driven thin-film transistor N23. The gate of the constant-current circuit-controlled thin-film transistor N51 is connected to a power line that provides a constant voltage DIVH.

[0170] The numerical specifications described for the pixel circuit in Figure 25 are changed as follows depending on the change in the polarity of the thin-film transistor. VH2 + Vth ≤ DIVH ≤ PAM-G voltage Here, we set PAM-G voltage = PAM_DATA + Vth.

[0171] Furthermore, in the pixel circuits described with reference to Figures 22 and 24, at least some of the P-type thin-film transistors can be replaced with N-type thin-film transistors. Also, in the pixel circuits described with reference to Figures 25 and 30, some thin-film transistors may be composed of P-type thin-film transistors, and other thin-film transistors may be composed of N-type thin-film transistors. For example, in the pixel circuits of Figures 22 and 24, if the thin-film transistor M41 is an N-type thin-film transistor, its gate is connected to the gate of the driving transistor. The capacitance C conditions of capacitance 124 described in Embodiment 3 can also be applied to the pixel circuits of this embodiment.

[0172] While embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. Those skilled in the art can easily modify, add to, and transform each element of the above embodiments within the scope of the present disclosure. It is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of symbols]

[0173] 10 Pixel Circuit 11 Micro LEDs 12 PWM circuit 14 Constant current circuit 121 PWM circuit driving thin-film transistor 122 Additional drive thin-film transistors for PWM circuits 124, C21 capacity M41, M51 Thin-Film Transistors M23 Constant Current Driven Thin Film Transistor

Claims

1. A pixel circuit that controls a light-emitting element, A constant current control circuit, which includes a first thin-film transistor and controls the current flowing through the light-emitting element, A pulse width modulation circuit outputs a control signal for the first thin-film transistor based on the input grayscale data voltage and ramp signal, Includes, The first thin-film transistor controls the current flowing through the light-emitting element, The aforementioned pulse width modulation circuit is Pulse width modulation driven thin-film transistor, A second thin-film transistor is positioned between the pulse-width modulation driving thin-film transistor and the output node of the control signal, and a constant voltage is input to its gate. A pixel circuit, including one.

2. A pixel circuit according to claim 1, The first thin-film transistor is a switch. Pixel circuit.

3. A pixel circuit according to claim 1, The first thin-film transistor controls the magnitude and interruption of the current flowing through the light-emitting element. Pixel circuit.

4. A pixel circuit according to claim 1, The conductivity types of the first thin-film transistor, the pulse width modulation driving thin-film transistor, and the second thin-film transistor are the same. Pixel circuit.

5. A pixel circuit according to claim 1, A switch thin-film transistor is arranged between the pulse width modulation driving thin-film transistor and the second thin-film transistor. Pixel circuit.

6. The pixel circuit according to claim 2, The second thin-film transistor is a P-type thin-film transistor, The constant voltage is represented by VREF, and the positive power supply voltage of the pulse width modulation circuit and the low voltage of the control signal are represented by VH2 and VGL, respectively. VGL<VREF≦VH2-1.5 The condition is met. Pixel circuit.

7. The pixel circuit according to claim 2, The second thin-film transistor is an N-type thin-film transistor, The constant voltage is represented by VREF, and the negative power supply voltage and the high voltage of the control signal of the pulse width modulation circuit are represented by VL2 and VGH, respectively. VL2+1.5≦VREF<VGH The condition is met. Pixel circuit.

8. A pixel circuit according to claim 1, The capacitance between the gate of the first thin-film transistor and the power line is further included, The drain of the pulse width modulation drive thin film transistor and the source of the second thin film transistor are connected. The source or drain of the second thin-film transistor is connected to one end of the capacitance and the gate of the first thin-film transistor. Pixel circuit.

9. The pixel circuit according to claim 8, The capacitance of the aforementioned capacitor is 10 fF or more and 300 fF or less. Pixel circuit.

10. The pixel circuit according to claim 2, The constant voltage input to the gate of the second thin-film transistor is the same as the power supply voltage of the other pixel circuit. The constant voltage and the power supply voltage share the same power line. Pixel circuit.

11. The pixel circuit according to claim 2, The constant current control circuit further includes a constant current circuit, The first thin-film transistor is a switch thin-film transistor positioned between the constant current circuit and the light-emitting element. Pixel circuit.

12. The pixel circuit according to claim 3, The second thin-film transistor is a P-type thin-film transistor, The constant voltage is represented by DIVH, the positive power supply voltage of the pulse width modulation circuit is represented by VH2, the gate voltage of the first thin-film transistor is represented by PAM-G, and the threshold voltage of the first thin-film transistor is represented by Vth. PAM-G≦DIVH≦VH2+Vth The condition is met. Pixel circuit.

13. The pixel circuit according to claim 3, The second thin-film transistor is an N-type thin-film transistor, The constant voltage is represented by DIVH, the negative power supply voltage of the pulse width modulation circuit is represented by VH2, the gate voltage of the first thin-film transistor is represented by PAM-G, and the threshold voltage of the first thin-film transistor is represented by Vth. VH2+Vth≦DIVH≦PAM-G The condition is met. Pixel circuit.

14. A pixel circuit according to claim 1, The present invention further includes a third thin-film transistor connected between the gate of the first thin-film transistor and the source or drain of the second thin-film transistor, The gate of the third thin-film transistor is conductive to the source or drain of the third thin-film transistor. Pixel circuit.

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