Memory mapping based on usage

Abstract

The present invention provides a device, apparatus, and program for executing a software program. [Solution] An apparatus comprising a processing unit, at least one memory component, each connected to the processing unit and mapped to a memory address range of the processing unit, and a memory mapping circuit connected to the processing unit and the memory component, which in each of a plurality of iterations accesses statistical counters collected while the processing unit is executing a software program, generates a mapping between a first memory address range and a second memory address range, subject to the identification of the first range and the second range, in accordance with the analysis of the statistical counters, and in response to receiving a memory access command from the processing unit that includes a first memory address in the first range, is configured to replace the first memory address with a second memory address in the second range in accordance with the mapping in the memory access command.

Description

Technical Field

[0001] The present disclosure relates to computerized devices, and more specifically, but not exclusively, to computerized devices having two or more memory components.

[0002] For the sake of brevity, hereinafter the term "system" is used to mean a computerized system, and these terms are used interchangeably.

Background Art

[0003] There are numerous metrics for measuring the performance of a computerized system, such as throughput, i.e., the amount of tasks executed in a specified time interval, and latency, i.e., the amount of time a task is delayed before being executed. For example, improving the performance of a system by increasing the throughput of the system and additionally or alternatively reducing the latency of the system depends, among other factors, on the amount of computer resources available in the system and how well the various components of the system cooperate. For example, the performance of the system can be improved by reducing the latency when accessing memory and additionally or alternatively increasing the throughput of memory access.

[0004] Memory components with relatively high access characteristics, such as low-latency memory components or high-throughput memory components, such as static RAM (SRAM), are typically more expensive than memory components with lower access characteristics, such as dynamic RAM (DRAM). To balance system cost and performance, it is common to design a system's memory using two or more types of memory components. Some common system designs organize multiple memory components within multiple layers of memory, where smaller, faster layers act as caches for larger, slower layers, shadowing larger, slower layers. In some designs, there is a hierarchy of layers, with only the largest layer available for use by software programs, i.e., addressable using the application memory address of the software program, while the other layers in the hierarchy function as hierarchical caches.

[0005] Some other system designs make all layers of memory addressable using the application memory address of a software program. In such systems, the system's performance is affected by the distribution of the software program's application memory across multiple layers of memory, i.e., across one or more memory components of the system. If the software program's application memory comprises multiple application memory regions, performance can be improved when frequently accessed application memory regions are stored in one or more high-performance memory components, while low-performance memory components are used to store application memory regions that are not accessed very often.

[0006] The term Non-Uniform Memory Access (NUMA) refers to a computerized system with two or more memory components, where several characteristics of memory access from processing units to memory components, such as latency and, additionally or alternatively, throughput, depend on the system topology, such as the location of the memory components relative to the processing units. Similar to the systems described above, in a system with NUMA, system performance may be affected by the distribution of application memory for software programs among one or more memory components. [Overview of the Initiative]

[0007] This disclosure includes a description of apparatus and methods for memory management. In some embodiments described herein, a memory mapping circuit is used to map the application memory of a software program executed by a processing unit to one or more memory components connected to a processing unit, without requiring calculations by the processing unit and without affecting a memory mapping table used by an operating system executed by the processing unit. Furthermore, in such embodiments, the memory mapping circuit is configured to replace a first memory address in the first memory address range with a second memory address in the second memory address range in memory access commands received from the processing unit, according to a mapping between a first memory address range and a second memory address range generated according to an analysis of one or more statistical counters collected while the processing unit executes the software program. By using the memory mapping circuit to generate a mapping between the first memory address range and the second memory address range, and by replacing memory addresses in memory access commands according to the generated mapping, the amount of processing overhead required from the processing unit to update the distribution of multiple application memory areas of the software program among one or more memory components is reduced, and therefore the performance of the apparatus is improved.

[0008] The above-mentioned and other objectives are achieved by the features of the independent claim. Further forms of implementation are evident from the dependent claims, specification, and drawings. [Means for solving the problem]

[0009] According to the first embodiment, the apparatus for executing a software program includes a processing unit, at least one memory component, each connected to the processing unit and mapped to at least one memory address range among a plurality of memory address ranges of the processing unit, and a memory mapping circuit connected to the processing unit and at least one memory component, which in each management iteration of a plurality of management iterations accesses one or more of a plurality of statistical counters collected while the processing unit is executing the software program, and generates a mapping between a first memory address range among the plurality of memory address ranges and a second memory address range among the plurality of memory address ranges, on the condition that the first memory address range and the second memory address range are identified, in accordance with the analysis of one or more statistical counters, and in response to receiving at least one memory access command from the processing unit that includes a first memory address within the first memory address range, the device for executing a software program includes a processing unit, at least one memory access command, which replaces the first memory address with a second memory address within the second memory address range according to the mapping.

[0010] According to a second aspect, a method for managing memory in a device for executing one or more software programs includes, in each management iteration of a plurality of management iterations, a memory mapping circuit connected to a processing unit and at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range among a plurality of memory address ranges of the processing unit, accessing one or more of a plurality of statistical counters collected while the processing unit is executing at least one of the one or more software programs; generating a mapping between a first memory address range among the plurality of memory address ranges and a second memory address range among the plurality of memory address ranges, on the condition that the first memory address range and the second memory address range are identified, in accordance with an analysis of the one or more statistical counters; and in response to receiving at least one memory access command from the processing unit, which includes a first memory address within the first memory address range, replacing the first memory address with a second memory address within the second memory address range in accordance with the mapping in at least one memory access command.

[0011] According to a third aspect, a software program product for memory management includes a non-temporary computer-readable storage medium and a first program instruction, in each management iteration of a plurality of management iterations, a memory mapping circuit connected to a processing unit and at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range among a plurality of memory address ranges of the processing unit, and the memory mapping circuit accesses one or more of a plurality of statistical counters collected while the processing unit is executing at least one of one or more software programs, and the one or more statistical counters The system comprises: a first program instruction for generating a mapping between a first memory address range and a second memory address range, based on the analysis, provided that the first and second memory address ranges are identified; and a second program instruction for replacing the first memory address with a second memory address within the second memory address range in at least one memory access command in the second memory access command, in accordance with the mapping, in response to receiving at least one memory access command from a processing unit, which includes a first memory address within the first memory address range. In a third embodiment, the first and second program instructions are executed by at least one computerized processor from a non-temporary computer-readable storage medium.

[0012] In one implementation of the first and second embodiments, the multiple statistical counters include high-access counters, low-access counters, and multiple range-access counters, each associated with one of a plurality of memory address ranges. Optionally, accessing one or more statistical counters includes accessing at least one of the low-access counters and high-access counters, performing other analyses involving at least one of the low-access counters and high-access counters, and accessing at least one range-access counter according to other results of the other analyses. By using watermark counters, such as high-access or low-access counters, in addition to the multiple range-access counters, the amount of access to the multiple range-access counters is reduced, thereby reducing the amount of computing resources required for memory mapping compared to accessing all of the multiple range-access counters.

[0013] In other implementations of the first and second embodiments, the device further comprises a processing unit and at least one memory tracking circuit connected to at least one memory component. Optionally, at least one of a plurality of statistical counters is implemented in at least one memory tracking circuit configured to update at least one of the plurality of statistical counters in each tracking iteration of a plurality of tracking iterations in response to the receipt of a memory access command from the processing unit. Implementing statistical counters in the memory tracking circuit reduces the amount of computing resources required to track one or more memory accesses compared to implementing statistical counters in the page tables of an operating system executed by a processing unit running a software program. Optionally, a memory mapping circuit is further configured to access one or more of the plurality of statistical counters by accessing at least one memory tracking circuit. Optionally, the memory mapping circuit is further configured to set at least one of a low access threshold and a high access threshold in at least one memory tracking circuit. Optionally, the memory mapping circuit sets at least one of a low access threshold and a high access threshold in at least one memory tracking circuit according to further results of further further analysis comprising one or more statistical counters. By setting low access thresholds and additionally or alternatively high access thresholds, the accuracy of high and low access counters is improved, and the accuracy of memory mapping calculated according to one or more statistical counters is improved.

[0014] In further implementations of the first and second embodiments, the memory mapping circuit further comprises a plurality of address mappings, each mapping one of a plurality of memory address ranges to a media address range, the media address range being another of the plurality of memory address ranges. By mapping one of the plurality of memory address ranges to a media address range which is another of the plurality of memory address ranges, it becomes possible to move the application memory region of a software program from one memory component to another memory component without changing the operating system's page table that maps the application address of the software program to the physical address of the processing unit, thereby reducing the amount of interruption to one or more services provided by the device running the software program. Optionally, generating a mapping between the first memory address range and the second memory address range includes updating each media address range in each address mapping of the first memory address range to become the second memory address range. Optionally, the memory mapping circuit is configured to perform a plurality of management iterations while the processing unit is running the software program. By performing multiple management iterations that generate memory mappings while the processing unit executes the software program, the performance of the device executing the software program can be improved without increasing the amount of interruption to one or more services provided by the device executing the software program.

[0015] In further implementations of the first and second embodiments, the memory mapping circuit is further configured to copy at least one data value stored in the first memory component of at least one memory component associated with the first memory address range to the second memory component of at least one memory component associated with the second memory address range, provided that it identifies the first memory address range and the second memory address range according to an analysis of a plurality of statistical counters. Optionally, the application memory of the software program comprises a plurality of application memory areas, each stored in one of at least one memory component. Optionally, at least one data value is part of at least one application memory area among the plurality of application memory areas. By copying one or more data values ​​that are part of the application memory of the software program, the performance of the device running the software program is improved without increasing the amount of interruption to one or more services provided by the device running the software program.

[0016] In further implementations of the first and second embodiments, the processing unit executes a software program by running an operating system having an operating system page size for memory management. Optionally, at least one of a plurality of memory address ranges addresses a different amount of memory than the operating system page size. Mapping memory using memory address ranges with range sizes not equal to any of the sets of operating system page sizes improves the accuracy of the analysis of one or more statistical counters and thus improves the performance of the device executing the software program.

[0017] Other systems, methods, features, and advantages of this disclosure will become apparent to those skilled in the art upon consideration of the following drawings and detailed description. All such further systems, methods, features, and advantages are contained within this description, are within the scope of this disclosure, and are intended to be protected by the appended claims.

[0018] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the implementation relates. Similar or equivalent methods and materials to those described herein may be used in the implementation or testing of the implementation, but exemplary methods and / or materials are described below. In case of any conflict, the patent specification, including the definitions, shall prevail. Furthermore, materials, methods, and examples are illustrative and not necessarily intended to be limiting.

[0019] With reference to the accompanying drawings, several embodiments are described herein merely as examples. With particular reference here to the drawings, it is emphasized that the details shown are illustrative and for illustrative purposes only. In this regard, the description made with reference to the drawings will make it clear to those skilled in the art how the embodiments may be carried out. [Brief explanation of the drawing]

[0020] [Figure 1] This is a schematic block diagram of an exemplary apparatus according to several embodiments. [Figure 2] This is a schematic block diagram of an exemplary address mapping according to several embodiments. [Figure 3] This is a schematic block diagram of an exemplary memory mapping according to several embodiments. [Figure 4] This is a schematic block diagram of another exemplary memory mapping according to several embodiments. [Figure 5] This flowchart schematically represents the flow of optional operations for memory mapping according to several embodiments. [Modes for carrying out the invention]

[0021] As used herein, the term "processing unit" refers to any kind of programmable or non-programmable circuit configured to perform the operations described below. The processing unit may comprise hardware as well as software. For example, the processing unit may comprise one or more processors and a temporary or non-temporary memory carrying a program that causes the processing unit to perform its respective operations when the program is executed by the one or more processors.

[0022] In addition, as used herein, the term "physical address" means the address used by the processing unit within a memory access request to access a memory component. In addition, as used herein, the term "application address" means the address used in an application. The application address may be a virtual address, in which case the application address needs to be translated to a physical address for the purpose of accessing one or more memory components. In addition, as used herein, the term "media address" means the address recognized by a memory component. The processing unit may use the media address within a memory access request. Optionally, the memory address within a memory access request is mapped to a media address. As used herein, the term "memory mapping" refers to mapping the application memory address of a software program to the physical address within the memory access request transmitted by the processing unit. Such mapping may be used to translate the application address to a physical address that identifies the location within the memory component in which the application data or instructions are stored.

[0023] In addition, as used herein, both the terms “memory access request” and “memory access command” are used interchangeably to mean a request to access a memory component for the purpose of reading from it and writing to it additionally or alternatively. A memory access request may be generated when executing a computer instruction in a software program that includes a memory access computer instruction.

[0024] In addition, both the terms “memory address range” and “memory address range” used in this specification are used interchangeably to mean a range of memory addresses.

[0025] To allocate each of a plurality of application memory regions to one or more memory components connected to a processing unit so that the performance of the system is improved, some systems track accesses to the one or more memory components and use the collected tracking information to identify application memory regions to be moved from one memory component to another. Some existing tracking methods maintain access counters in a page table used by an operating system executed by the processing unit to map the application addresses of software programs to the physical addresses of the processing unit. Some such methods update the counters in the page table each time the memory is accessed. Analysis of multiple counters in the page table requires merging the counters of multiple virtual pages mapped to a common physical page. Some methods further require sorting multiple counters to classify page table entries, for example, to identify page table entries that describe high-access application memory regions. Additionally, moving an application memory region from one memory component to another requires the processing unit's computational resources to update the page table and, in some cases, to copy the application memory region from one memory component to another. Such methods degrade the performance of the system because they require the processing unit's computational resources. Further, one or more means provided by a system executing a software program may be interrupted while the page table is being updated.

[0026] To reduce the amount of computing resources used by a processing unit to map application memory to one or more memory components, in some embodiments described herein, this disclosure proposes generating a mapping between one or more physical addresses of a processing unit and one or more media addresses of one or more memory components, and using a memory mapping circuit connected to the processing unit and one or more memory components to replace the memory address of a memory access command with the media address of one of the memory components in a memory access command received from the processing unit in accordance with the generated mapping. Optionally, the memory address of the memory access command is a first physical memory address within a first memory address range of the processing unit, and the memory address range is one of a plurality of memory address ranges of the processing unit. Optionally, the media address is a second physical memory address within a second memory address range of the plurality of memory address ranges. Such a mapping between one or more physical addresses used by the processing unit and one or more media addresses recognized by one or more memory components allows application memory regions to be moved from one memory component to another without modifying the operating system's page table that maps application addresses of software programs to the processing unit's physical addresses. By refraining from modifying the page table, the amount of interruption to one or more services provided by the system running the software program is reduced. Optionally, the memory mapping circuit generates mappings in each of multiple managed iterations. Optionally, the memory mapping circuit generates mappings while the processing unit is running the software program.

[0027] Optionally, the mapping is generated according to an analysis of one or more statistical counters collected while the processing unit executes a software program. Optionally, the statistical counters indicate multiple memory access commands. For example, if the processing unit has multiple memory address ranges and each of one or more memory components is mapped to one or more of the multiple memory address ranges, the statistical counters may be range access counters associated with the memory address ranges, indicating the number of times the memory address range is accessed within multiple memory access commands. Optionally, the statistical counters indicate the amount of range access counters that satisfy an identified criterion. For example, the statistical counters may be watermark counters indicating the amount of range access counters exceeding a high access threshold, where the high access threshold indicates the amount of access to memory address ranges considered high. Alternatively, the watermark counters may indicate the amount of range access counters below a low access threshold, where the low access threshold indicates the amount of other access to memory address ranges considered low. Optionally, the statistical counters indicate the amount of memory access commands received from the processing unit. Optionally, one or more processing circuits receive a memory access command in each of the multiple iterations and update at least one of the multiple statistical counters in each of the multiple iterations.

[0028] By performing the analysis using a memory mapping circuit, the amount of computing resources required from the processing unit to perform the analysis is reduced compared to performing the analysis using the processing unit itself. This improves the system's performance when running the software program, for example by increasing throughput and, additionally or alternatively, by reducing latency when executing one or more tasks of the software program.

[0029] Optionally, the memory mapping circuit is further configured to copy one or more data values ​​stored in a first memory component of one or more memory components to a second memory component of one or more memory components, where the first memory component is associated with a first memory address range and the second memory component is associated with a second memory address range. Optionally, the memory mapping circuit copies one or more data values ​​from the first memory component to the second memory component, provided that it identifies the first and second memory address ranges according to the analysis of one or more statistical counters. Copying one or more data values ​​by the memory mapping circuit reduces the amount of interruption to one or more services provided by a system running a software program compared to copying one or more data values ​​by a processing unit.

[0030] Optionally, at least one of one or more statistical counters is implemented in one or more tracking circuits connected to the processing unit and one or more memory components. Implementing statistical counters in the tracking circuits reduces the amount of resources used by the processing unit to track multiple memory accesses, for example, reducing the amount of memory access performed by the processing unit, and additionally or alternatively, reducing the amount of processor cycles of the processing unit used to compute memory mappings. Optionally, the memory mapping circuit is further configured to constitute one or more tracking circuits.

[0031] When a processing unit executes an operating system, the operating system may address multiple memory components using multiple operating system memory pages. It is common not to use an arbitrary page size for multiple operating system memory pages; that is, each of the multiple operating system memory pages has one of an identified set of page sizes. When memory access tracking is performed using the operating system's page table, the granularity of the memory access tracking follows the page size of each of the multiple operating system memory pages. In some embodiments described herein, at least one identified memory address range among multiple memory address ranges has a range size that is not equal to any of the set of page sizes. By tracking multiple memory access commands according to multiple memory address ranges using one or more range access counters, multiple memory access commands can be tracked at a different granularity than the operating system's page size, thereby improving the accuracy of the memory mapping calculated according to multiple statistical counters compared to the memory mapping calculated when tracking follows the operating system's page size, and thus improving the accuracy of the allocation of multiple application memory regions to one or more memory components, and improving system performance.

[0032] Before describing at least one embodiment in detail, it should be understood that the embodiments are not necessarily limited in their application to the structural and arrangement and / or method details of the components described and / or shown in the following description and / or drawings and / or examples. The embodiments described herein are possible in other embodiments or can be implemented or performed in various ways.

[0033] Embodiments may be systems, methods, and / or computer program products. A computer program product may include a computer-readable storage medium (or a set of mediums) having computer-readable program instructions for causing a processor to execute aspects of the embodiments.

[0034] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction-executing device. A computer-readable storage medium may, but is not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital multipurpose disks (DVDs), memory sticks, floppy disks, and any suitable combination of the above. As used herein, computer-readable storage media should not be construed as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through optical fiber cables), or transient signals themselves, such as electrical signals transmitted through wires.

[0035] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium or via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network, to each computing / processing device or to an external computer or external storage device. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0036] The computer-readable program instructions for performing the operation of the embodiments may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code, and may be natively compiled or compiled just-in-time (JIT), and may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, Java, and Object-Oriented Fortran, interpreted programming languages ​​such as JavaScript and Python, and traditional procedural programming languages ​​such as the "C" programming language, Fortran, or similar programming languages. The computer-readable program instructions may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or it may be connected to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by personalizing the electronic circuit using state information of computer-readable program instructions in order to perform an aspect of the embodiment.

[0037] The aspects of the embodiments are described herein in relation to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to the embodiments. It will be understood that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0038] These computer-readable program instructions may be provided to a general-purpose computer, a dedicated computer, or a processor of another programmable data processing device for manufacturing a machine, such that instructions executed via the processor of a computer or other programmable data processing device create means for performing functions / operations specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct computers, programmable data processing devices, and / or other devices to function in a particular way, and as a result, a computer-readable storage medium having stored instructions may include a product containing instructions that perform modes of functions / operations specified in one or more blocks of a flowchart and / or block diagram.

[0039] Computer-readable program instructions may also be loaded onto a computer, another programmable device, or another device to generate a computer-executed process by causing the computer, another programmable device, or other device to perform a series of action steps so that the instructions executed on the computer, another programmable device, or other device perform a function / operation specified in one or more blocks of a flowchart and / or block diagram.

[0040] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible embodiments of systems, methods, and computer program products according to various embodiments. In this regard, each block in a flowchart or block diagram may represent a module, segment, or part of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions described in a block may occur in a different order than that shown in the diagram. For example, two consecutively shown blocks may actually be executed substantially simultaneously, or blocks may be executed in reverse order depending on the functionality they relate to. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs a specified function or operation, or a combination of dedicated hardware and computer instructions.

[0041] Herein, we refer to Figure 1, which shows a schematic block diagram of an exemplary apparatus according to several embodiments. In such embodiments, the processing unit 101 is connected to at least one memory component 120.

[0042] For brevity, the term “memory component 120” will hereafter be used to mean “at least one memory component 120,” and these terms will be used interchangeably. Optionally, memory component 120 comprises one memory component, for example, memory component 120C. Optionally, memory component 120 comprises multiple memory components, for example, memory component 120A, memory component 120B, and memory component 120C. The memory components may be random access memory (RAM) components, for example, SRAM components or DRAM components. Other examples of memory components include read-only memory (ROM) components, electrically erasable programmable ROM (EEPROM), and non-volatile RAM (NVRAM). Optionally, one or more of the memory components 120 are electrically coupled to the processing unit 101. Optionally, one or more of the memory components 120 are connected to the processing unit 101 via a host memory controller (not shown).

[0043] Optionally, one or more of the memory components 120 are cache memory components of the processing unit 101. Optionally, one or more of the memory components 120 are connected to other cache memory components (not shown) additionally connected to the processing unit 101.

[0044] Optionally, one or more memory tracking circuits 130 are connected to the processing unit 101 and the memory components 120. Optionally, each of the memory components 120 is mapped to at least one of a plurality of memory address ranges of the processing unit 101.

[0045] Here, we also refer to Figure 2, which shows a schematic block diagram of an exemplary address mapping 200 according to several embodiments. In this example, the memory component 120A is mapped to memory address ranges 201A, 201B, and 201C of a plurality of memory address ranges 201. Therefore, when the processing unit 101 accesses one of the memory addresses among memory address ranges 201A, 201B, and 201C, the processing unit 101 accesses the memory component.

[0046] Similarly, memory component 120B is mapped to memory address range 201D of multiple memory address ranges 201, and memory component 120C is mapped to memory address ranges 201E and 201F of multiple memory address ranges 201.

[0047] Optionally, the processing unit 101 executes an operating system that addresses the memory component 120 using multiple operating system memory pages. Optionally, each of the multiple operating system memory pages has a page size that is one of an identified set of page sizes. Optionally, at least one of the multiple memory address ranges 201 has a size that is not a member of the identified set of page sizes.

[0048] Let us refer to Figure 1 again. Optionally, the memory mapping circuit 110 is connected to the processing unit 101 and the memory component 120.

[0049] Optionally, the memory mapping circuit 110 includes multiple address mappings. Optionally, each of the multiple address mappings maps one of the multiple memory address ranges 201 to a media address range, and the media address range is one of the other memory address ranges 201.

[0050] Here, we also refer to Figure 3, which shows a schematic block diagram of an exemplary memory mapping 300 according to several embodiments. In this example, a plurality of address mappings 321 include an address mapping 321A, which maps a memory address range 201A to a media address range, for example, the memory address range 201A, associated with a memory component 120A.

[0051] Similarly, in this example, multiple address mappings 321 include address mapping 321D, where address mapping 321D maps the memory address range 201D to another range of memory addresses associated with the memory component 120B, for example, another range of media addresses which is the memory address range 201D.

[0052] In addition, in this example, multiple address mappings 321 include address mapping 321E, where address mapping 321E maps the memory address range 201E to a further range of media addresses associated with the memory component 120C, for example, the memory address range 201E.

[0053] Furthermore, in this example, the multiple address mappings 321 include address mapping 321B which maps to memory address range 201B, address mapping 321C which maps to memory address range 201C, and address mapping 321F which maps to memory address range 201F.

[0054] If the application memory of a software program executed by the processing unit 101 comprises multiple application memory areas 301, one or more of the multiple memory areas may be stored in one of the memory components and associated with one of the multiple memory address ranges 201. In this example, application memory area 301A of the multiple application memory areas 301 is stored in memory component 120A and associated with memory address range 201A. When the processing unit 101 sends a memory access command to the application memory area 301A, the memory access command includes a first memory address within the memory address range 201A. When the address mapping 321A maps the memory address range 201A to the media address range which is the memory address range 201A, the memory component 120A responds to the memory address command.

[0055] Similarly, application memory area 301B, one of the multiple application memory areas 301, is stored in memory component 120B and associated with memory address range 201D, and application memory area 301C, one of the multiple application memory areas 301, is stored in memory component 120C and associated with memory address range 201E.

[0056] According to some embodiments, the memory mapping circuit 110 optionally generates a new mapping for one of a plurality of memory address ranges 201.

[0057] Here, also refer to Figure 4, which shows a schematic block diagram of another exemplary memory mapping 400 according to several embodiments. In this example, a new memory mapping 421A is generated instead of memory mapping 321A, and this memory mapping 421A maps the memory address range 201A to a new media address range, which is a memory address range in memory component 120C, for example, memory address range 201F. Optionally, the application memory area 301A associated with the memory address range 201A is stored here in memory component 120C rather than memory component 120A. In this example, when the processing unit 101 sends a new memory access command to access the application memory area 301A, the new memory access command includes a first memory address in the memory address range 201A. In this example, since the address mapping 421A maps the memory address range 201A to a new media address range which is the memory address range 201F, in some embodiments, the memory mapping circuit 120 replaces the first memory address with a second memory address in the new memory access command so that the memory component 120C responds to the new memory address command instead of the memory component 120A.

[0058] Therefore, in this example, without changing the page table that maps multiple application memory regions 301 to multiple memory address ranges 201, the processing unit 101 accesses the application memory region 301A using the memory address range 201A, even though the application memory region 301A is stored in memory component 120C as before and not in memory component 120A.

[0059] To manage memory, the memory mapping circuit 110 in system 100 may implement one of the following optional methods.

[0060] Here, we also refer to Figure 5, which shows a flowchart schematically representing an optional operation flow 500 for memory mapping according to several embodiments.

[0061] For the sake of brevity, the term "mapping circuit" will henceforth be used to mean "memory mapping circuit," and these terms will be used interchangeably.

[0062] In such embodiments, in 501, the mapping circuit 110 accesses one or more of a plurality of statistical counters collected while the processing unit 101 executes a software program. Optionally, the plurality of statistical counters comprises a plurality of range access counters, each associated with one of a plurality of memory address ranges 201. Optionally, the plurality of statistical counters comprises one or more watermark counters, each associated with the frequency of access to a memory component. A watermark counter may indicate the amount of a memory access range accessed with a frequency associated with the watermark counter. A watermark counter may be a high access counter indicating the amount of range access counters for a plurality of range accesses exceeding a high access threshold, indicating frequent access to each memory component associated with a range access counter exceeding a high access threshold. For example, a range access counter for memory address range 201A exceeding a high access threshold may indicate frequent access to memory component 120A associated with memory address range 201A. Another example of a watermark counter is a low access counter indicating the amount of range access counters for a plurality of range accesses exceeding a low access threshold. There may be three or more watermark counters, each associated with one of several access frequencies to a memory component. Each of the three or more watermark counters may also be associated with an access threshold indicating the access frequency it is associated with, i.e., it indicates the amount of range access counters of multiple range access counters that exceed the threshold associated with the watermark counter.

[0063] Optionally accessing one or more statistical counters includes the mapping circuit accessing at least one of the low-access counters and high-access counters. Optionally accessing one or more statistical counters includes the mapping circuit performing an initial analysis that includes the accessed low-access counters and additionally or alternatively high-access counters. Optionally accessing one or more statistical counters includes the mapping circuit accessing at least one range-access counter according to the initial results of the initial analysis.

[0064] Optionally, in each of one or more access iterations, the mapping circuit 110 accesses one or more range access counters at a time. Optionally, in each of one or more access iterations, the mapping circuit 110 accesses a subset of multiple range access counters. Optionally, the management component 110 refuses to access at least one range access counter on the condition that it identifies a termination condition, for example, receiving an amount of a range access counter that exceeds a threshold equal to the value of a previously accessed watermark counter.

[0065] Optionally, at least one of a plurality of statistical counters is implemented in one or more memory tracking circuits 130. Optionally, one or more memory tracking circuits 130 are configured to update at least one of the plurality of statistical counters in each tracking iteration of a plurality of tracking iterations in response to receiving a memory access command from the processing unit 101. Optionally, the memory mapping circuit accesses one or more statistical counters by accessing one or more memory tracking circuits 130.

[0066] Optionally, at least one of the multiple statistical counters is implemented in one of the memory components 120. In some cases, one of the memory components implementing at least one other statistical counter is a cache memory component of the processing unit 101. Optionally, at least one of the multiple statistical counters is implemented in other cache memory components connected to one or more of the memory components 120.

[0067] Optionally, the memory mapping circuit 110 accesses one or more statistical counters while the processing unit 101 executes a software program.

[0068] In step 502, the mapping circuit 110 optionally performs an analysis of one or more statistical counters. Optionally, in step 507, the mapping circuit 110 identifies a first memory address range, e.g., memory address range 201A, and a second memory address range, e.g., memory address range 201F. In some cases, the mapping circuit 110 identifies the first and second memory address ranges according to the analysis of one or more statistical counters. For example, if the results of the analysis indicate high-frequency access to the application memory area 301A using memory address range 201A, the mapping circuit 110 may identify memory address range 201A as the first memory address range.

[0069] In 510, the mapping circuit 110 optionally generates a mapping between a first memory address range and a second memory address range, for example, a mapping 421A between memory address range 201A and memory address range 201F. Optionally, mapping 421A is generated by updating the media address range of mapping 321A from memory address range 210A to memory address range 201F.

[0070] Optionally, the memory mapping circuit 110 generates the mapping while the processing unit 101 executes the software program.

[0071] Optionally, in 520, the mapping circuit 110 copies one or more data values, for example, at least a portion of the application memory area 301A, from the memory component 120A associated with the memory address range 201A to the memory component 120C associated with the memory address range 201F.

[0072] Optionally, before generating mapping 421A and before copying one or more data values, the mapping circuit 110 stops access from the processing unit 101 to memory components 120A and 120C. Optionally, after copying one or more data values, the processing circuit 110 re-enables access from the processing unit 101 to memory components 120A and 120C.

[0073] Optionally, copying one or more data values ​​from memory component 120A to memory component 120C involves swapping one or more data values ​​with one or more other data values ​​stored in memory component 120C, such that after the swap, one or more data values ​​are stored in memory component 120C and one or more other data values ​​are stored in memory component 120A. Optionally, the swap between one or more data values ​​and one or more other data values ​​may involve using one or more intermediate memory areas. Optionally, one or more intermediate memory areas are located in one of the memory components 120. Optionally, one or more intermediate memory areas are located in the mapping circuit 110.

[0074] Optionally, the mapping circuit 110 repeats one or more of 501, 502, 507, 510, and 520 in each of the multiple management iterations. Optionally, the mapping circuit 110 executes multiple management iterations while the processing unit 101 executes the software program.

[0075] Optionally, at 540, the memory mapping circuit 110 receives one or more memory access commands from the processing unit 101. Optionally, one or more memory access commands include a first memory address within the memory address range 201A. Optionally, in response to receiving one or more memory access commands, at 541, the mapping circuit 110 replaces the first memory address in one or more memory access commands with a second memory address within the memory address range 201F, according to the memory mapping 421A.

[0076] Optionally, while executing the software program, the processing unit 101 sends one or more memory access commands to optionally access the application memory of the software program, for example, the application memory area 301A.

[0077] Optionally, the memory mapping circuit 110 sets one or more thresholds in one or more memory tracking circuits 130, such as low access thresholds or high access thresholds. Optionally, the memory mapping circuit 110 performs further analysis, including one or more statistical counters. Optionally, the memory mapping circuit 110 sets one or more thresholds according to further results of the further analysis.

[0078] The memory mapping circuit 110 optionally sets a low access threshold and additionally or alternatively sets a high access threshold in at least one of a plurality of management iterations while the processing unit 101 is executing a software program.

[0079] The descriptions of various embodiments are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications, or technical improvements to the technology available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0080] During the term of this patent application, it is anticipated that many related memory mapping and memory tracking circuits will be developed, and the scope of the terms "memory mapping circuit" and "memory tracking circuit" is intended to a priori include all such new technologies.

[0081] As used in this specification, the term "about" refers to ±10%.

[0082] The terms "to have," "to possess," "to include," "to contain," and "to have," and their conjugations, all mean "to include but not limited to these." This term encompasses the terms "to consist of" and "to essentially consist of."

[0083] The phrase "consisting essentially of" means that the configuration or method may include additional components and / or steps, but only if the additional components and / or steps do not substantially alter the basic and novel features of the claimed configuration or method.

[0084] As used herein, the singular forms “a,” “an,” and “the” include plural references unless otherwise explicitly indicated by the context. For example, the terms “compound” or “at least one compound” may include multiple compounds, including mixtures thereof.

[0085] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any embodiment described as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments, and / or should not be excluded from incorporating features from other embodiments.

[0086] The term “optionally” is used herein to mean “provided in some embodiments but not in other embodiments.” Any particular embodiment may include several “optional” features, provided that such features do not conflict.

[0087] Through this application, various embodiments may be presented in scope form. It should be understood that scope form descriptions are merely for convenience and brevity and should not be interpreted as inflexible limitations on the scope of the embodiments. Therefore, scope descriptions should be considered to specifically disclose all conceivable sub-ranges and the individual numbers within those ranges. For example, a scope description such as 1-6 should be considered to specifically disclose sub-ranges such as 1-3, 1-4, 1-5, 2-4, 2-6, 3-6, and the individual numbers within those ranges, e.g., 1, 2, 3, 4, 5, and 6. This applies regardless of the width of the range.

[0088] Whenever a numerical range is indicated in this specification, it means that any cited number (fraction or integer) within that range is included. The phrases “in the range between” the first indicator and the second indicator, and “in the range from” the first indicator to the second indicator, are used interchangeably in this specification and mean that the first and second indicators, as well as all fractions and integers between them, are included.

[0089] For clarity, it is understood that certain features of embodiments described in the context of separate embodiments may be given in combination in a single embodiment. Conversely, various features of embodiments described in the context of a single embodiment for the sake of brevity may be given separately, in any suitable partial combination, or as appropriate in any other described embodiment. Certain features described in the context of different embodiments should not be considered essential features of those embodiments unless the embodiment is inoperable without those elements.

[0090] While embodiments have been described in conjunction with their specific embodiments, it is evident that many alternative, modified, and variant forms are apparent to those skilled in the art. Therefore, it is intended to encompass all such alternative, modified, and variant forms that fall within the spirit and broad scope of the appended claims.

[0091] All publications, patents, and patent applications referenced herein are incorporated herein by reference in their entirety, as if each individual publication, patent, or patent application were specifically and individually referred to when it is stated that such publications, patents, or patent applications should be incorporated herein by reference. Furthermore, any reference or specification of any prior art in this application should not be construed as an acknowledgment that such prior art is available as prior art to the present invention. Nor should it be construed as necessarily limiting such prior art to the extent that titles are used. Furthermore, any priority documents of this application are incorporated herein by reference in their entirety. [Explanation of Symbols]

[0092] 100 Systems 101 Processing Unit 110 Memory Mapping Circuit 120 memory components 120A Memory Components 120B Memory Components 120C Memory Components 130 Memory tracking circuit 200 Address Mappings 201 Memory address range 201A Memory Address Range 201B Memory Address Range 201C Memory Address Range 201D Memory Address Range 201E Memory Address Range 201F Memory Address Range 300 memory mappings 301 Application memory area 301A Access Application Memory Area 301B Application memory area 301C Application Memory Area 321 Address Mapping 321A Address Mapping 321B Address Mapping 321C Address Mapping 321D Address Mapping 321E Address Mapping 321F Address Mapping 400 memory mappings 421A New memory mapping 500 Operation Flow

Claims

1. A device for executing a software program, Processing unit and Each of these includes at least one memory component connected to the processing unit and mapped to at least one memory address range among a plurality of memory address ranges of the processing unit, A memory mapping circuit connected to the processing unit and the at least one memory component, In each control iteration of multiple control iterations, The processing unit accesses one or more of the statistical counters collected while the software program is running, In accordance with the analysis of the one or more statistical counters, a mapping is generated between a first memory address range and a second memory address range among the plurality of memory address ranges, provided that the first memory address range and the second memory address range are identified, and In response to receiving at least one memory access command from the processing unit, which includes a first memory address within the first memory address range, the at least one memory access command replaces the first memory address with a second memory address within the second memory address range according to the mapping. A memory mapping circuit configured as follows, A device equipped with the following features.

2. The apparatus according to claim 1, wherein the plurality of statistical counters comprises a high access counter, a low access counter, and a plurality of range access counters, each associated with one of the plurality of memory address ranges.

3. The processing unit and the at least one memory tracking circuit are further connected to the at least one memory component, At least one of the plurality of statistical counters is implemented in the at least one memory tracking circuit, which is configured to update at least one of the plurality of statistical counters in each tracking iteration of the plurality of tracking iterations in response to receiving a memory access command from the processing unit, The memory mapping circuit is further configured to access one or more of the plurality of statistical counters by accessing at least one of the memory tracking circuits. The apparatus according to claim 1 or 2.

4. The memory mapping circuit further comprises a plurality of address mappings, each of which maps one of the plurality of memory address ranges to a media address range, wherein the media address range is one of the plurality of memory address ranges. Generating the mapping between the first memory address range and the second memory address range includes updating the respective media address ranges of the respective address mappings of the first memory address range to match the second memory address range. The apparatus according to any one of claims 1 to 3.

5. The memory mapping circuit is Provided that the first memory address range and the second memory address range are identified in accordance with the analysis of the plurality of statistical counters, at least one data value stored in the first memory component of the at least one memory component associated with the first memory address range is copied to the second memory component of the at least one memory component associated with the second memory address range. The apparatus according to any one of claims 1 to 4, further configured as follows.

6. The application memory of the software program comprises a plurality of application memory areas, each of which is stored in one of the at least one memory component. The at least one data value is part of at least one application memory area among the plurality of application memory areas. The apparatus according to claim 5.

7. The apparatus according to any one of claims 1 to 6, wherein the memory mapping circuit is configured to perform the plurality of management iterations while the processing unit is executing the software program.

8. Accessing one or more of the aforementioned statistical counters means Accessing at least one of the low access counter and the high access counter, Performing another analysis that includes at least one of the low-access counter and the high-access counter, Accessing at least one range access counter in accordance with other results of the aforementioned other analysis, The apparatus according to any one of claims 2 to 7, including the apparatus described in any one of claims 2 to 7.

9. The apparatus according to any one of claims 3 to 8, wherein the memory mapping circuit is further configured to set at least one of a low access threshold and a high access threshold in the at least one memory tracking circuit.

10. The apparatus according to claim 9, wherein the memory mapping circuit sets at least one of the low access threshold and the high access threshold in accordance with further results of further analysis comprising one or more statistical counters in the at least one memory tracking circuit.

11. The processing unit executes the software program by running an operating system having an operating system page size for memory management. At least one of the plurality of memory address ranges addresses an amount of memory different from the operating system page size. The apparatus according to any one of claims 1 to 10.

12. A method for managing memory in a device for running one or more software programs, In each of the multiple management iterations, a memory mapping circuit is connected to a processing unit and at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range among a plurality of memory address ranges of the processing unit by the memory mapping circuit. The processing unit accesses one or more statistical counters collected while executing at least one of the one or more software programs, Steps include: generating a mapping between a first memory address range and a second memory address range among the plurality of memory address ranges, based on the analysis of one or more statistical counters, on the condition that the first memory address range and the second memory address range are identified; In response to receiving at least one memory access command from the processing unit, which includes a first memory address within the first memory address range, the first memory address in the at least one memory access command is replaced with a second memory address within the second memory address range according to the mapping. A method that includes this.

13. A software program product for memory management, Non-temporary computer-readable storage medium and A first program instruction, In each of the multiple management iterations, a memory mapping circuit is connected to a processing unit and at least one memory component connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range among a plurality of memory address ranges of the processing unit by the memory mapping circuit. The processing unit accesses one or more of the statistical counters collected while executing at least one of the one or more software programs, and In accordance with the analysis of one or more statistical counters, a mapping is generated between a first memory address range and a second memory address range among the plurality of memory address ranges, provided that the first memory address range and the second memory address range are identified. The first program instruction for, A second program instruction, in response to receiving from the processing unit at least one memory access command including a first memory address within the first memory address range, the second program instruction replaces the first memory address with a second memory address within the second memory address range in the at least one memory access command according to the mapping, Equipped with, The first and second program instructions are executed by at least one computerized processor from the non-temporary computer-readable storage medium. Software program products.

Images