Electronic device and its control method and system-on-chip

Abstract

The present invention provides an electronic device with increased operational stability, a control method for the electronic device, and a system-on-a-chip. [Solution] The electronic device according to the present invention comprises a battery, a charging circuit, a power management module, and a processor operatively connected to the battery and the charging circuit and including a central processing unit (CPU) and a plurality of blocks (IP blocks). The charging circuit is configured to send a first overcurrent warning signal to the processor when the current value flowing through the entire electronic device is greater than or equal to a first threshold current, and the power management module is configured to send a second overcurrent warning signal to the processor when the current value flowing through the entire electronic device is greater than or equal to a second threshold current. When at least one of the first overcurrent warning signal or the second overcurrent warning signal is received, the processor is configured to reduce at least one of a plurality of operating clock frequencies set for each of the CPU and the plurality of blocks.

Description

Technical Field

[0001] Various embodiments disclosed in the present invention relate to an electronic device, a control method thereof, and a system-on-chip.

Background Art

[0002] Functions for protecting an electronic device are applied to an electronic device such as a portable terminal. When a current equal to or greater than a specified value flows through the electronic device or the voltage of the battery of the electronic device is equal to or less than a specified value, the circuit and / or battery of the electronic device may be damaged. To protect the circuit and / or battery of the electronic device, an over current protection (OCP) function and / or a sudden momentary power loss (SMPL) reset function can be applied.

[0003] The over current protection function includes a function of cutting off the power supplied to the electronic device and turning off the electronic device when a current equal to or greater than a specified value flows through the electronic device. The SMPL reset function includes a power-off function of turning off the electronic device when the voltage of the battery of the electronic device is equal to or less than a specified value.

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the over current protection function or the SMPL reset function is executed during the operation of the electronic device, the power may be cut off during the operation of the electronic device, which may cause inconvenience to the user during the use of the electronic device. In order to reduce the phenomenon that the power is cut off during the operation of the electronic device, it may include a function for reducing the execution of the over current protection function and / or a function for reducing the execution of the SMPL reset function. If an electronic device controls only the central processing unit through functions to reduce the execution of overcurrent protection and / or SMPL reset functions, the execution of overcurrent protection or SMPL reset functions by other modules within the processor and / or other modules outside the processor may cause the electronic device to lose power and its usability to decrease.

[0005] The various embodiments disclosed in this invention provide an electronic device, a control method for the electronic device, and a system-on-a-chip that increase operational stability by controlling various modules of the electronic device to prevent the electronic device from turning off due to the execution of an overcurrent protection function and / or an SMPL reset function. [Means for solving the problem]

[0006] An electronic device according to one embodiment of the present invention comprises a battery, a charging circuit, a power management module, and a processor operationally connected to the battery and the charging circuit, including a central processing unit (hereinafter referred to as CPU) and a plurality of blocks (IP blocks), wherein the charging circuit is configured to transmit a first overcurrent warning signal to the processor when the current value flowing through the entire electronic device is greater than or equal to a first threshold current, and the power management module is configured to transmit a second overcurrent warning signal to the processor when the current value flowing through the entire electronic device is greater than or equal to a second threshold current, and when at least one of the first overcurrent warning signal or the second overcurrent warning signal is received, the processor is configured to reduce at least one of a plurality of operating clock frequencies set for each of the CPU and the plurality of blocks.

[0007] Furthermore, a System on Chip (SoC) according to one embodiment of the present invention has a processor including a central processing unit (CPU) and a plurality of blocks (IP blocks), wherein the processor is configured to receive a first overcurrent warning signal when the current level of the entire electronic device is equal to or greater than a first threshold current, and to receive a second overcurrent warning signal when the current level of the entire electronic device is equal to or greater than a second threshold current, and the processor is configured to perform at least one operation to reduce at least one of a plurality of operating clock frequencies set for each of the CPU and the plurality of blocks based on at least one of the first overcurrent warning signal or the second overcurrent warning signal.

[0008] Furthermore, a control method for an electronic device according to one embodiment of the present invention is characterized by comprising the steps of: the charging circuit of the electronic device transmitting a first overcurrent warning signal to a processor including the central processing unit (hereinafter referred to as CPU) of the electronic device when the current consumption of the electronic device is equal to or greater than a first threshold current; the power management module of the electronic device transmitting a second overcurrent warning signal to the processor when the current value flowing through the electronic device is equal to or greater than a second threshold current; the processor receiving at least one of the first overcurrent warning signal or the second overcurrent warning signal; and the processor reducing at least one of a plurality of operating clock frequencies set for each of the CPU and a plurality of blocks included in the processor. [Effects of the Invention]

[0009] According to the embodiments disclosed in the present invention, the drop in the battery voltage level can be reduced, keeping the battery voltage level above the value at which an SMPL reset occurs, thereby reducing the frequency of SMPL resets. By doing so, the phenomenon of electronic devices turning off during use can be reduced, and the operational stability of the electronic devices can be increased. Furthermore, according to the embodiments disclosed in the present invention, SMPL resets can be reduced even when the battery voltage is maintained below a specified value in a low-temperature environment.

[0010] Furthermore, according to the embodiments disclosed in the present invention, SMPL resets can also be reduced when the voltage drop increases due to an increase in current flowing to other blocks and / or other components of electronic devices such as displays within the processor, causing the battery voltage to fall below a specified value.

[0011] Furthermore, the present invention can provide various other effects that can be directly or indirectly understood through it. [Brief explanation of the drawing]

[0012] [Figure 1] This is a block diagram of an electronic device in a network environment according to an embodiment of the present invention. [Figure 2a] This is a block diagram of an electronic device according to one embodiment of the present invention. [Figure 2b] This is a block diagram of an electronic device according to another embodiment of the present invention. [Figure 3a] This is a block diagram showing a charging circuit, power management module, first logic circuit, and processor for an electronic device according to one embodiment of the present invention. [Figure 3b] This is a block diagram showing a charging circuit, power management module, first logic circuit, and processor for an electronic device according to one embodiment of the present invention. [Figure 4] This waveform diagram shows the overcurrent and overcurrent warning signals according to one embodiment of the present invention. [Figure 5a] This is a block diagram of an electronic device according to one embodiment of the present invention. [Figure 5b] This is a block diagram of an electronic device according to one embodiment of the present invention. [Figure 6] This is a flowchart illustrating a control method for an electronic device according to one embodiment of the present invention.

[0013] In connection with the description of the drawings, the same or similar reference numerals can be used for the same or similar components.

Best Mode for Carrying Out the Invention

[0014] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. However, it should not be construed as limiting the present invention to specific embodiments, but should be understood to include various modifications, equivalents, and / or alternatives of the embodiments of the present invention.

[0015] FIG. 1 is a block diagram of an electronic device 101 within a network environment 100 according to an embodiment of the present invention. Referring to FIG. 1, in the network environment 100, the electronic device 101 communicates with the electronic device 102 via a first network 198 (e.g., a short-range wireless communication network), or communicates with the electronic device 104 or the server 108 via a second network 199 (e.g., a long-range wireless communication network). According to one embodiment, the electronic device 101 communicates with the electronic device 104 via the server 108. According to one embodiment, the electronic device 101 includes a processor 120, a memory 130, an input module 150, an acoustic output module 155, a display module 160, an audio module 170, a sensor module 176, an interface 177, a connection terminal 178, a haptic module 179, a camera module 180, a power management module 188, a battery 189, a communication module 190, a subscriber identification module 196, or an antenna module 197. In one embodiment, at least one of those components (e.g., the connection terminal 178) may be omitted from the electronic device 101, and one or more other components may be added. In one embodiment, some of those components (e.g., sensor module 176, camera module 180, or antenna module 197) may be integrated into one component (e.g., display module 160).

[0016] Processor 120 can execute software (e.g., program 140), for example, to control at least one other component (e.g., hardware or software component) of electronic device 101 connected to processor 120, and perform various data processing or operations. According to one embodiment, as at least part of data processing or operations, processor 120 stores instructions or data received from other components (e.g., sensor module 176 or communication module 190) in volatile memory 132, processes the instructions or data stored in volatile memory 132, and stores the result data in non-volatile memory 134.

[0017] According to one embodiment, processor 120 may include main processor 121 (e.g., a central processing unit or an application processor), or a sub-processor 123 (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together with it. For example, when electronic device 101 includes main processor 121 and sub-processor 123, sub-processor 123 may use less power than main processor 121 or may be set to be specialized for a specified function. Sub-processor 123 may be implemented separately from or as part of main processor 121.

[0018] The subprocessor 123 controls, for example, at least a portion of the functions or states related to at least one component of the electronic device 101 (e.g., display module 160, sensor module 176, or communication module 190) on behalf of the main processor 121 when the main processor 121 is inactive (e.g., in sleep mode), or together with the main processor 121 when the main processor 121 is active (e.g., running an application). According to one embodiment, the subprocessor 123 (e.g., an image signal processor or a communication processor) may be implemented as part of other functionally related components (e.g., a camera module 180 or a communication module 190). According to one embodiment, the subprocessor 123 (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models.

[0019] Artificial intelligence models can be generated through machine learning. Such learning may be performed, for example, on the electronic device 101 on which the artificial intelligence is run, or on another server (e.g., server 108). Learning algorithms include, but are not limited to, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. Artificial intelligence models can include multiple layers of artificial neural networks. Artificial neural networks may be deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), restricted Boltzmann machines (RBM), deep belief networks (DBN), bidirectional recurrent deep neural networks (BRDNN), deep Q-networks, or any combination of two or more of these, but are not limited to the examples mentioned above. Artificial intelligence models may include software structures in addition to or as an alternative to hardware structures.

[0020] The memory 130 stores various data used by at least one component of the electronic device 101 (e.g., the processor 120 or the sensor module 176). The data includes, for example, input or output data relating to software (e.g., program 140) and its associated instructions. Memory 130 may include volatile memory 132 or non-volatile memory 134.

[0021] The program 140 is stored as software in memory 130 and may include, for example, an operating system 142, middleware 144, or an application 146.

[0022] The input module 150 receives instructions or data used by the components of the electronic device 101 (e.g., the processor 120) from outside the electronic device 101 (e.g., a user). The input module 150 may include, for example, a microphone, mouse, keyboard, keys (e.g., buttons), or digital pen (e.g., stylus pen).

[0023] The acoustic output module 155 outputs an acoustic signal to the outside of the electronic device 101. The audio output module 155 may include, for example, a speaker or a receiver. Speakers are used for general purposes such as multimedia playback or playback of recordings. The receiver is used to receive incoming phone calls. According to one embodiment, the receiver may be implemented separately from or as part of the speaker.

[0024] The display module 160 provides information visually to an external party (e.g., a user) outside of the electronic device 101. The display module 160 includes, for example, a display, a hologram device, or a projector, and a control circuit for controlling said device. According to one embodiment, the display module 160 may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the strength of the force generated by a touch.

[0025] Audio module 170 converts sound into electrical signals, or vice versa, converts electrical signals into sound. According to one embodiment, the audio module 170 acquires sound via the input module 150, or outputs sound via the sound output module 155, or via an external electronic device (e.g., electronic device 102) (e.g., speaker or headphones) directly or wirelessly connected to the electronic device 101.

[0026] The sensor module 176 detects the operating state of the electronic device 101 (e.g., power or temperature) or the external environmental state (e.g., user status), and generates an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module 176 may include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0027] Interface 177 supports one or more specified protocols that can be used to connect electronic device 101 to an external electronic device (e.g., electronic device 102) directly or wirelessly. According to one embodiment, the interface 177 may include, for example, an HDMI® (high definition multimedia interface), a USB (universal serial bus) interface, an SD card interface, or an audio interface.

[0028] The connection terminal 178 includes a connector through which the electronic device 101 can be physically connected to an external electronic device (e.g., electronic device 102). According to one embodiment, the connection terminal 178 may include, for example, an HDMI® connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0029] The haptic module 179 converts electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that the user can perceive through touch or kinesthetic sense. According to one embodiment, the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0030] The camera module 180 captures both still and moving images. According to one embodiment, the camera module 180 may include one or more lenses, an image sensor, an image signal processor, or a flash.

[0031] The power management module 188 manages the power supplied to the electronic device 101. According to one embodiment, the power management module 188 can be implemented, for example, as at least part of a PMIC (power management integrated circuit).

[0032] The battery 189 supplies power to at least one component of the electronic device 101. According to one embodiment, the battery 189 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0033] The communication module 190 supports the establishment of a direct (e.g., wired) or wireless communication channel between the electronic device 101 and an external electronic device (e.g., electronic device 102, electronic device 104, or server 108), and the execution of communication over the established communication channel. The communication module 190 operates independently of the processor 120 (e.g., the application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module 190 may include a wireless communication module 192 (e.g., a cellular communication module, a short-range wireless communication module, or a GNSS (global navigation satellite system) communication module) or a wired communication module 194 (e.g., a LAN (local area network) communication module or a power line communication module).

[0034] Of these communication modules, the relevant communication module communicates with an external electronic device 104 via a first network 198 (e.g., a short-range communication network such as Bluetooth®, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network 199 (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., LAN or WAN)). Such various communication modules may be integrated into a single component (e.g., a single chip), or they may be implemented using multiple separate components (e.g., multiple chips). The wireless communication module 192 uses subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 196 to verify or authenticate the electronic device 101 within a communication network such as the first network 198 or the second network 199.

[0035] The wireless communication module 192 supports 5G networks and next-generation communication technologies beyond 4G networks, such as NR access technology (new radio access technology). NR access technology supports high-speed transmission of large amounts of data (eMBB (enhanced mobile broadband)), minimizing terminal power consumption and access from multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module 192 supports high-frequency bands (e.g., mmWave bands) to achieve, for example, a high data transmission rate.

[0036] The wireless communication module 192 supports various technologies to ensure performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, or large-scale antennas. The wireless communication module 192 supports various requirements specified in the electronic device 101, external electronic devices (e.g., electronic device 104), or network system (e.g., second network 199). According to one embodiment, the wireless communication module 192 supports a peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mMTC, or U-plane latency (e.g., 0.5 ms or less for both downlink (DL) and uplink (UL), or 1 ms or less for round trip) for realizing URLLC.

[0037] The antenna module 197 transmits or receives signals or power to an external device (e.g., an external electronic device). According to one embodiment, the antenna module 197 may include an antenna that includes a radiator consisting of a conductor or conductive pattern formed on a substrate (e.g., PCB). According to one embodiment, the antenna module 197 may include multiple antennas (e.g., an array antenna). In that case, at least one antenna suitable for the communication method used in the communication network, such as the first network 198 or the second network 199, can be selected from multiple antennas, for example, by the communication module 190. Signals or power are transmitted or received between the communication module 190 and an external electronic device via at least one selected antenna. According to one embodiment, in addition to the radiator, other components (e.g., an RFIC (radio frequency integrated circuit)) may be further formed as part of the antenna module 197.

[0038] According to one embodiment, the antenna module 197 forms an mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC located on or adjacent to a first surface (e.g., the bottom surface) of the printed circuit board capable of supporting a specified high-frequency band (e.g., the mmWave band), and a plurality of antennas (e.g., array antennas) located on or adjacent to a second surface (e.g., the top or side surface) of the printed circuit board capable of transmitting or receiving signals in the specified high-frequency band.

[0039] At least some of the above components are connected to each other by a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., instructions or data) with each other.

[0040] According to one embodiment, commands or data are transmitted or received between the electronic device 101 and an external electronic device 104 via a server 108 connected to a second network 199. Each of the external electronic devices (102 or 104) may be of the same type as electronic device 101, or it may be of a different type. According to one embodiment, all or part of the operations performed by the electronic device 101 may be performed by one or more external electronic devices (102, 104, and 108). For example, if electronic device 101 performs a certain function or service automatically or in response to a request from a user or another device, instead of performing the function or service itself, or in addition to doing so, electronic device 101 may request one or more external electronic devices to perform at least a part of that function or service. One or more external electronic devices that receive a request perform at least a portion of the requested function or service, or any further function or service related to the request, and transmit the result of the performance to the electronic device 101. The electronic device 101 provides the above results either as is or after further processing, as at least part of the response to the request.

[0041] To achieve this, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technologies can be used. The electronic device 101 provides, for example, an ultra-low latency service using distributed computing or mobile edge computing. In other embodiments, the external electronic device 104 may include an IoT (Internet of Things) device. Server 108 may be an intelligent server using machine learning and / or neural networks. According to one embodiment, an external electronic device 104 or server 108 may be included within the second network 199. The electronic device 101 can be applied to intelligent services (e.g., smart homes, smart cities, smart cars, or healthcare) based on 5G communication technology and IoT-related technologies.

[0042] Figure 2a is a block diagram of an electronic device (e.g., electronic device 101 in Figure 1) according to one embodiment of the present invention. An electronic device 101 according to one embodiment includes a battery 189, a charging circuit 210, a power management module 188, and a processor 120. In one embodiment, the charging circuit 210 and the power management module 188 may be composed of different chips. In other embodiments, the charging circuit 210 and the power management module 188 may be comprised of a single chip.

[0043] In one embodiment, the battery 189 supplies current to the charging circuit 210. The charging circuit 210 includes a circuit for charging the battery 189. The charging circuit 210 includes an intermediate frequency power management integrated circuit (IF PMIC). In one embodiment, the charging circuit 210 receives current from the battery 189. The charging circuit 210 measures the magnitude of the received current. The charging circuit 210 supplies current to the power management module 188. The charging circuit 210 controls the magnitude and / or output timing of the received current and sends it to the power management module 188.

[0044] In one embodiment, the charging circuit 210 transmits a first overcurrent warning signal to the first logic circuit 230. The first overcurrent warning signal is a signal generated by the charging circuit 210 to warn that a first threshold current is flowing in the electronic device 101 that enables the overcurrent protection (OCP) function to be performed. The overcurrent protection function is a function that shuts off the power supplied to the electronic device and turns off the electronic device when the current flowing through the electronic device 101 is equal to or greater than the first threshold current. The first threshold current can be approximately 6.2A. The first overcurrent warning signal is commonly referred to as the "OCP_WARN_Charger" signal. The charging circuit 210 performs an overcurrent protection function if the magnitude of the total current flowing through the electronic device 101 is greater than or equal to the first threshold current for a first threshold time. The first threshold time can be approximately 100 ms. The charging circuit 210 outputs a first overcurrent warning signal to the power management module 188 if the total current flowing through the electronic device 101 is greater than or equal to the first threshold current for a second threshold time. The second threshold time is a shorter time than the first threshold time. For example, the second threshold time could be approximately 3 ms.

[0045] In one embodiment, the power management module 188 supplies current to the processor 120. The power management module 188 includes an application processor power management integrated circuit (AP PMIC). The power management module 188 supplies the current necessary for the processor 120 to operate.

[0046] In one embodiment, the power management module 188 supplies current to the display module 160. The power management module 188 supplies the current necessary for the display module 160 to operate. The power management module 188 supplies drive current to drive the pixels arranged in the display module 160 in order for the display module 160 to display a screen.

[0047] In one embodiment, the power management module 188 supplies current to the power transmission module 220. The power transmission module 220 transmits power to external devices such as other electronic devices. For example, the power transmission module 220 performs a power sharing function. For example, the power transmission module 220 includes an on-the-go (OTG) connection. The power management module 188 supplies the current necessary for the power transmission module 220 to operate. The power management module 188 supplies a charging current to the power transmission module 220 for charging external devices such as other electronic devices.

[0048] In one embodiment, the power management module 188 transmits a second overcurrent warning signal to the processor 120. The second overcurrent warning signal is a signal generated by the power management module 188 to warn that the conditions for performing the overcurrent protection function in the electronic device 101 have been met. The second overcurrent warning signal is commonly referred to as the "OCP_WARN_CPU Buck" signal. The power management module 188 outputs a second overcurrent warning signal if the magnitude of the total current flowing through the electronic device 101 is greater than or equal to the second threshold current. The second threshold current is different from the first threshold current. For example, the second threshold current has a higher value than the first threshold current. The first overcurrent warning signal is the current relative to the voltage of the battery 189, and the second overcurrent warning signal is the current at the buck voltage of the central processing unit. Therefore, in terms of power, the power due to the first threshold current is higher than the power due to the second threshold current. The power management module 188 outputs a second overcurrent warning signal if the total current flowing through the electronic device 101 is greater than or equal to the second threshold current for a third threshold time. The third threshold time is different from the first and second threshold times.

[0049] In one embodiment, the power management module 188 transmits a reset warning signal to the first logic circuit 230. The reset warning signal is a signal generated by the power management module 188 to warn that the conditions for performing the SMPL (sudden momentary power loss) reset function in the electronic device 101 are approaching. The SMPL reset function is one of the power-off functions that turns off the electronic device 101 when the voltage of the battery 189 of the electronic device 101 is below a first threshold voltage. The reset warning signal is commonly referred to as the "SMPL_WARN" signal. The power management module 188 determines that the voltage of the battery 189 is below the second threshold voltage if the voltage of the power management module 188 is below the second threshold voltage, and outputs a reset warning signal. The second threshold voltage is higher than the first threshold voltage. Therefore, the SMPL reset function is prevented from being executed by outputting a reset warning signal when the voltage of battery 189 reaches the second threshold voltage before it reaches the first threshold voltage.

[0050] In one embodiment, the first logic circuit 230 receives a first overcurrent warning signal and a reset warning signal. The first logic circuit 230 includes logic gates for selectively processing a first overcurrent warning signal and a reset warning signal, or for processing them together. For example, the first logic circuit 230 could be an OR gate. As another example, the first logic circuit 230 could be an AND gate. The first logic circuit 230 generates a warning signal based on the first overcurrent warning signal and the reset warning signal. The warning signal is a signal that warns that the power to the electronic device 101 may be cut off in order to protect the electronic device 101. The first logic circuit 230 transmits a warning signal to the processor 120.

[0051] In one embodiment, the processor 120 controls the operation of a plurality of blocks (IP (intellectual property) blocks) contained within the processor 120. Multiple blocks (IP blocks) include at least a portion of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), and a bus (BUS). When the processor 120 receives a warning signal or a second overcurrent warning signal, it controls the drive frequency of the clocks that drive each of the multiple blocks. For example, when the processor 120 receives a warning signal or a second overcurrent warning signal, it reduces the operating clock frequency set by dynamic voltage frequency scaling (DVFS) for each of the multiple blocks.

[0052] In one embodiment, the processor 120 controls the operation of the display module 160. When the processor 120 receives a warning signal or a second overcurrent warning signal, it controls the current supplied to the display module 160. For example, when the processor 120 receives a warning signal or a second overcurrent warning signal, it reduces the brightness of the display module 160 screen and decreases the current supplied to the display module 160.

[0053] In one embodiment, the processor 120 controls the operation of the power transmission module 220. When the processor 120 receives a warning signal or a second overcurrent warning signal, it controls the current supplied to the power transmission module 220. For example, when the processor 120 receives a warning signal or a second overcurrent warning signal, it reduces the rate at which the power transmission module 220 charges the external device, thereby reducing the current supplied to the power transmission module 220.

[0054] The charging circuit 210 according to the embodiment disclosed in this invention transmits a first overcurrent warning signal to the first logic circuit 230. The processor 120 according to the embodiment disclosed in the present invention receives a warning signal from the first logic circuit 230 based on a first overcurrent warning signal and a reset warning signal. Therefore, the processor 120 according to the embodiment disclosed in the present invention can prevent the execution of an overcurrent protection function or an SMPL reset function by at least one of the multiple blocks included in the processor 120. Furthermore, the processor 120 according to the embodiment disclosed in this invention can prevent other modules, such as the external display module 160 or power transmission module 220, from executing an overcurrent protection function or an SMPL reset function. Furthermore, the processor 120 according to the embodiments disclosed in this invention can prevent the overcurrent protection function or the SMPL reset function from being executed in the electronic device 101 due to any other factors.

[0055] A system on a chip (SoC) including a processor 120 according to an embodiment of the present invention includes a dedicated pin designated to receive a warning signal based on the reception of a reset warning signal when the current level of the entire electronic device 101 is greater than or equal to a first threshold current and the voltage level of the electronic device 101 is less than or equal to a second threshold voltage. The processor 120 is configured to perform at least one of the following actions in response to the first overcurrent warning signal and the reset warning signal: reducing the operating clock frequency of the central processing unit included in the processor 120, reducing the brightness of the display 160 controlled by the processor 120, and reducing the charging current of the power transmission module 220 controlled by the processor 120.

[0056] Figure 2b is a block diagram 250 of an electronic device according to another embodiment of the present invention (e.g., electronic device 101 in Figure 1). An electronic device 101 according to another embodiment of the present invention includes a battery 189, a charging circuit 210, a power management module 188, and a processor 120. The battery 189, charging circuit 210, and power management module 188 of the electronic device 101 in other embodiments may be substantially identical to the battery 189, charging circuit 210, and power management module 188 of the electronic device 101 in one embodiment described with reference to Figure 2a.

[0057] In one embodiment, the processor 120 includes a first general-purpose input / output (GPIO) pin 251 and a second general-purpose input / output pin 252. The processor 120 receives the first overcurrent warning signal via the first general-purpose input / output pin 251. The processor 120 receives a reset warning signal via the second general-purpose input / output pin 252.

[0058] In one embodiment, the processor 120 controls the operation of at least one of a plurality of blocks contained within the processor 120 based on at least one of a first overcurrent warning signal and a reset warning signal. For example, when the processor 120 receives a first overcurrent warning signal via the first general-purpose input / output pin 251, it controls at least one of several operating clock frequencies set for each of the multiple blocks.

[0059] In one embodiment, the processor 120 controls the operation of the display module 160 based on at least one of the first overcurrent warning signal and the reset warning signal. For example, when the processor 120 receives a first overcurrent warning signal via the first general-purpose input / output pin 251, it reduces the brightness of the display module 160 screen. The processor 120 controls the operation of the power transmission module 220 based on at least one of the first overcurrent warning signal and the reset warning signal. For example, when the processor 120 receives a first overcurrent warning signal via the first general-purpose input / output pin 251, it reduces the rate at which the power transmission module 220 charges the external device.

[0060] Figure 3a is a block diagram 300 showing a charging circuit 210, a power management module 188, a first logic circuit 230, and a processor 120 of an electronic device (e.g., electronic device 101 in Figure 1) according to one embodiment of the present invention.

[0061] In one embodiment, the charging circuit 210 receives current from the battery 189. The charging circuit 210 transmits current to the power management module 188. The charging circuit 210 detects the current flowing through the entire electronic device 101. A charging circuit 210 according to one embodiment includes a switch 311, a first current detection circuit 312, a first timer 313, a second logic circuit 314, and a first pin 315.

[0062] In one embodiment, the switch 311 receives current from the battery 189. Switch 311 is a QBAT FET (Battery Q-point Field Effect Transistor), which is a field-effect transistor that sets the operating point (Q-point) at which it begins receiving current from the battery 189. Switch 311 receives from pin 1 315 whether the overcurrent protection function is disabled or enabled. Switch 311 closes when the overcurrent protection function is disabled. When the switch 311 is closed, it transmits the current from the battery 189 to the first current detection circuit 312. Switch 311 is switched to the open state when the overcurrent protection function is enabled. When switch 311 is open, it blocks the current flowing in from battery 189.

[0063] In one embodiment, the first current detection circuit 312 receives current from the switch 311. The first current detection circuit 312 detects the magnitude of the current from the switch 311. The first current detection circuit 312 transmits the current from the switch 311 to the power management module 188. The first current detection circuit 312 transmits a first notification signal to the second logic circuit 314 if the magnitude of the current from the switch 311 is equal to or greater than the first threshold current. The first threshold current can be approximately 6.2A.

[0064] In one embodiment, the first timer 313 measures the elapsed time. The first timer 313 measures the time during which the magnitude of the current received by the first current detection circuit 312 is equal to or greater than the first threshold current. The first timer 313 transmits a second notification signal to the second logic circuit 314 if the magnitude of the current received by the first current detection circuit 312 is greater than or equal to the first threshold current for a first threshold time. The first threshold time can be approximately 100 ms. The first timer 313 transmits a third notification signal to the second logic circuit 314 if the magnitude of the current received by the first current detection circuit 312 is greater than or equal to the first threshold current for a second threshold time. The second threshold time can be approximately 3 ms.

[0065] In one embodiment, the second logic circuit 314 receives a first notification signal from the first current detection circuit 312. The second logic circuit 314 receives the second notification signal or the third notification signal from the first timer 313. The second logic circuit 314 includes a logic gate for processing both the first notification signal and the second or third notification signal. For example, the second logic circuit 314 could be a logic AND gate. The second logic circuit 314 performs an overcurrent protection function based on the first notification signal and the second notification signal. The second logic circuit 314 generates a first overcurrent warning signal based on the first notification signal and the third notification signal.

[0066] In one embodiment, the second logic circuit 314 performs an overcurrent protection function based on the first notification signal and the second notification signal. The overcurrent protection function is transmitted to switch 311. For example, the second logic circuit 314 performs an overcurrent protection function if both the received first notification signal and the second notification signal are in the enable state. In one embodiment, the second logic circuit 314 transmits a first overcurrent warning signal based on the first notification signal and / or the third notification signal to the first pin 315. For example, the second logic circuit 314 transmits the first overcurrent warning signal to the first pin 315 if both the received first notification signal and the third notification signal are in the enabled state. In one embodiment, the second logic circuit 314 may consist of a hardware circuit that transmits an active-low signal to the first pin 315, which is a dedicated pin for connecting the charging circuit 210 and the processor 120.

[0067] In one embodiment, the first pin 315 receives a first overcurrent warning signal from the second logic circuit 314. The first pin 315 receives a first overcurrent warning signal based on the first notification signal and / or the third notification signal. The first pin 315 transmits the first overcurrent warning signal to the first logic circuit 230. The first pin 315 is designated to transmit a warning signal to the processor 120 if the current flowing through the entire electronic device 101 is greater than or equal to the first threshold current for a second threshold time that is shorter than the first threshold time for which the overcurrent protection function is activated. The first pin 315 is designated to transmit a first overcurrent warning signal to the first logic circuit 230 connected to the processor 120 when the current flowing through the entire electronic device 101 is greater than or equal to a first threshold current.

[0068] In one embodiment, the power management module 188 receives a voltage from the battery 189. The power management module 188 receives current from the charging circuit 210. The power management module 188 transmits voltage and current to the processor 120. The power management module 188 controls the voltage and current transmitted to the processor 120. A power management module 188 according to one embodiment includes a voltage detection circuit 321, a second current detection circuit 322, a second pin 323, and a third pin 324.

[0069] In one embodiment, the voltage detection circuit 321 receives a voltage from the battery 189. The voltage detection circuit 321 generates a reset warning signal if the received voltage of the battery 189 is below the second threshold voltage. The second threshold voltage is higher than the first threshold voltage at which the SMPL reset function is executed. The reset warning signal is a signal that prevents the execution of the SMPL reset function by indicating that the voltage of battery 189 is approaching the first threshold voltage at which the SMPL reset function is executed. The voltage detection circuit 321 transmits a reset warning signal to the first logic circuit 230 via the second pin 323.

[0070] In one embodiment, the second current detection circuit 322 receives current from the first current detection circuit 312. The second current detection circuit 322 transmits the received current to the processor 120. In one embodiment, the second current detection circuit 322 generates a second overcurrent warning signal if the received current is greater than or equal to the first threshold current for a third threshold time. The first threshold current is the value at which the overcurrent protection function is activated. The second overcurrent warning signal is a signal that notifies that the current flowing through the entire electronic device 101 has reached the first threshold current at which the overcurrent protection function is activated, thereby preventing the overcurrent protection function from being activated. The second current detection circuit 322 transmits a second overcurrent warning signal to the processor 120 via the third pin 324.

[0071] In one embodiment, the second pin 323 receives a reset warning signal from the voltage detection circuit 321. The second pin 323 transmits a reset warning signal to the first logic circuit 230. In one embodiment, the third pin 324 receives a second overcurrent warning signal from the second current detection circuit 322. The third pin 324 transmits the second overcurrent warning signal to the processor 120.

[0072] In one embodiment, the power management module 188 includes a second pin 323, which is configured to transmit a signal to the processor 120 indicating that the voltage level of the electronic device 101 is below a second threshold voltage. The power management module 188 includes a third pin 324, which is configured to transmit a signal to the processor 120 indicating that the current flowing through the electronic device 101 is greater than or equal to a first threshold current.

[0073] In one embodiment, the first logic circuit 230 receives a first overcurrent warning signal from the charging circuit 210. The first logic circuit 230 receives the first overcurrent warning signal from the first pin 315. In one embodiment, the first logic circuit 230 receives a reset warning signal from the power management module 188. The first logic circuit 230 receives a reset warning signal from the second pin 323.

[0074] In one embodiment, the first logic circuit 230 generates a warning signal based on the first overcurrent warning signal and the reset warning signal. For example, the first logic circuit 230 generates a warning signal when at least one of the first overcurrent warning signal and the reset warning signal becomes enabled or active. The first logic circuit 230 transmits the generated warning signal to the processor 120.

[0075] In one embodiment, the processor 120 acquires a warning signal from the first logic circuit 230. The processor 120 receives a second overcurrent warning signal from the power management module 188. The processor 120 controls the overall operation of the electronic device 101 based on the warning signal and the second overcurrent warning signal. The processor 120 includes at least one pin dedicated to receiving signals from the charging circuit 210 and the power management module 188 corresponding to current or voltage levels. A processor 120 according to one embodiment includes a fourth pin 331, a fifth pin 332, a signal acquisition unit 333, a clock control unit 334, a central processing unit (CPU) 335, a first block (IP block) 336, a second block 337, and a third block 338.

[0076] In one embodiment, the fourth pin 331 receives a warning signal from the first logic circuit 230. The fourth pin 331 transmits a warning signal to the signal acquisition unit 333. In one embodiment, the fifth pin 332 receives a second overcurrent warning signal from the power management module 188. Pin 5 331 receives the second overcurrent warning signal from the second current detection circuit 332. The fifth pin 332 transmits the second overcurrent warning signal to the signal acquisition unit 333.

[0077] In one embodiment, the signal acquisition unit 333 acquires a warning signal and / or a second overcurrent warning signal. The signal acquisition unit 333 acquires a warning signal from the fourth pin 331. The signal acquisition unit 333 acquires the second overcurrent warning signal from the fifth pin 332. When the signal acquisition unit 333 receives at least one of the warning signal and the second overcurrent warning signal, it transmits a notification signal to the clock control unit 334.

[0078] In one embodiment, the clock control unit 334 controls the clock signals supplied for the operation of the central processing unit 335, the first block 336, the second block 337, and / or the third block 338. The clock control unit 334 sets the clock signal supplied to the central processing unit 335 to the first clock. The clock control unit 334 sets the clock signal supplied to the first block 336 to the second clock. The clock control unit 334 sets the clock signal supplied to the second block 337 to the third clock. The clock control unit 334 sets the clock signal supplied to the third block 338 to the fourth clock.

[0079] In one embodiment, the clock control unit 334 receives a notification signal from the signal acquisition unit 333. When the clock control unit 334 receives a notification signal, it controls the operating clock frequency of the first clock, the operating clock frequency of the second clock, the operating clock frequency of the third clock, and / or the operating clock frequency of the fourth clock. The operating clock frequency is the operating frequency value set by dynamic voltage frequency scaling (DVFS) within the frequency range of the clock signal. The operating clock frequency is the operating frequency value of the dynamic voltage frequency scaling policy applied to the central processing unit and / or block to which the clock signal is supplied. The operating clock frequency may be a frequency value set separately from the dynamic voltage frequency scaling itself. In one embodiment, the clock control unit 334 is controlled by the central processing unit 335. Control of the clock control unit 334 is performed by the interrupt handler of the central processing unit 335.

[0080] In one embodiment, when the clock control unit 334 receives a notification signal, it reduces the clock frequency of the first clock, which is a clock signal supplied to the central processing unit 335. When the clock control unit 334 receives a notification signal, it reduces the clock frequency of the first clock by a value stored in a register inside the processor 120 or by a set percentage. For example, when the clock control unit 334 receives a notification signal, it reduces the clock frequency of the first clock by half. As another example, when the clock control unit 334 receives a notification signal, it may reduce the clock frequency of the first clock to 1 / 3, 2 / 3, 1 / 4, 3 / 4, 1 / 5, 2 / 5, 3 / 5, or 4 / 5. In one embodiment, when the clock control unit 334 receives a notification signal, it reduces at least one of the operating clock frequencies of the second clock of the first block 336, the third clock of the second block 337, and the fourth clock of the third block 338.

[0081] In one embodiment, the central processing unit 335 controls the clock control unit 334 using an interrupt handler. The central processing unit 240 sets each of the multiple operating clock frequencies by dynamic voltage frequency scaling. The central processing unit 335 reduces at least one of the operating clock frequencies of the first clock of the central processing unit 335, the second clock of the first block 336, the third clock of the second block 337, and the fourth clock of the third block 338. In one embodiment, the central processing unit 335 reduces at least one of the operating clock frequencies by a value or a set percentage stored in a register inside the processor 120. For example, the central processing unit 335 reduces at least one of the operating clock frequencies by half.

[0082] In one embodiment, the central processing unit 335 reduces the current flowing through the entire electronic device 101 and the voltage drop in the battery 189 by reducing at least one of the operating clock frequencies of the first clock of the central processing unit 335, the second clock of the first block 336, the third clock of the second block 337, and the fourth clock of the third block 338. The central processing unit 335 maintains the total current flowing through the electronic device 101 below the first threshold current by reducing the total current flowing through the electronic device 101. The central processing unit 335 maintains the voltage level of the battery 189 above the first threshold voltage by reducing the voltage drop across the battery 189. The central processing unit 335 reduces the execution of the overcurrent protection function by maintaining the current flowing throughout the electronic device 101 below the first threshold current. The central processing unit 335 reduces the execution of the SMPL reset function by maintaining the voltage level of the battery 189 above the first threshold voltage. Therefore, the phenomenon in which the overcurrent protection function and / or SMPL reset function are executed while the electronic device 101 is in use and the electronic device 101 is turned off can be reduced. By reducing the phenomenon of the electronic device 101 being turned off during use, the operational stability of the electronic device 101 can be increased.

[0083] In one embodiment, the first block 336, the second block 337, and / or the third block 338 may be circuits, elements, modules, and / or buses that perform specified functions in a processor 120 configured as a system on a chip (SoC). Block 336 may be a graphics processing unit (GPU). Block 337 in the second block may be a neural network processing unit (NPU). Block 3, 338 could be a bus. Block 338 (e.g., bus) may include a group of signal lines for data communication. For example, the third block 338 may include at least one or more combinations of the address bus, data bus, and control bus. However, it is not limited to that, and the processor 120 may include multiple blocks such as MMC (multimedia card) and / or UFS (universal flash storage).

[0084] Figure 3b is a figure 350 showing a charging circuit 210, a power management module 188, and a processor 120 of an electronic device (e.g., electronic device 101 in Figure 1) according to another embodiment of the present invention. The charging circuit 210 and power management module 188 of the electronic device 101 according to another embodiment of the present invention are substantially identical to the charging circuit 210 and power management module 188 of the electronic device 101 according to one embodiment described with reference to Figure 3a.

[0085] In one embodiment, the processor 120 includes a first general-purpose input / output pin 251 and a second general-purpose input / output pin 252. The processor 120 receives a first overcurrent warning signal from the first pin 315 of the charging circuit 210 via the first general-purpose input / output pin 251. The processor 120 receives a reset warning signal from the second pin 323 of the power management module 188 via the second general-purpose input / output pin 252. In one embodiment, the processor 120 controls the operation of at least one of a plurality of blocks contained within the processor 120 based on at least one of a first overcurrent warning signal and a reset warning signal. For example, in response to the signal acquisition unit 333 receiving a first overcurrent warning signal via the first general-purpose input / output pin 251, the processor 120 controls at least one of a plurality of operating clock frequencies set for the central processing unit 335, the first block 336, the second block 337, and the third block 338, respectively.

[0086] Figure 4 is a waveform diagram 400 showing the overcurrent 410 and the first overcurrent warning signal 420 according to one embodiment of the present invention. In one embodiment, when the overcurrent 410 is in a high (H) state, the current flowing through the electronic device 101 is set to be equal to or greater than the first threshold current. When the overcurrent 410 is in a low (L) state, the current flowing through the electronic device 101 is kept below the first threshold current.

[0087] In one embodiment, if the first overcurrent warning signal 420 is in a disabled state, the first overcurrent warning signal is not transmitted to the processor 120. If the first overcurrent warning signal 420 is in the enabled state, the first overcurrent warning signal is transmitted to the processor 120. In one embodiment, if the overcurrent 410 remains high for a second threshold time T2, the first overcurrent warning signal 420 is switched to an enabled state. The second threshold time T2 is shorter than the first threshold time during which the overcurrent protection function is activated. For example, the second threshold time could be approximately 3 ms.

[0088] In one embodiment, the charging circuit 210 outputs a first overcurrent warning signal to the power management module 188 if the total current flowing through the electronic device 101 is equal to or greater than the first threshold current for a second threshold time T2. The second threshold time T2 is shorter than the first threshold time. Therefore, the charging circuit 210 can quickly notify that the total current flowing through the electronic device 101 is equal to or greater than the first threshold current. In one embodiment, the charging circuit 210 detects if the total current of the electronic device 101 reaches a first threshold current at which the overcurrent protection function is activated, and if the current is greater than or equal to the first threshold current for a second threshold time T1, before the first threshold time at which the overcurrent protection function is activated has elapsed. The charging circuit 210 generates a first overcurrent warning signal and outputs it to a designated pin (e.g., pin 315 in Figure 3). The charging circuit 210 transmits a first overcurrent warning signal to a first logic circuit (e.g., the first logic circuit 230 in Figure 3), and the first logic circuit 230 transmits the warning signal to the processor 120.

[0089] Figure 5a is a block diagram 500 showing an electronic device according to one embodiment of the present invention (e.g., electronic device 101 in Figure 1). An electronic device 101 according to one embodiment of the present invention includes a charging circuit 210, a power management module 188, a first logic circuit 230, a processor 120, a display power management module 550, a display module 160, a first module 560, and a connection part 570 connected to an external device 580.

[0090] In one embodiment, the charging circuit 210 transmits current to the power management module 188. The first current detection circuit 312 of the charging circuit 210 transmits current to the second current detection circuit 322 of the power management module 188.

[0091] In one embodiment, the temperature measuring unit 510 is located inside the electronic device 101. The temperature measuring unit 510 may include a thermistor. The temperature measuring unit 510 measures the temperature inside the electronic device 101. The temperature measurement unit 510 may be located separately from the processor 120. The temperature measuring unit 510 may be located adjacent to the battery 189, or it may be located on the surface of the battery 189. The temperature measuring unit 510 measures the temperature of the battery (e.g., battery 189 in Figure 3). The temperature measuring unit 510 measures the temperature around the battery 189. The temperature measuring unit 510 transmits the measured temperature to the first calculation circuit 520.

[0092] In one embodiment, the first arithmetic circuit 520 receives the temperature inside the electronic device 101 and / or the temperature around the electronic device 101, as measured by the temperature measuring unit 510. The first calculation circuit 520 compares the temperature measured by the temperature measuring unit 510 with a preset first temperature. The first arithmetic circuit 520 transmits the comparison result between the temperature measured by the temperature measurement unit 510 and the first temperature to the processor 120. In one embodiment, the first calculation circuit 520 sets the period for the temperature measuring unit 510 to measure the temperature inside the electronic device 101. The first arithmetic circuit 520 may be located separately from the processor 120. However, it is not limited to that, and the first arithmetic circuit 520 may be included in the processor 120. The first arithmetic circuit 520 transmits the set period to the processor 120.

[0093] In one embodiment, the first arithmetic circuit 520 sets the period based on the temperature measured by the temperature measuring unit 510. The first arithmetic circuit 520 determines that the temperature is at room temperature if the temperature measured by the temperature measuring unit 510 is equal to or greater than the first temperature. The first arithmetic circuit 520 determines that a low-temperature state is present if the temperature measured by the temperature measuring unit 510 is less than the first temperature. The first arithmetic circuit 520 sets the period to the first hour under normal temperature conditions. The first arithmetic circuit 520 sets the period to the second time when the temperature is low. The second hour is a larger value than the first hour.

[0094] In one embodiment, the processor 120 receives a warning signal from the first logic circuit 230. The processor 120 receives the result of comparing the temperature measured by the first arithmetic circuit 520 with the first temperature. The processor 120 controls the overall operation of the electronic device 101 based on warning signals and comparison results. The processor 120 includes a fourth pin 331, a second timer 530, a third logic circuit 540, a CPU 335, a first block 336, a second block 337, a third block 338, and a fourth block 339.

[0095] In one embodiment, the fourth pin 331 receives a warning signal from the first logic circuit 230. The fourth pin 331 transmits a warning signal to the third logic circuit 540.

[0096] In one embodiment, the second timer 530 receives the comparison result from the first arithmetic circuit 520. The second timer 530 transmits the comparison result to the third logic circuit 540.

[0097] In one embodiment, the third logic circuit 540 receives a warning signal and a comparison result. The third logic circuit 540 transmits a control signal to at least one of the CPU 335, the first block 336, the second block 337, the third block 338, and the fourth block 339 based on the comparison result and the warning signal. For example, the third logic circuit 540 transmits control signals to the CPU 335 and the third block 338 based on the comparison result and warning signals.

[0098] In one embodiment, the CPU 335 receives a control signal from the third logic circuit 540. Based on the control signal, the CPU 335 reduces the power and / or voltage consumed by at least one of the CPU 335, the first block 336, the second block 337, the third block 338, and the fourth block 339. For example, the CPU 335 reduces the operating clock frequency of at least one of the first block 336, second block 337, third block 338, and fourth block 339 based on the control signal.

[0099] In one embodiment, the charging circuit 210 supplies current to the display power management module 550, the first module 560, and the connection part 570.

[0100] In one embodiment, the display power management module 550 supplies current to the display module 160.

[0101] In one embodiment, the first module 560 is a module located inside the electronic device 101 and performing a function. For example, the first module 560 may be a communication circuit (e.g., wireless communication module 192 in Figure 1), a camera (e.g., camera module 180 in Figure 1), or a speaker (e.g., acoustic output module 155 in Figure 1). However, it is not limited to that, and the electronic device 101 can have various modules for performing various functions.

[0102] In one embodiment, the connection part 570 is connected to an external device 580. The external device 580 may be another smartphone or wearable device. The connection part 570 supplies charging current to the external device 580. For example, connection part 570 is a USB connector. For example, the connection unit 570 is an on-the-go (OTG) connection device or a power sharing connection device. The connection portion 570 to the external device 580 may be included in a power transmission module (e.g., the power transmission module 220 in Figure 2).

[0103] In one embodiment, the processor 120 controls the current flowing to the display power management module 550, the first module 560, and / or the connection 570 based on the warning signal and the second overcurrent warning signal. If a warning signal or a second overcurrent warning signal is enabled, the processor 120 controls the charging circuit 210 to reduce the current flowing to the display power management module 550, the first module 560, and / or the connection 570.

[0104] In one embodiment, the processor 120 is configured to reduce at least one of the following when a warning signal or a second overcurrent warning signal is enabled: the brightness of the display module 160, the resolution of the camera 180, and the volume of the speaker 155. In one embodiment, when a warning signal or a second overcurrent warning signal is enabled, the processor 120 performs control to reduce the current consumption of the electronic device 101 to below the first threshold current. The processor 120 reduces the brightness of the display module 160 in order to reduce the current consumption of the electronic device 101 to below a first threshold value. The processor 120 reduces the resolution of the camera 180 in order to reduce the current consumption of the electronic device 101 to below the first threshold current. The processor 120 reduces the volume of the speaker 155 in order to reduce the current consumption of the electronic device 101 to below the first threshold current. The processor 120 controls the display 160, camera 180, and / or speaker 155 so as to reduce the current consumption of the electronic device 101 to below a first threshold current and maintain the battery 189 voltage above the first threshold voltage.

[0105] Figure 5b is a block diagram 590 showing an electronic device according to another embodiment of the present invention (e.g., electronic device 101 in Figure 1). An electronic device 101 according to another embodiment of the present invention includes a charging circuit 210, a power management module 188, a processor 120, a display power management module 550, a display module 160, a first module 560, and a connection part 570 connected to an external device 580. The charging circuit 210, power management module 188, display power management module 550, display module 160, first module 560, and connection part 570 of the electronic device 101 according to another embodiment of the present invention are substantially the same as the charging circuit 210, power management module 188, display power management module 550, display module 160, first module 560, and connection part 570 of the electronic device 101 according to one embodiment described with reference to Figure 5a.

[0106] In one embodiment, the processor 120 includes a first general-purpose input / output pin 251 and a second general-purpose input / output pin 252. The processor 120 receives a first overcurrent warning signal from the charging circuit 210 via the first general-purpose input / output pin 251. The processor 120 receives a reset warning signal from the second pin 323 of the power management module 188 via the second general-purpose input / output pin 252.

[0107] In one embodiment, the processor 120 controls the operation of at least one of a plurality of blocks contained within the processor 120 based on at least one of a first overcurrent warning signal and a reset warning signal. For example, in response to the third logic circuit 540 receiving a first overcurrent warning signal via the first general-purpose input / output pin 251, the processor 120 controls at least one of a plurality of operating clock frequencies set for each of the CPU 335, the first block 336, the second block 337, the third block 338, and the fourth block 339. In one embodiment, the processor 120 controls the current flowing to the display power management module 550, the first module 560, and / or the connection 570 based on at least one of the first overcurrent warning signal and the reset warning signal. For example, the processor 120 reduces the brightness of the display module 160 in response to the third logic circuit 540 receiving a first overcurrent warning signal via the first general-purpose input / output pin 251. As another example, the processor 120 reduces the current flowing through the connector 570 in response to the third logic circuit 540 receiving a first overcurrent warning signal via the first general-purpose input / output pin 251.

[0108] Figure 6 is a flowchart 600 illustrating a control method for an electronic device (e.g., the electronic device 101 in Figure 1) according to one embodiment of the present invention.

[0109] In one embodiment, the charging circuit of the electronic device 101 (e.g., the charging circuit 210 in Figure 2) acquires the current consumption of the electronic device 101 in step 610. The charging circuit 210 monitors the total current consumption of the electronic device 101, including the supply current. The supplied current may include current for charging external devices such as on-the-go devices (e.g., external device 580 in Figure 5).

[0110] In one embodiment, the charging circuit 210 of the electronic device 101 checks in step 615 whether the current consumption is equal to or greater than the first threshold current for a second threshold time. The charging circuit 210 checks whether the current consumption is equal to or greater than the first threshold current for a second threshold time that is shorter than the first threshold time for which the overcurrent protection function is performed. If the charging circuit 210's current consumption is less than the first threshold current (step 615-No), it proceeds to step 620. If the charging circuit 210's current consumption is greater than or equal to the first threshold current (stage 615-Yes), it can proceed to stage 625.

[0111] In one embodiment, the charging circuit 210 of the electronic device 101 disables the first overcurrent warning signal in step 620. The charging circuit 210 maintains the first overcurrent warning signal in a high state. In one embodiment, the charging circuit 210 of the electronic device 101 enables the first overcurrent warning signal in step 625. The charging circuit 210 switches the first overcurrent warning signal to a low state. In one embodiment, the power management module of the electronic device 101 (e.g., the power management module 188 in Figure 2) acquires the voltage of the battery (e.g., the battery 189 in Figure 1) in step 630. The power management module 188 monitors the voltage of the battery 189.

[0112] In one embodiment, the power management module 188 of the electronic device 101 checks in step 635 whether the voltage of the battery 189 is below the second threshold voltage. The power management module 188 checks whether the voltage of the battery 189 is less than or equal to a second threshold voltage, which is higher than the first threshold voltage at which the SMPL reset function is executed. The power management module 188 proceeds to step 640 if the voltage of the battery 189 is higher than the second threshold voltage (step 635-No). The power management module 188 proceeds to step 645 if the voltage of the battery 189 is below the second threshold voltage (step 635 - Yes).

[0113] In one embodiment, the charging circuit 210 of the electronic device 101 can disable the reset warning signal in step 640. The charging circuit 210 maintains the SMPL reset warning signal in a high state. In one embodiment, the charging circuit 210 of the electronic device 101 enables a reset warning signal in step 645. The charging circuit 210 switches the SMPL reset warning signal to a low state. In one embodiment, the processor of the electronic device 101 (e.g., the processor 120 in Figure 2) enables a reset warning interrupt request in step 650. Processor 120 enables the overcurrent warning IRQ signal. The processor 120 performs control to prevent a reset operation from occurring.

[0114] In one embodiment, the processor 120 of the electronic device 101 disables the reset warning interrupt request in step 655, reduces the operating clock frequency of the central processing unit (e.g., the central processing unit 335 in Figure 3), and starts a timer (e.g., the second timer 530 in Figure 5). The processor 120 performs an operation at the kernel layer to reduce the operating clock frequency of the central processing unit 335. In one embodiment, the processor 120 of the electronic device 101 proceeds to step 660 when the timer 530 has elapsed for a specified time interval in step 655. If the first overcurrent warning signal and the reset warning signal are disabled in step 655, the processor 120 proceeds to step 670.

[0115] In one embodiment, the processor 120 of the electronic device 101 reduces the operating clock frequency of the central processing unit 335 and restarts the timer 530 to increase the counter in step 660. When the timer 530 has elapsed for the specified time interval, the counter increments the count by 1. In one embodiment, the processor 120 of the electronic device 101 repeats step 660 if the timer 530 has elapsed and the counter of the timer 530 is less than a threshold number of times. In step 660, if the timer 530 has elapsed and the counter of the timer 530 is equal to or greater than the threshold number of times, the processor 120 proceeds to step 665. If the first overcurrent warning signal and the reset warning signal are disabled in step 660, the processor 120 proceeds to step 670.

[0116] In one embodiment, the processor 120 of the electronic device 101 reduces the maximum clock frequency of the central processing unit 335, the graphics processing unit (e.g., the first block 336 in Figure 3), the bus (e.g., the third block 338 in Figure 3), the brightness of the screen (e.g., the display module 160 in Figure 5), and the current consumption of the power transmission module (e.g., the power transmission module 220 in Figure 2) in step 665, and restarts the timer 530. The processor 120 uses a framework to reduce the current consumption of the power transmission module 220.

[0117] In one embodiment, the processor 120 of the electronic device 101 repeats step 665 when the timer 530 has elapsed. If the first overcurrent warning signal and the reset warning signal are disabled in step 665, the processor 120 proceeds to step 670. In one embodiment, the processor 120 of the electronic device 101 releases power control and initializes the timer 530 in step 670.

[0118] Various forms of electronic devices are possible according to the various embodiments disclosed in this invention. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. The electronic devices according to embodiments of the present invention are not limited to the devices described above.

[0119] The various embodiments of the present invention and the terminology used herein should be understood not to limit the technical features described herein to any particular embodiment, but to include various modifications, equivalents, or substitutions of such embodiments. In relation to the description of the drawings, similar or related components shall be given similar reference numerals. A singular noun corresponding to an item may include one or more of the aforementioned items unless the context clearly indicates otherwise. In this specification, each of the phrases such as "A or B," "A and B or at least one of A or B," "A, B or C," "A, B and C or at least one of A, B or C," and "A, B or C or at least one of A, B or C" may include any one of the items listed together in the phrase, or any possible combination thereof. Terms such as "first," "second," "first," and "second" are used simply to distinguish the relevant component from other relevant components and do not limit the relevant component in any other way (e.g., importance or procedure). When one component (e.g., component 1) is referred to as "coupled" or "connected" to another component (e.g., component 2), with or without the terms "functionally" or "communically," it means that component can be connected to the other component directly (e.g., by wire), wirelessly, or via component 3.

[0120] As used in various embodiments of this specification, the term "module" may include units implemented in hardware, software, or firmware, and can be used interchangeably with terms such as logic, logic block, component, and circuit. A module can be a set of components, or the smallest unit or part thereof of components that perform one or more functions. For example, according to one embodiment of the present invention, the module can be implemented in the form of an ASIC (application-specific integrated circuit).

[0121] Various embodiments of this specification may be implemented as software (e.g., program 140) containing one or more instruction words stored in a storage medium (e.g., internal memory 136 or external memory 138) readable by a machine (e.g., electronic device 101). For example, the processor (e.g., processor 120) of a device (e.g., electronic device 101) calls at least one instruction from one or more instruction words stored in a storage medium and executes it. This allows the device to be operated to perform at least one function according to at least one command word that is invoked. One or more instruction words may contain code generated by a compiler or code that can be executed by an interpreter. The device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, "non-temporary" simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily on the storage medium.

[0122] According to one embodiment of the present invention, the methods according to various embodiments disclosed herein may be provided in a computer program product. Computer program products may be traded as goods between sellers and buyers. Computer program products may be distributed in the form of a device-readable storage medium (e.g., CD-ROM) (compact disc read-only memory), or online (e.g., download or upload) via an application store (e.g., Play Store®) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of a computer program product may be temporarily stored or temporarily generated on a storage medium readable by devices such as the manufacturer's servers, application store servers, or relay server memory.

[0123] According to various embodiments of the present invention, each of the above-mentioned components (e.g., a module or a program) may include one or more individuals, and some of the individuals may be separated and arranged in other components. According to various embodiments of the present invention, one or more of the above-described components or operations may be omitted, and one or more other components or operations may be added. Alternatively or additionally, multiple components (e.g., modules or programs) may be integrated into a single component. In that case, the integrated component can perform one or more functions of each of the multiple components in the same or similar manner as they were performed by the corresponding component among the multiple components prior to the integration. According to various embodiments of the present invention, the operations performed by the module, program, or other components may be performed sequentially, in parallel, repeatedly, or heuristically, or one or more operations may be performed in other steps, omitted, or one or more other operations may be added. [Explanation of Symbols]

[0124] 101, 102, 104 Electronic equipment 108 servers 120 processors 121 Main Processor 123 subprocessors 130 memory 132 Volatile memory 134 Non-volatile memory 136 internal memory 138 External memory 140 programs 142 Operating Systems 144 Middleware 146 applications 150 Input Modules 155 Audio Output Module 160 display modules 170 Audio Modules 176 Sensor Modules 177 Interfaces 178 Connection terminals 179 Haptic Modules 180 Camera Module 188 Power Management Modules 189 batteries 190 Communication Module 192 Wireless Communication Module 194 Wired communication module 196 Subscriber Identification Module 197 Antenna Module 198 First Network 199 Second Network 210 Charging circuit 220 Power Transmission Modules 311 Switch 312 First Current Detection Circuit 313 First Timer 321 Voltage detection circuit 322 Second Current Detection Circuit 333 Signal acquisition unit 334 Clock Control Unit 335 Central Processing Unit (CPU) 336 Block 1 337 Block 2 338 Block 3 339 Block 4 410 Overcurrent 420 1st overcurrent warning signal 510 Temperature measurement section 530 Second Timer 550 Display Power Management Module 560 Module 1 570 Connection part 580 External device

Claims

1. An electronic device, Battery and Charging circuit and Power management module and The device has a processor that is operationally connected to the battery and the charging circuit, and includes a central processing unit (CPU) and a plurality of blocks (IP blocks), The charging circuit is configured to transmit a first overcurrent warning signal to the processor when the total current flowing through the electronic device is equal to or greater than a first threshold current. The power management module is configured to transmit a second overcurrent warning signal to the processor when the current value flowing through the entire electronic device is equal to or greater than the second threshold current. An electronic device characterized in that, when at least one of the first overcurrent warning signal or the second overcurrent warning signal is received, the processor is set to reduce at least one of the operating clock frequencies set for each of the CPU and the plurality of blocks.

2. The electronic device according to claim 1, further characterized in that the processor is configured to reduce the brightness of the display when the first overcurrent warning signal or the second overcurrent warning signal is received.

3. The electronic device according to claim 1, further characterized in that the processor is configured to reduce the charging current of the power transmission module when the first overcurrent warning signal or the second overcurrent warning signal is received.

4. The electronic device according to claim 1, wherein the processor is further configured to set each of the plurality of operating clock frequencies by dynamic voltage frequency scaling (DVFS).

5. The electronic device according to claim 1, characterized in that the processor is further configured to decrease at least one of the following: a first operating clock frequency set for the CPU, a second operating clock frequency set for the graphics processing unit (GPU) among the plurality of blocks, or a third operating clock frequency set for the neural network processing unit (NPU) among the plurality of blocks, if the current value flowing to the electronic device after a first time has elapsed is equal to or greater than the first threshold current.

6. The aforementioned processor, While decreasing the operating clock frequency of at least one of the above, the counter of the timer inside the processor is increased. The electronic device according to claim 5, further configured to decrease at least one of the first operating clock frequencies, the second operating clock frequency, or the third operating clock frequency when the counter is equal to or greater than a specified threshold number of times.

7. The electronic device according to claim 1, characterized in that the charging circuit is configured to transmit the first overcurrent warning signal to the processor if the current value is equal to or greater than the first threshold current during a second threshold time that is shorter than the first threshold time for which the overcurrent protection function is performed.

8. The electronic device according to claim 1, further configured to transmit a reset warning signal to the processor when the voltage of the power management module is below a threshold voltage.

9. The electronic device according to claim 8, characterized in that the reset warning signal is a signal that prevents the execution of the SMPL (sudden momentary power loss) reset function.

10. System on Chip (SoC), The system has a processor comprising a central processing unit (hereinafter referred to as CPU) and multiple blocks (IP blocks), The processor is configured to receive a first overcurrent warning signal when the total current level of the electronic device is equal to or greater than a first threshold current, and to receive a second overcurrent warning signal when the total current level of the electronic device is equal to or greater than a second threshold current. The system-on-chip is characterized in that the processor is configured to perform at least one operation that reduces at least one of a plurality of operating clock frequencies set for each of the CPU and the plurality of blocks, based on at least one of the first overcurrent warning signal or the second overcurrent warning signal.

11. The system-on-chip according to claim 10, characterized in that the plurality of blocks include a graphics processing unit (GPU) and a neural network processing unit (NPU).

12. The system-on-chip according to claim 10, wherein the processor is further configured to decrease at least one of the following: a first operating clock frequency set for the CPU, a second operating clock frequency set for the graphics processing unit (GPU) among the plurality of blocks, or a third operating clock frequency set for the neural network processing unit (NPU) among the plurality of blocks, if the current value flowing to the electronic device after a first time has elapsed is equal to or greater than the first threshold current.

13. The processor increases the counter while decreasing the first operating clock frequency each time the timer elapses. The system-on-chip according to claim 12, further configured to decrease the first operating clock frequency, the second operating clock frequency, the third operating clock frequency, and the fourth operating clock frequency when the counter is equal to or greater than a threshold number of times.

14. The system-on-chip according to claim 12, characterized in that the processor is configured to receive the first overcurrent warning signal if the current value is greater than or equal to the first threshold current during a second threshold time that is shorter than the first threshold time for which the overcurrent protection function is performed.

15. The system-on-chip according to claim 10, further characterized in that the processor is configured to receive a reset warning signal when the voltage of the power management module of the electronic device is below a threshold voltage.

16. A method for controlling an electronic device, The charging circuit of the electronic device transmits a first overcurrent warning signal to a processor including the central processing unit (hereinafter referred to as CPU) of the electronic device when the current consumption of the electronic device is equal to or greater than a first threshold current. The power management module of the electronic device transmits a second overcurrent warning signal to the processor when the current flowing through the electronic device is equal to or greater than a second threshold current. The processor receives at least one of the first overcurrent warning signal or the second overcurrent warning signal, A method for controlling an electronic device, characterized in that the processor has the step of reducing at least one operating clock frequency among a plurality of operating clock frequencies set for each of the CPU and a plurality of blocks included in the processor.

17. The method for controlling an electronic device according to claim 16, characterized in that the step of reducing the at least one operating clock frequency includes, if the current value flowing through the electronic device after a first time has elapsed is greater than or equal to the first threshold current, the step of reducing at least one of the first operating clock frequency set for the CPU, the second operating clock frequency set for the graphics processing unit (GPU) among the plurality of blocks, or the third operating clock frequency set for the neural network processing unit (NPU) among the plurality of blocks.

18. The step of reducing at least one of the above is, A step of increasing the counter of the timer inside the processor while decreasing the at least one operating clock frequency, A method for controlling an electronic device according to claim 17, comprising the step of reducing at least one of the first operating clock frequency, the second operating clock frequency, or the third operating clock frequency if the counter is equal to or greater than a specified threshold number of times.

19. The control method for an electronic device according to claim 16, further comprising the step of transmitting a reset warning signal to the processor when the voltage of the power management module is below a threshold voltage.

20. The control method for an electronic device according to claim 19, characterized in that the reset warning signal is a signal that prevents the execution of the SMPL (sudden momentary power loss) reset function.

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