A latch-based level shifter circuit with self-biasing properties.

Abstract

The present invention provides an integrated circuit that includes a latch-based level shifter circuit having a self-bias. [Solution] The optical drive circuit 100 includes a buffer circuit 110, a non-level shift latch circuit 120, a level shift latch circuit 130, a pull-down circuit 140, a pull-up circuit 150, and an inductive circuit 160. The buffer circuit 110 receives the input signal D on the input node 102. in The pull-down circuit 140, pull-up circuit 150, and inductive circuit 160 receive the output signal D on the output node 104 of the optical drive circuit. out This forms an output stage circuit that provides power to the transmitter (TX) bump 170. The TX bump 170 is coupled to an electro-optical transducer 180, such as an electric field absorption modulator (EAM), a ring modulator (RM), or any other suitable electro-optical transducer.

Description

[Technical Field]

[0001] (Government rights) This invention was developed by the Defense Advanced Research Projects Agency. This invention was made with the support of the U.S. Government under contract number HR0011-19-3-0004, to which it was awarded. The U.S. Government has certain rights in this invention.

[0002] (Field of invention) Examples of the present disclosure generally relate to integrated circuits that include latch-based level shifter circuits having a self-bias. [Background technology]

[0003] An integrated circuit (IC) can implement level shifter circuits to change the level or voltage amplitude of a signal. For example, a level shifter circuit can change the level or voltage amplitude of a signal that could be up to a first supply voltage to a level or voltage amplitude that could be up to a second different supply voltage. Level shifter circuits can be implemented between different voltage domains within an IC. Level shifter circuits can be incorporated into or implemented as drive circuits, such as optical drive circuits. An optical drive circuit can change the voltage amplitude of a signal that could be up to a lower supply voltage of an IC (e.g., used to generate a signal) to a voltage amplitude that can be up to a higher supply voltage sufficient to drive an optical device. [Overview of the project]

[0004] The examples described herein generally relate to integrated circuits that include latch-based level shifter circuits with self-biasing. By providing bias at the latch node, the common-mode voltage of each signal output on the latch's output node and input to the output stage circuit can remain at an appropriate level, even at high frequencies and / or reduced supply voltages. In addition, in some examples, the output signal output on the output node of the output stage circuit can hold long sequences of logic "1" and long sequences of logic "0" without drooping.

[0005] An example described herein is an integrated circuit. This integrated circuit includes a first latch circuit, a second latch circuit, and an output stage circuit. The first latch circuit has a first latch node and a first output node. The first latch node is electrically coupled to a signal input node. The first latch circuit includes a first bias circuit electrically connected to the first latch node and configured to provide a bias voltage at the first latch node. The second latch circuit has a second latch node and a second output node. The second latch node is electrically coupled to a signal input node. The second latch circuit includes a second bias circuit electrically connected to the second latch node and configured to provide a bias voltage at the second latch node. The output stage circuit has a first input node, a second input node, and a third output node. The first input node is electrically connected to the first output node. The second input node is electrically connected to the second output node. The output stage circuit is configured to responsively pull up and pull down the voltage of the third output node in response to the voltages of the first and second input nodes, respectively.

[0006] Another example described herein is an integrated circuit. This integrated circuit includes a level shifter circuit. The level shifter circuit includes a non-level shift latch circuit and a level shift latch circuit. The non-level shift latch circuit has a first latch node and a first output node. The first latch node is electrically coupled to the signal input node of the level shifter circuit. The non-level shift latch circuit includes a first DC bias circuit configured to provide a first DC bias voltage at the first latch node. The level shift latch circuit has a second latch node and a second output node. The second latch node is electrically coupled to the signal input node of the level shifter circuit. The level shift latch circuit includes a second DC bias circuit configured to provide a second DC bias voltage at the second latch node.

[0007] Another example described herein is a method for operating an integrated circuit. An input signal is received at an input node. The input node is electrically coupled to a first latch node and a second latch node. A non-level-shift latch circuit includes a first latch node and a first DC bias circuit electrically connected to the first latch node. A level-shift latch circuit includes a second latch node and a second DC bias circuit electrically connected to the second latch node. A non-level-shift signal is generated by the non-level-shift latch circuit based on a signal on the first latch node. A level-shift signal is generated by the level-shift latch circuit based on a signal on the second latch node. An output signal is output from an output stage circuit. The output stage circuit generates an output signal in response to a non-level-shift signal and a level-shift signal.

[0008] These and other embodiments may be understood by referring to the following "Modes for Carrying Out the Invention".

[0009] To ensure a detailed understanding of the above features, a more specific explanation, concisely summarized above, can be provided by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0010] [Figure 1] Several examples illustrate exemplary level shifter circuits. [Figure 2] This is a flowchart illustrating how to operate an integrated circuit, including a level shifter circuit, using several examples.

[0011] For ease of understanding, the same reference numeral is used to indicate identical elements common to multiple drawings, where possible. It is intended that elements in one example may be usefully incorporated into others. [Modes for carrying out the invention]

[0012] The examples described herein generally relate to integrated circuits including latch-based level shifter circuits having self-biasing properties. While the embodiments of the examples described herein generally relate to level shifter circuits, certain examples are described in relation to optical drive circuits. Generally, in the examples described herein, the level shifter circuit includes latches electrically connected between different pairs of supply nodes configured to be at different supply voltages. Each latch has a latch node to be biased. In some examples, the latch node is a complementary device (e.g., complementary metal-oxide-semiconductor (CMO)). S) The input and output nodes of an inverter, such as an inverter, are biased by being electrically connected. Each output node of the latch is electrically connected to the input node of the output stage circuit, and the output stage circuit is configured to pull up and pull down the voltage on the output nodes of the output stage circuit in response. By providing bias at the latch node, the signal output on the output node of the latch and input to the output stage circuit is biased. Each common-mode voltage can remain at an appropriate level even at high frequencies and / or reduced supply voltages. In addition, in some examples, for example, by matching the drive capability of the bias inverter with the drive capability of the feedback inverter of each latch, the output signal output to the output node of the output stage circuit can hold long sequences of logic "1" and long sequences of logic "0" without drooping.

[0013] Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of the features. They are not intended to be an exhaustive description of the invention described in the claims, nor to limit the scope of the invention described in the claims. In addition, illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to a particular example are not necessarily limited to that example and may be implemented in any other example, even if not illustrated or explicitly described as such. Furthermore, while the methods described herein may be described in a particular sequence of operations, other methods in other examples may be implemented in various other sequences (e.g., including different serial or parallel executions of various operations) with more or fewer operations.

[0014] In the following description, various signals (e.g., voltage and / or current) are described in relation to the operation of various circuits. The described signals indicate the corresponding nodes to which the signal is applied or propagated, and further indicate nodes to which they are communicatively coupled and / or electrically connected. For example, the description of a signal output from a first circuit and input to a second circuit indicates that the output node of the first circuit (from which the signal is output) is communicatively coupled and / or electrically connected to the input node of the second circuit (to which the signal is input). Explicit descriptions of such nodes may be omitted in the following description, but those skilled in the art will readily understand their presence.

[0015] Figure 1 shows exemplary level shifter circuits in several examples. In the illustrated examples, the level shifter circuit is also the optical drive circuit 100. The level shifter circuit, in this example the optical drive circuit 100, receives an input signal D which may have a relatively low voltage amplitude. in The output signal D, which receives the signal, may have a relatively high voltage amplitude. out It is configured to generate the input signal D. in The first supply voltage VDD1 may have a relatively low voltage amplitude between it and the ground potential, and the output signal D out The first supply voltage VDD1 may have a relatively high voltage amplitude between the second supply voltage VDD2 and the ground potential, and the second supply voltage VDD2 is greater than the first supply voltage VDD1. In some embodiments, the first supply voltage VDD1 may be equal to about 0.9 volts and the second supply voltage VDD2 may be equal to about 1.8 volts. In other examples, the first supply voltage VDD1 and the second supply voltage VDD2 may be other suitable voltages.

[0016] The example in Figure 1 is illustrated and described using a grounding node, a first supply node VDD1, and a second supply node VDD2 (which are supplied with ground potential, first supply voltage VDD1, and second supply voltage VDD2). In other examples, different supply voltages or potentials may be implemented. More generally, the grounding node and ground potential can be considered as the first supply node and first supply voltage, respectively; the first supply node VDD1 and first supply voltage VDD1 can be considered as the second supply node and second supply voltage, respectively; and the second supply node VDD2 and second supply voltage VDD2 can be considered as the third supply node and third supply voltage, respectively. In this comprehensive explanation, the second supply voltage is greater than the first supply voltage, and the third supply voltage is greater than the second supply voltage.

[0017] The optical drive circuit 100 includes a buffer circuit 110, a non-level shift latch circuit 120, and It includes a bell-shift latch circuit 130, a pull-down circuit 140, a pull-up circuit 150, and an inductive circuit 160. In the illustrated example, the buffer circuit 110 receives the input signal D on the input node 102. in The pull-down circuit 140, the pull-up circuit 150, and the inductive circuit 160 are configured to receive the output signal D on the output node 104 of the optical drive circuit 100. out The output stage circuit of the optical drive circuit 100 provides the signal to the transmitter (TX) bump 170. The TX bump 170 can be coupled to an electro-optic transducer 180, such as an electro-absorption modulator (EAM), a ring modulator (RM), or any other suitable electro-optic transducer.

[0018] Although described as optical drive circuit 100, the buffer circuit 110, non-level shift latch circuit 120, level shift latch circuit 130, pull-down circuit 140, and pull-up circuit 150 can be implemented as latch-based level shifter circuits for any suitable application. Those skilled in the art will readily understand such applications.

[0019] The buffer circuit 110 is either the input node 102 or electrically connected to the input node 102, and the input signal D in The buffer circuit 110 has an input node configured to receive the input signal D. The buffer circuit 110 includes inverters 111 and 112 electrically connected in series between the input node 102 and the first node N1. The input node of inverter 111 is electrically connected to the input node 102 of the buffer circuit 110. The output node of inverter 111 is electrically connected to the input node of inverter 112. The output node of inverter 112 is the output node of the buffer circuit 110 and is electrically connected to the first node N1. Inverters 111 and 112 include power nodes electrically connected to a first supply node VDD1 and a ground node. The first supply node VDD1 is configured to be a first supply voltage VDD1 when operating, and the ground node is configured to be at ground potential when operating. Inverters 111 and 112 receive the input signal D so that it has a rail-to-rail voltage amplitude between ground potential (e.g., 0 volts) and the first supply voltage VDD1. in It can be used to buffer and drive. In some examples, inverters 111 and 112 may each be complementary device (e.g., CMOS) inverters.

[0020] The output node of buffer circuit 110 (electrically connected to, for example, the first node N1) is electrically connected to the input node of non-level-shift latch circuit 120 and the input node of level-shift latch circuit 130. The non-level-shift latch circuit 120 includes capacitor 121 and inverters 122, 123, 124. The first terminal of capacitor 121 is the input node of non-level-shift latch circuit 120 and is electrically connected to the output node of buffer circuit 110. The second terminal of capacitor 121 (opposite to the first terminal of capacitor 121), the input node of inverter 122, the output node of inverter 123, and the input and output nodes of inverter 124 are electrically connected to each other to form a latch node N1A. The output node of inverter 122 and the input node of inverter 123 are electrically connected to each other to form the output node N2 of non-level-shift latch circuit 120. The output node N2 of non-level-shift latch circuit 120 is electrically connected to the input node of pull-down circuit 140. Each of inverters 122, 123, 124 includes a power node electrically connected to the first supply node VDD1 and the ground node. In some examples, each of inverters 122, 123, 124 can be a complementary device (e.g., CMOS) inverter.

[0021] Capacitor 121 can block the DC component of input signal D in Inverters 122, 123 form an inverter latch configured to store the logical complement value of input signal D in at output node N2. The electrically connected inverter 124 is a DC bias circuit and provides a self-bias voltage to non-level-shift latch circuit 120. Inverter 12 The self-bias provided by 4 (e.g., DC bias voltage) allows the latches formed by inverters 122 and 123 to maintain the correct bias, even when the transition strength at latch node N1A is low, such as when the first supply voltage VDD1 during operation is below the nominal value. This further allows the logic complement values ​​stored at output node N2 to maintain the correct common-mode voltage. By blocking the DC component with capacitor 121, the latches formed by inverters 122 and 123 are blocked by the input signal D in At the edge, transitions between logical states are possible.

[0022] The level shift latch circuit 130 includes a capacitor 131 and inverters 132, 133, and 134. The first terminal of capacitor 131 is the input node of the level shift latch circuit 130 and is electrically connected to the output node of the buffer circuit 110. The second terminal of capacitor 131 (opposite the first terminal of capacitor 131), the input node of inverter 132, the output node of inverter 133, and the input and output nodes of inverter 134 are electrically connected to each other to form latch node N1B. The output node of inverter 132 and the input node of inverter 133 are electrically connected to each other to form output node N3 of the level shift latch circuit 130. Output node N3 of the level shift latch circuit 130 is electrically connected to the input node of the pull-up circuit 150. Inverters 132, 133, and 134 each include a power node electrically connected to a second supply node VDD2 and a first supply node VDD1. The second supply node VDD2 is configured to have a second supply voltage VDD2 when in operation. In some examples, inverters 132, 133, and 134 may each be complementary device (e.g., CMOS) inverters.

[0023] Capacitor 131 receives the input signal D in The DC component of the input signal D can be blocked. Inverters 132 and 133 can block the DC component of the input signal. inAn inverting latch is formed, configured to store the logical complement value of at output node N3. Furthermore, since the power nodes of inverters 132 and 133 are electrically connected between the second supply node VDD2 and the first supply node VDD1, which are provided with the second supply voltage VDD2 and the first supply voltage VDD1 respectively, the level shift latch circuit 130 also receives the input signal D in The input signal D is level-shifted. in The level shift signal D is the logical complement of the first supply voltage VDD1 and has a voltage amplitude approximately between the second supply voltage VDD2 and the first supply voltage VDD1. high This can generate the DC component. The electrically connected inverter 134 is a DC bias circuit and provides a self-bias voltage to the level shift latch circuit 130. The self-bias (e.g., DC bias voltage) provided by inverter 134 allows the latches formed by inverters 132 and 133 to maintain the correct bias even when the transition strength at latch node N1B is small, such as when the second supply voltage VDD2 during operation is below the nominal value. This further allows the logic complement value stored at output node N3 to maintain the correct common-mode voltage. With capacitor 131 blocking the DC component, the latches formed by inverters 132 and 133 receive the input signal D in At the edge, transitions between logical states are possible.

[0024] During operation, inverter 124 provides a bias voltage at latch node N1A that may be VDD1 / 2 in the illustrated example, assuming the ground potential is 0V, and inverter 134 provides a bias voltage at latch node N1B that may be (VDD2+VDD1) / 2 in the illustrated example. Input signal D in When is driven to a high logic state, the signal on the first node N1 is driven to a high logic state (e.g., the first supply voltage VDD1) by the buffer circuit 110, thereby driving the signals on latch nodes N1A and N1B, respectively, to a high logic state (e.g., the first supply voltage VDD1).

[0025] In response to a high logic state on latch node N1A, inverter 122 outputs to output node N By driving 2 to a low logic state (e.g., ground potential), and in response to the low logic state on output node N2, inverter 123 attempts to drive latch node N1A high toward the first supply voltage VDD1. Inverter 124 attempts to drive latch node N1A toward the bias voltage (e.g., VDD1 / 2). In some examples, the driving capabilities of inverters 123 and 124 are equal. More specifically, each n-type transistor in inverter 123 can have the same channel width and channel length as each n-type transistor in inverter 124 (and vice versa), and each n-type transistor in inverter 123 can have the same channel width and channel length as each p-type transistor in inverter 124 (and vice versa). Inverter 123 may have the same physical layout as inverter 124 in an integrated circuit. Assuming that inverters 123 and 124 have the same drive capability, latch node N1A is driven towards (3 / 4)VDD1, which is greater than the switching threshold of inverter 122 that would cause inverter 122 to continue driving output node N2 to a low logic state.

[0026] In response to a high logic state on latch node N1B, inverter 132 drives output node N3 to a low logic state (e.g., the first supply voltage VDD1), and in response to a low logic state on output node N3, inverter 133 attempts to drive latch node N1B high toward the second supply voltage VDD2. Inverter 134 attempts to drive latch node N1B toward the bias voltage (e.g., (VDD2 + VDD1) / 2). In some examples, the driving capabilities of inverters 133 and 134 are equal. More specifically, each n-type transistor in inverter 133 can have the same channel width and channel length as each n-type transistor in inverter 134 (and vice versa), and each n-type transistor in inverter 133 can have the same channel width and channel length as each p-type transistor in inverter 134 (and vice versa). Inverter 133 may have the same physical layout as inverter 134 in an integrated circuit. Assuming that inverters 133 and 134 have the same drive capability, latch node N1B is driven towards [(3 / 4)VDD2 + (1 / 4)VDD1], which is greater than the switching threshold of inverter 132 that would cause inverter 132 to continue driving output node N3 into a low logic state.

[0027] Input signal D in When it is driven to a low logic state, the signal on the first node N1 is driven to a low logic state (e.g., ground potential) by the buffer circuit 110, and thereby the signals on latch nodes N1A and N1B are driven to a low logic state (e.g., ground potential).

[0028] In response to a low logic state on latch node N1A, inverter 122 drives output node N2 to a high logic state (e.g., the first supply voltage VDD1), and in response to a low logic state on output node N2, inverter 123 attempts to drive latch node N1A low toward ground potential. Inverter 124 attempts to drive latch node N1A toward the bias voltage (e.g., VDD1 / 2). Assuming that inverters 123 and 124 have the same driving capability as described above, latch node N1A will be driven toward (1 / 4)VDD1, which is less than the switching threshold of inverter 122 that would cause inverter 122 to continue driving output node N2 to a high logic state.

[0029] In response to a low logic state on latch node N1B, inverter 132 drives output node N3 to a high logic state (e.g., the second supply voltage VDD2), and in response to a high logic state on output node N3, inverter 133 attempts to drive latch node N1B low toward the first supply voltage VDD1. Inverter 134 attempts to drive latch node N1B toward the bias voltage (e.g., (VDD2 + VDD1) / 2). Assuming that inverters 133 and 134 have the same driving capability as described above, the latch node N1B is driven towards [(1 / 4)VDD2 + (3 / 4)VDD1], which is less than the switching threshold of inverter 132 that causes inverter 132 to continue driving output node N3 into a high logic state.

[0030] The power nodes of inverters 122, 123, and 124 are electrically connected to the first supply node VDD1 and the ground node, so the input signal D in The input signal D does not necessarily have to be level-shifted by inverters 122 and 123. The non-level-shift latch circuit 120 receives the input signal D via output node N2. in The non-level-shift signal D is the logical complement of the logical complement of the signal D. low The pull-down circuit 140 can be supplied with the input signal D. The level shift latch circuit 130 receives the input signal D. inThe voltage amplitude can be level-shifted from a relatively low voltage range (between 0 volts and the first supply voltage VDD1) to a relatively high voltage range (between the first supply voltage VDD1 and the second supply voltage VDD2). Input signal D in The resulting level shift signal D is the logical complement of high This can be supplied to the pull-up circuit 150 via output node N3.

[0031] The pull-down circuit 140 has a first n-type transistor 141 (for example, an n-type field-effect transistor (FET)) and a second n-type transistor 142. The circuit includes a third n-type transistor 143. The gate node of the first n-type transistor 141 is electrically connected to the output node N2 of the non-level-shift latch circuit 120, which receives a non-level-shift signal D in the pull-down circuit 140. low This is the input node of the pull-down circuit 140 that provides the following. The first n-type transistor 141 has a drain node that is electrically connected to the source node of the second n-type transistor 142. The second n-type transistor 142 has a bias node N bias Output node N has a gate node electrically connected to it and is inductively coupled to the output node 104 of the optical drive circuit 100. N It has a drain node that is electrically connected to it. Bias node N bias In the illustrated example, it is electrically connected to the first supply node VDD1. The first n-type transistor 141 has a source node electrically connected to the drain node of the third n-type transistor 143. The third n-type transistor 143 has a gate node electrically connected to the first control node CTR_1 and a source node electrically connected to the ground node.

[0032] The pull-up circuit 150 includes a first p-type transistor 151 (e.g., a p-type FET), a second p-type transistor 152, and a third p-type transistor 153. The gate node of the first p-type transistor 151 is electrically connected to the output node N3 of the level-shift latch circuit 130 to receive the level-shift signal D high This is the input node of the pull-up circuit 150, which provides power to the pull-up circuit 150. The first p-type transistor 151 has a drain node that is electrically connected to the source node of the second p-type transistor 152. The second p-type transistor 152 has a bias node N bias Output node N has a gate node electrically connected to it and is inductively coupled to the output node 104 of the optical drive circuit 100. p The first p-type transistor 151 has a drain node electrically connected to the drain node of the third p-type transistor 153. The third p-type transistor 153 has a gate node electrically connected to the second control node CTR_2 and a source node electrically connected to the second supply node VDD2.

[0033] Generally, the first control signal CTR_1 applied to the first control node CTR_1 is the output signal D on the output node 104. out It can be used to control or adjust the falling edge transition of the output signal D, and the second control signal CTR_2 applied on the second control node CTR_2 is used to control the falling edge transition of the output signal D out It can be used to control or adjust the rising edge transition of the signal. More specifically, the pull-down circuit 140 controls the output signal D based on the first control signal CTR_1. out The pull-up circuit 150 may be configured to adjust the falling edge transition of the output signal D based on the second control signal CTR_2. out Adjust the rising edge transition. It can be configured as follows. In some embodiments, the pull-up circuit 150 and the pull-down circuit 140 are independent of each other, and the output signal D out The rising edge transitions and falling edge transitions can be controlled or adjusted, respectively.

[0034] The inductive circuit 160 includes a first inductor 161 and a second inductor 162 electrically connected between the pull-up circuit 150 and the pull-down circuit 140. As shown in Figure 1, the first inductor 161 is connected to the drain node (e.g., output node N) of the second p-type transistor 152. P The second inductor 162 is electrically connected between the drain node of the second n-type transistor 142 (for example, the output node N) and the output node 104. N ) is electrically connected to the output node 104. In some implementations, inductors 161 and 162 may each be the same size and shape, and may be stacked on top of each other within the integrated circuit chip on which the optical drive circuit 100 is disposed. In this way, inductors 161 and 162 may be electromagnetically coupled to each other, thereby resulting in mutual inductance between inductors 161 and 162 that can increase the overall inductance of the inductive circuit 160.

[0035] As mentioned above, input signal D in When the signal is driven to a high logic state (e.g., the first supply voltage VDD1 or nearby), inverter 122 drives output node N2 to a low logic state (e.g., ground potential), and inverter 132 drives output node N3 to a low logic state (e.g., the first supply voltage VDD1). Therefore, in such a situation, the non-level shift signal D low This is a low logic state (e.g., ground potential), and the level shift signal D high This is a low logic state (e.g., the first supply voltage VDD1).

[0036] Non-level shift signal D low Because the signal is low (for example, at ground potential), the first n-type transistor 141 is kept in a non-conductive or open state, thereby isolating the output node 104 from ground potential. Level shift signal D highWhen the signal is low (for example, the first supply voltage VDD1), the first p-type transistor 151 can be turned on and become either conductive or closed, and may be affected by the state of the third p-type transistor 153 resulting from the second control signal CTR_2. In addition, the first supply voltage VDD1 is applied to the gate node of the second p-type transistor 152, and therefore the second p-type transistor 152 can also be turned on and may be affected by the state of the third p-type transistor 153. As a result, both the first p-type transistor 151 and the second p-type transistor 152 may be conductive, and may pull the output node 104 towards the second supply voltage VDD2 through the first inductor 161.

[0037] Input signal D in When the signal is driven to a low logic state (e.g., ground potential or near it), inverter 122 drives output node N2 to a high logic state (e.g., first supply voltage VDD1), and inverter 132 drives output node N3 to a high logic state (e.g., second supply voltage VDD2). Thus, the non-level shift signal D low This is a high logic state (e.g., first supply voltage VDD1), and the level shift signal D high This is a high logic state (e.g., a second supply voltage VDD2).

[0038] Non-level shift signal D low When the voltage is high (for example, the first supply voltage VDD1), the first n-type transistor 141 can be turned on and become either conductive or closed, and may be affected by the state of the third n-type transistor 143 resulting from the first control signal CTR_1. In addition, the first supply voltage VDD1 is applied to the gate node of the second n-type transistor 142, and therefore the second n-type transistor 142 can also be turned on and may be affected by the state of the third n-type transistor 143. As a result, both the first n-type transistor 141 and the second n-type transistor 142 may be conductive, and may pull the output node 104 toward ground potential via the second inductor 162. T signal D highWhen the voltage is high (for example, the second supply voltage VDD2), the first p-type transistor 151 is kept in a non-conductive or open state, thereby isolating the output node 104 from the second supply voltage VDD2.

[0039] The optical driving circuit 100 is configured to increase the voltage amplitude of an electrical signal to a level more suitable for an optical signal, for example. More specifically, the input signal D in The output signal D generated by the optical drive circuit 100 has a voltage amplitude between the ground potential and the first supply voltage VDD1 (for example, 0V to 0.9V), but has a voltage amplitude between the ground potential and the first supply voltage VDD1. out This has a voltage amplitude between the ground potential and the second supply voltage VDD2 (for example, 0V to 1.8V).

[0040] The inductive circuit 160 can reduce or isolate parasitic capacitance in the pull-down circuit 140 and the pull-up circuit 150, thereby reducing the overall load capacitance of the optical drive circuit 100, and thus reducing the output signal D out This enables faster edge transitions in the output signal D. More specifically, the first inductor 161 controls the output signal D. out During the rising edge transition, the parasitic capacitance in the pull-up circuit 150 can be reduced or isolated, and the second inductor 162 controls the output signal D out During the falling edge transition, parasitic capacitance within the pull-down circuit 140 can be reduced or isolated. Therefore, at high data rates, the optical drive circuit 100 in Figure 1 can handle the output signal D out It may be possible to transition between the ground potential and the second supply voltage VDD2 (for example, between the logic low state and the logic high state, respectively) at a sufficiently fast rate. The inductive circuit 160 can be adapted to a relatively large output load capacitance associated with, for example, the TX bump 170 (which may be 70-90 fF in some implementations) and / or the electro-optic transducer 180.

[0041] In addition, nonlinear distortion caused by one or more components of the electro-optic transducer 180 affects the output signal D outThis can cause an asymmetric response to the rising and falling edges, which can result in the converted optical signal having asymmetric rising and falling edges. The optical drive circuit 100 can also compensate for the nonlinear distortion caused by the electro-optic transducer 180 by, for example, independently adjusting the rising and falling edge transitions of the output signal. In this way, the optical drive circuit disclosed herein can compensate for the asymmetric response of the electro-optic transducer to the rising and rising edge transitions of the output signal generated by the optical drive circuit.

[0042] In some examples, the first control signal CTR_1 and the second control signal CTR_2 are output signal D out This can be based at least partially on information showing the asymmetric response of the electro-optic transducer 180 to the rising edge transitions and falling edge transitions of the output signal D. out The rate of the rising edge transition and / or the output signal D out The rate of the falling edge transition is adjusted by the first control signal CTR_1 and the second control signal CTR_2, respectively, and the output signal D out This provides pre-emphasis and can compensate for the inherent nonlinearity of the electro-optic transducer 180.

[0043] The first control signal CTR_1 selectively adjusts the voltage applied to the gate node of the third n-type transistor 143, thereby causing the pull-down circuit 140 to output signal D out The rate at which the output node 104 is pulled down toward ground potential during the falling edge transition can be independently controlled or adjusted. For example, the voltage of the first control signal CTR_1 increases the current flow through the third n-type transistor 143, thereby increasing the output signal D out The voltage of the first control signal CTR_1 can be increased (to a higher positive voltage, etc.) to increase the rate of the falling edge transition, thereby reducing the current flow through the third n-type transistor 143, and thereby the output signal D outTo reduce the rate of the falling edge transition, it can be reduced (to a lower positive voltage, etc.). Similarly, the second control signal CTR_2 selectively adjusts the voltage applied to the gate node of the third p-type transistor 153. Then, the pull-up circuit 150 is connected to the output signal D out The rate at which the output node 104 is pulled towards the second supply voltage VDD2 during the rising edge transition can be independently controlled or adjusted. For example, the voltage of the second control signal CTR_2 increases the current flow through the third p-type transistor 153, thereby increasing the output signal D out The voltage of the second control signal CTR_2 can be reduced (to a less positive voltage, etc.) to increase the speed of the rising edge transition, thereby reducing the current flow through the third p-type transistor 153, and thereby the output signal D out The voltage can be increased (to a more positive voltage, etc.) to reduce the speed of the rising edge transition. In this way, the optical drive circuit 100 controls the output signal D out The rising edge transitions and falling edge transitions can be made to exhibit an asymmetry that compensates for the asymmetric response of the electro-optic transducer 180.

[0044] The first control signal CTR_1 and the second control signal CTR_2 may be generated by any suitable circuit provided within or coupled to the optical drive circuit 100. In the example shown in Figure 1, the optical drive circuit 100 is shown to include a memory 190 configured to provide or generate the first control signal CTR_1 and the second control signal CTR_2. The memory 190 may be any suitable memory circuit or storage device (such as non-volatile memory) capable of storing the voltage levels or values ​​indicating the voltage levels of the first control signal CTR_1 and the second control signal CTR_2. In some examples, the memory 190 may store multiple voltages or values ​​for each of the first control signal CTR_1 and the second control signal CTR_2. In some examples, the memory 190 may be coupled to one or more digital-to-analog converters (DACs) electrically coupled to the first control node CTR_1 and the second control node CTR_2. The voltage or value stored in memory 190 for the control signal CTR_2 may be based on the asymmetric response behavior of the electro-optic transducer 180. In some embodiments, the asymmetric response behavior of the electro-optic transducer 180 may be determined, for example, using an eye diagram. In other embodiments, the electro-optic transducer 180 may be based on the output signal D out A feedback signal can be provided that indicates its asymmetric response to rising edge transitions and falling edge transitions, and the feedback signal can be used to select and / or update the respective voltages or values ​​of the first control signal CTR_1 and the second control signal CTR_2 stored in memory 190.

[0045] The memory 190 can be programmed by the manufacturer of the optical drive circuit 100, by a tester of the optical drive circuit 100, by a user of the optical drive circuit 100, or by any combination thereof. In some embodiments, the memory 190 may be programmed in the field (by manual programming or over-the-air (OTA) updates, etc.) with suitable values ​​for the first control signal CTR_1 and the second control signal CTR_2. In addition, or alternatively, the values ​​for the first control signal CTR_1 and the second control signal CTR_2 stored in the memory 190 may be dynamically updated in the field.

[0046] In another embodiment, the memory 190 may be, for example, a look-up table (LUT) for storing a plurality of voltages or values ​​for each of a first control signal CTR_1 and a second control signal CTR_2 that can be selected in response to a selection signal. or may include the same. The selection signal may be based on or indicate a desired edge transition setting that compensates for the asymmetric response of the electro-optic transducer 180. In this way, the optical drive circuit 100 outputs the output signal D out This can provide a certain level of pre-emphasis to compensate for the nonlinearity in the electro-optic transducer 180.

[0047] In some examples, inductors 161, 162 and / or transistors 143, 153 (and corresponding memory 190) may be omitted. For example, in a level shifter circuit, transistors 143, 153 and memory 190 may be omitted if pre-distortion due to nonlinearity is not a concern. In such an example, the source node of the first n-type transistor 141 is The source node of the first p-type transistor 151 may be electrically connected to the ground node, and the source node of the first p-type transistor 151 may be electrically connected to the second supply node VDD2. Furthermore, the level shifter circuit may omit inductors 161, 162 if load capacitance and / or speed are not a concern. In such an example, the drain node of the second n-type transistor 142 may be electrically connected to the output node 104, and the drain node of the second p-type transistor 152 may be electrically connected to the output node 104. The level shifter circuit may be implemented, for example, between different power domains on the same integrated circuit chip, between different power domains on different integrated circuit chips, or in other applications.

[0048] Referring to the optical drive circuit 100 in general terms, the inverters 124 and 134 that provide self-bias in the non-level-shift latch circuit 120 and the level-shift latch circuit 130 respectively, receive the non-level-shift signal D low and level shift signal D high The appropriate common-mode voltage can be maintained for the non-level-shift latch circuit D (output from the non-level-shift latch circuit 120 and the level-shift latch circuit 130, respectively). Without inverters 124 and 134, when the supply voltage is reduced at high frequencies (e.g., 26.5 GHz or higher), the non-level-shift signal D low and level shift signal D high It was observed that the common-mode voltage decreased, and as a result, these signals became insufficient to pull up the voltage at output node 104 to pull-up circuit 150 and / or pull-down circuit 140, respectively. Therefore, at high frequencies with reduced supply voltage, without inverters 124, 134, the optical drive circuit does not pull up the output signal D at the output node. out It was observed that it could not be driven properly. When using inverters 124 and 134, the non-level shift signal D low and level shift signal D highThe common-mode voltage can be maintained at an appropriate level that allows the pull-up circuit 150 and pull-down circuit 140 to pull up and pull down the voltage at output node 104, respectively. Therefore, at high frequencies with reduced supply voltage, when inverters 124 and 134 are used, the optical drive circuit 100 can control the output signal D at output node 104. out It can be driven appropriately.

[0049] Furthermore, non-level shift signal D low and level shift signal D high The common-mode voltage can be maintained at different supply voltages over a wide frequency range. In this case as well, without inverters 124, 134, when the first supply voltage VDD1 is at the nominal voltage (e.g., VDD1 = 0.9), signal D low , D high The common-mode voltage was observed to drop to an unsuitable level at frequencies above approximately 29.4 GHz. Without inverters 124 and 134, the first supply voltage VDD1 was equal to the process voltage-temperature (PV). T) When reduced due to fluctuations, etc., the signal D low , D high The common-mode voltage drops to an unsuitable level at lower frequencies, such as above 29.4 GHz for VDD1 = 0.88 V and above 22.8 GHz for VDD1 = 0.86 V. When inverters 124 and 134 are used, signal D low , D high The common-mode voltage can be maintained at an appropriate level throughout the observed frequencies, such as up to 40 GHz.

[0050] As described above, in some examples, inverters 123 and 124 have the same driving capability, and inverters 133 and 134 have the same driving capability. This allows the latch nodes N1A and N1B of the non-level-shift latch circuit 120 and the level-shift latch circuit 130 to transition between a high logic state and a low logic state at high frequencies, and the output signal D outHowever, long sequences of low logic states (e.g., long sequences of logic "0") and long sequences of high logic states (e.g., long sequences of logic "1") are respectively input signal D in When input as such, it may be possible to maintain the respective voltages of the low and high logic states without droop. The ability to maintain the respective voltages of the low and high logic states without droop when a long sequence of low and high logic states is input indicates that the optical drive circuit 100 can operate at low frequencies, which indicates that the bandwidth (e.g., at lower frequencies) is not adversely affected. Note that in the example, inverters 123 and 124 may have different driving capacities, and inverters 133 and 134 may have different driving capacities. The same or similar effects can be achieved with inverters having different driving capacities by balancing having a driving capacity large enough to achieve the target common-mode voltage with a driving capacity small enough to allow each latch circuit to transition between the high and low states.

[0051] Figure 2 is a flowchart of Method 200 for operating an integrated circuit including a level shifter circuit, with some examples. Method 200 is described in relation to the optical drive circuit 100 in Figure 1. In the following description of Method 200 in relation to the optical drive circuit 100, it is assumed that the first control signal CTR_1 and the second control signal CTR_2 are set to appropriate values. Those skilled in the art will readily understand the applicability of the description of Method 200 to other level shifter circuits.

[0052] In block 202, the input signal is received at the input node of the level shifter circuit. For example, input signal D in This is received at input node 102. In some examples, input signal D in It has a voltage amplitude between the ground potential and the first supply voltage VDD1.

[0053] In block 204, the input signal is buffered through a buffer circuit. For example, input signal Din is input to the buffer circuit 110, and the buffered signal is output at the first node N1. In some examples, the buffered signal has a voltage amplitude between the ground potential and the first supply voltage VDD1.

[0054] In block 206, the buffered signal is input to the non-level-shift latch circuit and the level-shift latch circuit. For example, the signal on the first node N1 is input to the non-level-shift latch circuit 120 and the level-shift latch circuit 130. The non-level-shift latch circuit 120 includes a latch node N1A, and the level-shift latch circuit 130 includes a latch node N1B. The latch nodes N1A and N1B are electrically coupled to the first node N1 via respective capacitors 121 and 131, and are further electrically coupled to the input node 102 via the buffer circuit 110. The non-level-shift latch circuit 120 has a DC bias circuit (e.g., inverter 124) configured to be electrically connected to the latch node N1A and provide a bias voltage to the latch node N1A. The level-shift latch circuit 130 has a DC bias circuit (e.g., inverter 134) configured to be electrically connected to the latch node N1B and provide a bias voltage to the latch node N1B. The non-level-shift latch circuit 120 has a power node electrically connected to a ground node and a first supply node VDD1 that respectively provide the ground potential and the first supply voltage VDD1 to the non-level-shift latch circuit 120. The level-shift latch circuit 130 has a power node electrically connected to a first supply node VDD1 and a second supply node VDD2 that respectively provide the first supply voltage VDD1 and the second supply voltage VDD2 to the level-shift latch circuit 130. The second supply voltage VDD2 is greater than the first supply voltage VDD1.

[0055] In block 208, a non-level-shift signal is generated by the non-level-shift latch circuit based on the signal on the latch node of the non-level-shift latch circuit. For example, the non-level-shift latch circuit 120 generates a non-level-shift signal D based on the signal on the latch node N1A.low generates a non-level-shifted signal D low is, for example, the logical complement of the signal on the latch node N1A resulting from the inverter 122. In some examples, the non-level-shifted signal D low has a voltage amplitude between the ground potential and the first supply voltage VDD1.

[0056] In block 210, a level-shifted signal is generated by a level-shift latch circuit based on the signal on the latch node of the level-shift latch circuit. For example, the level-shift latch circuit 130 generates a level-shifted signal D high based on the signal on the latch node N1B. The level-shifted signal D high is, for example, the logical complement of the signal on the latch node N1B resulting from the inverter 132. In some examples, the level-shifted signal D high has a voltage amplitude between the first supply voltage VDD1 and the second supply voltage VDD2.

[0057] In block 212, an output signal is output from the output stage circuit, and the output signal is generated in response to the non-level-shifted signal and the level-shifted signal. For example, the output stage circuit includes a pull-down circuit 140 and a pull-up circuit 150. The pull-down circuit 140 is electrically connected between the ground node and the output node 104, and the pull-up circuit 150 is electrically connected between the output node 104 and the second supply node VDD2. The pull-down circuit 140 low responds to the non-level-shifted signal D low to pull down the voltage of the output node 104 and electrically isolate the output node 104 from the ground node. When the non-level-shifted signal D low is logically high, the pull-down circuit 140 pulls down the voltage of the output node 104 towards the ground potential, and when the non-level-shifted signal D highBased on this, the voltage of output node 104 is responsively pulled up, electrically isolating output node 104 from the second supply node VDD2. Level shift signal D high When logically low, the pull-up circuit 150 pulls up the voltage at output node 104 toward the second supply voltage VDD2, and the non-level shift signal D low When logically high, the pull-up circuit 150 electrically isolates the output node 104 from the second supply node VDD2. The voltage on the output node 104 is the output signal D out It forms the output signal D. In some examples, the output signal D out It has a voltage amplitude between the ground potential and the second supply voltage VDD2.

[0058] The above applies to specific examples, but other and further examples may be devised without departing from the basic scope, and the scope will be determined by the following "Claims".

Claims

1. It is an integrated circuit, A first latch circuit having a first latch node and a first output node, wherein the first latch node is electrically coupled to a signal input node, and the first latch circuit includes a first bias circuit electrically connected to the first latch node and configured to provide a bias voltage at the first latch node. A second latch circuit having a second latch node and a second output node, wherein the second latch node is electrically coupled to the signal input node, and the second latch circuit includes a second bias circuit electrically connected to the second latch node and configured to provide a bias voltage at the second latch node. An integrated circuit comprising: an output stage circuit having a first input node, a second input node, and a third output node, wherein the first input node is electrically connected to the first output node, the second input node is electrically connected to the second output node, and the output stage circuit is configured to responsively pull up and pull down the voltage of the third output node in response to the voltages of the first input node and the second input node, respectively.

2. The first latch circuit has a first power node and a second power node, the first power node is electrically connected to a first supply node, and the second power node is electrically connected to a second supply node. The second latch circuit has a third power node and a fourth power node, the third power node being electrically connected to the second supply node, and the fourth power node being electrically connected to the third supply node. The output stage circuit has a fifth power node and a sixth power node, the fifth power node being electrically connected to the first supply node, and the sixth power node being electrically connected to the third supply node. The integrated circuit according to claim 1, wherein the first supply node is configured to have a first supply voltage, the second supply node is configured to have a second supply voltage, and the third supply node is configured to have a third supply voltage, the second supply voltage being greater than the first supply voltage, and the third supply voltage being greater than the second supply voltage.

3. The first bias circuit each includes a first inverter having an input node and an output node electrically connected to the first latch node, The integrated circuit according to claim 1, wherein the second bias circuit includes a second inverter having an input node and an output node electrically connected to the second latch node.

4. The first latch circuit described above is A first inverter having an input node electrically connected to the first latch node and an output node electrically connected to the first output node, A second inverter having an input node electrically connected to the first output node and an output node electrically connected to the first latch node, In all cases, the input node and output node are electrically connected to the first latch node. The first bias circuit includes a third inverter, and the first bias circuit includes the third inverter. The second latch circuit described above is A fourth inverter having an input node electrically connected to the second latch node and an output node electrically connected to the second output node, The second output node has an input node electrically connected to the second latch node A fifth inverter having an output node electrically connected to the pedestrian, The integrated circuit according to claim 1, each comprising a sixth inverter having an input node and an output node electrically connected to the second latch node, wherein the second bias circuit includes the sixth inverter.

5. Each of the first inverter, the second inverter, and the third inverter has a first power node electrically connected to the first supply node, and each of the second power nodes electrically connected to the second supply node. The fourth inverter, the fifth inverter, and the third inverter each have a first power node electrically connected to the second supply node, and each have a second power node electrically connected to the third supply node. The output stage circuit is, A pull-down circuit electrically connected between the third output node and the first supply node, wherein the pull-down circuit has a first input node, A pull-up circuit electrically connected between the third output node and the third supply node, the pull-up circuit having the second input node, includes a pull-up circuit, The first supply node is configured to have a first supply voltage, The second supply node is configured to have a second supply voltage that is greater than the first supply voltage. The integrated circuit according to claim 4, wherein the third supply node is configured to have a third supply voltage greater than the second supply voltage.

6. The second inverter and the third inverter have the same driving capacity. The integrated circuit according to claim 4, wherein the fifth inverter and the sixth inverter have the same driving capability.

7. The output stage circuit is, A pull-down circuit electrically connected between the third output node and the first supply node, wherein the pull-down circuit has a first input node and the first supply node is configured to have a first supply voltage, The integrated circuit according to claim 1, comprising: a pull-up circuit electrically connected between the third output node and the second supply node, wherein the pull-up circuit has a second input node and the second supply node is configured to have a second supply voltage greater than the first supply voltage.

8. The pull-down circuit includes an n-type transistor having a source node and a drain node electrically connected between the third output node and the first supply node, the gate node of the n-type transistor being electrically connected to the first input node, The integrated circuit according to claim 7, wherein the pull-up circuit includes a p-type transistor having a source node and a drain node electrically connected between the third output node and the second supply node, and the gate node of the p-type transistor is electrically connected to the second input node.

9. An integrated circuit comprising a level shifter circuit, wherein the level shifter circuit is A non-level-shift latch circuit having a first latch node and a first output node, wherein the first latch node is electrically coupled to a signal input node of the level shifter circuit, and the non-level-shift latch circuit includes a first DC bias circuit configured to provide a first DC bias voltage at the first latch node. A latch circuit and An integrated circuit comprising: a level shift latch circuit having a second latch node and a second output node, wherein the second latch node is electrically coupled to the signal input node of the level shifter circuit, and the level shift latch circuit includes a second DC bias circuit configured to provide a second DC bias voltage at the second latch node.

10. The aforementioned level shifter circuit is A pull-down circuit electrically connected to the output node of the level shifter circuit, wherein the pull-down circuit is configured to pull down the voltage of the output node of the level shifter circuit in response to the voltage of the first output node, The integrated circuit according to claim 9, further comprising: a pull-up circuit electrically connected to the output node of the level shifter circuit, wherein the pull-up circuit is configured to pull up the voltage of the output node of the level shifter circuit in response to the voltage of the second output node.

11. The first DC bias circuit each includes a first inverter having an input node and an output node electrically connected to the first latch node, The integrated circuit according to claim 9, wherein the second DC bias circuit includes a second inverter having an input node and an output node electrically connected to the second latch node.

12. The non-level-shift latch circuit has power nodes electrically connected to a first supply node and a second supply node, the first supply node is configured to have a first supply voltage, the second supply node is configured to have a second supply voltage greater than the first supply voltage, and the non-level-shift latch circuit is configured to output a signal having a voltage amplitude between the first supply voltage and the second supply voltage on the first output node. The integrated circuit according to claim 9, wherein the level shift latch circuit has power nodes electrically connected to the second supply node and the third supply node, the third supply node is configured to have a third supply voltage greater than the second supply voltage, and the level shift latch circuit is configured to output a signal having a voltage amplitude between the second supply voltage and the third supply voltage on the second output node.

13. The level shifter circuit further includes an output stage circuit, and the output stage circuit is A pull-down circuit electrically connected between the first supply node and the output node of the level shifter circuit, The integrated circuit according to claim 12, comprising a pull-up circuit electrically connected between the output node of the level shifter circuit and the third supply node, wherein the output stage circuit is configured to output an output signal having a voltage amplitude between the first supply voltage and the third supply voltage on the output node of the level shifter circuit.

14. The integrated circuit according to claim 9, wherein the level shifter circuit further includes a buffer circuit having an input node electrically connected to the signal input node and an output node electrically coupled to the first latch node and the second latch node.

15. A method for operating an integrated circuit, wherein the method is The input node receives an input signal, the input node is electrically coupled to a first latch node and a second latch node, and the non-level-shift latch circuit is connected to the first latch node and a first DC battery electrically connected to the first latch node. The level shift latch circuit includes an ass circuit and a second DC bias circuit electrically connected to the second latch node, Based on the signal on the first latch node, the non-level-shifted latch circuit generates a non-level-shifted signal, Based on the signal on the second latch node, the level shift latch circuit generates a level shift signal, A method comprising outputting an output signal from an output stage circuit, wherein the output stage circuit generates the output signal in response to the non-level shift signal and the level shift signal.

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