Indication device

Abstract

To provide a display device that reduces the amount of image data transmitted while maintaining high display quality. [Solution] A display device having a display unit, a light-emitting unit, and a light-receiving unit. The display unit has a first display area and a first circuit area that overlap each other. The first display area has a plurality of first display pixels, and the first circuit area has a first driver circuit. The first driver circuit is electrically connected to each of the plurality of first display pixels via a plurality of first wirings that extend to the first display area. The light-emitting unit has the function of emitting first light, and the light-receiving unit has the function of detecting second light reflected when the first light is irradiated onto a subject, and the function of generating information based on the second light. The first driver circuit has the function of either transmitting a plurality of image signals to each of the plurality of first wirings, or transmitting the same image signal to two or more consecutively adjacent wirings among the plurality of first wirings, according to the information.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device and an electronic device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, methods for driving them, methods for manufacturing them, or methods for inspecting them. [Background technology]

[0003] In recent years, various improvements have been made to the display devices used in XR (Extended Reality or Cross Reality) devices such as VR (Virtual Reality) and AR (Augmented Reality), as well as mobile phones such as smartphones, tablet computers, and notebook PCs (personal computers). For example, development is underway to increase screen resolution, improve color reproduction (NTSC ratio), reduce the size of the drive circuit, and lower power consumption.

[0004] In particular, for XR-oriented electronic devices, increasing the pixel density (resolution) and color reproduction capabilities of the display device can make the displayed image sharper and enhance its sense of realism. Furthermore, Patent Document 1 discloses a high-pixel-count, high-resolution display device equipped with an organic EL light-emitting device.

[0005] Furthermore, eye-tracking technology is attracting attention in XR-oriented electronic devices. Eye-tracking is a method of measuring the movement of a user's eyeballs and tracking where the user is looking. Eye-tracking is expected to have applications in areas such as sports, education, marketing, hazard detection, health management, and user interfaces for electronic devices. For this reason, various eye-tracking methods have been proposed in recent years. For example, Patent Document 2 discloses an improved corneal reflection method (PCCR method) that calculates eye movement from images taken of the reflection point of the light and the pupil after irradiating light onto the cornea.

[0006] Furthermore, development is underway to add new functions to display devices by providing circuits other than the display pixel circuit in the display area of ​​the display device. For example, Patent Document 3 discloses a display device in which an imaging pixel circuit is included in addition to the display pixel circuit in the display area, and a method for detecting the eye or the area around the eye as an image using the display device. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] International Publication No. 2019 / 220278 [Patent Document 2] U.S. Patent Application Publication No. 2006 / 0238707 [Patent Document 3] International Publication No. 2019 / 243955 [Overview of the project] [Problems that the invention aims to solve]

[0008] As the resolution of a display device increases, the number of pixels it contains also increases. Displaying an image on a display device requires writing image data to each individual pixel, thus increasing the number of image signals, including image data, input to the device. In other words, the more pixels a display device has, the higher the amount of image data transmitted to it, potentially increasing the load on the interface used to input image data to the display device.

[0009] One aspect of the present invention aims to provide a display device with high display quality. Alternatively, one aspect of the present invention aims to provide a display device capable of reducing the amount of image data transmitted. Alternatively, one aspect of the present invention aims to provide an electronic device having the above-described display device. Alternatively, one aspect of the present invention aims to provide a novel display device or a novel electronic device.

[0010] Furthermore, the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention solves at least one of the problems listed above and other problems. Furthermore, one aspect of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0011] (1) One aspect of the present invention is a display device having a display unit, a light-emitting unit, a light-receiving unit, and a control unit. The display unit has a first display area and a first circuit area, the first display area being located in an area overlapping the first circuit area. The first display area has a plurality of first display pixels, and the first circuit area has a first driver circuit. The first driver circuit is electrically connected to a plurality of first wirings extending to the first display area, and each of the plurality of first display pixels is electrically connected to the plurality of first wirings. The light-receiving unit is electrically connected to the control unit, and the control unit is electrically connected to the first driver circuit. The light-emitting unit has the function of emitting first light. The light-receiving unit has the function of detecting second light reflected when the first light is irradiated onto an object, and the function of generating information based on the second light and transmitting the information to the control unit. The control unit has the function of generating a first signal based on the information and transmitting the first signal to the first driver circuit. Furthermore, the first driver circuit has the function of either transmitting multiple image signals to each of the multiple first wires in response to the first signal, or transmitting the same image signal to two or more consecutively adjacent wires among the multiple first wires.

[0012] (2) Alternatively, in one aspect of the present invention, the display unit in (1) above may have a configuration having a second display area and a second circuit area. In particular, it is preferable that the second display area is located in an area that overlaps with the second circuit area. Furthermore, it is preferable that the second display area has a plurality of second display pixels, and the second circuit area has a second driver circuit. Furthermore, it is preferable that the second driver circuit is electrically connected to a plurality of second wirings extending to the second display area, each of the plurality of second display pixels is electrically connected to the plurality of second wirings, and the control unit is electrically connected to the second driver circuit. Furthermore, it is preferable that the control unit has the function of generating a second signal based on information and transmitting the second signal to the second driver circuit, and it is preferable that the second driver circuit has the function of transmitting a plurality of image signals to each of the plurality of second wirings in response to the first signal, or transmitting the same image signal to two or more consecutively adjacent wirings among the plurality of second wirings. Furthermore, in the first display area, the number of first display pixels on which one image signal is written is different from the number of second display pixels on which one image signal transmitted to the second display area is written.

[0013] (3) Alternatively, one aspect of the present invention is a display device having a display unit, a light-emitting unit, a light-receiving unit, and a control unit. The display unit has a first display area and a first circuit area, the first display area being located in an area overlapping the first circuit area. The first display area has a plurality of first display pixels, and the first circuit area has a first driver circuit. The first driver circuit is electrically connected to a plurality of first wirings extending to the first display area, and each of the plurality of first display pixels is electrically connected to the plurality of first wirings. The light-receiving unit is electrically connected to the control unit, and the control unit is electrically connected to the first driver circuit. The light-emitting unit has the function of emitting first light. The light-receiving unit has the function of detecting second light reflected when the first light is irradiated onto an object, and the function of generating information based on the second light and transmitting the information to the control unit. The control unit has the function of generating a first signal based on the information and transmitting the first signal to the first driver circuit. Furthermore, the first driver circuit has the function of transmitting an image signal to each of the multiple first wires at a first frame frequency corresponding to the first signal.

[0014] (4) Alternatively, in one aspect of the present invention, the display unit in (3) above may have a configuration having a second display area and a second circuit area. In particular, it is preferable that the second display area is located in an area that overlaps with the second circuit area. Furthermore, it is preferable that the second display area has a plurality of second display pixels, and the second circuit area has a second driver circuit. Furthermore, it is preferable that the second driver circuit is electrically connected to a plurality of second wirings extending to the second display area, each of the plurality of second display pixels is electrically connected to the plurality of second wirings, and the control unit is electrically connected to the second driver circuit. Furthermore, it is preferable that the control unit has the function of generating a second signal based on information and transmitting the second signal to the second driver circuit, and it is preferable that the second driver circuit has the function of transmitting an image signal to each of the plurality of second wirings at a second frame frequency corresponding to the second signal. The first frame frequency shall be different from the second frame frequency.

[0015] (5) Alternatively, in one aspect of the present invention, in any one of (1) to (4) above, the first driver circuit may have a transistor that includes silicon in its channel formation region, and the first display pixel may have a transistor that includes a metal oxide in its channel formation region.

[0016] (6) Alternatively, in one aspect of the present invention, in any one of (1) to (5) above, the first display pixel may have a light-emitting device that includes an organic EL material.

[0017] (7) Alternatively, in one aspect of the present invention, in any one of (1) to (6) above, the first light and the second light may be visible light, or the first light and the second light may be infrared light.

[0018] (8) Alternatively, one aspect of the present invention is an electronic device having any one of the display devices described in (1) to (7) above, and a housing. The housing is shaped to be wearable on the user's head. [Effects of the Invention]

[0019] According to one aspect of the present invention, a display device with high display quality can be provided. Alternatively, according to one aspect of the present invention, a display device capable of reducing the amount of image data transmitted can be provided. Alternatively, according to one aspect of the present invention, an electronic device having the above-described display device can be provided. Alternatively, according to one aspect of the present invention, a novel display device or a novel electronic device can be provided.

[0020] Furthermore, the effects of one aspect of the present invention are not limited to those listed above. The effects listed above do not preclude the existence of other effects. These other effects are those described below and not mentioned in this section. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may, in some cases, not have the effects listed above. [Brief explanation of the drawing]

[0021] [Figure 1] Figures 1A and 1B are block diagrams showing an example configuration of a display device. [Figure 2] Figures 2A to 2C are schematic cross-sectional diagrams showing examples of the configuration of the display unit of a display device. [Figure 3] Figure 3A is a schematic plan view showing an example of the display unit of a display device, and Figure 3B is a schematic plan view showing an example of the drive circuit area of ​​a display device. [Figure 4] Figures 4A and 4B are schematic plan views showing examples of the configuration of the display unit of a display device. [Figure 5] Figure 5 is a block diagram showing an example of a circuit included in a display device. [Figure 6] Figure 6 is a block diagram showing an example of a circuit included in a display device. [Figure 7] Figure 7 is a block diagram showing an example of a display area included in a display device. [Figure 8] Figures 8A and 8B are circuit diagrams showing an example of a circuit included in a display device. [Figure 9] Figure 9 is a circuit diagram showing an example of a circuit included in a display device. [Figure 10] Figures 10A and 10B show an example in which the display surface of a display device is divided into multiple regions. [Figure 11]Figure 11A shows an example of dividing the display plane of a display device into multiple regions, and Figure 11B shows an example of the display plane of a display device. [Figure 12] Figures 12A and 12C show a portion of the plan view of the display unit of the display device, while Figures 12B and 12D are graphs showing an example of the amount of image data transmitted to each display area of ​​the display device. [Figure 13] Figures 13A and 13B show an example in which the display surface of a display device is divided into multiple regions. [Figure 14] Figure 14A shows an example of dividing the display plane of a display device into multiple regions, and Figure 14B shows an example of the display plane of a display device. [Figure 15] Figure 15 is a block diagram showing an example of the display unit configuration. [Figure 16] Figure 16 is a graph showing an example of the amount of image data input to a display device. [Figure 17] Figure 17 shows an example of the timing at which image data is input to each circuit of the display device. [Figure 18] Figures 18A and 18B show examples of electronic devices to which a display device is applied. [Figure 19] Figure 19A is a diagram showing an example of an electronic device to which a display device is applied, and Figures 19B and 19C illustrate examples of light paths between the display unit of the electronic device and the user's eyes. [Figure 20] Figure 20 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 21] Figures 21A to 21C are schematic cross-sectional views showing a portion of the configuration of a display device. [Figure 22] Figure 22 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 23] Figure 23 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 24] Figure 24 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 25]Figure 25 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 26] Figure 26 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 27] Figure 27 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 28] Figure 28 is a schematic cross-sectional view showing an example of the configuration of a display device. [Figure 29] Figures 29A to 29F show examples of the configuration of a light-emitting device. [Figure 30] Figures 30A to 30C show examples of the configuration of a light-emitting device. [Figure 31] Figure 31A is a circuit diagram showing an example of the configuration of a pixel circuit included in a display device, and Figure 31B is a schematic perspective view showing an example of the configuration of a pixel circuit included in a display device. [Figure 32] Figures 32A to 32D are circuit diagrams showing example configurations of pixel circuits included in a display device. [Figure 33] Figures 33A to 33D are circuit diagrams showing examples of the configuration of pixel circuits included in a display device. [Figure 34] Figures 34A to 34G are plan views showing an example of a pixel. [Figure 35] Figures 35A to 35F are plan views showing an example of a pixel. [Figure 36] Figures 36A to 36H are plan views showing an example of a pixel. [Figure 37] Figures 37A to 37D are plan views showing an example of a pixel. [Figure 38] Figure 38A is a schematic plan view showing an example of a transistor configuration, while Figures 38B and 38C are schematic cross-sectional views showing an example of a transistor configuration. [Figure 39] Figures 39A and 39B show examples of the configuration of a display module. [Figure 40] Figures 40A to 40F are diagrams showing examples of the configuration of electronic equipment. [Figure 41] Figures 41A to 41D are diagrams showing examples of the configuration of electronic equipment. [Figure 42] Figures 42A to 42C are diagrams showing examples of the configuration of electronic equipment. [Figure 43] Figures 43A to 43E show examples of the configuration of electronic equipment. [Figure 44] Figure 44 is a cross-sectional photograph of the display device used in the embodiment. [Figure 45] Figure 45 is a graph showing the gate-source voltage-drain current characteristics of the transistors in the display device used in the embodiment. [Figure 46] Figure 46 is a schematic perspective view of the display device used in the embodiment. [Figure 47] Figure 47 is a photograph showing an image displayed on the display device used in the embodiment. [Figure 48] Figure 48A is a block diagram showing the configuration of the display unit used in the embodiment, and Figure 48B is a diagram showing the display area of ​​the display unit used in the embodiment. [Figure 49] Figure 49 is a graph showing the power consumption of the display device estimated in the example. [Modes for carrying out the invention]

[0022] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (e.g., transistors, diodes, and photodiodes), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are all examples of semiconductor devices. Furthermore, for example, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may be semiconductor devices themselves or may have semiconductor devices.

[0023] Furthermore, when it is stated in this specification that X and Y are connected, it is assumed that this specification discloses the cases in which X and Y are electrically connected, functionally connected, and directly connected. Therefore, it is assumed that the disclosed connections are not limited to predetermined connections, such as those shown in the figures or text, but also include connections other than those shown in the figures or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0024] One example of a case where X and Y are electrically connected is that one or more elements that enable the electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, display devices, light-emitting devices, and loads) can be connected between X and Y. Note that a switch has the function of being controlled to be on or off. In other words, a switch has the function of controlling whether or not current flows by being in a conductive state (on state) or a non-conductive state (off state).

[0025] One example of a functionally connected X and Y is when one or more circuits that enable the functional connection between X and Y (for example, logic circuits (e.g., inverters, NAND gates, or NOR gates), signal conversion circuits (e.g., digital-to-analog converters, analog-to-digital converters, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as boost or buck converters, or level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplification circuits (e.g., circuits that can increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, or buffer circuits), signal generation circuits, memory circuits, or control circuits) are connected between X and Y. Note that, as an example, even if another circuit is placed between X and Y, if a signal output from X is transmitted to Y, X and Y are considered functionally connected.

[0026] Furthermore, when it is explicitly stated that X and Y are electrically connected, this includes both cases where X and Y are electrically connected (i.e., connected with another element or circuit in between) and cases where X and Y are directly connected (i.e., connected without another element or circuit in between).

[0027] Furthermore, this specification deals with circuit configurations in which multiple elements are electrically connected to wiring (wiring that supplies a constant potential or wiring that transmits a signal). For example, if X and wiring are directly connected, and Y and the wiring are directly connected, this specification may state that X and Y are directly electrically connected.

[0028] Furthermore, for example, it can be expressed as, "X, Y, the source (which may be rephrased as either the first or second terminal) and the drain (which may be rephrased as either the first or second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, transistor source, transistor drain, and Y." Or, "The source of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to Y, and X, transistor source, transistor drain, and Y are electrically connected in this order." Or, "X is electrically connected to Y via the source and drain of the transistor, and X, transistor source, transistor drain, and Y are provided in this connection order." By specifying the order of connections in the circuit configuration using similar methods of expression as these examples, the source and drain of the transistor can be distinguished and their technical scope can be determined. Note that these methods of expression are examples and are not limited to these methods of expression. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0029] Even if independent components are shown as electrically connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both a wire and an electrode. Therefore, in this specification, "electrically connected" includes cases where a single conductive film possesses the functions of multiple components.

[0030] Furthermore, in this specification, "resistive element" can refer to, for example, a circuit element having a resistance value higher than 0Ω, or wiring having a resistance value higher than 0Ω. Therefore, in this specification, "resistive element" includes wiring having a resistance value, a transistor, diode, or coil through which current flows between the source and drain. Therefore, the term "resistive element" may be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, terms such as "resistance," "load," or "region having a resistance value" may be replaced with the term "resistive element." The resistance value can be, for example, preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Also, for example, 1Ω or more and 1 × 10 9 It may also be less than or equal to Ω.

[0031] Furthermore, in this specification, "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Also, the terms "capacitive element," "parasitic capacitance," and "gate capacitance" may be replaced with the term "capacitance." Conversely, the term "capacitance" may be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." In addition, "capacitance" (including "capacitance" with three or more terminals) has a configuration that includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" may be replaced with terms such as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Also, the terms "one of the pair of terminals" or "the other of the pair of terminals" may be referred to as the first terminal or the second terminal, respectively. The capacitance value may be, for example, 0.05fF or more and 10pF or less. Alternatively, it may be, for example, 1pF or more and 10μF or less.

[0032] Furthermore, in this specification, a transistor has three terminals called the gate, source, and drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as either the source or the drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the potential applied to the three terminals of the transistor, one of the two input and output terminals becomes the source and the other becomes the drain. For this reason, in this specification, the terms source and drain may be interchangeable. Also, in this specification, when describing the connection relationships of a transistor, the notation "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) is used. Depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification, one of the gate or back gate of the transistor may be called the first gate, and the other of the gate or back gate of the transistor may be called the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, if a transistor has three or more gates, in this specification, each gate may be referred to as the first gate, second gate, third gate, and so on.

[0033] For example, in this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). Alternatively, the multi-gate structure allows for a voltage-current characteristic with a flat slope, where the current between the drain and source does not change much even when the voltage between the drain and source changes during operation in the saturation region. By utilizing this flat voltage-current characteristic, an ideal current source circuit or an active load with a very high resistance can be realized. As a result, a differential circuit or current mirror circuit with good characteristics can be realized.

[0034] Furthermore, in this specification, circuit elements such as "light-emitting devices" and "light-receiving devices" may have polarities called "anode" and "cathode." In the case of a "light-emitting device," it may be possible to make the "light-emitting device" emit light by applying a forward bias (applying a positive potential relative to the "cathode" to the "anode"). In the case of a "light-receiving device," it may be possible to generate a current between the "anode" and "cathode" by applying a zero bias or a reverse bias (applying a negative potential relative to the "cathode" to the "anode") and irradiating the "light-receiving device" with light. As described above, the "anode" and "cathode" may be treated as input / output terminals in circuit elements such as "light-emitting devices" and "light-receiving devices." In this specification, the "anode" and "cathode" in circuit elements such as "light-emitting devices" and "light-receiving devices" may be referred to as terminals (first terminal, second terminal, etc.). For example, one of the "anode" or "cathode" may be referred to as the first terminal, and the other as the second terminal.

[0035] Furthermore, even if a single circuit element is depicted in a circuit diagram, that element may actually comprise multiple circuit elements. For example, if one resistor is shown in a circuit diagram, it includes cases where two or more resistors are electrically connected in series. Similarly, if one capacitor is shown in a circuit diagram, it includes cases where two or more capacitors are electrically connected in parallel. Similarly, if one transistor is shown in a circuit diagram, it includes cases where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Likewise, if one switch is shown in a circuit diagram, it includes cases where the switch has two or more transistors, and these two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

[0036] Furthermore, in this specification, the term "node" can be replaced with "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on the circuit configuration and device structure. Also, "terminal" or "wiring" can be replaced with "node."

[0037] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0038] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are both described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are both described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0039] Furthermore, "electric current" refers to the phenomenon of electric charge movement (electrical conduction). For example, the statement "electrical conduction of positively charged elements is occurring" can be rephrased as "electrical conduction of negatively charged elements is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of electric charge movement associated with the movement of carriers (electrical conduction). Examples of carriers include electrons, holes, anions, cations, or complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, or vacuum). In addition, the "direction of current" in wiring, etc., is the direction in which positively charged carriers move and is expressed as a positive current quantity. In other words, the direction in which negatively charged carriers move is the opposite direction to the direction of the current and is expressed as a negative current quantity. Therefore, in this specification, if there is no specification regarding the positive or negative (or direction) of the current, the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0040] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0041] Furthermore, in this specification, phrases indicating placement such as "above" and "below" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases explained in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0042] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or directly below and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Similarly, for example, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Similarly, for example, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0043] Furthermore, in this specification, terms such as "rows" and "columns" may be used to describe matrix-like arrangements of components and their positional relationships. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terminology used is not limited to that described in the specification and can be appropriately rephrased depending on the context. For example, the expression "row direction" can sometimes be rephrased as "column direction" by rotating the orientation of the drawing shown by 90 degrees.

[0044] Furthermore, in this specification, wiring that electrically connects components arranged in a matrix can extend in the row direction or the column direction. For example, if this specification describes that "wiring A extends in the row direction," wiring A may also extend in the column direction. Similarly, if it describes that "wiring A extends in the column direction," wiring A may also extend in the row direction. In other words, the direction in which wiring that electrically connects components arranged in a matrix extends is not limited to the directions described in this specification, but may extend in the row direction or the column direction.

[0045] Furthermore, in this specification, the terms "film" and "layer" can be interchanged as needed. For example, the term "conductive layer" may be changed to "conductive film." Or, for example, the term "insulating film" may be changed to "insulating layer." Alternatively, depending on the circumstances, the terms "film" and "layer" can be omitted and replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to "conductor." Or, for example, the terms "insulating layer" or "insulating film" may be changed to "insulator."

[0046] Furthermore, in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, the terms "electrode," "wiring," or "terminal" may be replaced with the term "region" in some cases.

[0047] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" can be interchanged depending on the circumstances or situation. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line." The same applies in reverse, where terms such as "signal line" or "power line" can be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Similarly, the same applies in reverse, where terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances or situation. Similarly, the term "signal" may be changed to the term "potential."

[0048] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, if a metal oxide is included in the channel formation region of a transistor, that metal oxide may be referred to as an oxide semiconductor. In other words, if a metal oxide can constitute the channel formation region of a transistor having at least one of amplification, rectification, and switching functions, that metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor.

[0049] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Alternatively, metal oxides containing nitrogen may be called metal oxynitrides.

[0050] Furthermore, in this specification, semiconductor impurities refer to elements other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities can cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is a silicon layer, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0051] In this specification, a switch refers to a device that has the function of controlling whether or not to allow current to flow by being in a conductive (on) state or a non-conductive (off) state. Alternatively, a switch refers to a device that has the function of selecting and switching the path through which current flows. Therefore, a switch may have two or more terminals for conducting current in addition to control terminals. Examples include electrical switches and mechanical switches. In other words, a switch is not limited to any particular type, as long as it can control current.

[0052] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state where, for example, the source and drain electrodes of the transistor can be considered electrically short-circuited, or a state where current can flow between the source and drain electrodes. Conversely, the "non-conducting state" of the transistor refers to a state where the source and drain electrodes of the transistor can be considered electrically disconnected. When a transistor is used simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0053] One example of a mechanical switch is a switch that uses MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and it operates by controlling the conduction and non-conductivity through the movement of these electrodes.

[0054] Furthermore, in this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Also, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0055] In this specification, a structure in which different light-emitting layers are created or painted for each color of light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. Also, in this specification, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. A white light-emitting device can be combined with a colored layer (for example, a color filter) to create a full-color display device.

[0056] Furthermore, light-emitting devices can be broadly classified into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and it is preferable that the light-emitting unit includes one or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers should be selected such that the light-emitting colors of each layer are complementary. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. Also, when obtaining white light emission using three or more light-emitting layers, the light-emitting device should be configured so that the light-emitting colors of the three or more layers combine to emit white light as a whole.

[0057] A tandem device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, the device should be configured such that the light from the light-emitting layers of the multiple light-emitting units is combined to produce white light emission. The configuration for obtaining white light emission is the same as that for a single-structure device. In a tandem device, it is preferable to provide an intermediate layer, such as a charge-generating layer, between the multiple light-emitting units.

[0058] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem structure) with SBS structure light-emitting devices, SBS structure light-emitting devices can consume less power than white light-emitting devices. If you want to keep power consumption low, it is preferable to use SBS structure light-emitting devices. On the other hand, white light-emitting devices are preferable because their manufacturing process is simpler than that of SBS structure light-emitting devices, which can lead to lower manufacturing costs or higher manufacturing yields.

[0059] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at an angle of 60° or more and 120° or less.

[0060] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configuration examples are shown within one embodiment, these configuration examples can be appropriately combined with each other.

[0061] Furthermore, any content described in one embodiment (even partial content) may be applied to, combined with, or substituted for at least one of the contents described in another embodiment (even partial content) and one or more other embodiments (even partial content).

[0062] The content described in the embodiments refers to the content described using various figures or the content described using text in the specification in each embodiment.

[0063] Furthermore, a diagram (even a part of it) described in one embodiment can be combined with another part of that diagram, another diagram (even a part of it) described in the same embodiment, and at least one diagram (even a part of it) described in one or more other embodiments to form even more diagrams.

[0064] The embodiments described herein are explained with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Therefore, the present invention is not to be interpreted as being limited to the contents described in the embodiments. In the configuration of the invention in the embodiments, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. Also, in perspective views and the like, some components may be omitted in order to ensure clarity of the drawings.

[0065] Furthermore, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view is, for example, a diagram showing a view of the configuration from a direction perpendicular to the horizontal plane, or a diagram showing a cross-section of the configuration in the horizontal direction (either of these may be referred to as a plan view). In addition, hidden lines (e.g., dashed lines) may be included in the plan view to show the positional relationships of multiple elements included in the configuration, or the relationships of overlap of such multiple elements. In this specification, the term "plan view" may be replaced with the terms "projection view," "top view," or "bottom view." Also, depending on the situation, a cross-section of the configuration in a direction other than the horizontal direction may be referred to as a plan view.

[0066] Furthermore, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view is, for example, a diagram showing a view of the configuration from a direction perpendicular to the horizontal plane, or a diagram showing a view of the configuration cut in a direction perpendicular to the horizontal plane (either of these views may be called a cross-sectional view). In this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Also, depending on the situation, a cross-sectional view may refer to a view of the configuration cut in a direction other than the vertical direction, rather than a view of the configuration cut in a vertical direction.

[0067] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". In addition, in drawings, etc., when an identifying numeral such as "_1", "[n]", or "[m,n]" is accompanied by a reference numeral, the identifying numeral may be omitted in this specification if it is not necessary to distinguish them.

[0068] Furthermore, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, they may include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences.

[0069] (Embodiment 1) This embodiment describes a display device according to one aspect of the present invention.

[0070] <Example of display device configuration> Figure 1A is a block diagram showing an example configuration of a display device DP according to one aspect of the present invention.

[0071] The display device DP includes, as an example, a display unit DIS, an imaging light-emitting unit SHB, an imaging light-receiving unit SJB, and a control unit CTL.

[0072] Furthermore, the display unit DIS includes, as an example, a pixel array ALP, a drive circuit area DRV, and an interface IF.

[0073] The pixel array ALP is electrically connected to the drive circuit region DRV. The drive circuit region DRV is electrically connected to the interface IF and the control unit CTL. The imaging light-receiving unit SJB is also electrically connected to the control unit CTL.

[0074] The pixel array ALP, as an example, has multiple display pixels (for example, display pixels PX[1,1] to display pixels PX[m,n] in Figure 5 described later).

[0075] The drive circuit region (DRV) includes, for example, a drive circuit for driving multiple display pixels included in the pixel array (ALP). A specific configuration example of the drive circuit region (DRV) will be described later.

[0076] The interface (IF), for example, has the function of incorporating image data for displaying images on the display device (DP), which is output from a device located outside the display device (DP), into the drive circuit area (DRV). Examples of such external devices include recording media players, HDDs (Hard Disk Drives), and SSDs (Solid State Drives).

[0077] Furthermore, a GPU (Graphics Processing Unit) may be provided between the drive circuit area DRV and an externally located device. The GPU may be located inside the display device DP or outside the display device DP. If the GPU is located inside the display device DP, it may be integrated inside the interface IF.

[0078] The imaging light-receiving unit SJB has, for example, the function of capturing an image of a subject. Therefore, the imaging light-receiving unit SJB has a light-receiving device such as a photoelectric conversion element (pn-type or pin-type photodiode). In particular, when the display device DP is applied to an electronic device for XR, the subject can be the eyes of the user wearing the electronic device. That is, the imaging light-receiving unit SJB has the function of capturing an image of the user's eyes. The imaging light-receiving unit SJB also has the function of transmitting information about the captured image (e.g., current amount or potential) to the control unit CTL. For example, the light-receiving device of the imaging light-receiving unit SJB generates a charge corresponding to the amount of light incident on the light-receiving device, and the amount of current corresponding to that charge is transmitted to the control unit CTL.

[0079] The imaging light-emitting unit SHB functions, for example, as a light source for illuminating the subject of the imaging light-receiving unit SJB. Therefore, the imaging light-emitting unit SHB has a light-emitting device.

[0080] Furthermore, the light emitted by the imaging light-emitting unit SHB may be visible light or infrared light (sometimes called IR). Also, the light-receiving devices included in each of the imaging light-receiving units SJB can be determined according to the light emitted by the light-emitting device of the imaging light-emitting unit SHB. For example, if the light-emitting device of the imaging light-emitting unit SHB emits visible light, the light-receiving device should be a light-receiving device capable of receiving visible light. Also, for example, if the light-emitting device of the imaging light-emitting unit SHB emits infrared light, the light-receiving device should be a light-receiving device capable of receiving infrared light.

[0081] The control unit CTL, for example, has the function of performing image analysis on the image (user's eye) captured by the imaging light-receiving unit SJB. Since the image shows one or more of the lens, pupil, cornea, macula, and fovea, the control unit CTL can determine which part of the pixel array ALP the user is looking at by performing this image analysis.

[0082] One example of a method for determining where a user is looking using image analysis is the PCCR method.

[0083] Furthermore, the control unit CTL has the function of acquiring the region of the pixel array ALP that is in the user's line of sight (sometimes referred to as "the region the user is looking at") or its address through the image analysis described above. The control unit CTL also has the function of generating a signal corresponding to the region or address in the user's line of sight and transmitting the said signal to the drive circuit region DRV.

[0084] The circuitry included in the drive circuit area (DRV) receives a signal from the control unit (CTL) and, according to the content of the signal (the direction of the user's gaze), changes the method of writing image data to multiple display pixels included in the pixel array (ALP). Specifically, the circuitry included in the drive circuit area (DRV) changes the method of writing image data to multiple display pixels included in the pixel array (ALP) in order to improve the display quality of the area of ​​the pixel array (ALP) that is the direction of the user's gaze.

[0085] In the display device DP shown in Figure 1A, the imaging light-emitting unit SHB and the imaging light-receiving unit SJB are provided outside the display unit DIS. However, one aspect of the present invention is not limited to this configuration. For example, in one aspect of the present invention, as shown in Figure 1B, the display device may be configured such that the imaging light-emitting unit SHB and the imaging light-receiving unit SJB are provided in the pixel array ALP. In the display device DP of Figure 1B, the imaging light-emitting unit SHB can be, for example, an imaging light-emitting pixel included in the pixel array ALP. The imaging light-receiving unit SJB can be, for example, an imaging pixel included in the pixel array ALP. In other words, as shown in Figure 1B, the display device DP may be configured such that the pixel array ALP includes the aforementioned imaging light-emitting pixel and imaging pixel in addition to the display pixels that display an image.

[0086] Next, a specific example of the configuration of the display unit DIS will be described. Figure 2A is a schematic cross-sectional view showing an example of the configuration of the display unit DIS. As an example, the display unit DIS has a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

[0087] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL. The pixel layer PXAL is superimposed on the region including the drive circuit region DRV.

[0088] The circuit layer SICL comprises a substrate BS and a drive circuit region DRV.

[0089] As the substrate BS, for example, a semiconductor substrate (for example, a single-crystal substrate made of silicon or germanium) can be used. In addition to semiconductor substrates, other substrates BS include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base film. Examples of glass substrates include barium borosilicate glass, aluminobosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, or base film include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic resins can be used. Alternatively, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be used. Alternatively, other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper. Furthermore, if heat treatment is involved in the manufacturing process of the display device (DP), it is preferable to select a material with high heat resistance for the substrate (BS).

[0090] In this embodiment, the substrate BS is described as a semiconductor substrate made of silicon. Therefore, the transistor included in the drive circuit region DRV can be a transistor having silicon in its channel formation region (hereinafter referred to as a Si transistor).

[0091] The drive circuit area (DRV) is located on the circuit board (BS).

[0092] The wiring layer LINL is provided with wiring, for example. The wiring included in the wiring layer LINL functions as wiring that electrically connects, for example, the drive circuit included in the drive circuit region DRV located below and the circuit included in the pixel layer PXAL located above.

[0093] The pixel layer PXAL, for example, has the pixel array ALP described above.

[0094] Figure 3A is an example of a plan view of the display unit DIS. Note that the display unit DIS shown in Figure 3A is a plan view of the pixel layer PXAL, and can be a plan view of the pixel array ALP.

[0095] Furthermore, the pixel array ALP in Figure 3A is divided into, for example, p rows and q columns (where p is an integer greater than or equal to 1, and q is an integer greater than or equal to 1). Therefore, the display unit DIS has a configuration having display areas ARA[1,1] to ARA[p,q]. In Figure 3A, as an example, excerpts of the following display areas are shown: ARA[1,1], ARA[2,1], ARA[p-1,1], ARA[p,1], ARA[1,2], ARA[2,2], ARA[p-1,2], ARA[p,2], ARA[1,q-1], ARA[2,q-1], ARA[p-1,q-1], ARA[p,q-1], ARA[1,q], ARA[2,q], ARA[p-1,q], and ARA[p,q].

[0096] For example, if you want to divide the pixel array ALP into 32 regions, you can set p=4 and q=8 and apply it to Figure 3A. Incidentally, if the resolution of the display unit DIS is 8K4K, the number of display pixels will be 7680×4320. Also, if the sub-display pixels included in the display pixels are the three colors red (R), green (G), and blue (B), then the total number of sub-display pixels included in the pixel array ALP will be 7680×4320×3. Here, if the pixel array ALP of a display device DP with a resolution of 8K4K is divided into 32 regions, the number of display pixels per region will be 960×1080, and if the sub-display pixels included in that pixel are the three colors red (R), green (G), and blue (B), then the number of sub-display pixels per region will be 960×1080×3.

[0097] Here, we consider the drive circuit region DRV included in the circuit layer SICL when the pixel array ALP is divided into a region of p rows and q columns in Figure 3A.

[0098] Figure 3B is an example of a plan view of the display unit DIS, showing only the drive circuit region DRV included in the circuit layer SICL.

[0099] In Figure 3A, the pixel array ALP is divided into p x q regions, so each of the divided display regions ARA[1,1] to ARA[p,q] requires a corresponding drive circuit. Specifically, the drive circuit region DRV can also be divided into p x q regions, and a drive circuit can be provided in each of the divided regions.

[0100] The display unit DIS in Figure 3B shows a configuration in which the drive circuit area DRV is divided into a region of p rows and q columns. Therefore, the drive circuit area DRV has circuit areas ARD[1,1] through ARD[p,q]. In Figure 3B, as an example, each of the following is shown as an excerpt: circuit area ARD[1,1], circuit area ARD[2,1], circuit area ARD[p-1,1], circuit area ARD[p,1], circuit area ARD[1,2], circuit area ARD[2,2], circuit area ARD[p-1,2], circuit area ARD[1,q-1], circuit area ARD[2,q-1], circuit area ARD[p,q-1], circuit area ARD[1,q], circuit area ARD[2,q], circuit area ARD[p-1,q], and circuit area ARD[p,q].

[0101] Each of the circuit regions ARD[1,1] through ARD[p,q] includes a column driver circuit CLM, a row driver circuit RWD, and a frame memory FM. For example, the column driver circuit CLM and row driver circuit RWD contained in the circuit region ARD[h,k] (not shown in Figure 3B) located at the h-th row and k-th column (where h is an integer between 1 and p, and k is an integer between 1 and q) can drive multiple pixels contained in the display region ARA[h,k] located at the h-th row and k-th column of the display unit DIS.

[0102] The column driver circuit CLM includes, for example, a source driver circuit that transmits image signals to multiple pixels included in the corresponding display area ARA. The column driver circuit CLM may also include an amplification circuit for amplifying the image signals. Furthermore, the column driver circuit CLM may include a storage device such as a register for temporarily holding the image signal data. For this reason, it is preferable that the display unit DIS in Figure 2A is provided with wiring for electrically connecting the corresponding column driver circuit CLM and the pixels included in the display area ARA. The column driver circuit CLM may also include a digital-to-analog conversion circuit that converts the digital image signal into analog data.

[0103] The row driver circuit RWD includes, for example, a gate driver circuit for selecting multiple display pixels to which an image signal will be transmitted in the corresponding display area ARA. Therefore, it is preferable that the display unit DIS in Figure 2A is provided with wiring for electrically connecting the row driver circuit RWD and the pixels included in the corresponding display area ARA.

[0104] Frame memory FM has the function of holding, for example, the image signals transmitted to display pixels included in the corresponding display area ARA as electrical potentials.

[0105] In addition, the display unit DIS shown in Figures 2A, 3A, and 3B has a configuration in which the display area ARA[h,k] and the circuit area ARD[h,k] are superimposed on each other, but the display device according to one embodiment of the present invention is not limited to this. The configuration of the display device according to one embodiment of the present invention does not necessarily have to be such that the display area ARA[h,k] and the circuit area ARD[h,k] are superimposed on each other.

[0106] For example, as shown in Figure 2B, the display unit DIS may be configured such that not only the drive circuit area DRV but also the area LIA is provided on the substrate BS.

[0107] For example, wiring is provided in region LIA. Furthermore, the wiring included in region LIA may be electrically connected to the wiring included in wiring layer LINL. In this case, the display unit DIS may be configured such that the circuits included in the drive circuit region DRV and the circuits included in the pixel layer PXAL are electrically connected by the wiring included in region LIA and the wiring included in wiring layer LINL. Alternatively, the display unit DIS may be configured such that the circuits included in the drive circuit region DRV and the wiring, or circuits, included in region LIA are electrically connected via the wiring included in wiring layer LINL.

[0108] Furthermore, the LIA region may include a GPU as an example. If the display unit DIS includes a touch panel, the LIA region may include a sensor controller for controlling the touch sensors included in the touch panel. If liquid crystal elements are used as the display elements of the display unit DIS, a gamma correction circuit may be included. The LIA region may also include a controller that processes input signals from outside the display unit DIS. Finally, the LIA region may include a voltage generation circuit for generating voltages to supply to the aforementioned circuits and the drive circuits included in the circuit region ARD.

[0109] Furthermore, if an EL correction circuit is used as the display element of the display unit DIS, an EL correction circuit may be included. For example, it may have a function to appropriately adjust the amount of current input to the EL light-emitting device containing the EL material. Since the brightness of an EL light-emitting device containing the EL material is proportional to the current when it emits light, if the characteristics of the drive transistor electrically connected to the EL light-emitting device are not good, the brightness of the light emitted by the EL light-emitting device may be lower than the desired brightness. The EL correction circuit can, for example, monitor the amount of current flowing to the EL light-emitting device and, when the amount of current is less than the desired amount, increase the amount of current flowing to the EL light-emitting device to increase the brightness of the light emitted by the EL light-emitting device. Conversely, when the amount of current is greater than the desired amount, it can adjust the amount of current flowing to the EL light-emitting device to be smaller.

[0110] Figure 4A is an example of a plan view of the display unit DIS shown in Figure 2B, showing the drive circuit area DRV (shown by a solid line) and the display unit DIS (shown by a dotted line). In addition, the display unit DIS in Figure 4A shows, as an example, a configuration in which the drive circuit area DRV is surrounded by the area LIA (Figure 4B shows an example of a plan view of a display device DP showing only the circuit layer SICL). Therefore, as shown in Figure 4A, the drive circuit area DRV is arranged to overlap the inside of the pixel array ALP in a plan view.

[0111] Furthermore, the display unit DIS shown in Figure 4A is assumed to have the pixel array ALP divided into display areas ARA[1,1] to ARA[p,q], similar to Figure 3A, and the drive circuit area DRV is also assumed to be divided into circuit areas ARD[1,1] to ARD[p,q].

[0112] As shown in Figure 4A, as an example, the correspondence between the display area ARA and the circuit area ARD, which includes the drive circuits that drive the pixels contained in the display area ARA, is illustrated with thick arrows. Specifically, the drive circuits contained in circuit area ARD[1,1] drive the pixels contained in the display area ARA[1,1], and the drive circuits contained in circuit area ARD[2,1] drive the pixels contained in the display area ARA[2,1]. Furthermore, the drive circuits contained in circuit area ARD[p-1,1] drive the pixels contained in the display area ARA[p-1,1], and the drive circuits contained in circuit area ARD[p,1] drive the pixels contained in the display area ARA[p,1]. In addition, the drive circuits contained in circuit area ARD[1,q] drive the pixels contained in the display area ARA[1,q], and the drive circuits contained in circuit area ARD[2,q] drive the pixels contained in the display area ARA[2,q]. Furthermore, the drive circuits contained in circuit region ARD[p-1,n] drive the pixels contained in display region ARA[p-1,q], and the drive circuits contained in circuit region ARD[p,q] drive the pixels contained in display region ARA[p,q]. In other words, although not shown in Figure 4A, the drive circuits contained in circuit region ARD[h,k] located in row h and column k drive the pixels contained in display region ARA[h,k].

[0113] In Figure 2B, by electrically connecting the drive circuit contained in the circuit region ARD within the circuit layer SICL and the pixels contained in the display region ARA within the pixel layer PXAL using wiring contained in the wiring layer LINL, the configuration of the display unit DIS can be such that the display region ARA[h,k] and the circuit region ARD[h,k] do not necessarily overlap each other. Therefore, the positional relationship of the drive circuit region DRV is not limited to the plan view of the display device DP shown in Figure 4A, and the arrangement of the drive circuit region DRV can be freely determined.

[0114] Although the display unit DIS shown in Figures 2A and 2B is configured with a wiring layer LINL, one aspect of the present invention is not limited to this. A display device according to one aspect of the present invention may, for example, have a configuration in which a pixel layer PXAL is arranged on a circuit layer SICL, as shown in Figure 2C.

[0115] Furthermore, the arrangement of the column driver circuit CLM and the row driver circuit RWD in each of the circuit regions ARD[1,1] to ARD[p,q] shown in Figures 3B and 4A is not limited to the configuration of the display device according to one embodiment of the present invention. In Figures 3B and 4A, the column driver circuit CLM and the row driver circuit RWD are arranged so as to intersect each other (forming a cross), but within a single circuit region ARD, the column driver circuit CLM and the row driver circuit RWD may be arranged in various shapes.

[0116] Next, we will describe an example of the configuration of the display area ARA[h,k] and the circuit area ARD[h,k]. Figure 5 is a block diagram showing an excerpt of the display area ARA[h,k] and the circuit area ARD[h,k] in the display device DP shown in Figures 1A and 3A to 4B.

[0117] In Figure 5, the display area ARA[h,k] has multiple display pixels PX. These multiple display pixels PX are arranged in an m x n matrix within the display area ARA[h,k] (where m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). Note that Figure 5 only shows the display pixels PX[1,1], PX[m,1], PX[1,n], PX[m,n], and PX[i,j] (where i is an integer between 1 and m, and j is an integer between 1 and n) within the display area ARA[h,k].

[0118] Furthermore, as shown in Figure 5, similar to Figures 3B and 4A, the circuit region ARD[h,k] includes a row driver circuit RWD, a column driver circuit CLM, and a frame memory FM. In addition, Figure 5 illustrates the display region ARA[h,k] and the circuit region ARD[h,k], as well as the drive circuit region DRV and the interface IF and control unit CTL included in the drive circuit region DRV.

[0119] The row driver circuit RWD is electrically connected to each of the wirings GL[1] to GL[m], for example. The column driver circuit CLM is electrically connected to wirings SL[1] to SL[n], for example. The frame memory FM is electrically connected to the row driver circuit RWD and the column driver circuit CLM. The interface IF is electrically connected to the control unit CTL and the frame memory FM. The control unit CTL is electrically connected to the row driver circuit RWD, the column driver circuit CLM, and the frame memory FM within the drive circuit area DRV. The display pixel PX[i,j] is electrically connected to wiring SL[j] and wiring GL[i].

[0120] Each of the display pixels PX[1,1] to PX[m,n] can, for example, be a pixel to which either or both a liquid crystal display device and / or a light-emitting device are applied. Examples of light-emitting devices include light-emitting devices containing organic light-emitting diodes (OLEDs), inorganic light-emitting diodes, LEDs (including micro-LEDs), QLEDs (Quantum-dot Light-Emitting Diodes), or semiconductor lasers. In this embodiment, it is assumed that a light-emitting device containing an organic light-emitting diode is applied to the display pixel PX. In particular, the brightness of the light emitted from a light-emitting device capable of high-brightness emission can be, for example, 500 cd / m². 2 Preferably 1000 cd / m² 2 More than 10000cd / m 2 More preferably, 2000 cd / m² 2 More than 5000cd / m 2 The following is possible:

[0121] As described above, the row driver circuit RWD includes a circuit that has the function of selecting at least one of the first to m rows of the display area ARA[h,k] to which the image data signal will be supplied, and transmitting a selection signal to a plurality of display pixels PX located in the selected row. The selection signal can be, for example, an analog potential, a digital potential (high-level potential or low-level potential), or a pulse potential.

[0122] Furthermore, the row driver circuit RWD may not only select one wire from wiring GL[1] to wiring GL[m] and transmit a selection signal to that wire, but may also have the function of transmitting the same selection signal to two or more consecutively adjacent wires from wiring GL[1] to wiring GL[m]. In other words, the row driver circuit RWD can simultaneously select display pixels PX located in two or more consecutively adjacent rows. In addition, the row driver circuit RWD may have the function of changing its frame frequency based on a signal from the control unit CTL, which will be described later.

[0123] Furthermore, as described above, the column driver circuit CLM includes a circuit that has the function of transmitting an image data signal to the display pixels PX included in the display area ARA[h,k]. The image data signal can be, for example, an analog potential, a digital potential (high-level potential or low-level potential), or a pulse potential.

[0124] Furthermore, the column driver circuit CLM may not only select one wire from wiring SL[1] to SL[n] and transmit a selection signal to that wire, but may also have the function of transmitting the same selection signal to two or more consecutively adjacent wires from wiring SL[1] to SL[n]. In other words, the column driver circuit CLM can simultaneously transmit the same image signal to two or more consecutively adjacent display pixels PX arranged in columns. In addition, the column driver circuit CLM may have the function of changing the frame frequency of the column driver circuit CLM based on a signal from the control unit CTL, which will be described later.

[0125] As described above, the interface IF has the function of inputting image data for displaying images on the display device DP, which is input from an external device to the display device DP, into the drive circuit area DRV. In addition, as shown in Figure 5, the interface IF has the function of inputting the said image data into the frame memory FM. Furthermore, the interface IF has the function of inputting command signals for controlling the display device DP, which are input from an external device to the control unit CTL.

[0126] The frame memory FM, for example, has the function of temporarily holding image data transmitted from the interface IF. The frame memory FM also has the function of temporarily holding the address of the display pixel PX to which the image data will be written. Furthermore, the frame memory FM may have the function of changing its frame frequency based on a signal from the control unit CTL, which will be described later.

[0127] In Figure 5, the control unit CTL has, for example, the function of controlling the number of rows to which the row driver circuit RWD transmits a selection signal at one time. Similarly, the control unit CTL also has, for example, the function of controlling the number of columns to which the column driver circuit CLM transmits the same image signal. In this case, the control unit CTL can transmit control signals to the row driver circuit RWD and the column driver circuit CLM, respectively, to perform the above operations.

[0128] Furthermore, the control unit CTL may, for example, have a function to control the frame frequencies of the row driver circuit RWD, the column driver circuit CLM, and the frame memory FM. In this case, the control unit CTL may transmit signals to each of the row driver circuit RWD, the column driver circuit CLM, and the frame memory FM to change the frame frequency.

[0129] Furthermore, if the display device DP has the configuration shown in Figure 1B, that is, if the pixel array ALP includes an imaging light-emitting unit SHB and an imaging light-receiving unit SJB, the block diagram in Figure 5 can be rewritten as, for example, the block diagram in Figure 6.

[0130] The block diagram in Figure 6 differs from the block diagram in Figure 5 in that the display area ARA[h,k] includes the imaging pixels PV[1,1] to PV[m,n], and the drive circuit area DRV includes the sensor row driver circuit TXD and the sensor column driver circuit POD.

[0131] In Figure 6, the imaging pixels PV[1,1], PV[m,1], PV[1,n], PV[m,n], and PV[i,j] are selected from among the imaging pixels PV[1,1] to PV[m,n].

[0132] In Figure 6, the display area ARA[h,k] has pixels PU[1,1] to PU[m,n]. Pixel PU[1,1] includes a display pixel PX[1,1] and an imaging pixel PV[1,1]; pixel PU[m,1] includes a display pixel PX[m,1] and an imaging pixel PV[m,1]; pixel PU[1,n] includes a display pixel PX[1,n] and an imaging pixel PV[1,n]; pixel PU[m,n] includes a display pixel PX[m,1] and an imaging pixel PV[m,n]; and pixel PU[i,j] includes a display pixel PX[i,j] and an imaging pixel PV[i,j]. In other words, in the display area ARA[h,k], similar to the display area ARA[h,k] in Figure 5, pixels PU[1,1] to PU[m,n] are arranged in an m x n matrix.

[0133] In Figure 6, pixels PU[1,1], PU[m,1], PU[1,n], PU[m,n], and PU[i,j] are selected from pixels PU[1,1] to PU[m,n].

[0134] The sensor row driver circuit TXD is electrically connected to each of the wirings TXL[1] through TXL[m], for example. The sensor row driver circuit POD is electrically connected to the wirings POL[1] through POL[n], for example. The imaging pixel PV[i,j] is electrically connected to the wiring TXL[i] and the wiring POL[j].

[0135] Each of the imaging pixels PV[1,1] to PV[m,n] shown in Figure 6 corresponds to the imaging light-receiving unit SJB in Figures 1(A) and 1(B). Therefore, each of the imaging pixels PV[1,1] to PV[m,n] can be a pixel having a light-receiving device such as a photoelectric conversion element (for example, a pn-type or pin-type photodiode).

[0136] Furthermore, if each of the display pixels PX[1,1] to PX[m,n] shown in Figure 6 has a light-emitting device, each of the display pixels PX[1,1] to PX[m,n] can also be used as a light-emitting pixel for imaging. In other words, each of the display pixels PX[1,1] to PX[m,n] shown in Figure 6 can not only display an image but also emit the light necessary for imaging. In this case, each of the display pixels PX[1,1] to PX[m,n] corresponds to the light-emitting unit SHB for imaging in Figures 1(A) and 1(B). In addition, the display area ARA[h,k] may be provided with light-emitting pixels for imaging separately from the display pixels PX[1,1] to PX[m,n] (not shown).

[0137] The sensor row driver circuit TXD, for example, has the function of selecting the row to be imaged in the display area ARA[h,k]. The imaging method in the example configuration shown in Figure 6 may be either a rolling shutter method or a global shutter method.

[0138] The sensor array driver circuit POD, for example, has the function of reading out data captured by the image pixel PV in the display unit DIS. For this reason, the sensor array driver circuit POD is sometimes referred to as a readout circuit. The sensor array driver circuit POD may also include an amplification circuit for amplifying the data and an analog-to-digital conversion circuit.

[0139] In the example configuration shown in Figure 6, the sensor row driver circuit TXD and the sensor column driver circuit POD are located outside the circuit region ARD[h,k], but the sensor row driver circuit TXD and the sensor column driver circuit POD may also be located inside the circuit region ARD[h,k].

[0140] As described above, by applying the configuration example shown in Figure 6 to the display device DP, the display device DP of Figure 1B can be configured, in which an imaging light-emitting unit SHB and an imaging light-receiving unit SJB are provided within the pixel array ALP.

[0141] One aspect of the present invention is a display device that divides a pixel array into multiple regions and can change the display quality of each region according to the user's line of sight. In particular, by lowering the display quality in regions far from the user's line of sight, the amount of image data transmitted to the pixel array can be reduced. Examples of methods for changing the display quality include changing the screen resolution and changing the frame rate.

[0142] <Change screen resolution> First, we will explain how to change the screen resolution in each divided region of the pixel array of a display device. This explanation will use the display unit DIS of the display device DP shown in Figures 3A to 4B.

[0143] For example, if the screen resolution of the display unit DIS of the display device DP is set to 8K4K, the number of display pixels PX included in the display unit DIS will be 7680 x 4320. Now, if the screen resolution of the display unit DIS of the display device DP is changed to 4K2K (3840 x 2160), the matrix of display pixels PX of the display unit DIS is divided into a 2x2 area, and the 4 display pixels PX included in each area are treated as 1 pixel. By transmitting the same image signal to the 4 display pixels PX included in the same area, the display device DP can be driven as a display device with a 4K2K screen resolution. Also, if the screen resolution of the display unit DIS of the display device DP is changed to FHD (1920 x 1080 pixels), the matrix of display pixels PX of the display unit DIS is divided into a 4x4 area, and the 16 display pixels PX included in each area are treated as 1 pixel. By transmitting the same image signal to the 4 display pixels PX included in the same area, the 8K4K display device DP can be driven as a display device with an FHD screen resolution. Furthermore, when changing the screen resolution of the display unit DIS of the display device DP to HD (1280 x 720 pixels), the matrix of display pixels PX of the display unit DIS is divided into a 6x6 area, and the 36 display pixels PX contained in each area are treated as one pixel. By transmitting the same image signal to the 36 display pixels PX contained in the same area, the 8K4K display device DP can be driven as a display device with an HD screen resolution.

[0144] The above is an example of changing the screen resolution of the display unit DIS of the display device DP, but as mentioned above, the screen resolution can be changed for each display area ARA in the display device DP.

[0145] Figure 7 shows a block diagram of a display area ARA[h,k] containing multiple display pixels PX. Note that Figure 7 shows a selection of display pixels PX[1,1], PX[2,1], PX[3,1], PX[4,1], PX[1,2], PX[2,2], PX[3,2], PX[4,2], PX[1,3], PX[2,3], PX[3,3], PX[4,3], PX[1,4], PX[2,4], PX[3,4], and PX[4,4].

[0146] When the screen resolution of the display unit DIS of the display device DP is set to 8K4K, and the display unit DIS is divided into a 4x8 display area (i.e., when p=4 and q=8 in Figures 3A to 4B), the number of display pixels PX contained in one display area ARA is 960×1080. In this case, in Figure 7, the display area ARA[h,k] displays an image with the area PSR enclosed by the dotted line as 1 pixel.

[0147] Here, consider the case where the matrix in the display area ARA[h,k] of Figure 7, where the display pixels PX are located, is divided into a 2x2 area PSR_HF (the area enclosed by the solid line). In this case, the four display pixels PX contained in each area PSR_HF are treated as one pixel, and by transmitting the same image signal to the four display pixels PX contained in the same area PSR_HF, the display area ARA[h,k] can display an image with the area PSR_HF as one pixel. In other words, the screen resolution of the display area ARA[h,k] can be considered to be 480 x 540 pixels. Also, since the same image signal is written to the four display pixels PX of the 2x2 area PSR_HF, the amount of image data transmitted to the display area ARA[h,k] with a reduced screen resolution of 480 x 540 pixels is one-quarter of the amount of image data transmitted at the normal screen resolution.

[0148] Similarly, consider the case where the matrix in the display area ARA[h,k] of Figure 7, where the display pixels PX are located, is divided into a 4x4 area PSR_QT (the area enclosed by the dashed line). In this case, by transmitting the same image signal to the 16 display pixels PX contained in the same area PSR_QT, the display area ARA[h,k] can display an image by treating the area PSR_QT containing the 16 display pixels PX as one pixel. In other words, the screen resolution of the display area ARA[h,k] can be considered as 240x270 pixels. Also, since the same image signal is written to the 16 display pixels PX in the 4x4 area PSR_QT, the amount of image data transmitted to the display area ARA[h,k] with a reduced screen resolution of 240x270 pixels is 1 / 16th of the amount of image data transmitted at the normal screen resolution.

[0149] Furthermore, although not shown in the diagram, consider the case where the matrix in the display area ARA[h,k] of Figure 7, where the display pixels PX are located, is divided into a 6x6 area. In this case, by transmitting the same image signal to the 36 display pixels PX contained in the same area, the display area ARA[h,k] can display an image by treating the area containing the 36 display pixels PX as one pixel. In other words, the screen resolution of the display area ARA[h,k] can be considered as 160x180 pixels. Also, since the same image signal is written to the 36 display pixels PX contained in the 6x6 area, the amount of image data transmitted to the display area ARA[h,k] with a reduced screen resolution of 160x180 pixels is 1 / 36th of the amount of image data transmitted at the normal screen resolution.

[0150] As described above, by reducing the screen resolution of the display area ARA[h,k], the amount of image data written to the display area ARA[h,k] can be reduced. In other words, the load on the interface IF that handles image data input from outside the display device DP can be reduced. Furthermore, because the amount of image data displayed on the display device DP is reduced, the burden on each circuit in the drive circuit area DRV can be reduced.

[0151] <<Example configuration of column driver circuit CLM and row driver circuit RWD>> Next, we will describe example configurations for the column driver circuit CLM and the row driver circuit RWD, which are included in the circuit area ARD corresponding to the display area ARA, where the screen resolution can be changed.

[0152] Figure 8A shows an example configuration of a column driver circuit CLM that can be applied to the circuit area ARD of the display device DP described above. Figure 8A also shows a frame memory FM to illustrate its connection to the column driver circuit CLM.

[0153] Furthermore, Figure 8B shows an example configuration of a row driver circuit RWD that can be applied to the circuit area ARD of the display device DP described above.

[0154] The column driver circuit CLM in Figure 8A, as an example, includes a drive circuit SD, switches SWa[1] to SWa[n], and switches SWb[1] to SWb[n-1].

[0155] Furthermore, the drive circuit SD may include, for example, circuits SDa[1] to SDa[n].

[0156] Furthermore, the row driver circuit RWD in Figure 8B includes, as an example, a drive circuit GD, switches SWc[1] to SWc[n], and switches SWd[1] to SWd[n-1].

[0157] Furthermore, each of the multiple switches shown in Figures 8A and 8B can be replaced with an electrical switch, such as an analog switch or a transistor. In particular, it is preferable to use the above-mentioned transistor as the electrical switch for each of the multiple switches shown in Figures 8A and 8B, and it is more preferable to use an OS transistor. Alternatively, each of the multiple switches shown in Figures 8A and 8B may be replaced with a mechanical switch, for example.

[0158] Furthermore, the on-state and off-state control of switches SWa[1] to SWa[n], SWb[1] to SWb[n-1], SWc[1] to SWc[n], and SWd[1] to SWd[n-1] shown in Figures 8A and 8B is performed by the control unit CTL. Specifically, the control unit CTL can decide whether to turn on or off each of switches SWa[1] to SWa[n], SWb[1] to SWb[n-1], SWc[1] to SWc[n], and SWd[1] to SWd[n-1] based on the results of image analysis of the image captured by the imaging light receiving unit SJB (for example, the user's eye). For this reason, the control unit CTL has the function of transmitting control signals to each switch included in the column driver circuit CLM and the row driver circuit RWD, respectively.

[0159] Each input terminal of circuit SDa[1] through circuit SDa[n] is electrically connected to the frame memory FM.

[0160] The output terminal of circuit SDa[1] is electrically connected to the first terminal of switch SWa[1]. Also, the output terminal of circuit SDa[n] is electrically connected to the first terminal of switch SWa[n]. Furthermore, when J is an integer between 2 and n-1 (inclusive), the output terminal of circuit SDa[J] is electrically connected to the first terminal of switch SWa[J].

[0161] The second terminal of switch SWa[1] is electrically connected to the first terminal of switch SWb[1] and to wiring SL[1]. Also, the second terminal of switch SWa[J] is electrically connected to the second terminal of switch SWb[J-1], the first terminal of switch SWb[J], and to wiring SL[J]. Furthermore, the second terminal of switch SWa[n] is electrically connected to the second terminal of switch SWb[n] and to wiring SL[n].

[0162] The drive circuit SD functions, for example, as a source driver circuit. Specifically, each of circuits SDa[1] to SDa[n] has the function of acquiring digital data from the frame memory FM corresponding to the image to be displayed on the pixel array ALP, converting the digital data into analog data, and outputting the analog data to its respective output terminal.

[0163] The drive circuit GD functions, for example, as a gate driver circuit. Specifically, the drive circuit GD has the function of acquiring a signal from the control unit CTL or frame memory FM that includes the row (address) of the display pixel PX to rewrite the image, and transmitting a selection signal to the selected row.

[0164] Next, we will describe the driving methods for the column driver circuit (CLM) and the row driver circuit (RWD).

[0165] First, let's consider a case where the display area ARA is set to the normal screen resolution, and an image is displayed in the display area ARA.

[0166] In this case, in the column driver circuit CLM, all switches SWa[1] through SWa[n] are turned ON, and all switches SWb[1] through SWb[n-1] are turned OFF.

[0167] As a result, one of circuits SDa[1] to SDa[n] can transmit an image signal to the corresponding wiring among wirings SL[1] to SL[n].

[0168] Furthermore, in the row driver circuit RWD, all switches SWc[1] through SWc[n] are turned ON, and all switches SWd[1] through SWd[n-1] are turned OFF.

[0169] This allows the drive circuit GD to transmit a selection signal to the corresponding wiring among wiring GL[1] to wiring GL[n].

[0170] Through the above operation, the column driver circuit CLM can select one row at a time from the pixel array ALP where the display pixels PX on which images are written are located. The row driver circuit RWD can then transmit the corresponding image signal to each of the display pixels PX[1,1] through PX[m,n] included in the pixel array ALP. In other words, this operation allows the display area ARA to display images at the normal screen resolution.

[0171] Next, let's consider a case where, for example, the display area ARA is set to a screen resolution of one-quarter of the normal screen resolution, and an image is displayed in the display area ARA. In this case, m and n in the display area ARA are both multiples of 2.

[0172] In this case, in the column driver circuit CLM, switches SWa[J+1] and SWb[J+1] are turned ON, and switches SWa[J+2] and SWb[J+2] are turned OFF. Here, J is defined as 0 or an even number between 1 and n-1 (inclusive).

[0173] As a result, circuit SDa[J+1] can transmit the same image signal to both wiring SL[J+1] and wiring SL[J+2]. In other words, it can transmit the same image signal to both the multiple display pixels PX located in column J+1 and the multiple display pixels PX located in column J+2.

[0174] Furthermore, in the row driver circuit RWD, switches SWc[K+1] and SWd[K+1] are turned ON, and switches SWc[K+2] and SWd[K+2] are turned OFF. Here, K is defined as 0, or an even number between 1 and m-1 (inclusive).

[0175] This allows the drive circuit GD to transmit image signals to wiring GL[K+1] and wiring GL[K+2]. In other words, it can transmit the same selection signal to both the multiple display pixels PX located in row K+1 and the multiple display pixels PX located in row K+2.

[0176] Therefore, the above operation allows the m x n matrix of the pixel array ALP to be divided into a 2 x 2 region, and the same image signal and the same selection signal can be transmitted to the four display pixels PX contained within that region. Furthermore, as described above, by treating the four display pixels PX contained within the 2 x 2 region as one pixel, the screen resolution of the display region ARA can be reduced to one-quarter.

[0177] Next, let's consider a case where, for example, the display area ARA is set to a screen resolution of 1 / 16th of the normal screen resolution, and an image is displayed in the display area ARA. In this case, m and n in the display area ARA are both multiples of 4.

[0178] In this case, in the column driver circuit CLM, switches SWa[J+1] and SWb[J+1] through SWb[J+3] are turned ON, and switches SWa[J+2] through SWa[J+4] and SWb[J+4] are turned OFF. Here, J is defined as 0, or a multiple of 4 between 1 and n-1.

[0179] As a result, circuit SDa[J+1] can transmit the same image signal to each of the wirings SL[J+1] through SL[J+4]. In other words, it can transmit the same image signal to multiple display pixels PX located in column J+1, multiple display pixels PX located in column J+2, multiple display pixels PX located in column J+3, and multiple display pixels PX located in column J+4.

[0180] Furthermore, in the row driver circuit RWD, switches SWc[K+1] and SWd[K+1] through SWd[K+3] are turned ON, and switches SWc[K+2] through SWc[K+4] and SWd[K+4] are turned OFF. Here, K is 0, or a multiple of 4 between 1 and m-1.

[0181] As a result, the drive circuit GD can transmit image signals to wiring GL[K+1] through wiring GL[K+4]. In other words, it can transmit the same selection signal to each of the multiple display pixels PX located in row K+1, row K+2, row K+3, and row K+4.

[0182] Therefore, the above operation allows the m x n matrix of the pixel array ALP to be divided into a 4 x 4 region, and the same image signal and the same selection signal can be transmitted to the 16 display pixels PX contained within that region. Furthermore, as described above, by treating the 16 display pixels PX contained within the 4 x 4 region as one pixel, the screen resolution of the display region ARA can be reduced to 1 / 16th.

[0183] Next, let's consider a case where, for example, the display area ARA is set to a screen resolution of 1 / 36th of the normal screen resolution, and an image is displayed in the display area ARA. In this case, m and n in the display area ARA are both multiples of 6.

[0184] In this case, in the column driver circuit CLM, switches SWa[J+1] and SWb[J+1] through SWb[J+5] are turned ON, and switches SWa[J+2] through SWa[J+6] and SWb[J+6] are turned OFF. Here, J is defined as 0, or a multiple of 6 between 1 and n-1.

[0185] As a result, circuit SDa[J+1] can transmit the same image signal to each of the wirings SL[J+1] through SL[J+6]. In other words, it can transmit the same image signal to multiple display pixels PX located in column J+1, multiple display pixels PX located in column J+2, multiple display pixels PX located in column J+3, multiple display pixels PX located in column J+4, multiple display pixels PX located in column J+6, and multiple display pixels PX located in column J+6.

[0186] Furthermore, in the row driver circuit RWD, switches SWc[K+1] and SWd[K+1] through SWd[K+5] are turned ON, and switches SWc[K+2] through SWc[K+6] and SWd[K+6] are turned OFF. Here, K is 0, or a multiple of 6 between 1 and m-1.

[0187] As a result, the drive circuit GD can transmit image signals to wiring GL[K+1] through GL[K+6]. In other words, it can transmit the same selection signal to each of the multiple display pixels PX located in row K+1, row K+2, row K+3, row K+4, row K+5, and row K+6.

[0188] Therefore, the above operation allows the m x n matrix of the pixel array ALP to be divided into a 6 x 6 region, and the same image signal and the same selection signal can be transmitted to the 36 display pixels PX contained within that region. Furthermore, as described above, by treating the 36 display pixels PX contained within the 6 x 6 region as one pixel, the screen resolution of the display region ARA can be reduced to 1 / 36th.

[0189] In the above example of lowering the screen resolution, the row driver circuit RWD was described as simultaneously sending selection signals to multiple rows. However, the row driver circuit RWD may also send selection signals sequentially to one row at a time instead of multiple rows.

[0190] Furthermore, the configuration of one or both of the column driver circuit CLM and row driver circuit RWD described above is not limited to one aspect of the present invention. For example, the column driver circuit CLM in Figure 8A may be configured without one or more switches selected from switches SWb[1] to SWb[n-1]. As a specific example, the column driver circuit CLM may be configured as shown in Figure 9. The column driver circuit CLM in Figure 9 differs from the column driver circuit CLM in Figure 8A in that it does not have a switch SWb[J] (where J is a multiple of 4 of 1 or more). In the column driver circuit CLM in Figure 9, n is a multiple of 4 of 1 or more. By using the column driver circuit CLM in Figure 9, the same image signal can be transmitted to up to four columns of wiring.

[0191] <<Changing screen resolution based on user gaze>> The above explained that the display device DP can change the screen resolution for each display area ARA. Here, we will explain the operation of detecting which area of ​​the pixel array ALP the user's gaze is looking at and changing the screen resolution for each display area ARA. Eye tracking will be discussed later.

[0192] Figure 10A shows an example where the display unit DIS of the display device DP is divided into a 16x16 display area (i.e., p=16 and q=16 in Figures 3A to 4B).

[0193] Also, assume that the display device DP is provided with a function to detect the user's line of sight. Therefore, the display device DP can determine which part of the pixel array ALP the user is looking at. For example, in FIG. 10A, the area ASU is an area determined to be the area that the user is looking at (the user's line of sight destination) by the eye tracking function of the display device DP.

[0194] Since there is the area ASU at the user's line of sight destination, the user can clearly visually recognize the area ASU. On the other hand, it becomes difficult for the user to clearly visually recognize an area away from the area ASU (an area included in the user's visual field but not the user's line of sight destination, an area that the user is not gazing at). Conversely, the image displayed in the display area ARA away from the area ASU is not consciously noticed by the user, so there is little need to improve the display quality of the display area ARA.

[0195] Here, as shown in FIG. 10A, the display device DP sets an area ALPa around the area ASU based on the area ASU detected by the eye tracking function, sets an area ALPb so as to surround the periphery of the area ALPa, sets an area ALPc so as to surround the periphery of the area ALPb, and sets an area ALPd so as to surround the periphery of the area ALPc. Then, the screen resolution is set for each of the display areas ARA included in the areas ALPa to ALPd. Here, the screen resolution of the display area ARA included in the area ALPa is R a is set as, the screen resolution of the display area ARA included in the area ALPb is R b is set as, the screen resolution of the display area ARA included in the area ALPc is R c is set as, the screen resolution of the display area ARA included in the area ALPd is R d is set as. In particular, R a is higher than R b , R b is higher than R c , and R c is preferably higher than R d .

[0196] As described above, by increasing the screen resolution of the display area ARA surrounding the area ASU, which is the user's line of sight, and decreasing the screen resolution of the display area ARA that is far from the area ASU, the amount of image data transmitted to the display unit DIS of the display device DP can be reduced. This eliminates the need for high performance in the interface for transmitting image data to the display device DP, thus reducing power consumption and costs. In addition, the circuits in the circuit area ARD that drive the display pixels PX included in the low-resolution display area ARA also consume less power because the amount of image data transmitted to the display area ARA is reduced.

[0197] Furthermore, since it is difficult for users to clearly see the display area ARA that is far from the area ASU, lowering the screen resolution of the display area ARA that is far from the area ASU and thereby lowering the display quality of the image displayed on the entire pixel array ALP will have little impact on the user's perception of the image displayed on the pixel array ALP.

[0198] Furthermore, if the user's gaze moves and the position of region ASU changes, the positions and ranges of regions ALPa, ALPb, ALPc, and ALPd may also change. For example, as shown in Figure 10B or Figure 11A, when the region the user's gaze is directed at changes from region ASU to region ASU_AF, the positions of regions ALPa, ALPb, ALPc, and ALPd change. In the example of change in Figure 10B, the ranges (sizes) of regions ALPa and ALPb remain unchanged, while the range of region ALPc shrinks and the range of region ALPd expands. Figure 11A shows an example of change when the region the user's gaze is directed at changes from region ASU to region ASU_AF, which is near the edge of the pixel array ALP, where the ranges of regions ALPa, ALPb, and ALPc shrink and the range of region ALPd expands.

[0199] Furthermore, if the eye-tracking function of the display device DP does not detect the user's gaze, the display device DP may set all of the pixel array ALP to region ALPe, as shown in Figure 11B. Examples of situations where the user's gaze is not detected include when the user's eyelids are closed or when the user is asleep. The screen resolution of the display region ARA included in region ALPe may be lower than that of region ALPd, for example. Alternatively, the display device DP may choose not to transmit an image signal to the display pixels PX of the display region ARA included in region ALPe. In other words, the display device DP may choose not to transmit a black image signal to the display pixels PX of the display region ARA included in region ALPe.

[0200] In the display device DP shown in Figures 10A and 10B, the display unit DIS is divided into four regions: ALPa, ALPb, ALPc, and ALPd, and each of these regions is set to a different screen resolution. However, the display device according to one embodiment of the present invention is not limited to this. For example, the display unit DIS of the display device DP may be divided into two, three, or five or more regions, and each region may be set to a different screen resolution.

[0201] <Changing the frame frequency> Next, we will explain how to change the frame frequency in each divided region of the pixel array of the display device. This explanation will use the display unit DIS of the display device DP shown in Figures 3A to 4B.

[0202] For example, if the frame frequency of the pixel array ALP of the display device DP is set to 120Hz (sometimes written as fps), the display device DP will write images 120 times per second. If the frame frequency of the pixel array ALP of the display device DP is changed to 60Hz, the display device DP will write images 60 times per second. In this case, the amount of image data (transmission rate) transmitted per second to the pixel array ALP will be half the amount of image data transmitted per second at 120Hz. Furthermore, if the frame frequency of the pixel array ALP of the display device DP is changed to 30Hz, the amount of image data (transmission rate) transmitted per second to the pixel array ALP will be one-quarter the amount of image data transmitted per second at 120Hz.

[0203] Furthermore, if the frame frequency of the pixel array ALP of the display device DP is changed to 180Hz, the amount of image data (transmission amount) per second required to rewrite the image displayed on the pixel array ALP will be 1.5 times the amount of image data per second transmitted at 120Hz. Also, if the frame frequency of the pixel array ALP of the display device DP is changed to 240Hz, the amount of image data (transmission amount) per second required to rewrite the image displayed on the pixel array ALP will be twice the amount of image data per second transmitted at 120Hz.

[0204] The above describes an example of changing the frame frequency of the pixel array ALP of a display device DP, but the frame frequency may also be changed for each display area ARA in the display device DP.

[0205] The display device DP in Figure 12A, as an example, has a pixel array ALP that includes display area ARA[1,1], display area ARA[2,1], display area ARA[1,2], and display area ARA[2,2].

[0206] When the frame frequencies of the display areas ARA[1,1], ARA[2,1], ARA[1,2], and ARA[2,2] included in the display unit DIS are set to 120Hz, the amount of image data transmitted to each of the display areas ARA[1,1], ARA[2,1], ARA[1,2], and ARA[2,2] will be equal to each other (see Figure 12B). Here, the amount of image data transmitted to each of the display areas ARA[1,1], ARA[2,1], ARA[1,2], and ARA[2,2] is D PS Let's assume that.

[0207] Here, as shown in Figure 12C, the frame frequency of display area ARA[1,1] is changed to 30Hz, and the frame frequency of display area ARA[2,1] is changed to 60Hz.

[0208] In the display area ARA[1,1], by lowering the frame frequency from 120Hz to 30Hz, the amount of image data transmitted to the display area ARA[1,1] is D PS This results in a 4 / 4 ratio. In other words, by lowering the frame frequency from 120Hz to 30Hz, the amount of image data transmitted to the display area ARA[1,1] is reduced to 3D PS It can be reduced by 4.

[0209] Furthermore, by lowering the frame frequency from 120Hz to 60Hz in the display area ARA[2,1], the amount of image data transmitted to the display area ARA[2,1] is D PS This results in a ratio of / 2. In other words, by lowering the frame frequency from 120Hz to 60Hz, the amount of image data transmitted to the display area ARA[2,1] is reduced by D PS It can be reduced by 2.

[0210] Here, the amount of transmission reduced in display area ARA[1,1] and display area ARA[2,1] can be allocated to one or more areas selected from display area ARA[1,2] and display area ARA[2,2].

[0211] For example, the reduced transmission amount in the display area ARA[1,1] is 3D PS / 4 may be added to the amount of image data transmitted to display area ARA[2,2]. In this case, the amount of image data transmitted to display area ARA[2,2] is 7D PS This results in a value of / 4, and by increasing the frame frequency of the display area ARA[2,2] to 210Hz, it becomes possible to transmit image data to the display area ARA[2,2] (see Figures 12C and 12D).

[0212] Also, for example, the reduced transmission amount D in the display area ARA[2,1] PS The value of / 2 may be increased to the amount of image data transmitted to the display area ARA[1,2]. In this case, the amount of image data transmitted to the display area ARA[1,2] is 3D PS This results in a value of / 2, and by increasing the frame frequency of the display area ARA[1,2] to 180Hz, it becomes possible to transmit image data to the display area ARA[1,2] (see Figures 12C and 12D).

[0213] <<Changes to frame rate based on user gaze>> The above explained that the display device DP can change the frame frequency for each display area ARA. Here, we will explain the operation of detecting which area of ​​the pixel array ALP the user's gaze is looking at and changing the frame frequency for each display area ARA. Eye tracking will be discussed later.

[0214] Please note that explanations may be omitted in parts that overlap with the "Changing Screen Resolution" section mentioned above.

[0215] Figure 13A, like Figure 10A, shows an example where the pixel array ALP of the display device DP is divided into a 16x16 display area (i.e., p=16 and q=16 in Figures 3A to 4B).

[0216] Furthermore, the display device DP is assumed to have a function to detect the user's gaze, similar to that in Figure 10A. Therefore, the display device DP shown in Figure 13A can determine which part of the pixel array ALP the user is looking at. Regarding the region ASU shown in Figure 13A, refer to the explanation in Figure 10A.

[0217] As explained in Figure 10A, users can clearly see the area ASU, and do not consciously pay attention to areas away from the area ASU (areas that are within the user's field of vision but not in the user's line of sight, or areas that the user is not focusing on). Therefore, since users do not consciously pay attention to images displayed in the display area ARA, which is away from the area ASU, there is little need to improve the display quality of that display area ARA.

[0218] Here, the display device DP, based on the region ASU detected by the eye-tracking function, sets region ALPa around region ASU as shown in Figure 13A, sets region ALPb to surround the periphery of region ALPa, sets region ALPc to surround the periphery of region ALPb, and sets region ALPd to surround the periphery of region ALPc. Then, it sets the frame frequency for each of the display regions ARA contained within regions ALPa to ALPd. Here, the frame frequency of the display region ARA contained within region ALPa is set to f a Let f be the frame frequency of the display area ARA included in area ALPb. b Let f be the frame frequency of the display area ARA included in area ALPc. c Let f be the frame frequency of the display area ARA included in area ALPd. d In particular, f a is f b Make it higher than f b is f c Make it higher than f c is f d It is preferable to make it higher than that.

[0219] Specifically, as described in FIGS. 12A to 12D, the amount of image data transmitted to the display area ARA included in the area ALPa is made larger than the amount of image data transmitted to the display area ARA included in the area ALPb, and the amount of image data transmitted to the display area ARA included in the area ALPb is made larger than the amount of image data transmitted to the display area ARA included in the area ALPc, and the amount of image data transmitted to the display area ARA included in the area ALPc is made larger than the amount of image data transmitted to the display area ARA included in the area ALPd.

[0220] A specific example will be described below. FIG. 15 is an example of a block diagram of the display device DP shown in FIGS. 3A to 4B. Here, as an example, it is assumed that the interface IF can input image data to all circuit areas ARD at a frame frequency of 120 Hz. Also, let the maximum value of the image data that the interface IF can transmit to all circuit areas ARD at a frame frequency of 120 Hz be D MAX be.

[0221] Further, FIG. 16 shows a graph indicating the amount of image data input to the interface IF from the outside of the display device DP. For example, when driving all of the pixel array ALP of the display device DP at a frame frequency of 120 Hz (described as normal in FIG. 16), it shows that the amount of image data of D MAX is input to the interface IF.

[0222] Further, FIG. 17 is a diagram showing the timing when image data is input to the interface IF, the timing when image data is input to the frame memories FM of the areas ALPa to ALPd, and the timing when image data is input to the display areas ARA of the areas ALPa to ALPd.

[0223] Here, consider the case in Figure 13A where the frame frequency of the display area ARA of area ALPa is set to 240Hz, the frame frequency of the display area ARA of area ALPb is set to 120Hz, the frame frequency of the display area ARA of area ALPc is set to 60Hz, and the frame frequency of the display area ARA of area ALPd is set to 30Hz, and the display device DP is driven accordingly. In this case, control signals are provided from the control unit CTL so that the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPa is driven at 240Hz, the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPb is driven at 120Hz, the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPc is driven at 60Hz, and the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPd is driven at 30Hz.

[0224] The interface IF, which operates at a frame frequency of 120 Hz, receives data Da, data Db, data Dc, and data Dd in the first frame (see interface IF in Figures 16 and 17). Data Da is image data to be displayed in the display area ARA contained in area ALPa, data Db is image data to be displayed in the display area ARA contained in area ALPb, data Dc is image data to be displayed in the display area ARA contained in area ALPc, and data Dd is image data to be displayed in the display area ARA contained in area ALPd.

[0225] Furthermore, as shown in Figures 16 and 17, in the second frame, data Da and data Db are input to interface IF. In the third frame, data Da, data Db, and data Dc are input to interface IF, and in the fourth frame, data Da and data Db are input to interface IF.

[0226] Furthermore, from the 5th frame onward, image data input will be repeated in the same manner as from the 1st to the 4th frame.

[0227] Furthermore, since the frame frequency of the display area ARA in area ALPa is 240Hz, the amount of data Da input to the interface in the first to fourth frames is twice the amount of data transmitted when the frame frequency is 120Hz. Therefore, Figure 16 shows two data Da values ​​for each frame.

[0228] Furthermore, as shown in Figure 17, in the second frame, the frame memory FM of region ALPa (labeled FM(ALPa) in Figure 17) receives the two data Da inputs that were entered into the interface IF in the first frame. Also, the frame memory FM of region ALPb (labeled FM(ALPb) in Figure 17) receives the data Db input that was entered into the interface IF in the first frame. Also, the frame memory FM of region ALPc (labeled FM(ALPc) in Figure 17) receives the data Dc input that was entered into the interface IF in the first frame. Also, the frame memory FM of region ALPd (labeled FM(ALPd) in Figure 17) receives the data Dd input that was entered into the interface IF in the first frame.

[0229] Furthermore, as shown in Figure 17, in the third frame, the display area ARA of region ALPa (labeled ARA(ALPa) in Figure 17) receives the two data Da inputs that were entered into region ALPa's frame memory FM in the second frame. Also, the display area ARA of region ALPb (labeled ARA(ALPb) in Figure 17) receives the data Db input that was entered into region ALPb's frame memory FM in the second frame. Also, the display area ARA of region ALPc (labeled ARA(ALPc) in Figure 17) receives the data Dc input that was entered into region ALPc's frame memory FM in the second frame. Also, the display area ARA of region ALPd (labeled ARA(ALPd) in Figure 17) receives the data Dd input that was entered into region ALPd's frame memory FM in the second frame.

[0230] Similarly, the data Da and data Db input to interface IF in the second frame are input to display areas ARA of area ALPa and area ALPb, respectively, two frames later.

[0231] Similarly, each of the data Da to Dc input to interface IF in the third frame is input to the respective display area ARA of area ALPa to ALPc two frames later.

[0232] Similarly, the data Da and data Db input to interface IF in the fourth frame are input to display areas ARA of area ALPa and area ALPb, respectively, two frames later.

[0233] To summarize the above, in the display area ARA included in area ALPa, the image is rewritten twice per frame; in the display area ARA included in area ALPb, the image is rewritten once per frame; in the display area ARA included in area ALPc, the image is rewritten once every two frames; and in the display area ARA included in area ALPa, the image is rewritten once every four frames.

[0234] In other words, by performing the above operations, as shown in Figure 17, the display area ARA included in area ALPa can display an image at a frame frequency of 240 Hz, the display area ARA included in area ALPb can display an image at a frame frequency of 120 Hz, the display area ARA included in area ALPc can display an image at a frame frequency of 60 Hz, and the display area ARA included in area ALPa can display an image at a frame frequency of 30 Hz.

[0235] In Figure 16, when the display device DP is operated at a frame frequency of 120Hz, the interface IF receives a D signal every frame. MAXThe amount of image data is input. On the other hand, by having the display device DP perform the operation described above, the amount of image data input to the interface can be reduced by data Dv2 in the second frame, data Dv3 in the third frame, and data Dv4 in the fourth frame.

[0236] As described above, by increasing the frame frequency of the display area ARA surrounding the area ASU, which is the user's line of sight, and decreasing the frame frequency of the display area ARA far from the area ASU, the amount of image data transmitted to the display unit DIS of the display device DP can be reduced. This eliminates the need for high performance in the interface for transmitting image data to the display device DP, thus reducing power consumption and costs. Furthermore, since it is difficult for users to clearly see the display area ARA far from the area ASU, even if the screen resolution of the display area ARA far from the area ASU is lowered, and the display quality of the image displayed on the entire display unit DIS is reduced, the impact on the user's viewing of the image displayed on the display unit DIS is small.

[0237] Furthermore, if the user's gaze moves and the position of region ASU changes, the positions and ranges of regions ALPa, ALPb, ALPc, and ALPd may also change. For example, as shown in Figure 13B or Figure 14A, when the region the user's gaze is directed towards changes from region ASU to region ASU_AF, the positions of regions ALPa, ALPb, ALPc, and ALPd change. In the example of change in Figure 13B, the ranges (sizes) of regions ALPa and ALPb remain unchanged, while the range of region ALPc shrinks and the range of region ALPd expands. Figure 14A shows an example of change when the region the user's gaze is directed towards changes from region ASU to region ASU_AF, which is near the edge of the display unit DIS. In this example, the ranges of regions ALPa, ALPb, and ALPc shrink, and the range of region ALPd expands.

[0238] Furthermore, if the eye-tracking function of the display device DP fails to detect the user's gaze, the display device DP may set the entire display unit DIS to region ALPe, as shown in Figure 14B. Examples of situations where the user's gaze is not detected include when the user's eyelids are closed or when the user is asleep. The frame frequency of the display region ARA included in region ALPe may be lower than, for example, region ALPd. Alternatively, the frame frequency of region ALPe may be set to 0. In other words, the display device DP may stop transmitting image signals to the display pixels PX of the display region ARA included in region ALPe.

[0239] In the display device DP shown in Figures 13A and 13B, the display unit DIS is divided into four regions: ALPa, ALPb, ALPc, and ALPd, and each of these regions is set to a different frame frequency. However, the display device according to one embodiment of the present invention is not limited to this. For example, the display unit DIS of the display device DP may be divided into two, three, or five or more regions, and each region may be set to a different frame frequency.

[0240] <Example configuration of an electronic device that enables eye-tracking> This section describes an example configuration for an electronic device that enables eye-tracking.

[0241] Figure 18A shows an electronic device (head-mounted display) to which the display device DP of Figure 1A is applied. The electronic device HMD has a housing KYT. The housing KYT has a shape that can be worn on a human head. The housing KYT is equipped with display devices DP_L and DP_R, which correspond to the display device DP described above. Figure 18A shows the left eye ME_L and the right eye ME_R of a user when the user is wearing the electronic device HMD.

[0242] Specifically, the display device DP_L is provided in the housing KYT so as to be located in front of the left eye ME_L of the user wearing the electronic device HMD. That is, in a front view, the left eye ME_L of the user and the display device DP_L have an overlapping area with each other. Also, the display device DP_R is provided in the housing KYT so as to be located in front of the right eye of the user wearing the electronic device HMD. That is, in a front view, the right eye ME_R of the user and the display device DP_R have an overlapping area with each other.

[0243] The electronic device HMD also has an imaging light emitting unit SHB_L, an imaging light emitting unit SHB_R, an imaging light receiving unit SJB_L, and an imaging light receiving unit SJB_R, and each of the listed ones is provided in the housing KYT. Note that the imaging light emitting unit SHB_L and the imaging light emitting unit SHB_R correspond to the imaging light emitting unit SHB in FIG. 1A, and the imaging light receiving unit SJB_L and the imaging light receiving unit SJB_R correspond to the imaging light receiving unit SJB in FIG. 1A.

[0244] The imaging light emitting unit SHB_L and the imaging light receiving unit SJB_L function as devices for tracking the line of sight of the left eye ME_L of the user. Specifically, the imaging light emitting unit SHB_L has a function of irradiating imaging light LGTI_L to the left eye ME_L of the user, and the imaging light receiving unit SJB_L has a function of detecting the light LGTR_L reflected from the left eye ME_L of the user.

[0245] The imaging light receiving unit SJB_L can obtain an image of the left eye ME_L of the user by detecting the light LGTR_L from the left eye ME_L of the user. Since the lens, pupil, cornea, macula, or fovea is shown in the image, the electronic device HMD can determine which part of the display device DP_L the left eye ME_L of the user is looking at by performing image analysis on the image. Thereby, the line of sight of the left eye ME_L of the user can be detected.

[0246] Furthermore, the imaging light-emitting unit SHB_R and the imaging light-receiving unit SJB_R function as devices for tracking the gaze of the user's right eye ME_R. Specifically, the imaging light-emitting unit SHB_R has the function of illuminating the user's right eye ME_R with imaging light LGTI_R, and the imaging light-receiving unit SJB_R has the function of detecting light LGTR_R reflected from the user's right eye ME_R.

[0247] Similarly, the imaging light-receiving unit SJB_R can acquire an image of the user's right eye ME_R by detecting the light LGTR_R from the user's right eye ME_R. Since this image includes the lens, pupil, cornea, macula, or fovea, the electronic device HMD can perform image analysis on this image to determine which part of the display device DP_R the user's right eye ME_R is looking at. This enables the detection of the user's right eye ME_R's line of sight.

[0248] The light emitted by either or both of the imaging light-emitting units SHB_L and SHB_R may be visible light or infrared light (sometimes called IR). Furthermore, the light-receiving devices included in the imaging light-receiving units SJB_L and SJB_R can be determined according to the light emitted by the imaging light-emitting units SHB_L and SHB_R. For example, if the imaging light-emitting unit SHB_L (or SHB_R) emits visible light, the light-receiving device should be capable of receiving visible light. Similarly, if the imaging light-emitting unit SHB_L (or SHB_R) emits infrared light, the light-receiving device should be capable of receiving infrared light.

[0249] Furthermore, gaze detection performed by an electronic device HMD may be performed on either the left or right eye, rather than both eyes. For example, if gaze detection is only to be performed on the left eye, the electronic device HMD can be configured as shown in Figure 18B, with an imaging light-emitting unit SHB_L and an imaging light-receiving unit SJB_L surrounding the display device DP_L, thereby capturing the user's left eye ME_L. Alternatively, if it is not necessary to capture the user's right eye ME_R, the electronic device HMD may be configured as shown in Figure 18B, without an imaging light-emitting unit SHB_R and an imaging light-receiving unit SJB_R surrounding the display device DP_R.

[0250] Furthermore, while the electronic HMD shown in Figures 18A and 18B has a configuration in which one imaging light-emitting unit and one imaging light-receiving unit are provided so as to sandwich one display device on the left and right, one aspect of the present invention is not limited to this. In one aspect of the present invention, the electronic device may have a configuration in which the positions of the imaging light-emitting unit and the imaging light-receiving unit are swapped in Figures 18A and 18B. Also, in one aspect of the present invention, the electronic device may have a configuration in which one imaging light-emitting unit and one imaging light-receiving unit are provided so as to sandwich one display device from above and below. Also, in one aspect of the present invention, the electronic device may have a configuration in which multiple imaging light-emitting units are provided around the display device. Also, in one aspect of the present invention, the electronic device may have a configuration in which multiple imaging light-receiving units are provided around the display device.

[0251] Furthermore, the imaging light-emitting unit and the imaging light-receiving unit may be located inside the display device rather than outside it.

[0252] The electronic device HMD shown in Figure 19A is a head-mounted display to which the display device shown in Figure 1B is applied. Specifically, the pixels included in the display device include light-emitting pixels that function as image-capturing light-emitting units and image-capturing pixels that function as image-capturing light-receiving units. For example, in the electronic device HMD of Figure 19A, the display device DP_L has pixels PU_L that include display pixels for displaying images, light-emitting pixels, and image-capturing pixels, and the display device DP_R has pixels PU_R that include display pixels for displaying images, light-emitting pixels, and image-capturing pixels.

[0253] The light-emitting pixels in pixel PU_L have the function of illuminating the user's left eye ME_L with light LGTI_L, and the imaging pixels in pixel PU_L have the function of detecting light LGTR_L reflected from the user's left eye ME_L. Similarly, the light-emitting pixels in pixel PU_R have the function of illuminating the user's right eye ME_R with light LGTI_R, and the imaging pixels in pixel PU_R have the function of detecting light LGTR_R reflected from the user's right eye ME_R.

[0254] Next, we will explain the path of light LGTI_L (light LGTI_R) from the light-emitting pixels in pixel PU_L (pixel PU_R) to the user's left eye ME_L (user's right eye ME_R), and the path of light LGTR_L (light LGTR_R) from the user's left eye ME_L (user's right eye ME_R) to the light-receiving device in pixel PU_L (pixel PU_R) that detects.

[0255] Figures 19B and 19C are cross-sectional views showing, as an example, a display device DP corresponding to display device DP_L or display device DP_R, and the user's eye ME corresponding to the user's left eye ME_L or the user's right eye ME_R. Figures 19B and 19C also show cross-sectional views of the lens LNS, which functions as an optical system.

[0256] In Figures 19B and 19C, the display device DP has, as an example, a plurality of pixel PUs. Preferably, the plurality of pixel PUs are arranged regularly, for example, in a matrix.

[0257] Each of the imaging light-emitting pixels included in the multiple pixel PUs has the function of emitting light that can be captured by the light-receiving device included in the pixel PU onto the display surface of the display device DP. For example, Figure 19B shows how optical LGTI is emitted from the imaging light-emitting pixels included in the pixel PU onto the display surface of the display device DP.

[0258] Furthermore, the lens LNS has the function of refracting light emitted from the display device DP and directing it towards the user's eye ME. For example, Figure 19B shows how the lens LNS refracts light LGTI and directs it towards the user's eye ME.

[0259] Furthermore, the display pixels included in multiple pixel PUs have the function of emitting light onto the display surface of the display device DP based on the image signal input to the display device DP. The path of the light based on the image signal can be considered to be the same as the path of the light LGTI emitted by the imaging light-emitting pixel. In particular, the user can recognize the light (image) focused on the macula YH on the retina MM as a point or area in their line of sight.

[0260] Furthermore, in Figure 19B, the user's eye ME includes the cornea KM, ciliary body MYT (in this specification, the ciliary zonules (zonial zonules) are also included in the ciliary body MYT), lens SST, vitreous humor GT, retina MM, choroid MRM, sclera KYM, and optic nerve SK.

[0261] Furthermore, a portion of the retinal MM contains the macular yellow hemisphere (YH). The macular YH has a high concentration of cells that are responsible for recognizing fine details and colors. The foveal CSK is also located within the macular YH. The user perceives the light (image) focused by the macular YH in their eye as a point or area of ​​their line of sight.

[0262] For example, Figure 19B shows how the light LGTI emitted from the imaging light-emitting pixels included in the pixel PU of the display device DP is focused onto the macula YH via the lens LNS and the crystalline lens SST.

[0263] The lens (SST) of the user's eye (ME) functions, for example, as a lens to focus light onto the foveal center (CSK) as described above. The ciliary body (MYT) also has the function of changing the thickness of the lens (SST). The degree of light focusing onto the foveal center (CSK) can be adjusted by changing the thickness of the lens (SST). In other words, the lens (SST) and ciliary body (MYT) can adjust the focus of light entering the user's eye (ME).

[0264] Furthermore, the distance between the display device DP and the lens LNS (or the distance between the lens LNS and the user's eye ME) can be freely determined. For example, the distance between the display device DP and the lens LNS is preferably the distance at which the light emitted from the display pixel circuit is focused onto the retina MM of the user's eye ME.

[0265] As described above, by changing the thickness of the lens SST, or by changing the distance between the display device DP and the lens LNS, light from multiple display pixels or multiple imaging light-emitting pixels included in the display device DP can be focused onto the retina MM.

[0266] When light is incident on an object perpendicular to it, it is reflected in the direction 180 degrees from the direction of incidence. In other words, the path of light incident perpendicular to an object and the path of light reflected by that object roughly coincide.

[0267] Therefore, optical LGTR, which is reflected light from the macula YH, reaches the pixel PU via roughly the same path as optical LGTI, as shown in Figure 19B. Specifically, optical LGTR is received by the imaging pixels contained within the pixel PU.

[0268] Therefore, in the display device DP, by performing the imaging operation using the imaging pixels included in all pixel PUs, the retina MM and the macula YH, a part of the retina MM, can be captured as an image. Furthermore, since the user recognizes the light (image) incident on the macula YH as the point or region of their gaze, it is possible to determine which region of the display image on the display device DP the user is looking at from the position (coordinates) where the macula YH is captured in the image.

[0269] Specifically, the address of the image pixel that captured the macula (YH) is obtained from the image, and the display pixels contained within the same pixel are identified. The light emitted by the display pixels contained within the same pixel as the image pixel that captured the macula (YH) reaches the macula (YH). As a result, the display image displayed by the display pixels contained within the same pixel as the image pixel that captured the macula (YH) in the display image of the display device DP represents the area that the user is looking at.

[0270] In this embodiment, gaze detection is performed by the control unit CTL of the display device DP as an example, but the present invention is not limited to this. For example, image analysis based on gaze detection related to the display device DP may be performed by an external server (control computer) instead of the control unit CTL of the display device DP. In other words, the image acquired by the display device DP may be temporarily sent to an external server, the server may perform image analysis and send the analysis results to the display device DP, and the display device may operate according to the result of gaze detection.

[0271] Similarly, processing related to the electronic device HMD (such as image processing) may also be performed on an external server (control computer). A system in which processing is performed on an external server (control computer) to the display device DP (or electronic device HMD), and the processing results are sent to the display device DP (or electronic device HMD) to operate the display device DP (or electronic device HMD) is sometimes called a thin client system. In this case, the display device DP (or electronic device HMD) is sometimes called a thin client terminal.

[0272] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0273] (Embodiment 2) This embodiment describes an example of the configuration of a display device according to one aspect of the present invention.

[0274] <Example of display device configuration 1> Figure 20 is a cross-sectional view showing an example of a display device according to one embodiment of the present invention. The display device 1000 shown in Figure 20 has a configuration in which a pixel circuit, a drive circuit, etc. are provided on a substrate 310, for example. The configuration of the display device DP, etc., shown in Figure 1A of the embodiment described above can be the configuration of the display device 1000 in Figure 20. The pixel circuit described in this embodiment can be the display pixel described in the embodiment described above.

[0275] Furthermore, for example, the circuit layer SICL, the wiring layer LINL, and the pixel layer PXAL shown in the display device DP of Figure 2A can be configured as shown in the display device 1000 of Figure 20. The circuit layer SICL, as an example, has a substrate 310, on which a transistor 300 is formed. Above the transistor 300, the wiring layer LINL is provided, and the wiring layer LINL is provided with wiring that electrically connects the transistor 300, the transistor 500 (described later), the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B (described later). Above the wiring layer LINL, the pixel layer PXAL is provided, as an example, has a transistor 500 and a light-emitting device 130 (in Figure 16, light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B).

[0276] The substrate 310 can be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other examples of substrates 310 include SOI substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films. Examples of glass substrates include barium borosilicate glass, aluminobosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or polytetrafluoroethylene (PTFE). Alternatively, synthetic resins such as acrylic resin are also used. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Alternatively, other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper. Furthermore, if the manufacturing process of the display device 1000 includes heat treatment, it is preferable to select a material with high heat resistance for the substrate 310.

[0277] The diagonal size of the display device can be determined, for example, by the type and size of the substrate 310. For example, when manufacturing a display device with a diagonal size of 10 inches or less, 5 inches or less, 1.5 inches or less, or 1 inch or less for applications such as XR devices or wearable information terminals, a semiconductor substrate can be used as the substrate 310.

[0278] Furthermore, there are no particular limitations on the aspect ratio of the display device 1000. For example, the display device 1000 can support various aspect ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.

[0279] In this embodiment, the substrate 310 is described as a semiconductor substrate having silicon as its material.

[0280] The transistor 300 is provided on a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 consisting of a part of the substrate 310, and low-resistance regions 314a and 314b that function as a source region or drain region. Therefore, the transistor 300 is a Si transistor. In Figure 20, one of the source or drain of the transistor 300 is shown to be electrically connected to the conductors 330 and 356, which will be described later, via the conductor 328, which will be described later. However, the electrical connection configuration of the display device according to one aspect of the present invention is not limited to this. In one aspect of the present invention, for example, the gate of the transistor 300 may be electrically connected to the conductors 330 and 356, which will be described later, via the conductor 328.

[0281] The transistor 300 can be made into a fin type, for example, by configuring the top surface and the side surface in the channel width direction of the semiconductor region 313 to cover the conductor 316 via an insulator 315 that functions as a gate insulating film. By making the transistor 300 a fin type, the effective channel width can be increased, and the on-characteristics of the transistor 300 can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 300.

[0282] The transistor 300 may be either a p-channel or an n-channel type. Alternatively, multiple transistors 300 may be provided, using both p-channel and n-channel types.

[0283] The region where the channel of the semiconductor region 313 is formed, the region near it, and the low-resistance regions 314a and 314b which become the source region or drain region preferably contain a semiconductor such as a silicon-based semiconductor, and more specifically, preferably single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed using, for example, germanium, silicon-germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

[0284] The conductor 316, which functions as a gate electrode, can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum. Alternatively, the conductor 316 can be made of a conductive material such as a metallic material, an alloy material, or a metal oxide material.

[0285] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use titanium nitride and tantalum nitride, or both, as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use tungsten and aluminum, or both, as laminated materials for the conductor, and using tungsten is particularly preferable in terms of heat resistance.

[0286] The element isolation layer 312 is provided to separate multiple transistors formed on the substrate 310. The element isolation layer can be formed using, for example, the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0287] Note that the transistor 300 shown in Figure 20 is just one example, and its structure is not limited to this example. Any suitable transistor can be used depending on the circuit configuration, driving method, etc. For example, transistor 300 may have a planar structure instead of a fin type.

[0288] In the transistor 300 shown in Figure 20, insulators 320, 322, 324, and 326 are stacked in order from the substrate 310 side.

[0289] For insulators 320, 322, and 326, one or more selected from silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, and aluminum nitride may be used.

[0290] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and the term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0291] The insulator 322 may also function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment using chemical mechanical polishing (CMP) to improve its flatness.

[0292] Furthermore, it is preferable to use an insulating film (referred to as a barrier insulating film) for the insulator 324 that has barrier properties to prevent the diffusion of impurities such as water and hydrogen from the substrate 310 or the transistor 300, etc., to the region above the insulator 324 (for example, the region where the transistor 500, light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B are provided). Therefore, it is preferable to use an insulating material for the insulator 324 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., the above impurities do not easily permeate it). Also, depending on the situation, it is preferable to use an insulating material for the insulator 324 that has the function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), copper atoms, etc. (i.e., the above oxygen does not easily permeate it). Alternatively, it is preferable to have the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0293] As an example of a film with hydrogen barrier properties, silicon nitride formed by the CVD (Chemical Vapor Deposition) method can be used.

[0294] The amount of hydrogen desorption can be analyzed using methods such as thermal desorption spectroscopy (TDS). For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0295] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, the relative permittivity of the insulator 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0296] Furthermore, insulators 320, 322, 324, and 326 have conductors 328, 330, etc., embedded in them, which connect to light-emitting devices and the like that are provided above insulator 326. Conductors 328, 330, etc., have the function of a plug or wiring. Conductors that have the function of a plug or wiring may be grouped together and assigned the same reference numeral. Also, in this specification, the wiring and the plug that connects to the wiring may be an integrated unit. That is, there may be cases where a part of the conductor functions as wiring, and cases where a part of the conductor functions as a plug.

[0297] The plugs and wiring (conductor 328 or conductor 330) can be made from one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, either in a single layer or in a laminated form. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, with tungsten being preferred. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0298] Wiring layers may be provided on the insulator 326 and the conductor 330. For example, in Figure 20, insulators 350, 352, and 354 are sequentially stacked on top of insulators 326 and conductor 330. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as plugs or wiring for connecting to transistor 300. Conductors 356 can be made using the same material as conductors 328 and 330.

[0299] For example, it is preferable that insulator 350, like insulator 324, is an insulator having barrier properties against one or more substances selected from hydrogen, oxygen, and water. Also, as insulators 352 and 354, it is preferable to use insulators with relatively low dielectric constants in order to reduce parasitic capacitance between wirings, similar to insulator 326. Furthermore, insulators 352 and 354 have the functions of an interlayer insulating film and a planarizing film. In addition, it is preferable that conductor 356 contains a conductor having barrier properties against one or more substances selected from hydrogen, oxygen, and water.

[0300] For example, tantalum nitride can be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from the transistor 300 while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0301] Furthermore, an insulator 512 is provided above the insulator 354 and the conductor 356.

[0302] In Figure 20, the transistor 500 is provided on the insulator 512. It is preferable to use a material that has barrier properties against oxygen or hydrogen for the insulator 512. Specifically, for the insulator 512, one or more selected from silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, or aluminum nitride may be used.

[0303] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor (for example, transistor 500), the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between transistor 500 and transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0304] Furthermore, for example, the same material as the insulator 320 can be used for the insulator 512. Also, by applying materials with relatively low dielectric constants to these insulators, parasitic capacitance between wiring can be reduced. For example, a silicon oxide film or a silicon oxynitride film can be used for the insulator 512.

[0305] Furthermore, an insulator 514 is provided on the insulator 512, and a transistor 500 is provided on the insulator 514. In addition, an insulator 574 is formed on the transistor 500, and an insulator 581 is formed on the insulator 574.

[0306] The insulators 574 and 581 will be described in detail in Embodiment 3.

[0307] It is preferable to use a film (a barrier film) that suppresses impurities such as water and hydrogen in the insulator 514, in the region where the transistor 500 is provided, from the region below the substrate 310 or the insulator 512 where circuit elements are provided. Therefore, for example, silicon nitride formed by the CVD method can be used for the insulator 514.

[0308] As described above, the transistor 500 shown in Figure 20 is an OS transistor that includes a metal oxide in its channel formation region. The OS transistor will be described in detail in Embodiment 3.

[0309] Insulators 592 and 594 are formed sequentially on insulator 581. Conductors 596 are embedded in insulators 592 and 594. Conductors 596 function as a plug or wiring for connecting to transistor 300. Conductors 596 can be provided using the same material as conductors 328 and 330.

[0310] For example, it is preferable that the insulator 592, like the insulator 324, is an insulator having barrier properties against one or more substances selected from hydrogen, oxygen, or water. Also, similar to the insulator 326, it is preferable that the insulator 594 is an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance that occurs between the wirings. Furthermore, the insulator 594 functions as an interlayer insulating film and a planarizing film. It is also preferable that the conductor 596 contains a conductor having barrier properties against one or more substances selected from hydrogen, oxygen, or water.

[0311] Insulators 598 and 599 are formed on the insulator 594 and the conductor 597.

[0312] For example, the insulator 598 is preferably an insulator that has barrier properties against one or more substances selected from hydrogen, oxygen, and water, similar to the insulator 324. Furthermore, for the insulator 599, similar to the insulator 326, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between the wiring. The insulator 599 also functions as an interlayer insulating film and a planarization film.

[0313] A light-emitting device 130R, a light-emitting device 130G, a light-emitting device 130B, and a connection portion 140 are formed on the insulator 599.

[0314] The connection portion 140 is sometimes called the cathode contact portion and is electrically connected to the cathode electrodes of the light-emitting devices 130R, 130G, and 130B, respectively. In Figure 20, the connection portion 140 includes one or more conductors selected from conductors 112a to 112c (described later), one or more conductors selected from conductors 126a to 126c (described later), one or more conductors selected from conductors 129a to 129c (described later), a common layer 114 (described later), and a common electrode 115 (described later).

[0315] The connection portion 140 may be provided so as to surround all four sides of the display unit, or it may be provided inside the display unit (for example, between adjacent light-emitting devices 130).

[0316] The light-emitting device 130R includes a conductor 112a, a conductor 126a on the conductor 112a, and a conductor 129a on the conductor 126a. All of the conductors 112a, 126a, and 129a can be called pixel electrodes, or only a part of them can be called pixel electrodes.

[0317] The light-emitting device 130G includes a conductor 112b, a conductor 126b on the conductor 112b, and a conductor 129b on the conductor 126b. Similar to the light-emitting device 130R, all of the conductors 112b, 126b, and 129b can be called pixel electrodes, or only a part of them can be called pixel electrodes.

[0318] The light-emitting device 130B includes a conductor 112c, a conductor 126c on the conductor 112c, and a conductor 129c on the conductor 126c. Similar to the light-emitting devices 130R and 130G, all of the conductors 112c, 126c, and 129c can be called pixel electrodes, or only a portion of them can be called pixel electrodes.

[0319] Conductors 112a to 112c and conductors 126a to 126c can be fitted with a conductive layer that functions as a reflective electrode, for example. The conductive layer functioning as a reflective electrode can be made of a conductor with high reflectivity to visible light, such as silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu(APC) film). Furthermore, conductors 112a to 112c and conductors 126a to 126c can be fitted with a laminated film of aluminum sandwiched between a pair of titanium (a laminated film in the order of Ti, Al, Ti), or a laminated film of silver sandwiched between a pair of indium tin oxides (a laminated film in the order of ITO, Ag, ITO).

[0320] Alternatively, for example, a conductive layer that functions as a reflective electrode may be used in conductors 112a to 112c, and a highly transparent conductor may be used in conductors 126a to 126c. Examples of highly transparent conductors include silver-magnesium alloys and indium tin oxide (sometimes called ITO).

[0321] For example, conductive layers that function as transparent electrodes can be used for the conductors 129a to 129c. As the conductive layer that functions as a transparent electrode, for example, the highly light-transmitting conductor described above can be used.

[0322] Furthermore, a microcavity structure (micro-resonator structure) may be provided in the light-emitting device 130, which will be described in detail later. A microcavity structure refers to a structure in which the distance between the lower surface of the light-emitting layer and the upper surface of the lower electrode is set to a thickness corresponding to the wavelength of the light color emitted by the light-emitting layer. In this case, it is preferable to use a conductive material having light-transmitting and light-reflecting properties for the conductors 129a to 129c, which are the upper electrodes (common electrodes), and to use a conductive material having light-reflecting properties for the conductors 112a to 112c and 126a to 126c, which are the lower electrodes (pixel electrodes).

[0323] A microcavity structure refers to a structure in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the light to be amplified). As a result, the light reflected back by the lower electrode (reflected light) interferes significantly with the light that directly enters the upper electrode from the light-emitting layer (incident light). Therefore, the phases of the reflected light and the incident light, both of which have wavelengths of λ, can be matched, and the light emitted from the light-emitting layer can be further amplified. On the other hand, if the reflected light and the incident light have wavelengths other than λ, the phases will not match, and the light will attenuate without resonance.

[0324] Conductor 112a is connected to conductor 596 embedded in insulator 594 through an opening provided in insulator 599. Furthermore, the end of conductor 126a is located outside the end of conductor 112a. The ends of conductor 126a and conductor 129a are aligned or approximately aligned.

[0325] The conductors 112b, 126b, and 129b in the light-emitting device 130G, and conductors 112c, 126c, and 129c in the light-emitting device 130B, are the same as conductors 112a, 126a, and 129a in the light-emitting device 130R, so a detailed explanation is omitted.

[0326] The conductors 112a, 112b, and 112c have recesses formed in them so as to cover the openings provided in the insulator 519. Layer 128 is embedded in these recesses.

[0327] Layer 128 has the function of flattening the recesses of conductors 112a, conductors 112b, and conductors 112c. Conductors 126a, conductors 126b, and conductors 126c, which are electrically connected to conductors 112a, conductors 112b, and conductors 112c, are provided on conductors 112a, conductors 112b, and conductors 112c and on layer 128. Therefore, the regions that overlap with the recesses of conductors 112a, conductors 112b, and conductors 112c can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixels.

[0328] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material.

[0329] Layer 128 can suitably be an insulating layer having an organic material. For example, layer 128 can be made of acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins. Alternatively, a photosensitive resin can be used as layer 128. Examples of photosensitive resins include positive-type materials and negative-type materials.

[0330] By using a photosensitive resin, layer 128 can be fabricated using only exposure and development processes, thereby reducing the impact of dry etching or wet etching on the surfaces of conductors 112a, 112b, and 112c. Furthermore, by forming layer 128 using a negative-type photosensitive resin, it may be possible to form layer 128 using the same photomask (exposure mask) used to form the openings of the insulator 519.

[0331] Although Figure 20 shows an example in which the upper surface of layer 128 has a flat portion, the shape of layer 128 is not particularly limited. Figures 21A to 21C show examples of variations of layer 128.

[0332] As shown in Figures 21A and 21C, the upper surface of layer 128 can be configured to have a shape in which the center and its vicinity are recessed in a cross-sectional view, that is, a shape having a concave curved surface.

[0333] Furthermore, as shown in Figure 21B, the upper surface of layer 128 can be configured to have a shape that bulges in the center and its vicinity when viewed in cross-section, that is, a shape with a convex curved surface.

[0334] Furthermore, the upper surface of layer 128 may have one or both of a convex and a concave surface. Also, the number of convex and concave surfaces on the upper surface of layer 128 is not limited and can be one or more.

[0335] Furthermore, the height of the top surface of layer 128 and the height of the top surface of the conductor 112a may be the same or approximately the same, or they may be different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of the conductor 112a.

[0336] Furthermore, Figure 21A can be seen as an example in which the layer 128 is housed inside a recess formed in the conductor 112a. On the other hand, as shown in Figure 21C, the layer 128 may be located outside the recess formed in the conductor 112a, that is, the width of the upper surface of the layer 128 may be wider than that of the recess.

[0337] Light-emitting device 130R has a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. Light-emitting device 130G has a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. Light-emitting device 130B has a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

[0338] The first layer 113a is formed to cover the top and side surfaces of conductor 126a and conductor 129a. Similarly, the second layer 113b is formed to cover the top and side surfaces of conductor 126b and conductor 129b. Similarly, the third layer 113c is formed to cover the top and side surfaces of conductor 126c and conductor 129c. Therefore, the entire region where conductors 126a, 126b, and 126c are provided can be used as the light-emitting region of light-emitting devices 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixels.

[0339] In the light-emitting device 130R, the first layer 113a and the common layer 114 can be collectively referred to as the EL layer. Similarly, in the light-emitting device 130G, the second layer 113b and the common layer 114 can be collectively referred to as the EL layer. Similarly, in the light-emitting device 130B, the third layer 113c and the common layer 114 can be collectively referred to as the EL layer.

[0340] The configuration of the light-emitting device in this embodiment is not particularly limited and may be a single structure or a tandem structure.

[0341] The first layer 113a, the second layer 113b, and the third layer 113c are processed into island-like structures using photolithography. As a result, the first layer 113a, the second layer 113b, and the third layer 113c each have an angle of nearly 90 degrees between the top surface and the side surface at their edges. On the other hand, for example, an organic film formed using an FMM (Fine Metal Mask) tends to gradually thin out towards the edges, and for example, the top surface is formed in a sloping shape over a range of 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0342] The first layer 113a, the second layer 113b, and the third layer 113c have a clear distinction between their top and side surfaces. As a result, in adjacent first layer 113a and second layer 113b, one side surface of the first layer 113a and one side surface of the second layer 113b are positioned opposite each other. This is true for any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

[0343] Each of the first layer 113a, the second layer 113b, and the third layer 113c has at least one light-emitting layer. For example, it is preferable that the first layer 113a has a light-emitting layer that emits red light, the second layer 113b has a light-emitting layer that emits green light, and the third layer 113c has a light-emitting layer that emits blue light. In addition, each light-emitting layer may be made of a color other than those mentioned above, such as cyan, magenta, yellow, or white.

[0344] Furthermore, the first layer 113a, the second layer 113b, and the third layer 113c may each have one or more of the following: a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0345] For example, the first layer 113a, the second layer 113b, and the third layer 113c may have a hole injection layer, a hole transport layer, an emissive layer, and an electron transport layer. An electron blocking layer may also be present between the hole transport layer and the emissive layer. Furthermore, an electron injection layer may be present on the electron transport layer.

[0346] Furthermore, for example, each of the first layer 113a, the second layer 113b, and the third layer 113c may have an electron injection layer, an electron transport layer, an emissive layer, and a hole transport layer. In particular, it is preferable that in each of the first layer 113a, the second layer 113b, and the third layer 113c, the electron injection layer, the electron transport layer, the emissive layer, and the hole transport layer are stacked in this order. A hole block layer may also be provided between the electron transport layer and the emissive layer. A hole injection layer may also be provided on the hole transport layer.

[0347] Preferably, the first layer 113a, the second layer 113b, and the third layer 113c each have an emissive layer and a carrier transport layer (electron transport layer or hole transport layer) on the emissive layer. Since the surfaces of the first layer 113a, the second layer 113b, and the third layer 113c may be exposed during the manufacturing process of the display device, providing the carrier transport layer on the emissive layer suppresses exposure of the emissive layer to the outermost surface and reduces damage to the emissive layer. This improves the reliability of the light-emitting device and the light-receiving device.

[0348] Furthermore, the first layer 113a, the second layer 113b, and the third layer 113c may have, for example, a configuration comprising a first light-emitting unit, a charge-generating layer, and a second light-emitting unit. For example, it is preferable that the first layer 113a has two or more light-emitting units that emit red light, the second layer 113b has two or more light-emitting units that emit green light, and the third layer 113c has two or more light-emitting units that emit blue light.

[0349] The second light-emitting unit preferably includes a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Since the surface of the second light-emitting unit is exposed during the manufacturing process of the display device, providing the carrier transport layer on the light-emitting layer suppresses exposure of the light-emitting layer to the outermost surface, thereby reducing damage to the light-emitting layer. This improves the reliability of the light-emitting device.

[0350] The common layer 114 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B.

[0351] Furthermore, the common electrode 115 is shared by light-emitting devices 130R, 130G, and 130B. Also, as shown in Figure 20, the common electrode 115, which is shared by multiple light-emitting devices, is electrically connected to a conductor included in the connection part 140.

[0352] The sides of the first layer 113a, the second layer 113b, and the third layer 113c are covered by insulators 125 and 127, respectively. A mask layer 118a is located between the first layer 113a and insulator 125. A mask layer 118a is also located between the second layer 113b and insulator 125, and a mask layer 118a is located between the third layer 113c and insulator 125. A common layer 114 is provided on the first layer 113a, the second layer 113b, the third layer 113c, insulator 125, and insulator 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to multiple light-emitting devices.

[0353] The insulator 125 can be an insulating layer having an inorganic material. For example, one or more inorganic insulating films selected from oxide insulating films, nitride insulating films, oxidative nitride insulating films, and nitride oxide insulating films can be used for the insulator 125. The insulator 125 may be a single layer or a laminated structure. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, indium gallium zinc oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, or tantalum oxide films. Examples of nitride insulating films include silicon nitride films or aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxidative nitride films or aluminum oxidative nitride films. Examples of nitride oxide insulating films include silicon nitride films and aluminum nitride films. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer during the formation of the insulator 127 described later. In particular, by applying an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD (Atomic Layer Deposition) method to the insulator 125, it is possible to form an insulator 125 with fewer pinholes and excellent function in protecting the EL layer. Alternatively, the insulator 125 may have a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulator 125 may have a laminated structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0354] Preferably, the insulator 125 functions as a barrier insulating layer against water and / or oxygen. Furthermore, preferably, the insulator 125 has the function of suppressing the diffusion of water and / or oxygen. Also, preferably, the insulator 125 has the function of capturing or fixing (also known as gettering) water and / or oxygen.

[0355] The insulator 125 functions as a barrier insulating layer or has a gettering function, thereby suppressing the intrusion of impurities (typically water and / or oxygen) that could diffuse from the outside into each light-emitting device. This configuration makes it possible to provide highly reliable light-emitting devices and, furthermore, highly reliable display panels.

[0356] Furthermore, it is preferable that the insulator 125 has a low impurity concentration. This prevents impurities from entering the EL layer from the insulator 125 and degrading the EL layer. Also, by lowering the impurity concentration in the insulator 125, the barrier properties against water and oxygen, or both, can be improved. For example, it is desirable that the hydrogen concentration and carbon concentration of the insulator 125, preferably both, are sufficiently low.

[0357] As the insulator 127, an insulating layer having an organic material can be suitably used. Preferably, a photosensitive organic resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin may be used. Furthermore, the viscosity of the material for the insulator 127 should be between 1 cP and 1500 cP, and preferably between 1 cP and 12 cP. By setting the viscosity of the material for the insulator 127 within the above range, the tapered insulator 127, as described later, can be formed relatively easily. Note that in this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0358] Furthermore, the insulator 127 only needs to have a tapered shape on its side surface, as will be described later, and the organic materials that can be used for the insulator 127 are not limited to those mentioned above. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins may be used as the insulator 127. In addition, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used as the insulator 127. Furthermore, for example, a photoresist may be used as the photosensitive resin for the insulator 127. In addition, the photosensitive resin may be a positive-type material or a negative-type material.

[0359] The insulator 127 may be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting device, the insulator 127 can suppress light leakage (stray light) from the light-emitting device to adjacent light-emitting devices through the insulator 127. This improves the display quality of the display panel. Furthermore, since the display quality can be improved without using a polarizing plate in the display panel, the display panel can be made lighter and thinner.

[0360] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). In particular, it is preferable to use a resin material which is made by laminating or mixing two or more color filter materials, as this can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, it is possible to create a black or near-black resin layer.

[0361] The insulator 127 can be formed using wet film deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating. In particular, it is preferable to form the organic insulating film that will become the insulator 127 by spin coating.

[0362] The insulator 127 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature when forming the insulator 127 is typically 200°C or lower, preferably 180°C or lower, more preferably 160°C or lower, more preferably 150°C or lower, and more preferably 140°C or lower.

[0363] In the following, the structure of the insulator 127 will be explained using the structure of the insulator 127 between light-emitting devices 130R and 130G as an example. The same applies to the insulator 127 between light-emitting devices 130G and 130B, and between light-emitting devices 130B and 130R. In addition, in the following, the end of the insulator 127 on the second layer 113b will be used as an example, but the same applies to the end of the insulator 127 on the first layer 113a and the end of the insulator 127 on the third layer 113c.

[0364] Preferably, the insulator 127 has a tapered shape with a taper angle θ1 on its side surface when viewed in cross-section of the display device. The taper angle θ1 is the angle between the side surface of the insulator 127 and the substrate surface. However, it is not limited to the substrate surface; it may also be the angle between the side surface of the insulator 127 and the upper surface of the flat portion of the insulator 125, the upper surface of the flat portion of the second layer 113b, or the upper surface of the flat portion of the pixel electrode 111b. Furthermore, by making the side surface of the insulator 127 tapered, the side surface of the insulator 125 and the side surface of the mask layer 118a may also become tapered.

[0365] The taper angle θ1 of the insulator 127 is less than 90°, preferably 60° or less, and more preferably 45° or less. By making the side edges of the insulator 127 have such a forward taper shape, the common layer 114 and common electrode 115 provided on the side edges of the insulator 127 can be coated with good coverage without causing stepped breaks or localized thinning. As a result, the in-plane uniformity of the common layer 114 and common electrode 115 can be improved, and the display quality of the display device can be improved.

[0366] Furthermore, in a cross-sectional view of the display device, it is preferable that the upper surface of the insulator 127 has a convex curved shape. The convex curved shape of the upper surface of the insulator 127 is preferably a shape that bulges gently towards the center. It is also preferable that the protruding curved portion at the center of the upper surface of the insulator 127 is smoothly connected to the tapered portion at the side end. By giving the insulator 127 such a shape, the common layer 114 and the common electrode 115 can be formed on the entire surface of the insulator 127 with good coverage.

[0367] Furthermore, the insulator 127 is formed in the region between the two EL layers (for example, the region between the first layer 113a and the second layer 113b). In this case, part or all of the insulator 127 is positioned between the side edge of one EL layer (for example, the first layer 113a) and the side edge of the other EL layer (for example, the second layer 113b).

[0368] Furthermore, it is preferable that one end of the insulator 127 overlaps with the pixel electrode 111a and the other end of the insulator 127 overlaps with the pixel electrode 111b. With this structure, the end of the insulator 127 can be formed on a generally flat region of the first layer 113a (second layer 113b). Therefore, it becomes relatively easy to process the tapered shape of the insulator 127 as described above.

[0369] As described above, by providing an insulator 127 or the like, it is possible to prevent the formation of stepped sections and locally thinned areas in the common layer 114 and common electrode 115 from the generally flat region of the first layer 113a to the generally flat region of the second layer 113b. Therefore, it is possible to suppress connection failures caused by stepped sections and increases in electrical resistance caused by locally thinned areas in the common layer 114 and common electrode 115 between each light-emitting device.

[0370] The display device of this embodiment can reduce the distance between light-emitting devices. Specifically, the distance between light-emitting devices, the distance between EL layers, or the distance between pixel electrodes can be less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of this embodiment has a region where the distance between two adjacent island-shaped EL layers is 1 μm or less, preferably a region of 0.5 μm (500 nm) or less, and more preferably a region of 100 nm or less. By reducing the distance between each light-emitting device in this way, a display device with high resolution and a large aperture ratio can be provided.

[0371] A protective layer 131 is provided on the light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B, respectively. The protective layer 131 functions as a passivation film that protects the light-emitting device 130. By providing a protective layer 131 that covers the light-emitting device, it is possible to suppress the intrusion of impurities such as water and oxygen into the light-emitting device, thereby improving the reliability of the light-emitting device 130.

[0372] For example, aluminum oxide, silicon nitride, or silicon nitride oxide can be used for the protective layer 131.

[0373] The protective layer 131 and the substrate 110 are bonded together via the adhesive layer 107. For sealing the light-emitting device, a solid sealing structure or a hollow sealing structure can be applied. In Figure 20, the space between the substrate 310 and the substrate 110 is filled with the adhesive layer 107, indicating a solid sealing structure. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), indicating a hollow sealing structure. In this case, the adhesive layer 107 may be provided so as not to overlap with the light-emitting device. Furthermore, the space may be filled with a resin different from the adhesive layer 107, which is provided in a frame shape.

[0374] Various types of curing adhesives can be used for the adhesive layer 107, including UV-curing photocuring adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, epoxy resins with low moisture permeability are preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0375] The display device 1000 is a top-emission type. The light emitted by the light-emitting device is emitted towards the substrate 110. Therefore, it is preferable to use a material with high transparency to visible light for the substrate 110. For example, for the substrate 110, a substrate with high transparency to visible light can be selected from among substrates applicable to substrate 310 and substrate BS. The pixel electrodes contain a material that reflects visible light, and the counter electrodes (common electrodes 115) contain a material that transmits visible light.

[0376] By applying the above configuration examples to a display device, it is possible to realize a display device with high resolution and high detail. Specifically, for example, it may be possible to realize a display device with resolutions of HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), and 8K (7680 x 4320 pixels). Furthermore, specifically, for example, it may be possible to realize a display device with detail of 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more.

[0377] It should be noted that the display device according to one aspect of the present invention is not limited to the configuration of the display device 1000 shown in Figure 20. The display device according to one aspect of the present invention may be a configuration of the display device 1000 of Figure 20 with appropriate modifications. Below, an example of a modification of the display device of Figure 20, which is a display device according to one aspect of the present invention, will be described.

[0378] <Example of display device configuration 2> For example, the pixel layer PXAL of the display device 1000 shown in Figure 20 may have a configuration in which two or more transistors 500 are stacked. The display device 1000A shown in Figure 22 is an example of a configuration in which two layers of transistors 500, which are included in the pixel layer PXAL of the display device 1000 of Figure 20, are stacked. Note that only the pixel layer PXAL of the display device 1000A shown in Figure 22 is illustrated, and the circuit layer SICL and wiring layer LINL can be referenced from the configuration of the display device 1000 in Figure 22.

[0379] If you want to increase the number of transistors included in the pixels of the display device 1000, you can apply the configuration shown in the display device 1000A of Figure 22.

[0380] <Example of display device configuration 3> Furthermore, for example, the circuit layer SICL of the display device 1000 shown in Figure 20 may have an OS transistor stacked above the transistor 300. The display device 1000B1 shown in Figure 23 is an example of a configuration in which the circuit layer SICL of the display device 1000 of Figure 20 has an OS transistor, transistor 300OS, stacked above the transistor 300. Note that the display device 1000B1 shown in Figure 23 only shows the layers containing the circuit layer SICL, the wiring layer LINL, and the transistor 500 of the pixel layer PXAL, and for the layers containing the light-emitting device of the pixel layer PXAL, the configuration of the display device 1000 in Figure 20 can be referred to.

[0381] Because fabricating p-type semiconductors using metal oxides is difficult from the standpoint of mobility and reliability, circuits composed of OS transistors are often n-channel unipolar circuits. Therefore, in the display device 1000B1 shown in Figure 23, the transistor 300OS can be made an n-type transistor and the transistor 300 a p-type transistor, and the circuit included in the circuit layer SICL in Figure 23 can be configured as a CMOS circuit. In particular, a circuit configured with an n-type transistor for the OS transistor and a p-type transistor for the Si transistor is sometimes called an LTPO.

[0382] Furthermore, for example, the circuit layer SICL of the display device 1000 shown in Figure 20 may have an OS transistor formed in place of the transistor 300. The display device 1000B2 shown in Figure 24 is an example of a configuration in which the circuit layer SICL of the display device 1000 in Figure 20 has an OS transistor, transistor 300OS, formed in place of the transistor 300.

[0383] In the display device 1000B2 shown in Figure 24, substrates other than semiconductor substrates can be used for the substrate 310. For example, the substrate 310 can be a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing fibrous material, or a base film. If heat treatment is included in the manufacturing process of the display device, it is preferable to select a material with high heat resistance for the substrate 310.

[0384] Furthermore, for example, the circuit layer SICL of the display device 1000 shown in Figure 20 may be configured by bonding multiple substrates together. The circuit layer SICL of the display device 1000B4 shown in Figure 25 has a substrate 310 and a substrate 310A, with the upper surface of substrate 310 and the lower surface of substrate 310A bonded together. Note that Figure 25 only shows the circuit layer SICL and the layers containing the transistor 500 of the pixel layer PXAL; for the wiring layer LINL and the layers containing the light-emitting device of the pixel layer PXAL, refer to the configuration of the display device 1000 in Figure 20.

[0385] In the display device 1000B4 shown in Figure 25, the configuration from the substrate 310 to the insulator 326 and conductor 330 should be described with reference to the explanation of the display device 1000 in Figure 20.

[0386] Insulators 350 and 352 are formed sequentially on the insulator 326 and conductor 330, similar to the display device 1000 in Figure 20.

[0387] Furthermore, openings are formed in the regions of the insulator 350 and the insulator 352 that overlap with a portion of the conductor 330, and the conductor 358 is provided to fill these openings. The conductor 358 is also formed on the insulator 352. Subsequently, the conductor 358 is patterned into the form of wiring, terminals, or pads by an etching process or the like.

[0388] Examples of materials that can be used as the conductor 358 include copper, aluminum, tin, zinc, tungsten, silver, platinum, and gold. Preferably, the conductor 358 is composed of the same components as the material used in the conductor 319A, which will be described later.

[0389] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then a planarization process using chemical mechanical polishing (CMP) or the like is performed until the conductor 376 is exposed. This allows the conductor 376 to be formed on the substrate 310 as wiring, terminals, or pads.

[0390] It is preferable that the insulator 380 uses a film (a barrier film) that suppresses the diffusion of impurities such as water and hydrogen. In other words, it is preferable that the insulator 380 uses a material that can be used for insulator 324. Alternatively, as insulator 380, for example, an insulator with a relatively low dielectric constant may be used to reduce parasitic capacitance that occurs between wirings, similar to insulator 326. In other words, the insulator 380 may use a material that can be used for insulator 326. Furthermore, it is preferable that the insulator 380 is composed of the same components as the material used for insulator 382, ​​which will be described later.

[0391] Next, the substrate 310A will be described. Substrate 310A can be, for example, a semiconductor substrate that can be applied to substrate 310.

[0392] Furthermore, transistors, insulators, and conductors are formed on substrate 310A, similar to substrate 310. Specifically, transistor 300A is formed on substrate 310A, insulator 320A is formed to cover transistor 300A, and insulators 322A, 324A, 326A, and 350A are formed sequentially on insulator 320A. Note that the material applicable to insulator 320 can be used for insulator 320. Similarly, the material applicable to insulator 322 can be used for insulator 322, the material applicable to insulator 324 can be used for insulator 324, the material applicable to insulator 326 can be used for insulator 326, and the material applicable to insulator 350 can be used for insulator 350.

[0393] Furthermore, insulators 320A and 322A have a conductor 328A embedded in them that functions as a plug or wiring, similar to conductor 328. Similarly, insulators 324A and 326A have a conductor 330A embedded in them that functions as a plug or wiring, similar to conductor 330. Note that conductor 328A can be made from a material applicable to conductor 328, and conductor 330A can be made from a material applicable to conductor 330.

[0394] For details regarding the configuration of the display device 1000B4 above the insulator 350A, please refer to the description of the display device 1000.

[0395] Furthermore, an insulator 382 is formed on the side of the substrate 310A opposite to the side on which the transistor 300A is formed. As described above, the insulator 382 can be made of the same material as the insulator 380.

[0396] Furthermore, insulators 320A and 322A have openings not only where the conductor 328A is formed, but also in the region that overlaps with the conductor 358. In addition, insulator 318A is formed on the side of the opening formed in the region that overlaps with the conductor 358, and conductor 319A is formed in the remaining opening. Conductor 319A is sometimes referred to as a TSV (Through Silicon Via).

[0397] As described above, the conductor 319A can be made of a material that is applicable to the conductor 358. The insulator 318A has the function of insulating the substrate 310A from the conductor 319A, for example. It is preferable to use a material that is applicable to the insulator 320 or the insulator 324 as the insulator 318A.

[0398] The insulator 380 and the conductor 358 function as bonding layers on the substrate 310 side, while the insulator 382 and the conductor 319A function as bonding layers on the substrate 310A side. In other words, the insulator 380 and the conductor 358 formed on the substrate 310 and the insulator 382 and the conductor 319A formed on the substrate 310A can be joined, for example, by a bonding process.

[0399] As a preliminary step before the bonding process, for example, a planarization process is performed on the substrate 310 to make the surface heights of the insulator 380 and the conductor 358 the same. Similarly, a planarization process is performed on the substrate 310 to make the surface heights of the insulator 382 and the conductor 319A the same.

[0400] In the bonding process, when joining insulator 380 and insulator 382, ​​that is, joining insulating layers, a hydrophilic bonding method can be used. This method involves first providing high flatness through polishing (for example, chemical mechanical polishing (CMP)), then bringing the surfaces that have been hydrophilically treated with oxygen plasma or the like into contact for temporary bonding, and finally performing permanent bonding through dehydration by heat treatment. Since hydrophilic bonding also involves bonding at the atomic level, a mechanically superior bond can be obtained.

[0401] Furthermore, when joining conductor 358 and conductor 319A, that is, joining conductors to conductors, a surface activation bonding method can be used, in which the oxide film and impurity adsorption layer on the surface are removed by sputtering or other means, and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method can be used, in which temperature and pressure are used in combination to bond the surfaces. In both cases, bonding occurs at the atomic level, so a bonding method with excellent electrical and mechanical properties can be obtained.

[0402] By performing the bonding process described above, the conductor 358 on the substrate 310 side can be electrically connected to the conductor 319A on the substrate 310A side. Furthermore, a mechanically strong connection can be obtained between the insulator 380 on the substrate 310 side and the insulator 382 on the substrate 310A side.

[0403] When bonding substrate 310 and substrate 310A, insulating layers and metal layers are present on each bonding surface. For example, a combination of surface activation bonding and hydrophilic bonding methods can be used. For instance, a method can be used in which the surface is cleaned after polishing, an anti-oxidation treatment is applied to the surface of the metal layer, and then a hydrophilic treatment is performed before bonding. Alternatively, the surface of the metal layer may be made of a metal that is difficult to oxidize, such as gold, and then a hydrophilic treatment may be performed.

[0404] Furthermore, a bonding method other than the one described above may be used to bond substrate 310 and substrate 310A. For example, flip-chip bonding may be used as a method for bonding substrate 310 and substrate 310A. When using flip-chip bonding, connection terminals such as bumps may be provided above the conductor 358 on substrate 310, or below the conductor 319A on substrate 310A. Examples of flip-chip bonding methods include injecting a resin containing anisotropic conductive particles between insulator 380 and insulator 382, ​​and between conductor 358 and conductor 319A, or using silver-tin solder for bonding. Alternatively, if both the bump and the conductor connected to the bump are made of gold, ultrasonic bonding can be used. Furthermore, in order to reduce physical stress such as impact, or to reduce thermal stress, in addition to the flip-chip bonding method described above, an underfill material may be injected between the insulator 380 and the insulator 382, ​​and between the conductor 358 and the conductor 319A. Also, for example, a die bonding film may be used to bond the substrate 310 and the substrate 310A.

[0405] <Example of display device configuration 4> Furthermore, for example, the protective layer 131 of the display device 1000 shown in Figure 20 may be a laminated structure of two or more layers, rather than a single layer. The protective layer 131 may be a three-layer laminated structure, for example, with an inorganic insulating material as the first layer, an organic insulating material as the second layer, and an inorganic insulating material as the third layer. Figure 26 shows a cross-sectional view of a part of the display device 1000E in which the protective layer 131, including protective layers 131a, 131b, and 131c, is a multilayer structure, with protective layer 131a being an inorganic insulating material, protective layer 131b being an organic insulating material, and protective layer 131c being an inorganic insulating material. As shown in Figure 26, by applying an organic insulating material to protective layer 131b, the protective layer 131b can be provided as a planarized film.

[0406] <Example of display device configuration 5> Furthermore, for example, the display device 1000 in Figure 20 may include a color layer (color filter). The display device 1000F in Figure 27, as an example, has a configuration in which a colored layer 166a, a colored layer 166b, and a colored layer 166c are included between the adhesive layer 107 and the substrate 110. The colored layers 166a to 166c can be formed on the substrate 110, for example. Also, if the light-emitting device 130R has a light-emitting layer that emits red (R) light, the light-emitting device 130G has a light-emitting layer that emits green (G) light, and the light-emitting device 130B has a light-emitting layer that emits blue (B) light, then the colored layer 166a is red, the colored layer 166b is green, and the colored layer 166c is blue.

[0407] <Example of display device configuration 6> Furthermore, for example, the display device 1000 in Figure 20 may include imaging pixels. For example, the display device 1000G shown in Figure 28 has a configuration that includes a light-receiving device 150 that detects light L, which is included in the imaging pixels.

[0408] For example, a pn-type or pin-type photodiode can be used as the light-receiving device 150. The light-receiving device 150 functions as a photoelectric conversion device that detects light incident on it and generates an electric charge. The amount of charge generated by the photoelectric conversion element is determined by the amount of incident light.

[0409] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving device 150. Organic photodiodes can be easily made thinner, lighter, and larger in area, and because they offer a high degree of freedom in shape and design, they can be applied to a variety of devices.

[0410] The light-receiving device 150 includes a conductor 112d, a conductor 126d on the conductor 112d, and a conductor 129d on the conductor 126d. All of the conductors 112d, 126d, and 129d can be called pixel electrodes, or only a part of them can be called pixel electrodes.

[0411] Furthermore, the light-receiving device 150 includes a conductor 112d on an insulator 599, a layer 113d on the conductor 112d, a common layer 114 on the layer 113d, and a common electrode 115 on the common layer 114.

[0412] Furthermore, layer 113d has a photoelectric conversion layer that is sensitive to visible light or infrared light wavelengths. The wavelength range to which the photoelectric conversion layer of layer 113d is sensitive may include one or more of the emission wavelength ranges of the first layer 113a, the second layer 113b, and the third layer 113c.

[0413] As shown in Figure 28, the display device DP in Figure 1B can be configured by providing a light-receiving device 150 in the pixel layer PXAL, as shown in the display device 1000G.

[0414] <Example of light-emitting device configuration> Next, we will describe an example configuration of a light-emitting device that can be applied to the display device described above.

[0415] As shown in Figure 29A, the light-emitting device has an EL layer 763 between a pair of electrodes (lower electrode 761 and upper electrode 762). The EL layer 763 can be a layer including layer 780, light-emitting layer 771, and layer 790.

[0416] The light-emitting layer 771 has at least a light-emitting substance (also called a light-emitting material).

[0417] When the lower electrode 761 is the anode and the upper electrode 762 is the cathode, layer 780 has one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a material with high hole transport properties (hole transport layer), and a layer containing a material with high electron blocking properties (electron blocking layer). Similarly, layer 790 has one or more of the following: a layer containing a material with high electron injection properties (electron injection layer), a layer containing a material with high electron transport properties (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). When the lower electrode 761 is the cathode and the upper electrode 762 is the anode, layers 780 and 790 have the opposite configurations to those described above.

[0418] A configuration having a layer 780, an emissive layer 771, and a layer 790 provided between a pair of electrodes can function as a single emissive unit, and in this specification, the configuration shown in Figure 29A is referred to as a single structure.

[0419] Furthermore, Figure 29B shows an example of a modification of the EL layer 763 in the light-emitting device shown in Figure 29A. Specifically, the light-emitting device shown in Figure 29B has a layer 781 on the lower electrode 761, a layer 782 on the layer 781, a light-emitting layer 771 on the layer 782, a layer 791 on the light-emitting layer 771, a layer 792 on the layer 791, and an upper electrode 762 on the layer 792.

[0420] When the lower electrode 761 is the anode and the upper electrode 762 is the cathode, for example, layer 781 can be a hole injection layer, layer 782 a hole transport layer, layer 791 an electron transport layer, and layer 792 an electron injection layer. Also, when the lower electrode 761 is the cathode and the upper electrode 762 is the anode, layer 781 can be an electron injection layer, layer 782 an electron transport layer, layer 791 a hole transport layer, and layer 792 a hole injection layer. By using such a layer structure, carriers can be efficiently injected into the light-emitting layer 771, and the efficiency of carrier recombination within the light-emitting layer 771 can be increased.

[0421] As shown in Figures 29C and 29D, a configuration in which multiple light-emitting layers (light-emitting layer 771, light-emitting layer 772, and light-emitting layer 773) are provided between layer 780 and layer 790 is also a variation of the single structure. Although Figures 29C and 29D show an example with three light-emitting layers, the light-emitting layers in a single-structure light-emitting device may be two layers or four or more layers. Furthermore, a single-structure light-emitting device may have a buffer layer between the two light-emitting layers.

[0422] Furthermore, as shown in Figures 29E and 29F, a configuration in which multiple light-emitting units (light-emitting units 763a and 763b) are connected in series via a charge generation layer 785 (also called an intermediate layer) is referred to as a tandem structure in this specification. The tandem structure may also be called a stacked structure. By using a tandem structure, a light-emitting device capable of high-brightness emission can be created. In addition, compared to a single structure, the tandem structure can reduce the current required to obtain the same brightness, thereby improving reliability.

[0423] Figures 29D and 29F show examples in which the display device has a layer 764 that overlaps with the light-emitting device. Figure 29D shows an example in which layer 764 overlaps with the light-emitting device shown in Figure 29C, and Figure 29F shows an example in which layer 764 overlaps with the light-emitting device shown in Figure 29E.

[0424] Layer 764 can be either a color conversion layer or a color filter (coloring layer), or both.

[0425] In Figures 29C and 29D, the light-emitting layers 771, 772, and 773 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. For example, light-emitting materials that emit blue light may be used for the light-emitting layers 771, 772, and 773. In subpixels that emit blue light, the blue light emitted by the light-emitting device can be extracted. In subpixels that emit red light and subpixels that emit green light, a color conversion layer is provided as layer 764 as shown in Figure 29D, which converts the blue light emitted by the light-emitting device into longer wavelength light, allowing for the extraction of red or green light.

[0426] Furthermore, light-emitting materials that emit light of different colors may be used for each of the light-emitting layers 771, 772, and 773. When the light emitted by each of the light-emitting layers 771, 772, and 773 is complementary in color, white light emission is obtained. For example, a single-structure light-emitting device preferably has a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a longer wavelength than blue.

[0427] For example, if a single-structure light-emitting device has three light-emitting layers, it is preferable that it has a light-emitting layer having a light-emitting material that emits red (R) light, a light-emitting layer having a light-emitting material that emits green (G) light, and a light-emitting layer having a light-emitting material that emits blue (B) light. The stacking order of the light-emitting layers can be, for example, red (R), green (G), blue (B) from the anode side, or red (R), green (B), blue (G) from the anode side. In this case, a buffer layer may be provided between the red (R) layer and the green (G) or blue (B) layer.

[0428] Furthermore, for example, when a single-structure light-emitting device has two light-emitting layers, a configuration is preferred in which one light-emitting layer has a light-emitting material that emits blue (B) light, and the other light-emitting layer has a light-emitting material that emits yellow (Y) light. This configuration may be referred to as a BY single structure.

[0429] A color filter may be provided as layer 764, as shown in Figure 29D. By passing white light through the color filter, light of the desired color can be obtained.

[0430] A light-emitting device that emits white light preferably contains two or more types of light-emitting materials. To obtain white light emission, one should select light-emitting materials such that the light emitted by each of the two or more materials is complementary in color. For example, by making the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer complementary, a light-emitting device that emits white light as a whole can be obtained. The same applies to light-emitting devices that have three or more light-emitting layers.

[0431] Furthermore, in Figures 29E and 29F, the light-emitting layer 771 and the light-emitting layer 772 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material.

[0432] For example, in a light-emitting device having subpixels that emit light of each color, light-emitting materials that emit blue light may be used in the light-emitting layer 771 and the light-emitting layer 772, respectively. In the subpixels that emit blue light, the blue light emitted by the light-emitting device can be extracted. In addition, in the subpixels that emit red light and the subpixels that emit green light, a color conversion layer is provided as layer 764 as shown in Figure 29F, which converts the blue light emitted by the light-emitting device into longer wavelength light, allowing red or green light to be extracted.

[0433] Furthermore, when using light-emitting devices with the configuration shown in Figure 29E or Figure 29F for sub-pixels that emit light of each color, different light-emitting materials may be used for each sub-pixel. Specifically, in a light-emitting device for a sub-pixel that emits red light, light-emitting materials that emit red light may be used for both the light-emitting layer 771 and the light-emitting layer 772. Similarly, in a light-emitting device for a sub-pixel that emits green light, light-emitting materials that emit green light may be used for both the light-emitting layer 771 and the light-emitting layer 772. In a light-emitting device for a sub-pixel that emits blue light, light-emitting materials that emit blue light may be used for both the light-emitting layer 771 and the light-emitting layer 772. A display device with such a configuration can be said to have a tandem structure light-emitting device and an SBS structure. Therefore, it can combine the advantages of both the tandem structure and the SBS structure. This enables high-brightness light emission and realizes a highly reliable light-emitting device.

[0434] Furthermore, in Figures 29E and 29F, luminescent materials emitting light of different colors may be used for the luminescent layer 771 and the luminescent layer 772. When the light emitted by the luminescent layer 771 and the light emitted by the luminescent layer 772 are complementary colors, white light emission is obtained. A color filter may be provided as layer 764 as shown in Figure 29F. By passing white light through the color filter, light of a desired color can be obtained.

[0435] In Figures 29E and 29F, examples are shown in which the light-emitting unit 763a has one light-emitting layer 771 and the light-emitting unit 763b has one light-emitting layer 772, but the design is not limited to this. The light-emitting unit 763a and the light-emitting unit 763b may each have two or more light-emitting layers.

[0436] Furthermore, while Figures 29E and 29F illustrate a light-emitting device having two light-emitting units, the device is not limited to this. A light-emitting device may have three or more light-emitting units.

[0437] Specifically, the configuration of the light-emitting device shown in Figures 30A to 30C is an example.

[0438] Figure 30A shows a configuration with three light-emitting units. A configuration with two light-emitting units may also be referred to as a two-stage tandem structure, and a configuration with three light-emitting units may be referred to as a three-stage tandem structure.

[0439] Furthermore, as shown in Figure 30A, the light-emitting device has a configuration in which multiple light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series via a charge generation layer 785 (charge generation layers 785a-b and charge generation layers 785b-c). Specifically, the light-emitting device shown in Figure 30A has a configuration in which light-emitting unit 763a, charge generation layers 785a-b, light-emitting unit 763b, charge generation layers 785b-c, and light-emitting unit 763c are stacked in this order. In addition, light-emitting unit 763a has layer 780a, light-emitting layer 771, and layer 790a, light-emitting unit 763b has layer 780b, light-emitting layer 772, and layer 790b, and light-emitting unit 763c has layer 780c, light-emitting layer 773, and layer 790c.

[0440] For details regarding charge generation layers 785a-b and 785b-c, please refer to the description of charge generation layer 785 above.

[0441] In the configuration shown in Figure 30A, it is preferable that the light-emitting layers 771, 772, and 773 each have a light-emitting material that emits light of the same color. Specifically, the configuration can be such that the light-emitting layers 771, 772, and 773 each have a red (R) light-emitting material (a so-called R\R\R three-stage tandem structure), the light-emitting layers 771, 772, and 773 each have a green (G) light-emitting material (a so-called G\G\G three-stage tandem structure), or the light-emitting layers 771, 772, and 773 each have a blue (B) light-emitting material (a so-called B\B\B three-stage tandem structure).

[0442] The light-emitting materials that each emit light of the same color are not limited to the above configuration. For example, as shown in Figure 30B, a tandem-type light-emitting device may be constructed by stacking multiple light-emitting units having multiple light-emitting materials. Figure 30B shows a configuration in which multiple light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785. Light-emitting unit 763a has layer 780a, light-emitting layers 771a, 771b, and 771c, and layer 790a, while light-emitting unit 763b has layer 780b, light-emitting layers 772a, 772b, and 772c, and layer 790b.

[0443] In the configuration shown in Figure 30B, the light-emitting layers 771a, 771b, and 771c are configured to emit white light (W) by selecting light-emitting materials that are complementary in color. Furthermore, the light-emitting layers 772a, 772b, and 772c are configured to emit white light (W) by selecting light-emitting materials that are complementary in color. That is, the configuration shown in Figure 30C is a two-stage tandem structure of W\W. There are no particular limitations on the stacking order of the complementary light-emitting materials in the light-emitting layers 771a, 771b, and 771c. The implementer can select the optimal stacking order as appropriate. Although not shown, a three-stage tandem structure of W\W\W, or a tandem structure of four or more stages, may also be used.

[0444] Furthermore, when using a tandem light-emitting device, there are two-stage tandem structures B\Y having a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, two-stage tandem structures RG\B having a light-emitting unit that emits red (R) and green (G) light and a light-emitting unit that emits blue (B) light, and a light-emitting unit that emits blue (B) light. Examples include a B\Y\B three-stage tandem structure having a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow-green (YG) light, and a light-emitting unit that emits blue (B) light in that order, and a B\YG\B three-stage tandem structure having a light-emitting unit that emits blue (B) light, a light-emitting unit that emits green (G) light, and a light-emitting unit that emits blue (B) light in that order.

[0445] Furthermore, as shown in Figure 30C, a combination of a light-emitting unit having one light-emitting material and a light-emitting unit having multiple light-emitting materials may be used.

[0446] Specifically, in the configuration shown in Figure 30C, multiple light-emitting units (light-emitting units 763a, 763b, and 763c) are connected in series via charge generation layers (charge generation layers 785a-b and 785b-c). Light-emitting unit 763a has layer 780a, light-emitting layer 771, and layer 790a; light-emitting unit 763b has layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b; and light-emitting unit 763c has layer 780c, light-emitting layer 773, and layer 790c.

[0447] For example, in the configuration shown in Figure 30C, a three-stage tandem structure of B\R·G·YG\B can be applied, where light-emitting unit 763a is a light-emitting unit that emits blue (B) light, light-emitting unit 763b is a light-emitting unit that emits red (R), green (G), and yellow-green (YG) light, and light-emitting unit 763c is a light-emitting unit that emits blue (B) light.

[0448] For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y and B, or a three-layer structure of B, X and B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R and G, or a three-layer structure of R, G and R. In addition, other layers may be provided between the two light-emitting layers.

[0449] Furthermore, in Figures 29C and 29D, as shown in Figure 29B, layer 780 and layer 790 may each be independently constructed as a laminated structure consisting of two or more layers.

[0450] Furthermore, in Figures 29E and 29F, the light-emitting unit 763a has layer 780a, light-emitting layer 771, and layer 790a, and the light-emitting unit 763b has layer 780b, light-emitting layer 772, and layer 790b.

[0451] When the lower electrode 761 is the anode and the upper electrode 762 is the cathode, layers 780a and 780b each have one or more of the following: a hole injection layer, a hole transport layer, and an electron blocking layer. Similarly, layers 790a and 790b each have one or more of the following: an electron injection layer, an electron transport layer, and a hole blocking layer. When the lower electrode 761 is the cathode and the upper electrode 762 is the anode, layers 780a and 790a have the opposite configurations to those described above, and layers 780b and 790b also have the opposite configurations to those described above.

[0452] When the lower electrode 761 is the anode and the upper electrode 762 is the cathode, for example, layer 780a has a hole injection layer and a hole transport layer on the hole injection layer, and may further have an electron blocking layer on the hole transport layer. Also, layer 790a has an electron transport layer and may further have a hole blocking layer between the light-emitting layer 771 and the electron transport layer. Also, layer 780b has a hole transport layer and may further have an electron blocking layer on the hole transport layer. Also, layer 790b has an electron transport layer and an electron injection layer on the electron transport layer, and may further have a hole blocking layer between the light-emitting layer 772 and the electron transport layer. When the lower electrode 761 is the cathode and the upper electrode 762 is the anode, for example, layer 780a has an electron injection layer and an electron transport layer on the electron injection layer, and may further have a hole blocking layer on the electron transport layer. Furthermore, layer 790a may have a hole transport layer and an electron blocking layer between the light-emitting layer 771 and the hole transport layer. Also, layer 780b may have an electron transport layer and an electron blocking layer on the electron transport layer. Furthermore, layer 790b may have a hole transport layer and a hole injection layer on the hole transport layer, and an electron blocking layer between the light-emitting layer 772 and the hole transport layer.

[0453] Furthermore, when fabricating a tandem light-emitting device, the two light-emitting units are stacked with a charge generation layer 785 in between. The charge generation layer 785 has at least a charge generation region. The charge generation layer 785 has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between the pair of electrodes.

[0454] Next, we will describe materials that can be used in light-emitting devices.

[0455] Of the lower electrode 761 and upper electrode 762, the electrode that extracts light preferably uses a conductive film that transmits visible light. Furthermore, it is preferable to use a conductive film that reflects visible light on the electrode that does not extract light. In addition, if the display device has a light-emitting device that emits infrared light, it is preferable to use a conductive film that transmits both visible light and infrared light on the electrode that extracts light, and a conductive film that reflects both visible light and infrared light on the electrode that does not extract light.

[0456] Furthermore, a conductive film that transmits visible light may also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer 763. In other words, the light emitted from the EL layer 763 may be reflected by the reflective layer and extracted from the display device.

[0457] As the material for forming the pair of electrodes of the light-emitting device, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Another example of such material is an aluminum alloy. An example of an aluminum alloy is an alloy of aluminum (Al), nickel (Ni), and lanthanum (La) (Al-Ni-La). Another example of such material is an alloy of silver, palladium, and copper (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, and graphene.

[0458] It is preferable that the light-emitting device has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting device has an electrode that is transparent to and reflective to visible light (a semi-transmissive / semi-reflective electrode), and the other has an electrode that is reflective to visible light (a reflective electrode). By having a microcavity structure in the light-emitting device, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting device.

[0459] Furthermore, it is preferable to use a conductor that has both transmittance and reflectivity to visible light for the semi-transparent / semi-reflective electrode. Alternatively, for example, the semi-transparent / semi-reflective electrode may have a laminated structure comprising a conductive layer that can be used as a reflective electrode and a conductive layer that can be used as an electrode that transmits to visible light (also called a transparent electrode).

[0460] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of a light-emitting device. The visible light reflectance of the semi-transparent / semi-reflective electrode shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes shall be 1 × 10⁻⁶ -2 A value of Ωcm or less is preferable.

[0461] A light-emitting device has at least a light-emitting layer. Furthermore, a light-emitting device may have layers other than the light-emitting layer that contain a material with high hole injection properties, a material with high hole transport properties, a hole-blocking material, a material with high electron transport properties, an electron-blocking material, a material with high electron injection properties, or a bipolar material (a material with high electron and hole transport properties). For example, a light-emitting device can have a configuration that includes, in addition to the light-emitting layer, one or more layers from among a hole injection layer, a hole transport layer, a hole-blocking layer, a charge generation layer, an electron-blocking layer, an electron transport layer, and an electron injection layer.

[0462] The light-emitting device may use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting device can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, or coating.

[0463] The light-emitting layer has one or more types of light-emitting materials. As appropriate, the light-emitting materials may include substances that emit light in colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red. Furthermore, materials that emit near-infrared light may also be used as light-emitting materials.

[0464] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0465] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0466] Examples of phosphorescent materials include organometallic complexes (especially iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (especially iridium complexes) using phenylpyridine derivatives having electron-withdrawing groups as ligands; platinum complexes; and rare earth metal complexes.

[0467] The light-emitting layer may contain one or more types of organic compounds (e.g., a host material and an assist material) in addition to the light-emitting substance (guest material). One or more types of organic compounds can be substances with high hole transport properties (hole transport materials) and / or substances with high electron transport properties (electron transport materials). As the hole transport material, one of the high hole transport materials that can be used in the hole transport layer, as described later, can be used. As the electron transport material, one of the high electron transport materials that can be used in the electron transport layer, as described later, can be used. Furthermore, one or more types of organic compounds may be bipolar materials or TADF materials.

[0468] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting device.

[0469] The hole injection layer is a layer that injects holes from the anode into the hole transport layer, and is a layer containing a material with high hole injection capabilities. Examples of materials with high hole injection capabilities include aromatic amine compounds and composite materials containing hole transport materials and acceptor materials (electron-accepting materials).

[0470] As the hole-transporting material, a material with high hole-transporting properties that can be used in the hole-transporting layer, as described later, can be used.

[0471] As acceptor materials, for example, oxides of metals belonging to groups 4 through 8 of the periodic table can be used. Specifically, examples of such metal oxides include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide. Among these, molybdenum oxide is particularly preferred because it is stable in the atmosphere, has low hygroscopicity, and is easy to handle. Organic acceptor materials containing fluorine can also be used. Furthermore, organic acceptor materials such as quinodimethane derivatives, chloranil derivatives, and hexaazatriphenylene derivatives can also be used.

[0472] For example, as a material with high hole injection properties, a material containing a hole transport material and an oxide of a metal belonging to Group 4 to Group 8 of the periodic table (typically molybdenum oxide) may be used.

[0473] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light-emitting layer. The hole transport layer is a layer containing a hole-transporting material. The hole-transporting material is 1 × 10⁻¹⁶ -6 cm 2 Materials having a hole mobility of 1 / Vs or higher are preferred. However, other materials can also be used as long as they have higher hole transport capabilities than electron transport. Preferred hole transport materials include π-electron-rich heteroaromatic compounds (e.g., carbazole derivatives, thiophene derivatives, and furan derivatives) and aromatic amines (compounds having an aromatic amine skeleton), which are materials with high hole transport capabilities.

[0474] The electron blocking layer is provided in contact with the light-emitting layer. The electron blocking layer is a layer containing a material that has hole-transporting properties and is capable of blocking electrons. Among the hole-transporting materials mentioned above, a material that has electron-blocking properties can be used for the electron blocking layer.

[0475] Because electron-blocking layers possess hole-transporting properties, they can also be called hole-transporting layers. Furthermore, among hole-transporting layers, those that exhibit electron-blocking properties can also be called electron-blocking layers.

[0476] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light-emitting layer. The electron transport layer is a layer containing an electron-transporting material. The electron-transporting material is 1 × 10⁻¹⁶ -6 cm 2 Materials having an electron mobility of 1 / Vs or higher are preferred. However, other materials can also be used as long as they have higher electron transport capabilities than holes. Examples of electron-transporting materials include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds containing nitrogen-containing heteroaromatic compounds.

[0477] The hole-blocking layer is provided in contact with the light-emitting layer. The hole-blocking layer is a layer containing a material that has electron-transporting properties and is capable of blocking holes. Among the electron-transporting materials mentioned above, a material that has hole-blocking properties can be used for the hole-blocking layer.

[0478] Because hole-blocking layers possess electron-transporting properties, they can also be called electron-transporting layers. Furthermore, among electron-transporting layers, those that exhibit hole-blocking properties can also be called hole-blocking layers.

[0479] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer, and is a layer containing a material with high electron injection capabilities. Alkali metals, alkaline earth metals, or compounds thereof can be used as materials with high electron injection capabilities. Composite materials containing both electron transport materials and donor materials (electron-donating materials) can also be used as materials with high electron injection capabilities.

[0480] Furthermore, it is preferable that the lowest unoccupied molecular orbital (LUMO) level of a material with high electron injection potential has a small difference (specifically, 0.5 eV or less) from the work function value of the material used as the cathode.

[0481] The electron injection layer contains, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), and calcium fluoride (CaF). x (where X is any number), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatrium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatrium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatrium (abbreviation: LiPPP), lithium oxide (LiO x Alkali metals such as cesium carbonate, alkaline earth metals, or compounds thereof can be used. The electron injection layer may also be a multilayer structure of two or more layers. For example, a multilayer structure in which lithium fluoride is used as the first layer and ytterbium is provided as the second layer can be used.

[0482] The electron injection layer may contain an electron transport material. For example, a compound having a lone pair of electrons and an electron-deficient heteroaromatic ring can be used as the electron transport material. Specifically, a compound having one or more rings selected from a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring can be used.

[0483] Furthermore, the LUMO level of organic compounds containing lone pairs of electrons is preferably between -3.6 eV and -2.3 eV. In general, the highest occupied molecular orbital (HOMO) level and the LUMO level of organic compounds can be estimated by methods such as cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, and inverse photoelectron spectroscopy.

[0484] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviated as BPhen), 2,9-di(naphthalene-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviated as NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviated as HATNA), or 2,4,6-tris[3'-(pyridine-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviated as TmPPPyTz) can be used in organic compounds containing lone pairs of electrons. NBPhen has a higher glass transition temperature (Tg) and superior heat resistance compared to BPhen.

[0485] As described above, the charge generation layer has at least a charge generation region. The charge generation region preferably contains an acceptor material, and preferably contains, for example, a hole transport material and an acceptor material applicable to the hole injection layer described above.

[0486] Furthermore, the charge generation layer preferably includes a layer containing a material with high electron injection potential. This layer can also be called an electron injection buffer layer. The electron injection buffer layer is preferably provided between the charge generation region and the electron transport layer. By providing an electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be relaxed, allowing electrons generated in the charge generation region to be easily injected into the electron transport layer.

[0487] The electron injection buffer layer preferably contains an alkali metal or an alkaline earth metal, and can, for example, be configured to contain an alkali metal compound or an alkaline earth metal compound. Specifically, the electron injection buffer layer preferably has an inorganic compound containing an alkali metal and oxygen, or an inorganic compound containing an alkaline earth metal and oxygen, and more preferably has an inorganic compound containing lithium and oxygen (for example, lithium oxide (Li2O)). In addition, any other material applicable to the electron injection layer described above can be suitably used for the electron injection buffer layer.

[0488] The charge generation layer preferably has a layer containing a material with high electron transport properties. This layer can also be called an electron relay layer. The electron relay layer is preferably provided between the charge generation region and the electron injection buffer layer. If the charge generation layer does not have an electron injection buffer layer, the electron relay layer is preferably provided between the charge generation region and the electron transport layer. The electron relay layer has the function of preventing interaction between the charge generation region and the electron injection buffer layer (or electron transport layer) and smoothly transferring electrons.

[0489] As the electron relay layer, it is preferable to use a phthalocyanine-based material such as copper(II) phthalocyanine (abbreviated as CuPc), or a metal complex having a metal-oxygen bond and an aromatic ligand.

[0490] Furthermore, the charge generation region, electron injection buffer layer, and electron relay layer described above may not be clearly distinguishable depending on their cross-sectional shape or characteristics.

[0491] The charge generation layer may have a donor material instead of an acceptor material. For example, the charge generation layer may have a layer containing an electron transport material and a donor material, which is applicable to the electron injection layer described above.

[0492] When stacking light-emitting units, the rise in driving voltage can be suppressed by providing a charge generation layer between the two light-emitting units.

[0493] <Example of pixel circuit configuration> Here, we will describe an example of a pixel circuit configuration that can be provided in the pixel layer PXAL.

[0494] Figures 31A and 31B show examples of pixel circuit configurations that can be provided in the pixel layer PXAL, and a light-emitting device 130 connected to the pixel circuit. Figure 31A shows the connections of each circuit element included in the pixel circuit 400 provided in the pixel layer PXAL, and Figure 31B schematically shows the hierarchical relationship between the circuit layer SICL, which includes the drive circuit 410, the layer OSL, which includes multiple transistors of the pixel circuit, and the light-emitting device 130, and the layer EML. The pixel layer PXAL of the display device 1000 shown in Figure 31B includes, as an example, the layer OSL and the layer EML. Transistors 500A, 500B, and 500C included in the layer OSL shown in Figure 31B correspond to transistor 500 in Figure 20. The light-emitting device 130 included in the layer EML shown in Figure 31B corresponds to light-emitting device 130R, light-emitting device 130G, or light-emitting device 130B in Figure 20.

[0495] The pixel circuit 400 shown as an example in Figures 31A and 31B comprises transistor 500A, transistor 500B, transistor 500C, and capacitor 600. Transistors 500A, 500B, and 500C can be transistors applicable to the transistor 200 described above, for example. That is, transistors 500A, 500B, and 500C can be or Si transistors. Alternatively, transistors 500A, 500B, and 500C can be transistors applicable to the transistor 500 described above, for example. That is, transistors 500A, 500B, and 500C can be or OS transistors. In particular, when transistors 500A, 500B, and 500C are OS transistors, it is preferable that each of transistors 500A, 500B, and 500C is equipped with a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or to receive a different signal from the gate electrode. Although Figures 31A and 31B show back gate electrodes for transistors 500A, 500B, and 500C, transistors 500A, 500B, and 500C may be configured without back gate electrodes.

[0496] Transistor 500B comprises a gate electrode electrically connected to transistor 500A, a first electrode electrically connected to light-emitting device 130, and a second electrode electrically connected to wiring ANO. Wiring ANO is a wire that provides a potential for supplying current to light-emitting device 130.

[0497] Transistor 500A comprises a first terminal electrically connected to the gate electrode of transistor 500B, a second terminal electrically connected to wiring SL which functions as a source line, and a gate electrode that has the function of controlling an on or off state based on the potential of wiring GL1 which functions as a gate line.

[0498] Transistor 500C comprises a first terminal electrically connected to wiring V0, a ​​second terminal electrically connected to the light-emitting device 130, and a gate electrode that has the function of controlling an on or off state based on the potential of wiring GL2 which functions as a gate line. Wiring V0 is a wiring for supplying a reference potential and a wiring for outputting the current flowing through the pixel circuit 400 to the drive circuit 410.

[0499] Capacitor 600 comprises a conductive film electrically connected to the gate electrode of transistor 500B and a conductive film electrically connected to the second electrode of transistor 500C.

[0500] The light-emitting device 130 includes a first electrode electrically connected to the first electrode of the transistor 500B, and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wire that provides a potential for supplying current to the light-emitting device 130.

[0501] This allows the intensity of light emitted by the light-emitting device 130 to be controlled in accordance with the image signal applied to the gate electrode of transistor 500B. Furthermore, variations in the gate-source voltage of transistor 500B can be suppressed by the reference potential of the wiring V0 provided via transistor 500C.

[0502] Furthermore, wiring V0 can output a current value that can be used to set pixel parameters. More specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 500B or the current flowing through light-emitting device 130 to the outside. The current output to wiring V0 can be converted into a voltage by, for example, a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by, for example, an AD converter and output to a circuit that performs color adjustment or brightness adjustment (sometimes called a correction circuit), or to a GPU.

[0503] In the configuration shown as an example in Figure 31B, the wiring electrically connecting the pixel circuit 400 and the drive circuit 410 can be shortened, thereby reducing the wiring resistance. As a result, data can be written at high speed, and the display device 1000 can be driven at high speed. This allows for a sufficient frame duration even with a large number of pixel circuits 400 in the display device 1000, thus increasing the pixel density of the display device 1000. Furthermore, increasing the pixel density of the display device 1000 improves the resolution of the image displayed by the display device 1000. For example, the pixel density of the display device 1000 can be set to 1000 ppi or more, or 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 1000 can be used, for example, as a display device for AR or VR, and can be suitably applied to electronic devices where the distance between the display unit and the user is close, such as head-mounted displays.

[0504] Although Figures 31A and 31B show a pixel circuit 400 having a total of three transistors as an example, the pixel circuit relating to one embodiment of the present invention is not limited to this. Below, we will describe examples of pixel circuit configurations applicable to the pixel circuit 400.

[0505] The pixel circuit 400A shown in Figure 32A illustrates transistors 500A and 500B, and capacitor 600. Figure 32A also illustrates the light-emitting device 130 connected to the pixel circuit 400A. Furthermore, wirings SL, GL, ANO, and VCOM are electrically connected to the pixel circuit 400A.

[0506] Transistor 500A's gate is electrically connected to wiring GL, and one of its source and drain is electrically connected to wiring SL, the other of which is connected to the gate of transistor 500B and one of the electrodes of capacitor 600. Transistor 500B's source and drain are electrically connected to wiring ANO, and the other of which is connected to the anode of light-emitting device 130. Capacitor 600's other electrode is electrically connected to the anode of light-emitting device 130. Light-emitting device 130's cathode is electrically connected to wiring VCOM.

[0507] The pixel circuit 400B shown in Figure 32B is a configuration in which transistor 500C is added to the pixel circuit 400A. Furthermore, wiring V0 is electrically connected to the pixel circuit 400B.

[0508] The pixel circuit 400C shown in Figure 32C is an example in which transistors 500A and 500B of the pixel circuit 400A are replaced with transistors in which the gate and back gate are electrically connected. Similarly, the pixel circuit 400D shown in Figure 32D is an example in which the same transistor is replaced with the pixel circuit 400B. This increases the current that the transistor can supply. Here, all transistors are replaced with transistors in which a pair of gates are electrically connected, but this is not the only option. Alternatively, transistors with a pair of gates that are electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates and the source are electrically connected.

[0509] The pixel circuit 400E shown in Figure 33A is a configuration in which a transistor 500D is added to the above-mentioned pixel circuit 400B. In addition, three wires (wires GL1, GL2, and GL3) that function as gate wires are electrically connected to the pixel circuit 400E.

[0510] Transistor 500D has its gate electrically connected to wiring GL3, and one of its source and drain is electrically connected to the gate of transistor 500B, while the other is electrically connected to wiring V0. Also, the gate of transistor 500A is electrically connected to wiring GL1, and the gate of transistor 500C is electrically connected to wiring GL2.

[0511] By simultaneously making transistors 500C and 500D conduct, the source and gate of transistor 500B become at the same potential, making transistor 500B non-conductive. This allows the current flowing to the light-emitting device 130 to be forcibly interrupted. Such a pixel circuit is suitable for display methods that alternate between display periods and off periods.

[0512] The pixel circuit 400F shown in Figure 33B is an example of adding a capacitance of 600A to the above pixel circuit 400E. The capacitance of 600A functions as a holding capacitance.

[0513] The pixel circuit 400G shown in Figure 33C and the pixel circuit 400H shown in Figure 33D are examples of applying transistors with electrically connected gates to the above-mentioned pixel circuit 400E or pixel circuit 400F, respectively. Transistors 500A, 500C, and 500D are transistors with electrically connected gates and back gates, while transistor 500B is a transistor with its gate electrically connected to its source.

[0514] <Pixel layout> This section describes pixel layout. There are no particular limitations on the arrangement of subpixels, and various methods can be applied. Examples of subpixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0515] Furthermore, the top surface shape of the sub-pixel can be, for example, a polygon such as a triangle, quadrilateral (including rectangles and squares), or pentagon, or a polygon with rounded corners, or an ellipse or a circle. Here, the top surface shape of the sub-pixel corresponds to the top surface shape of the light-emitting region of the light-emitting device.

[0516] A stripe array is applied to pixel 80 shown in Figure 34A. Pixel 80 shown in Figure 34A is composed of three subpixels: subpixel 80a, subpixel 80b, and subpixel 80c. For example, as shown in Figure 35A, subpixel 80a may be a red subpixel R, subpixel 80b a green subpixel G, and subpixel 80c a blue subpixel B.

[0517] The pixel 80 shown in Figure 34B has an S-stripe array applied to it. The pixel 80 shown in Figure 34B is composed of three subpixels: subpixel 80a, subpixel 80b, and subpixel 80c. For example, as shown in Figure 35B, subpixel 80a may be a blue subpixel B, subpixel 80b may be a red subpixel R, and subpixel 80c may be a green subpixel G.

[0518] Figure 34C shows an example where the subpixels of each color are arranged in a zigzag pattern. Specifically, in a top view, the upper edges of two subpixels aligned in the column direction (for example, subpixels 80a and 80b, or subpixels 80b and 80c) are offset. For example, as shown in Figure 35C, subpixel 80a may be a red subpixel R, subpixel 80b a green subpixel G, and subpixel 80c a blue subpixel B.

[0519] The pixel 80 shown in Figure 34D has sub-pixels 80a with a roughly trapezoidal top surface shape with rounded corners, sub-pixels 80b with a roughly triangular top surface shape with rounded corners, and sub-pixels 80c with a roughly square or roughly hexagonal top surface shape with rounded corners. Furthermore, sub-pixel 80a has a larger light-emitting area than sub-pixel 80b. Thus, the shape and size of each sub-pixel can be determined independently. For example, the size of a sub-pixel can be reduced to a level that provides a more reliable light-emitting device. For example, as shown in Figure 35D, sub-pixel 80a may be a green sub-pixel G, sub-pixel 80b may be a red sub-pixel R, and sub-pixel 80c may be a blue sub-pixel B.

[0520] A Pentile array is applied to pixels 70A and 70B shown in Figure 34E. Figure 34E shows an example in which pixels 70A having subpixels 80a and 80b and pixels 70B having subpixels 80b and 80c are arranged alternately. For example, as shown in Figure 35E, subpixel 80a may be a red subpixel R, subpixel 80b may be a green subpixel G, and subpixel 80c may be a blue subpixel B.

[0521] Pixels 70A and 70B shown in Figures 34F and 34G utilize a delta array. Pixel 70A has two subpixels (subpixels 80a and 80b) in the top row (1st row) and one subpixel (subpixel 80c) in the bottom row (2nd row). Pixel 70B has one subpixel (subpixel 80c) in the top row (1st row) and two subpixels (subpixels 80a and 80b) in the bottom row (2nd row). For example, as shown in Figure 35F, subpixel 80a may be a red subpixel R, subpixel 80b a green subpixel G, and subpixel 80c a blue subpixel B.

[0522] Figure 34F shows an example where each subpixel has a roughly square top shape with rounded corners, and Figure 34G shows an example where each subpixel has a circular top shape.

[0523] In photolithography, the finer the pattern being processed, the more significant the effects of light diffraction become. This compromises the fidelity of the pattern transfer to the photomask through exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, patterns with rounded corners are likely to form. Consequently, the top surface shape of subpixels may be a polygon with rounded corners, an ellipse, or a circle.

[0524] Furthermore, in a method for manufacturing a display device according to one aspect of the present invention, the EL layer is processed into an island shape using a resist mask. The resist film formed on the EL layer needs to be cured at a temperature lower than the heat resistance temperature of the EL layer. Therefore, depending on the heat resistance temperature of the EL layer material and the curing temperature of the resist material, the curing of the resist film may be insufficient. A resist film that is not sufficiently cured may take a shape that deviates from the desired shape during processing. As a result, the top surface shape of the EL layer may become a polygon with rounded corners, an ellipse, or a circle. For example, if an attempt is made to form a resist mask with a square top surface, a resist mask with a circular top surface may be formed, resulting in a circular top surface shape for the EL layer.

[0525] Furthermore, in order to achieve the desired shape of the upper surface of the EL layer, a technique (OPC (Optical Proximity Correction) technique) may be used to pre-correct the mask pattern so that the design pattern and the transferred pattern match. Specifically, in the OPC technique, a correction pattern is added to the corners of the shape on the mask pattern.

[0526] The pixels 80 shown in Figures 36A to 36C have a stripe arrangement applied to them.

[0527] Figure 36A shows an example where each subpixel has a rectangular top surface shape, Figure 36B shows an example where each subpixel has a top surface shape formed by connecting two semicircles and a rectangle, and Figure 36C shows an example where each subpixel has an elliptical top surface shape.

[0528] The pixels 80 shown in Figures 36D to 36F have a matrix array applied to them.

[0529] Figure 36D shows an example where each subpixel has a square top surface shape, Figure 36E shows an example where each subpixel has a roughly square top surface shape with rounded corners, and Figure 36F shows an example where each subpixel has a circular top surface shape.

[0530] The pixel 80 shown in Figures 36A to 36F is composed of four subpixels: subpixel 80a, subpixel 80b, subpixel 80c, and subpixel 80d. Each of the subpixels 80a, 80b, 80c, and 80d emits light of a different color. For example, subpixels 80a, 80b, 80c, and 80d can be red, green, blue, and white subpixels, respectively. For example, as shown in Figures 37A and 37B, subpixels 80a, 80b, 80c, and 80d can be red, green, blue, and white subpixels, respectively. Alternatively, subpixels 80a, 80b, 80c, and 80d can be red, green, blue, and subpixels of the imaging light-emitting pixel, respectively.

[0531] The sub-pixel 80d has a light-emitting device. This light-emitting device includes, for example, a pixel electrode, an EL layer, and a common electrode. The pixel electrode may be made of the same material as conductors 112a to 112c, or conductors 126a to 126c. The EL layer may be made of the same material as, for example, the first layer 113a, the second layer 113b, or the third layer 113c.

[0532] Furthermore, the sub-pixel 80d may be, for example, an imaging pixel. In this case, the sub-pixel 80d has a light-receiving device. The light-receiving device may, for example, have a pixel electrode, an active layer that functions as a photoelectric conversion layer, and a common electrode. It is also preferable to use an organic light-receiving device having a layer containing an organic compound. Organic light-receiving devices are easy to make thin, light, and large in area, and offer a high degree of freedom in shape and design, so they can be applied to various display devices.

[0533] Figure 36G shows an example where one pixel 80 is composed of two rows and three columns. Pixel 80 has three subpixels (subpixels 80a, 80b, and 80c) in the top row (1st row) and three subpixels 80d in the bottom row (2nd row). In other words, pixel 80 has subpixels 80a and 80d in the left column (1st column), subpixels 80b and 80d in the middle column (2nd column), and subpixels 80c and 80d in the right column (3rd column). As shown in Figure 36G, by aligning the arrangement of subpixels in the top row and the bottom row, it becomes possible to efficiently remove dust and other debris that may occur during the manufacturing process. Therefore, a display device with high display quality can be provided.

[0534] Furthermore, the three sub-pixels 80d shown in Figure 36G may be equipped with either an imaging light-emitting pixel, an imaging pixel, or both.

[0535] Figure 36H shows an example where one pixel 80 is composed of two rows and three columns. Pixel 80 has three subpixels (subpixels 80a, 80b, and 80c) in the top row (row 1) and one subpixel (subpixel 80d) in the bottom row (row 2). In other words, pixel 80 has subpixel 80a in the left column (column 1), subpixel 80b in the middle column (column 2), subpixel 80c in the right column (column 3), and subpixel 80d across these three columns.

[0536] Furthermore, in the pixel 80 shown in Figures 36G and 36H, for example, as shown in Figures 37C and 37D, sub-pixel 80a can be a red sub-pixel R, sub-pixel 80b can be a green sub-pixel G, sub-pixel 80c can be a blue sub-pixel B, and sub-pixel 80d can be a white sub-pixel W.

[0537] Furthermore, the insulators, conductors, and semiconductors disclosed herein can be formed by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). Examples of PVD methods include sputtering, resistance heating deposition, electron beam deposition, MBE (Molecular Beam Epitaxy), and PLD (Pulsed Laser Deposition). Examples of CVD methods include plasma CVD and thermal CVD. In particular, examples of thermal CVD methods include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (Alternative Laser Deposition).

[0538] Thermal CVD (Chemical Vapor Deposition) is a film deposition method that does not use plasma, and therefore has the advantage of not generating defects due to plasma damage.

[0539] In the thermal CVD method, the raw material gas and oxidizer may be simultaneously introduced into the chamber, the chamber pressure may be reduced to atmospheric pressure or reduced pressure, and the reaction may occur near or on the substrate, resulting in film deposition on the substrate.

[0540] Furthermore, the ALD method may also be performed by maintaining atmospheric pressure or reduced pressure inside the chamber, sequentially introducing the raw material gases for the reaction into the chamber, and repeating the order of gas introduction. For example, two or more types of raw material gases may be supplied to the chamber sequentially by switching each switching valve (also called a high-speed valve), and an inert gas (e.g., argon or nitrogen) may be introduced simultaneously with or after the first raw material gas to prevent mixing of multiple raw material gases, followed by the introduction of the second raw material gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and an inert gas may also be introduced simultaneously with the introduction of the second raw material gas. Alternatively, instead of introducing an inert gas, the first raw material gas may be discharged by vacuum evacuation before introducing the second raw material gas. The first raw material gas adsorbs onto the surface of the substrate to form a first thin layer, which then reacts with the second raw material gas introduced later to laminate a second thin layer on top of the first thin layer, forming a thin film. By controlling the order of gas introduction and repeating this process multiple times until the desired thickness is achieved, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness control is possible, making it suitable for fabricating fine FETs.

[0541] Thermal CVD methods such as MOCVD and ALD can form various films, including metal films, semiconductor films, and inorganic insulating films, as disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. However, the combinations are not limited to these; triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0542] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes the ALD method, two types of gases are used: a raw material gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (for example, hafnium alkoxide, tetrakisdimethylamide hafnium (TDMAH, Hf[N(CH3)2]4), etc.) and ozone (O3) as an oxidizing agent. Another example of a material is tetrakis(ethylmethylamide)hafnium.

[0543] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes the ALD method, two types of gases are used: a raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA, Al(CH3)3)) and H2O as an oxidizing agent. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0544] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes the ALD method, hexachlorodisilane is adsorbed onto the film deposition surface, and radicals of oxidizing gases (O2, nitrous oxide) are supplied to react with the adsorbed material.

[0545] For example, when depositing a tungsten film using a film deposition apparatus that utilizes the ALD method, an initial tungsten film is formed by sequentially introducing WF6 gas and B2H6 gas repeatedly, and then the tungsten film is formed by sequentially introducing WF6 gas and H2 gas repeatedly. Note that SiH4 gas may be used instead of B2H6 gas.

[0546] For example, when depositing an In-Ga-Zn-O film as an oxide semiconductor film using a film deposition apparatus that utilizes the ALD method, the film is formed by sequentially and repeatedly introducing a precursor (generally sometimes called a precursor or metal precursor) and an oxidizing agent (generally sometimes called a reactant or nonmetal precursor). Specifically, for example, an In-O layer is formed by introducing In(CH3)3 gas as a precursor and O3 gas as an oxidizing agent, then a GaO layer is formed by introducing Ga(CH3)3 gas as a precursor and O3 gas as an oxidizing agent, and then a ZnO layer is formed by introducing Zn(CH3)2 gas as a precursor and O3 gas as an oxidizing agent. Note that the order of these layers is not limited to this example. Furthermore, mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers may also be formed using these gases. Note that H2O gas obtained by bubbling water with an inert gas (for example, argon) may be used instead of O3 gas, but it is preferable to use O3 gas which does not contain H. Also, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Also, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Also, Zn(C2H5)2 gas may be used instead of Zn(CH3)2 gas.

[0547] Furthermore, there are no particular limitations on the aspect ratio of the display unit in the electronic device according to one embodiment of the present invention. For example, the display unit can support various aspect ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.

[0548] Furthermore, the shape of the display unit in the electronic device according to one aspect of the present invention is not particularly limited. For example, the display unit can be rectangular, polygonal (e.g., octagonal), circular, or elliptical in shape.

[0549] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0550] (Embodiment 3) In this embodiment, a transistor that can be used in a semiconductor device according to one aspect of the present invention, specifically the transistor 500 described in Embodiment 2, will be described.

[0551] <Example of transistor configuration> Figures 38A, 38B, and 38C are plan and cross-sectional views of a transistor 500 that can be used in a semiconductor device according to one aspect of the present invention. The transistor 500 can be applied to a semiconductor device according to one aspect of the present invention.

[0552] Figure 38A is a plan view of transistor 500. Figures 38B and 38C are cross-sectional views of transistor 500. Here, Figure 38B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 38A, and is also a cross-sectional view of transistor 500 in the channel length direction. Similarly, Figure 38C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 38A, and is also a cross-sectional view of transistor 500 in the channel width direction. Note that some elements have been omitted from the plan view in Figure 38A for clarity.

[0553] As shown in Figures 38A to 38C, the transistor 500 includes a metal oxide 531a disposed on a substrate (not shown), a metal oxide 531b disposed on the metal oxide 531a, conductors 542a and 542b disposed on the metal oxide 531b at a distance from each other, an insulator 580 disposed on the conductors 542a and 542b with an opening formed between the conductors 542a and 542b, a conductor 560 disposed in the opening, and an insulator 550 disposed between the metal oxide 531b, conductors 542a, conductors 542b, and insulator 580 and conductor 560. Here, as shown in Figures 38B and 38C, it is preferable that the upper surface of conductor 560 substantially coincides with the upper surfaces of insulator 550 and insulator 580. In the following, metal oxide 531a and metal oxide 531b may be collectively referred to as metal oxide 531. In addition, conductors 542a and 542b are sometimes collectively referred to as conductor 542.

[0554] In the transistor 500 shown in Figures 38A to 38C, the sides of the conductor 542a and conductor 542b facing the conductor 560 have a generally vertical shape. However, the transistor 500 shown in Figures 38A to 38C is not limited to this, and the angle between the side and bottom surfaces of the conductor 542a and conductor 542b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing sides of the conductor 542a and conductor 542b may have multiple surfaces.

[0555] In the transistor 500, a configuration is shown in which two layers of metal oxide 531a and metal oxide 531b are stacked in the region where the channel is formed (hereinafter also referred to as the channel formation region) and in its vicinity, but the present invention is not limited to this. For example, a single-layer structure of metal oxide 531b or a stacked structure of three or more layers may be provided. Furthermore, each of the metal oxide 531a and metal oxide 531b may have a stacked structure of two or more layers.

[0556] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source electrode or drain electrode, respectively. As described above, the conductor 560 is formed to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. Here, the arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be positioned in a self-aligned manner between the source electrode and the drain electrode. Therefore, since the conductor 560 can be formed without providing a positional margin, the occupied area of ​​the transistor 500 can be reduced. This makes it possible to make the display device high-resolution. It also makes it possible to make the display device have a narrow bezel.

[0557] As shown in Figure 38B, it is preferable that the conductor 560 has a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Although Figures 38B and 38C show the conductor 560 as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductor 560 may be a single-layer structure or a laminated structure of three or more layers.

[0558] The transistor 500 preferably includes an insulator 514 disposed on a substrate (not shown), an insulator 516 disposed on top of the insulator 514, a conductor 505 disposed so as to be embedded in the insulator 516, an insulator 522 disposed on top of the insulator 516 and the conductor 505, and an insulator 524 disposed on top of the insulator 522. It is preferable that a metal oxide 531a is disposed on top of the insulator 524.

[0559] As shown in Figures 38B and 38C, it is preferable that an insulator 554 is placed between insulator 522, insulator 524, metal oxide 531a, metal oxide 531b, conductor 542a, conductor 542b, and insulator 550 and insulator 580. Here, as shown in Figures 38B and 38C, it is preferable that the insulator 554 is in contact with the side surface of insulator 550, the top and side surface of conductor 542a, the top and side surface of conductor 542b, the side surface of metal oxide 531a, metal oxide 531b, and insulator 524, and the top surface of insulator 522.

[0560] It is preferable that insulators 574 and 581, which function as interlayer films, be placed on top of the transistor 500. Here, it is preferable that insulator 574 is placed in contact with the upper surfaces of the conductor 560, insulator 550, and insulator 580.

[0561] It is preferable that insulators 522, 554, and 574 have a function to suppress the diffusion of hydrogen (for example, hydrogen atoms and / or hydrogen molecules). For example, it is preferable that insulators 522, 554, and 574 have lower hydrogen permeability than insulators 524, 550, and 580. It is also preferable that insulators 522 and 554 have a function to suppress the diffusion of oxygen (for example, oxygen atoms and / or oxygen molecules). For example, it is preferable that insulators 522 and 554 have lower oxygen permeability than insulators 524, 550, and 580.

[0562] It is preferable that a conductor 540 (conductors 540a and 540b) is provided that is electrically connected to the transistor 500 and functions as a plug. In addition, an insulator 541 (insulators 541a and 541b) is provided in contact with the side surface of the conductor 540 that functions as a plug. That is, the insulator 541 is provided in contact with the inner wall of the opening of the insulators 554, 580, 574, and 581. Alternatively, a first conductor of the conductor 540 may be provided in contact with the side surface of the insulator 541, and a second conductor of the conductor 540 may be provided further inside. Here, the height of the upper surface of the conductor 540 and the height of the upper surface of the insulator 581 can be made to be approximately the same. Although the transistor 500 shows a configuration in which the first conductor and the second conductor of the conductor 540 are stacked, the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or as a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0563] In transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 531 (metal oxide 531a and metal oxide 531b) that includes the channel formation region. For example, it is preferable to use a metal oxide with a band gap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide that forms the channel formation region of metal oxide 531.

[0564] The above metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that it contains indium (In) and zinc (Zn). In addition, it is preferable that it contains element M. As element M, one or more of the following can be used: aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, it is preferable that element M is one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is even more preferable that element M contains one or both of gallium (Ga) and tin (Sn).

[0565] Furthermore, the thickness of the metal oxide 531b in the region that does not overlap with the conductor 542 may be thinner than the thickness of the metal oxide 531b in the region that overlaps with the conductor 542. This is formed by removing a portion of the upper surface of the metal oxide 531b when forming the conductors 542a and 542b. When a conductive film that will become the conductor 542 is deposited on the upper surface of the metal oxide 531b, a region with low resistance may be formed near the interface with the conductive film. In this way, by removing the region with low resistance located between the conductors 542a and 542b on the upper surface of the metal oxide 531b, it is possible to prevent the formation of a channel in that region.

[0566] According to one aspect of the present invention, a display device with a small size transistor and high resolution can be provided. Alternatively, a display device with a large on-current transistor and high brightness can be provided. Alternatively, a display device with a fast-operating transistor can be provided. Alternatively, a display device with a stable electrical characteristic transistor can be provided and highly reliable can be provided. Alternatively, a display device with a small off-current transistor can be provided and low power consumption can be provided.

[0567] A detailed configuration of the transistor 500, which can be used in a display device according to one aspect of the present invention, will be described.

[0568] The conductor 505 is arranged so as to have an overlapping region with the metal oxide 531 and the conductor 560. Furthermore, it is preferable that the conductor 505 is embedded in the insulator 516.

[0569] The conductor 505 comprises a conductor 505a and a conductor 505b. The conductor 505a is provided in contact with the bottom surface and side wall of an opening provided in the insulator 516. The conductor 505b is provided so as to be embedded in a recess formed in the conductor 505a. Here, the height of the upper surface of the conductor 505b is approximately equal to the height of the upper surface of the conductor 505a and the height of the upper surface of the insulator 516.

[0570] It is preferable to use a conductive material for the conductor 505a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, or NO2), or copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0571] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 505a, it is possible to suppress the diffusion of impurities such as hydrogen contained in the conductor 505b into the metal oxide 531 via the insulator 524. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 505a, it is possible to suppress the oxidation of the conductor 505b and the resulting decrease in conductivity. For example, it is preferable to use titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide as the conductive material that has the function of suppressing oxygen diffusion. Therefore, the conductor 505a may be configured as a single layer or a laminate of the above conductive material. For example, titanium nitride may be used for the conductor 505a.

[0572] Furthermore, it is preferable to use a conductive material whose main component is tungsten, copper, or aluminum for the conductor 505b. For example, tungsten may be used for the conductor 505b.

[0573] Here, the conductor 560 may function as a first gate electrode (for example, also called a top gate). Also, the conductor 505 may function as a second gate electrode (for example, also called a bottom gate). In that case, by changing the potential applied to the conductor 505 independently of the potential applied to the conductor 560, the V of transistor 500 can be controlled. th This can be controlled. In particular, by applying a negative potential to the conductor 505, the V of transistor 500 can be controlled. th This makes it possible to increase the voltage and decrease the off-current. Therefore, applying a negative potential to the conductor 505 reduces the drain current when the potential applied to the conductor 560 is 0V compared to when no potential is applied.

[0574] The conductor 505 should be larger than the channel-forming region in the metal oxide 531. In particular, as shown in Figure 38C, it is preferable that the conductor 505 extends to the region outside the end that intersects with the channel width direction of the metal oxide 531. That is, it is preferable that the conductor 505 and the conductor 560 are superimposed on the outside of the side surface in the channel width direction of the metal oxide 531, with an insulator in between.

[0575] With the above configuration, the channel-forming region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 505, which functions as the second gate electrode.

[0576] As shown in Figure 38C, the conductor 505 extends and functions as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided below the conductor 505.

[0577] The insulator 514 preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water or hydrogen into the transistor 500 from the substrate side. Therefore, it is preferable to use an insulating material for the insulator 514 that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, or NO2), or copper atoms (i.e., the above impurities are less permeable). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., the above oxygen is less permeable).

[0578] For example, it is preferable to use aluminum oxide or silicon nitride as the insulator 514. This suppresses the diffusion of impurities such as water or hydrogen from the substrate side to the transistor 500 side beyond the insulator 514. Alternatively, it suppresses the diffusion of oxygen contained in the insulator 524 toward the substrate side beyond the insulator 514.

[0579] The insulators 516, 580, and 581, which function as interlayer films, preferably have a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide may be used as appropriate for insulators 516, 580, and 581.

[0580] Insulators 522 and 524 function as gate insulators.

[0581] Here, it is preferable that the insulator 524 in contact with the metal oxide 531 desorbs oxygen upon heating. In this specification, the oxygen that is desorbed upon heating is sometimes referred to as excess oxygen. For example, the insulator 524 may be silicon oxide or silicon oxynitride as appropriate. By providing an oxygen-containing insulator in contact with the metal oxide 531, the oxygen deficiency in the metal oxide 531 can be reduced, and the reliability of the transistor 500 can be improved.

[0582] Specifically, it is preferable to use an oxide material in which some oxygen is desorbed upon heating as the insulator 524. An oxide that desorbs oxygen upon heating is one in which the amount of oxygen desorbed, converted to oxygen atoms, is 1.0 × 10¹⁶ as determined by TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 Preferably 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atoms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the film during the TDS analysis is preferably between 100°C and 700°C, or between 100°C and 400°C.

[0583] The insulator 522, like the insulator 514, preferably functions as a barrier insulating film that suppresses the ingress of impurities such as water and hydrogen into the transistor 500 from the substrate side. For example, it is preferable that the insulator 522 has lower hydrogen permeability than the insulator 524. By surrounding the insulator 524, the metal oxide 531, and the insulator 550 with the insulators 522, 554, and 574, it is possible to suppress the ingress of impurities such as water and hydrogen into the transistor 500 from the outside.

[0584] Furthermore, it is preferable that the insulator 522 has a function to suppress the diffusion of oxygen (for example, oxygen atoms and / or oxygen molecules) (i.e., it is difficult for the above-mentioned oxygen to permeate). For example, it is preferable that the insulator 522 has lower oxygen permeability than the insulator 524. It is preferable that the insulator 522 has a function to suppress the diffusion of oxygen and impurities, thereby reducing the diffusion of oxygen contained in the metal oxide 531 to the substrate side. In addition, it is possible to suppress the reaction of the conductor 505 with the oxygen contained in the insulator 524 and the metal oxide 531.

[0585] The insulator 522 may be an insulator containing an oxide of one or both of the insulating materials aluminum and hafnium. Preferably, the insulator containing an oxide of one or both of aluminum and hafnium is aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the metal oxide 531 and the incorporation of impurities such as hydrogen from the periphery of the transistor 500 into the metal oxide 531.

[0586] Alternatively, these insulators may be to which, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated onto the above insulators.

[0587] The insulator 522 may be a single-layer or multi-layer insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0588] Furthermore, the insulators 522 and 524 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials. For example, an insulator similar to the insulator 524 may be provided below the insulator 522.

[0589] The metal oxide 531 comprises a metal oxide 531a and a metal oxide 531b on the metal oxide 531a. By having the metal oxide 531a below the metal oxide 531b, the diffusion of impurities from structures formed below the metal oxide 531a to the metal oxide 531b can be suppressed.

[0590] Furthermore, it is preferable that the metal oxide 531 has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom. For example, if the metal oxide 531 contains at least indium (In) and element M, it is preferable that the ratio of the number of atoms of element M contained in metal oxide 531a to the total number of atoms of all elements constituting metal oxide 531a is higher than the ratio of the number of atoms of element M contained in metal oxide 531b to the total number of atoms of all elements constituting metal oxide 531b. It is also preferable that the atomic ratio of element M contained in metal oxide 531a to In is higher than the atomic ratio of element M contained in metal oxide 531b to In.

[0591] It is preferable that the energy at the lower end of the conduction band of metal oxide 531a is higher than the energy at the lower end of the conduction band of metal oxide 531b. In other words, it is preferable that the electron affinity of metal oxide 531a is smaller than the electron affinity of metal oxide 531b.

[0592] Here, at the junction of metal oxide 531a and metal oxide 531b, the energy level at the lower end of the conduction band changes smoothly. In other words, the energy level at the lower end of the conduction band at the junction of metal oxide 531a and metal oxide 531b can be said to change continuously or be continuously joined. To achieve this, it is desirable to lower the defect level density of the mixed layer formed at the interface between metal oxide 531a and metal oxide 531b.

[0593] Specifically, a mixed layer with a low defect level density can be formed if metal oxide 531a and metal oxide 531b have a common element other than oxygen (which is the main component). For example, if metal oxide 531b is In-Ga-Zn oxide, then metal oxide 531a may be In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide.

[0594] Specifically, for metal oxide 531a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. Similarly, for metal oxide 531b, a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1, 4:2:3, or 3:1:2 may be used.

[0595] In this case, the main carrier pathway is through the metal oxide 531b. By configuring the metal oxide 531a as described above, the defect level density at the interface between the metal oxide 531a and the metal oxide 531b can be reduced. As a result, the influence of interfacial scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current and high frequency characteristics.

[0596] A conductor 542 (conductor 542a and conductor 542b) that functions as a source electrode and a drain electrode is provided on the metal oxide 531b. It is preferable that the conductor 542 be a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy composed of the above metal elements, or an alloy combining two or more of the above metal elements. For example, it is preferable that the conductor 542 be tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0597] By providing the conductor 542 in contact with the metal oxide 531, the oxygen concentration in the vicinity of the conductor 542 on the metal oxide 531 may be reduced. Furthermore, a metal compound layer containing the metal in the conductor 542 and components of the metal oxide 531 may be formed in the vicinity of the conductor 542 on the metal oxide 531. In such cases, the carrier density increases in the region of the metal oxide 531 near the conductor 542, resulting in a low-resistance region.

[0598] Here, the region between the conductor 542a and the conductor 542b is formed superimposed on the opening of the insulator 580. This allows the conductor 560 to be positioned self-aligned between the conductor 542a and the conductor 542b.

[0599] The insulator 550 functions as a gate insulator. It is preferable that the insulator 550 be placed in contact with the upper surface of the metal oxide 531b. The insulator 550 can be silicon oxide, silicon oxynitride, silicon oxide nitride, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable.

[0600] Similar to the insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 is preferably 1 nm or more and 20 nm or less.

[0601] An insulator may be provided between the insulator 580, insulator 554, conductor 542, and meta...

Claims

[Claim 1] It has a display unit, a light-emitting unit, a light-receiving unit, and a control unit. The display unit has a first display area and a first circuit area, The first display area is located in an area that overlaps with the first circuit area. The first display area has a plurality of first display pixels, The first circuit region has a first driver circuit, The first driver circuit is electrically connected to a plurality of first wirings extending to the first display area. Each of the plurality of first display pixels is electrically connected to the plurality of first wirings, The light receiving unit is electrically connected to the control unit, The control unit is electrically connected to the first driver circuit, The light-emitting unit has the function of emitting a first light, The light receiving unit has the function of detecting a second light reflected when the first light is irradiated onto a subject, and the function of generating information based on the second light and transmitting the information to the control unit. The control unit has the function of generating a first signal based on the information and transmitting the first signal to the first driver circuit. The first driver circuit has the function of either transmitting multiple image signals to each of the multiple first wirings in response to the first signal, or transmitting the same image signal to two or more consecutively adjacent wirings among the multiple first wirings. Display device.

Images