Light-emitting device

Abstract

One objective is to provide a semiconductor device having transistors with different characteristics, specifically transistors with excellent dynamic characteristics (on-response and frequency characteristics (called f-response)) and transistors with suppressed off-current, on the same substrate. Another objective is to provide a simple method for fabricating such a semiconductor device. [Solution] An oxide semiconductor layer that is intrinsically or substantially intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsically intrinsic intrinsically

Description

[Technical Field]

[0001] This invention relates to a semiconductor device using a transistor.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general term, including semiconductor elements and circuits, electro-optical devices having semiconductor elements and circuits, and electronic devices. All the equipment consists of semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using semiconductor thin films formed on a substrate having an insulating surface. It is attracting attention. Transistors are used in semiconductor devices such as LCD televisions. Yes, silicon-based semiconductor materials are known as semiconductor thin films applicable to transistors. Oxide semiconductors are also attracting attention as another material.

[0004] Transistors are primarily made of semiconductors such as amorphous silicon or polycrystalline silicon. It is fabricated using materials. Transistors using amorphous silicon utilize field-effect transfer. Although the degree is low, it can accommodate the large area of ​​glass substrates, while polycrystalline silicon is used Transistors that have high field-effect mobility require crystallization processes such as laser annealing. It has characteristics such as being essential and not necessarily suitable for large-area glass substrates.

[0005] As materials for oxide semiconductors, zinc oxide or materials containing zinc oxide are known. And the electron carrier concentration is 10 18 / cm 3 Amorphous oxides (oxide semiconductors) that are less than Thin-film transistors formed from the above have been disclosed (Patent Documents 1 to 3).

[0006] In addition, in active matrix semiconductor devices typified by liquid crystal display devices, the screen size tends to increase to a diagonal size of 60 inches or more, and furthermore, development has been carried out with a screen size of 120 inches or more diagonal also taking into account the viewing angle. In addition, the screen resolution is also trending towards high-definition picture quality (HD, 1366×768), full high-definition picture quality (FHD, 1920×1080 ), and higher definition, and development of so-called 4K digital cinema display devices with a resolution of 3840×2048 or 4096×2160 is also being rushed.

[0007] With the increase in the definition of display devices, the number of pixels required has increased significantly. As a result, the writing time per pixel has become shorter, and transistors are required to have fast operating characteristics, a high on-current, etc. On the other hand, due to the recent energy depletion problem, there is also a demand for display devices with suppressed power consumption. Therefore, for transistors as well, those with low off-current and suppressed waste leakage current are required.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

[0010] Furthermore, oxide semiconductors deviate from their stoichiometric composition during the formation process. For example... Furthermore, the electrical conductivity of oxide semiconductors changes depending on whether there is an excess or deficiency of oxygen. Hydrogen introduced during the formation of a conductor thin film forms an oxygen (O)-hydrogen (H) bond and acts as an electron donor. It acts as a donor and is a factor that changes electrical conductivity. Furthermore, the OH bond is polar. Therefore, for active devices such as transistors made from oxide semiconductors, the characteristics This becomes a factor in the fluctuations.

[0011] Electron carrier concentration is 10 18 / cm 3 Even if it is less than, in the case of oxide semiconductors, It is an n-type transistor, and the on / off ratio of the transistor disclosed in the aforementioned patent document is 10 3 only obtain No. The reason why such transistors have a low on / off ratio is because the off-current is high. It is.

[0012] This invention was made under such technical background. Therefore, its purpose is , transistors with different characteristics, specifically dynamic characteristics (called on-response) and frequency characteristics (called f-response) A transistor with excellent performance and a transistor with suppressed off-current are mounted on the same substrate. One of the objectives is to provide a semiconductor device having the following characteristics. Furthermore, to provide the semiconductor device in a simple manner. One of the objectives is to provide a method for producing it. [Means for solving the problem]

[0013] To achieve the above objective, the present invention provides a material that is intrinsic or substantially intrinsic and has a crystalline region on its surface. We focused on oxide semiconductor layers containing [a specific component]. Intrinsic or substantially intrinsic semiconductors are found in oxide semiconductors. By removing impurities that act as electron donors, it achieves a larger energy gap than silicon semiconductors. A larger one should be used. Then, an insulating film is placed above and below the oxide semiconductor layer. By controlling the potential of a pair of conductive films, the position of the channels formed in the oxide semiconductor layer is changed. This allows us to control the electrical characteristics of the transistor.

[0014] One embodiment of the present invention provides a transistor with excellent dynamic characteristics and stable electrical characteristics on the same substrate. In a semiconductor device having a transistor that exhibits (for example, extremely reduced off-current) Yes. Specifically, impurities that act as electron donors are removed from oxide semiconductors, and silicon By using oxide semiconductors with a larger energy gap than conventional semiconductors, intrinsic or real A qualitatively intrinsic oxide semiconductor layer containing crystalline regions on its surface is used, and above and below the oxide semiconductor layer Multiple transistors, each having a configuration in which a conductive film is arranged via an insulating film, are located on the same substrate. It is a semiconductor device.

[0015] That is, one aspect of the present invention comprises a first electrode layer, a first insulating film on the first electrode layer, and a first An oxide semiconductor layer containing a crystalline region on the insulating film and an oxide semiconductor layer on the first electrode layer A second electrode layer in contact with the first electrode layer, with its end overlapping the first electrode layer, and a third electrode layer, and the second electrode A second insulating film including an oxide insulating film in contact with the oxide semiconductor layer, a third electrode layer, and the A semiconductor having a first electrode layer on an insulating film and a fourth electrode layer superimposed on an oxide semiconductor layer. It is a semiconductor device. Furthermore, the above semiconductor device uses an oxide semiconductor for the oxide semiconductor layer. It has multiple transistors with an energy gap of 2 eV or more.

[0016] Furthermore, one aspect of the present invention relates to a depletion-type transistor and an enhancement-type transistor. This is an inverter circuit comprising the above-mentioned semiconductor device, including a transistor.

[0017] Furthermore, one aspect of the present invention is a half having a pixel portion and a drive circuit portion that drives the pixel portion. It is a display device equipped with a conductive device.

[0018] Furthermore, in one aspect of the present invention, in the above semiconductor device, at least one transistor is The first electrode layer is used as the main gate electrode, and the other transistors use the fourth electrode layer as the main gate electrode. This is a driving method used as an electrode.

[0019] Furthermore, in one aspect of the present invention, in the above inverter circuit, a depletion type transistor The transistor uses the fourth electrode layer as the main gate electrode, and the enhancement-type transistor is This driving method uses the fourth electrode layer as the primary gate electrode.

[0020] Furthermore, in one aspect of the present invention, in the above-mentioned display device, at least one trace of the pixel portion The inverter uses the first electrode layer as the main gate electrode, and the drive circuit section has at least One transistor uses a driving method that utilizes the fourth electrode layer as the primary gate electrode.

[0021] Furthermore, in one aspect of the present invention, a first electrode layer is formed, and a first insulating film is formed on the first electrode layer. Then, an oxide semiconductor layer is formed on the first insulating film, and the oxide semiconductor layer is subjected to dehydration or dehydrogenation treatment. A crystalline region is formed on the surface, and the first electrode layer is in contact with the oxide semiconductor layer, with the edges being the first A second electrode layer and a third electrode layer are formed superimposed on the electrode layer, and the second electrode layer and the third electrode A second insulating film is formed, which includes an oxide insulating film in contact with the oxide semiconductor layer, and the second insulating film A semiconductor device having a first electrode layer and a fourth electrode layer superimposed on an oxide semiconductor layer on a film. This is a method for manufacturing the above semiconductor device. Furthermore, the above semiconductor device is made of an oxide semiconductor used in the oxide semiconductor layer. Multiple transistors with an energy gap of 2 eV or more are located on the same substrate.

[0022] In this specification, the term "EL layer" refers to the layer provided between a pair of electrodes of a light-emitting element. Therefore, the light-emitting layer containing an organic compound, which is a light-emitting material sandwiched between electrodes, is one of the EL layers. It is a manner.

[0023] In this specification, "light-emitting device" refers to an image display device, a light-emitting device, or a light source. This refers to the light source (including the lighting device). It also refers to the connector on the light-emitting device, such as an FPC (Flexible Printed Circuit). (printed circuit) or TAB (Tape Automate d Bonding) Tape or TCP (Tape Carrier Packaging) e) A module to which a TAB tape or TCP has been attached, with a printed circuit board at the end. A module or substrate on which light-emitting elements are formed is coated with COG (Chip On Glas s) All modules with ICs (integrated circuits) directly mounted using this method are also included as light-emitting devices. Let's assume that. [Effects of the Invention]

[0024] According to one embodiment of the present invention, the crystalline region of the oxide semiconductor layer is used as a channel formation region. This allows for faster operation of circuits in semiconductor devices. Furthermore, highly purified oxide semiconductors... By constructing a circuit using transistors made of solid material, the operation of the circuit in the semiconductor device can be stabilized. It can be made to have an off-current of 1 × 10⁻⁶. -13 Because it has been reduced to A or less. This allows for a reduction or miniaturization of the retention capacitance elements in semiconductor devices. A semiconductor device having transistors on the same substrate can be provided. Furthermore, the semiconductor device can be simplified It can be made using a convenient method. [Brief explanation of the drawing]

[0025] [Figure 1] A diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 2] A diagram illustrating a semiconductor device according to an embodiment. [Figure 3] A diagram illustrating an inverter circuit according to an embodiment. [Figure 4] A diagram illustrating a shift register according to an embodiment. [Figure 5] A diagram illustrating a pulse output circuit according to an embodiment. [Figure 6] A diagram illustrating a pulse output circuit according to an embodiment. [Figure 7] A diagram illustrating a pulse output circuit according to an embodiment. [Figure 8] A timing chart relating to an embodiment. [Figure 9] Block diagram of a display device according to the embodiment. [Figure 10] A diagram illustrating the drive circuit of a display device according to an embodiment. [Figure 11] A cross-sectional view and a plan view illustrating one aspect of the present invention. [Figure 12] A cross-sectional view illustrating one aspect of the present invention. [Figure 13] A cross-sectional view illustrating one aspect of the present invention. [Figure 14]A diagram illustrating the pixel equivalent circuit of a semiconductor device. [Figure 15] A cross-sectional view illustrating one aspect of the present invention. [Figure 16] A cross-sectional view and a plan view illustrating one aspect of the present invention. [Figure 17] A diagram illustrating examples of how electronic paper can be used. [Figure 18] An external view showing an example of an e-book. [Figure 19] External view showing examples of television equipment and digital photo frames. [Figure 20] An external view showing an example of a gaming machine. [Figure 21] An external view showing an example of a mobile phone. [Figure 22] A diagram illustrating the terminal section of a display device according to an embodiment. [Figure 23] A longitudinal cross-sectional view of an inverse staggered transistor using an oxide semiconductor. [Figure 24] Figure 23 shows the energy band diagram (schematic diagram) at the A-A' cross section. (A) When the voltage between the source and drain is equipotential (VD=0), (B) When a positive potential (VD>0) is applied to the drain relative to the source. [Figure 25] The energy band diagram (schematic) between B and B' in Figure 23 when the gate voltage is 0V. [Figure 26] Energy band diagram (schematic) between B and B' in Figure 23. (A) When a positive potential (VG>0) is applied to the gate (GE1), (B) When a negative potential (VG<0) is applied to the gate (GE1). [Figure 27] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Modes for carrying out the invention]

[0026] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. It is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. This does not mean that the same part or similar function is depicted in the drawings in this specification. Parts are denoted by the same symbol, and their explanations may be omitted.

[0027] (Embodiment 1) In this embodiment, a display device circuit is provided as one form of semiconductor device and method for manufacturing a semiconductor device. One method for manufacturing a circuit board and a circuit board is explained using Figure 1.

[0028] Figure 1(E) shows the cross-sectional structure of multiple transistors fabricated on a circuit board for a display device. An example is shown. Transistors 440A and 440B shown in Figure 1(E) are oxide semiconductor layers. This is a four-terminal structure in which a pair of electrode layers are arranged above and below the flannel-forming region, separated by an insulating film. Furthermore, a pair of electrode layers are arranged above and below the channel formation region of the oxide semiconductor layer, separated by an insulating film. A so-called dual-gate transistor is one embodiment of the four-terminal structure of this embodiment. Furthermore, transistor 440B is applied to the pixels of the display device, and transistor 440A is applied to the pixels. This section describes how this can be applied to a portion of the drive circuit located around the base component.

[0029] Transistor 440A has a first electrode layer 421a on a substrate 400 having an insulating surface, and 1. Insulating layer 402, oxide semiconductor layer 404a including crystalline region 405a, second electrode layer 45 It includes 5a and a third electrode layer 455b. It also covers transistor 440A and the crystal region A second insulating layer 428 is provided in contact with 405a, and a channel is formed via the second insulating layer 428. It has a fourth electrode layer 422a that overlaps the formation region. The first electrode layer 421a and the crystal region The oxide semiconductor layer 404a containing 405a is superimposed via the first insulating layer 402. Furthermore, a portion of the second electrode layer 455a and the third electrode layer 455b is an oxide semiconductor layer 404 It is formed by overlapping with the upper part of a.

[0030] Transistor 440B has a first electrode layer 421b on a substrate 400 having an insulating surface, and 1. Insulating layer 402, oxide semiconductor layer 404b including crystalline region 405b, second electrode layer 45 It includes 5c and a third electrode layer 455d. It also covers transistor 440B and the crystalline region. A second insulating layer 428 is provided in contact with 405b, and a channel is formed via the second insulating layer 428. It has a fourth electrode layer 422b that overlaps the formation region. The first electrode layer 421b and the crystal region The oxide semiconductor layer 404b containing 405b overlaps with the first insulating layer 402. Furthermore, a portion of the second electrode layer 455c and the third electrode layer 455d is the oxide semiconductor layer 404b It is formed by overlapping it on top of the other.

[0031] Transistors 440A and 440B have a dual-gate structure. In a dual-gate transistor, an insulating film is placed above and below the oxide semiconductor layer. Either one or both of the electrode layers can be used as the gate electrode layer. The electrode layer and the third electrode layer function as the source electrode layer and the drain electrode layer.

[0032] In this embodiment, the fourth electrode layer 422a of the transistor 440A is the It is used as the main gate electrode. Therefore, the second electrode layer 455 of the oxide semiconductor layer 404a The region in contact with a and the region in contact with the third electrode layer 455b of the oxide semiconductor layer 404a are sandwiched together. Therefore, a channel is formed in the region that is in contact with the second insulating layer 428 and overlaps with the fourth electrode layer 422a. It will be accomplished.

[0033] In this specification, the first electrode is arranged above and below the oxide semiconductor layer with an insulating film in between. Regarding the layers and the fourth electrode layer, if the potential of the first electrode layer is greater than or equal to the potential of the fourth electrode layer, The first electrode layer is called the main gate electrode, and the potential of the fourth electrode layer is greater than or equal to the potential of the first electrode layer. In this case, the fourth electrode layer shall be called the main gate electrode. Also, the first electrode layer and Either of the four electrode layers may be GND, 0V, or floating. stomach.

[0034] Furthermore, the first electrode layer 421b of transistor 440B is the main gate of the transistor. It is used as an electrode. Therefore, the region of the oxide semiconductor layer 404b that is in contact with the second electrode layer 455c The region is sandwiched between the region and the region in contact with the third electrode layer 455d of the oxide semiconductor layer 404b, and the first electrode layer A channel is formed in the region that is in contact with the marginal layer 402 and overlaps with the first electrode layer 421b.

[0035] Furthermore, transistor 440B has a first electrode layer 421b, a second electrode layer 455c, and a third By using a light-transmitting conductive film in the electrode layer 455d and the fourth electrode layer 422b, A transistor with photochromic properties can be used. A transistor with light-transmitting properties can be used in a display device. When applied to pixels, it can improve the aperture ratio of the pixels.

[0036] The conductive film having light-transmitting properties can be a conductive material that is transparent to visible light, for example, In-Sn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Z nO system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn -Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O oxide conductive materials The material can be applied, and when using the sputtering method, SiO2 should be 2% by weight or more and 10% by weight. A target containing less than % of SiOx (X>0) is used to form a transparent conductive film. It is best to include it and make it amorphous.

[0037] The first electrode layer 421a, the second electrode layer 455a, and the third electrode layer 4 of transistor 440A 55b and the fourth electrode layer 422a are Ti, Mo, W, Al, Cr, Cu, Ta A film mainly composed of elements selected from these can be formed as a single film or as a multilayer film of such elements. In particular, the second electrode layer 455a and the third electrode layer that are electrically connected to the oxide semiconductor layer 455b is preferably a material containing a metal with high oxygen affinity.

[0038] Examples of oxide semiconductor layers include the quaternary metal oxide In-Sn-Ga-Zn-O system and the three-layer system. The original metal oxide systems are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O Systems such as the In-Zn-O system, Sn-Zn-O system, and Al-Zn-O system, which are binary metal oxides. , Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, and monocrystalline metal oxides Oxide semiconductor films such as In-O, Sn-O, and Zn-O can be used. The oxide semiconductor layer may also contain SiO2.

[0039] Furthermore, as an oxide semiconductor layer, InMO3(ZnO) m Thin films denoted as (m>0) It can be used. Here, M is one or more selected from Ga, Al, Mn, and Co. It indicates a number of metallic elements. For example, M could be Ga, Ga and Al, Ga and Mn, or Ga And Co, etc. InMO3(ZnO) m Oxide semiconductors with a structure represented by (m>0) Among the layers, the oxide semiconductor with a structure containing Ga as M is the In-Ga-Zn-O mentioned above. This material is called an oxide semiconductor, and its thin film is also called an In-Ga-Zn-O film.

[0040] Furthermore, the oxide semiconductor layer contains RTA (Rapid Thermal Annealing). The product is treated with a high-temperature, short-time dehydration or dehydrogenation process such as a thermal annealing method. This heating process results in the surface layer of the oxide semiconductor layer having a particle size of 1 nm to 20 nm. It has a crystalline region composed of so-called nanocrystals (also written as nanocrystalline). The rest of the material is amorphous, or contains a mixture of amorphous and microcrystalline regions with microcrystals scattered within the amorphous region. It will be a mixture. Note that the size of the nanocrystals is just one example, and the invention is not limited to the above numerical range. It is not meant to be interpreted.

[0041] By using an oxide semiconductor layer with this configuration, the surface layer is composed of nanocrystals. Because of the presence of dense crystalline regions, n-type formation occurs due to the re-intrusion of water from the surface and the desorption of oxygen. This can be prevented. As a result, the deterioration of electrical characteristics affected by n-type conversion, specifically the increase in off-current, can be prevented. It can be prevented.

[0042] The crystalline region of the surface layer of the oxide semiconductor layer has a direction approximately perpendicular to the surface of the oxide semiconductor layer. It has c-axis oriented crystal grains. For example, In-Ga-Zn-O oxides. When using semiconductor materials, the crystalline region is defined as the c-axis of the In2Ga2ZnO7 crystal grain being oxide. The semiconductor layer is oriented in a direction approximately perpendicular to the surface of the semiconductor layer. Nanocrystals such that their axes are perpendicular to the substrate plane (or the surface of the oxide semiconductor layer) By arranging them, the direction of current in the transistor is the b of In2Ga2ZnO7. This corresponds to the axial direction (or a-axis direction).

[0043] Furthermore, the crystalline region may include elements other than crystal grains. Also, the crystalline structure of the crystal grains may vary. The following is not limited to the crystal structure described above; it may also contain crystal grains of other crystal structures. For example, In-Ga-Zn When using an O-based oxide semiconductor material, in addition to the crystal grains of In2Ga2ZnO7, I It may also contain nGaZnO4 crystal grains, etc.

[0044] Hereafter, using Figures 1(A) to 1(E), transistor 440A and transistor 440A are placed on the same substrate. This explains the process for manufacturing the ZISTA 440B.

[0045] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. The first electrode layer 421a and the first electrode layer 421b are formed by the process. To prevent this, at least the edges of the first electrode layer 421a and the first electrode layer 421b It is preferable to etch the material in such a way that a tapered shape is formed.

[0046] The resist mask may also be formed by an inkjet method. Since the photon process does not require a photomask, manufacturing costs can be reduced. Hmm, it can be applied not only to the first photolithography process, but also to other photolithography processes. Cut.

[0047] The substrate 400 can be barium borosilicate glass, aluminoborosilicate glass, or Alternatively, aluminosilicate glass and other materials produced by fusion or float processes are aluminosilicate glass. Potassium glass substrates, ceramic substrates, and other materials with heat resistance capable of withstanding the processing temperature of this manufacturing process. Plastic substrates can be used. Also, the surface of metal substrates such as stainless steel alloys can be used. A substrate with an insulating film may also be used.

[0048] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may be used. Alternatively, crystallized glass substrates can also be used.

[0049] The first electrode layer 421a and the first electrode layer 421b are made of aluminum, copper, molybdenum, Metal materials such as titanium, chromium, tantalum, tungsten, neodymium, scandium, or alloy materials mainly composed of these metal materials, or nitrogen composed of these metal materials It can be formed using an alloy in a single layer or in layers. Preferably, aluminum or copper. Formation with low-resistance metal materials is effective, but due to heat resistance and corrosion issues, high-melting-point metal materials are used. It is best to use them in combination. High melting point metal materials include molybdenum, titanium, chromium, and tahnitan. Tal, tungsten, neodymium, scandium, etc. can be used.

[0050] In this case, the aperture ratio is improved by using a light-transmitting conductive layer in some of the electrode layers and wiring layers. It is also possible to do so. Examples of transparent conductive layers include indium oxide, indium oxide Tin oxide alloy, indium oxide zinc alloy, zinc oxide, zinc aluminum oxide, oxynitridation An oxide conductive layer containing zinc-aluminum or zinc-gallium oxide can be used. .

[0051] Furthermore, the first electrode layer 421a and the first electrode layer 421b may be formed from different materials. For example, in order to improve the aperture ratio of the pixel portion, the first electrode layer 421b is made transparent to visible light. The first electrode layer 42 of the drive circuit is formed of a conductive layer having properties to suppress wiring resistance. 1a contains a conductive film mainly composed of metal, such as titanium, molybdenum, tungsten, and aluminum. A film primarily composed of elements selected from um, chromium, copper, and tantalum, can be made as a single film or as a combined film. These can also be formed using multilayer films.

[0052] Furthermore, the insulating layer that serves as the base film is made of substrate 400, the first electrode layer 421a, and the first electrode layer 42 It may be placed between 1b. The undercoat has the function of preventing the diffusion of impurity elements from the substrate 400. These include silicon nitride film, silicon oxide film, silicon nitride oxide film, or silicon oxide nitride film, selected from these. It can be formed by a layered structure consisting of one or more films.

[0053] Next, the first insulating layer 402 is formed on the first electrode layer 421a and the first electrode layer 421b. The first insulating layer 402 consists of a silicon oxide layer, a silicon oxide nitride layer, and a silicon nitride oxide layer. Single-layer or multilayer films such as layers, silicon nitride layers, aluminum oxide layers, and tantalum oxide layers It can be used. Furthermore, the film thickness can be set to 50 nm to 250 nm, and CVD or sputtering can be used. It is formed by methods such as the T method. The first insulating layer 402 has an oxide insulating layer on the side that is in contact with the oxide semiconductor layer. A configuration having a border layer is preferred.

[0054] Note that the oxide semiconductor (highly purified oxide semiconductor) that is i-type or substantially i-type by removing impurities used in this embodiment is extremely sensitive to interface states and interface charges, so the interface with the insulating film is important. Therefore, the insulating film in contact with the highly purified oxide semiconductor is required to be of high quality.

[0055] For example, high-density plasma CVD using microwaves (2.45 GHz) is preferable because it can form a dense and high-voltage-resistant high-quality insulating film. This is because by closely contacting the highly purified oxide semiconductor with the high-quality gate insulating film, the interface states can be reduced and the interface characteristics can be made good.

[0056] In addition, the insulating film obtained by a high-density plasma CVD apparatus has excellent step coverage because it can form a film with a constant thickness. Also, the insulating film obtained by a high-density plasma CVD apparatus can precisely control the thickness of a thin film.

[0057] Of course, if a high-quality insulating film can be formed as the gate insulating film, other film formation methods such as sputtering and plasma CVD can be applied. Also, an insulating film whose film quality and interface characteristics with the oxide semiconductor are modified by heat treatment after film formation is also good. In any case, it is needless to say that the film quality as the gate insulating film is good, and as long as it can reduce the interface state density with the oxide semiconductor and form a good interface.

[0058] The formation of the first insulating layer 402 is performed by a high-density plasma CVD apparatus. Here, the high-density plasma CVD apparatus refers to an apparatus that can achieve a plasma density of 1×10 11 / cm 3 or more. For example, by applying microwave power of 3kW to 6kW to generate plasma, The insulating film is deposited.

[0059] Monosilane gas (SiH4), nitrous oxide (N2O), and dilute gas are placed in the chamber as material gases. By introducing a system that generates high-density plasma under a pressure of 10 Pa to 30 Pa, it can insulate glass and other materials. An insulating film is formed on a substrate with a surface. Then, the supply of monosilane gas is stopped, and the atmosphere is exposed. Plasma treatment is performed on the insulating film surface by introducing nitrous oxide (N2O) and a noble gas without exposure to the elements. It is permissible to do so. At a minimum, it should be done by introducing nitrous oxide (N2O) and a noble gas onto the insulating film surface. The plasma treatment is performed after the deposition of the insulating film. The insulating film that has undergone the above process sequence is a film This insulating film is thin, and can ensure reliability even at thicknesses of less than 100 nm. .

[0060] When forming the first insulating layer 402, monosilane gas (SiH4) and sub-silane gas are introduced into the chamber. The flow rate ratio with nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The noble gases introduced into the bar include helium, argon, krypton, and xenon. While it is possible to use any of these methods, it is preferable to use argon, which is the least expensive.

[0061] Furthermore, insulating films obtained using a high-density plasma device can form films of a consistent thickness. It has excellent step coverage. In addition, insulating films obtained by high-density plasma devices are thin films. The thickness can be precisely controlled.

[0062] The insulating film obtained through the above process sequence is different from the insulating film obtained with a conventional parallel-plate type PCVD apparatus. The results differ significantly, and when comparing etching rates using the same etchant, Therefore, the insulating film obtained with a parallel-plate type PCVD apparatus is 10% or more slower or 20% or more slower, and high The insulating film obtained using a density plasma device can be described as a dense film.

[0063] Furthermore, as the first insulating layer 402, silicon oxide is produced by a CVD method using organic silane gas. It is also possible to form layers. As for organic silane gases, ethyl silicate (TEOS: chemical) is used. Formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), Tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane Sun (OMCTS), Hexamethyldisilazane (HMDS), Triethoxysilane (Si H(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. A silicon-containing compound can be used.

[0064] Furthermore, the first insulating layer 402 may be made of an oxide of aluminum, yttrium, or hafnium. A substance, nitride, oxidized nitride, or a type of nitride oxide or a compound thereof, containing at least two of these. Compounds containing the above components can also be used.

[0065] In this specification, an oxidized nitride is defined as a compound in which oxygen atoms are more abundant than nitrogen atoms. It refers to a substance with a large number of nitrogen atoms, and nitride oxides, in terms of their composition, have more nitrogen atoms than oxygen atoms. This refers to substances that are present in large quantities. For example, silicon oxidnitride film has a composition that includes nitrogen atoms. The number of oxygen atoms is greater than that of the child, and Rutherford backscattering (RBS) Backscattering Spectrometry and hydrogen forward scattering (H) The measurement was performed using FS (Hydrogen Forward Scattering). In total, the concentration range should be 50 atomic% to 70 atomic% for oxygen and 0.5 atomic% to 1 Less than 5 atomic percent, silicon 25 atomic percent to 35 atomic percent, hydrogen 0.1 atomic percent to 10 This refers to substances included in amounts less than an atomic percent. Furthermore, silicon nitride oxide film refers to its composition as follows: Therefore, when the number of nitrogen atoms is greater than the number of oxygen atoms, and when measured using RBS and HFS, the concentration The range is 5 atomic percent to 30 atomic percent for oxygen, and 20 atomic percent to 55 atomic percent for nitrogen. The range is 25 to 35 atomic percent silicon and 10 to 30 atomic percent hydrogen. This refers to the elements included in silicon oxide nitride or silicon nitride oxide. However, this does not include the atoms that make up silicon oxide nitride or silicon nitride oxide. When the total is set to 100 atomic%, the content ratios of nitrogen, oxygen, silicon, and hydrogen are within the above range. It shall be included within the enclosed area.

[0066] Next, a film thickness of 5 nm to 200 nm, preferably 10 nm, is applied to the first insulating layer 402. A oxide semiconductor film 403 of 20 nm or less is formed (Figure 1(A)).

[0067] Furthermore, before depositing the oxide semiconductor film 403, argon gas is introduced to generate plasma. By performing reverse sputtering, dust adhering to the surface of the first insulating layer 402 can be removed. Preferred. Reverse sputtering is a process where a voltage is not applied to the target side, and the substrate is subjected to an argon atmosphere. A method of modifying the surface by applying a voltage using an RF power supply to form plasma near the substrate. This is the case. Note that nitrogen, helium, etc. may be used instead of an argon atmosphere. The procedure can also be carried out in an argon atmosphere with added oxygen, N2O, etc. Alternatively, in an argon atmosphere... The process may also be carried out in an atmosphere containing Cl2, CF4, etc. After reverse sputtering, expose to the air. By forming an oxide semiconductor film without the first insulating layer 402 and the oxide semiconductor film 40 This prevents dirt and moisture from adhering to the interface of 3.

[0068] Oxide semiconductor films include the quaternary metal oxides mentioned earlier, such as the In-Sn-Ga-Zn-O system and , ternary metal oxides such as In-Ga-Zn-O system, In-Sn-Zn-O system, In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O systems, and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn- O-based, Zn-Mg-O-based, Sn-Mg-O-based, In-Mg-O-based, and monocrystalline metal oxides Certain oxide semiconductor films such as In-O, Sn-O, and Zn-O can be used. Furthermore, the oxide semiconductor film may also contain SiO2. The InMO3(ZnO) mentioned above m Thin films denoted as (m>0) can be used.

[0069] Furthermore, oxide semiconductor films are fabricated under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or Formed by sputtering in a mixed atmosphere of noble gas (typically argon) and oxygen. This is possible. Furthermore, when using the sputtering method, the SiO2 content should be between 2% and 10% by weight. Using a target containing SiOx(X>, crystallization is inhibited in oxide semiconductor films. You may include 0).

[0070] Here, an oxide semiconductor film deposition target containing In, Ga, and Zn (composition ratio of I n2O3:Ga2O3:ZnO = 1:1:1 [molar ratio], or In2O3:Ga2 Using O3:ZnO=1:1:2 (molar ratio), the distance between the substrate and the target is 100mm, pressure 0.6Pa, DC power supply 0.5kW, oxygen (oxygen flow rate ratio 100) The film is deposited under a %) atmosphere. Note that if a pulsed DC power supply is used, the following will occur during film deposition. This method is preferred because it reduces powdery material (also called particles or dust) and results in a more uniform film thickness distribution. In this embodiment, the oxide semiconductor film is an In-Ga-Zn-O based oxide semiconductor. Using a film deposition target, an In-Ga-Zn-O film with a thickness of 15 nm is deposited by sputtering. To form a film.

[0071] In this case, it is preferable to deposit the oxide semiconductor film while removing residual moisture in the processing chamber. This is to prevent hydrogen, hydroxyl groups, or water from being present in the oxide semiconductor film.

[0072] Furthermore, it is preferable to continuously deposit the oxide semiconductor film on the first insulating layer 402. This multi-chamber type sputtering apparatus uses silicon or silicon oxide (artificial quartz) sputtering. It has a get and a target for oxide semiconductor films, and at least for oxide semiconductor films The film deposition chamber equipped with the target has a cryopump as an exhaust means. Instead of a lyopump, a turbomolecular pump is used, and water is placed on the intake port of the turbomolecular pump. A configuration that includes a cold trap to adsorb particles and other substances is also possible.

[0073] The deposition chamber, which is evacuated using a cryopump, contains hydrogen atoms, for example, H2O, which contains hydrogen atoms. Because the compounds contained, carbon atoms, and compounds containing carbon atoms are exhausted, the film formation process in the film formation chamber is carried out. This method can reduce the concentration of impurities in the deposited oxide semiconductor film.

[0074] The sputtering gas used when depositing oxide semiconductor films is hydrogen, water, hydroxyl groups, or hydrides. Which impurities are removed to a concentration of several ppm or several ppb in high-purity gas? It is preferable.

[0075] Furthermore, the oxide semiconductor film may be deposited while heating the substrate. In this case, the substrate temperature is set to 100°C. The temperature should be between 5°C and 600°C, preferably between 200°C and 400°C. The substrate is heated while forming By forming a film, the concentration of impurities in the deposited oxide semiconductor film can be reduced. ru.

[0076] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering, which uses a DC power supply. There is DC sputtering, and also pulsed DC sputtering, which applies a pulsed bias. Sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing metal conductive films. It is used when forming thin films.

[0077] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0078] Furthermore, a sputtering apparatus that uses the magnetron sputtering method, which has a magnetic mechanism inside the chamber. Alternatively, ECR sputtering uses plasma generated with microwaves instead of glow discharge. There are sputtering machines that use this method.

[0079] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas components are deposited during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of these compounds, and during film formation... There is also a bias sputtering method that applies voltage to the circuit board.

[0080] Next, a second photolithography process is performed to form a resist mask, and In-Ga-Z The nO-based film is etched. For etching, organic ions such as citric acid and oxalic acid are used. Acids can be used as etchants. Edges of oxide semiconductor layers 404a and 404b By etching it into a tapered shape, it is possible to prevent the wiring from being cut off due to the stepped shape. Note that etching here is not limited to wet etching, but also includes dry etching. It's okay to be there.

[0081] Next, the oxide semiconductor layers 404a and 404b are dehydrated or dehydrogenated. Alternatively, the first heat treatment for dehydrogenation may involve resistance heating or lamp irradiation under an inert gas atmosphere. By which means, at a temperature between 500°C and 750°C (or below the strain point of the glass substrate) RTA for approximately 1 minute to 10 minutes, preferably at 650°C, and approximately 3 minutes to 6 minutes. This can be done using (Rapid Thermal Annealing) processing. The RTA method is used. If present, dehydration or dehydrogenation can be performed in a short time, and the temperature exceeds the strain point of the glass substrate. It can also be processed. Note that the heat treatment is not limited to this timing, but can also be done using photolithography. This process can be performed multiple times, such as before or after the film deposition process.

[0082] In this specification, heating treatment under an inert gas atmosphere such as nitrogen or a noble gas is referred to as dehydration. Alternatively, this is called a heat treatment for dehydrogenation. In this specification, this heat treatment is used to produce H2. Dehydrogenation is not simply defined as the process of removing H, OH, etc. For convenience, this process, including the dehydration or dehydrogenation, will be referred to as such.

[0083] From the heating temperature T used to dehydrate or dehydrogenate the oxide semiconductor layer, In the same furnace where the ionization was performed, without exposure to the atmosphere and without re-introducing water or hydrogen, It is important to lower the temperature to a low level. Dehydration or dehydrogenation occurs simultaneously with oxygen deficiency, and acid Converting the semiconductor layer to n-type (n - , n + (etc.), that is, after reducing resistance, oxygen is supplied. When a transistor is fabricated using an oxide semiconductor layer that has been made i-type by increasing its resistance, The threshold voltage value of the zista can be set to a positive value, resulting in a switch with so-called normally-off characteristics. A threshold element can be realized. The gate voltage of the transistor is as close to 0V as possible. For display devices, it is desirable that channels are formed by voltage. If the voltage value is negative, even if the gate voltage is 0V, electricity will still be present between the source and drain electrodes. The flow is prone to what is known as the normally-on characteristic. Active matrix display devices In this context, the electrical characteristics of the transistors that make up the circuit are important, and these electrical characteristics are displayed. It affects the performance of the device. In particular, the threshold voltage (Vth) among the electrical characteristics of a transistor. This is important. Even if the field effect mobility is high, the threshold voltage value is high, or the threshold voltage value If the threshold voltage is negative, it becomes difficult to control the circuit. In the case of a transistor, when the drive voltage is low, it does not function as a transistor for switching. It may not be able to perform its function and could become a burden. In the case of an n-channel transistor, A channel is formed and drain current begins to flow only when a positive voltage is applied to the drain voltage. A transistor is preferable. Transistors that do not form a channel unless the drive voltage is high or A transistor that forms a channel and allows drain current to flow even in a negative voltage state is a transistor that can be used in a circuit. It is unsuitable as a transistor to be used.

[0084] Furthermore, the gas atmosphere during cooling from the heating temperature T is the same as the gas atmosphere that was heated to the heating temperature T. You may switch to a different gas atmosphere. For example, the same gas atmosphere used for dehydration or dehydrogenation. Without exposing the material to the atmosphere in the furnace, high-purity oxygen gas or N2O gas, ultra-dry esters are used inside the furnace. The mixture is filled with a solution (with a dew point of -40°C or lower, preferably -60°C or lower) and cooled.

[0085] Furthermore, in the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. i. Alternatively, the purity of the inert gas introduced into the heat treatment device shall be 6N (99.9999%) or less. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferred It is preferable to keep the concentration below 0.1 ppm.

[0086] When the above heat treatment is performed under an inert gas atmosphere, the oxide semiconductor layer is subjected to the heat treatment. It becomes oxygen-deficient, resulting in lower resistance, i.e., n-type (n - (e.g., chemical transformation). Afterwards, an oxide semiconductor layer By forming an oxide insulating layer in contact with the oxide semiconductor layer, oxygen is supplied to the oxygen-deficient areas of the oxide semiconductor layer. This can be said to increase the resistance, or in other words, make it an i-type design. As a result, it has good electrical characteristics and reliability. This allows for the fabrication of high-quality transistors.

[0087] Oxide semiconductor layers that have been sufficiently dehydrated or dehydrogenated under the above conditions are analyzed by temperature-controlled desorption gas analysis. (TDS: Thermal Desorption Spectroscopy) 45 Even when heated to 0°C, the spectrum showing water desorption has two peaks, at least 250-3°C. The single peak that typically appears around 00°C is not detected.

[0088] Furthermore, the oxide semiconductor layer 404a and the oxide semiconductor layer 404b are multiply when they are formed. It is amorphous with many unbonded bonds, but in the first heating step of the above dehydration or dehydrogenation treatment By doing this, nearby unbonded bonds connect with each other, resulting in an ordered amorphous structure. This is possible. Furthermore, as ordering develops, amorphous regions with microcrystals scattered within them become amorphous and microcrystalline. A mixture of crystals, or entirely amorphous, is formed, with an oxide semiconductor layer 404a and an oxide semiconductor layer. Crystalline region 405a and crystalline region 405 are composed of nanocrystals on the surface of the conductive layer 404b b is formed (Figure 1(B)). Also, oxide semiconductor layer 404a and oxide semiconductor layer 4 The other regions of 04b are amorphous, and a mixture of amorphous and microcrystalline regions with microcrystals scattered within the amorphous region. It becomes a composite. Note that crystalline region 405a and crystalline region 405b are oxide semiconductor layer 404a , and part of the oxide semiconductor layer 404b, thereafter oxide semiconductor layer 404a, or acid The notation for the crystalline semiconductor layer 404b includes either the crystalline region 405a or the crystalline region 405b. It shall be assumed that the particle size of the microcrystals is between 1 nm and 20 nm, which are so-called nanocrystals. These are smaller in size than microcrystalline particles, which are generally called microcrystals. be.

[0089] Furthermore, in crystalline regions 405a and 405b, the c-axis orientation is perpendicular to the film surface. It is preferable that the following nanocrystals are formed, in which case the long axis is in the c-axis direction and the short axis is in the c-axis direction. Preferably, the wavelength is between 1 nm and 20 nm.

[0090] Furthermore, depending on the order of the process, a crystalline region may not be formed on the side surface of the oxide semiconductor layer. Crystalline regions are formed in the surface layer, excluding the surface layer. However, the area ratio of the side surface is small, and in this case... Even with this, the effects of suppressing the deterioration of electrical properties and improving insulation withstand voltage are maintained.

[0091] Furthermore, the first electrode layer 421a and the first electrode layer 421b are also subject to the conditions of the first heat treatment, Depending on the material, it may crystallize and form a microcrystalline film or a polycrystalline film. For example, the first In the case where indium tin oxide is used as the electrode layer 421a and the first electrode layer 421b The mixture crystallizes after a first heat treatment at 450°C for 1 hour, but it contains silicon oxide indium oxide When tin is used for the first electrode layer 421a and the first electrode layer 421b, crystallization does not occur. Kui.

[0092] Furthermore, the oxide semiconductor layers 404a and 404b after the first heat treatment become oxygen-deficient. The carrier concentration is higher than immediately after film formation, preferably 1 × 10⁻⁶ 18 / cm 3 The above career details This results in oxide semiconductor layers 404a and 404b with a degree of resistance and reduced resistance.

[0093] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is extracted and then subjected to a photolithography process to process it into island-shaped oxide semiconductor layers.

[0094] Next, although not shown in the diagram, there is a first electrode layer and a source electrode layer or drain electrode, which will be explained later. Openings (also called contact holes) for connecting the layers are formed in the first insulating layer 402. The first insulating layer 402 is then subjected to a mass by photolithography or inkjet method, etc. A mask is formed, and the first insulating layer 402 is selectively etched using the mask to make contact. A hole is formed. Note that the formation of the contact hole occurs after the formation of the first insulating layer 402, by oxidation. This may be performed before the formation of the monosemiconductor film 403.

[0095] Next, source electrodes and drain electrodes (same as above) are placed on oxide semiconductor layers 404a and 404b. A conductive film is formed (including wiring formed in a single layer). The conductive film has a thickness of 100 nm or more. It is formed with a thickness of 0 nm or less, preferably 200 nm to 300 nm.

[0096] The source electrode and drain electrode are made of metal materials such as Al, Cu, Cr, Ta, Ti, Mo, and W. It is formed from a material, or an alloy material having said metal material as a component. Also, a metal layer such as Al or Cu. A configuration in which a high-melting-point metal layer such as Cr, Ta, Ti, Mo, or W is laminated on one or both of the above. It is also acceptable to use Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. on Al films. Use an aluminum material to which elements that prevent the formation of hillocks and whiskers are added. This makes it possible to improve heat resistance.

[0097] The source electrode and drain electrode (including wiring formed in the same layer) are made of conductive metallic acid. It may also be formed from an oxide. Examples of conductive metal oxides include indium oxide (In2O3) and acid Tin oxide (SnO2), zinc oxide (ZnO), indium oxide tin alloy (In2O3) SnO2 (abbreviated as ITO), indium zinc oxide alloy (In2O3-ZnO) Alternatively, the metal oxide material may be made to contain silicon or silicon oxide. Yes, it is possible. Furthermore, it is not limited to a single layer containing the aforementioned elements; two or more layers can be used. The conductive film has at least enough heat resistance to withstand the second heat treatment that will be performed later. It is preferable that it has [this feature].

[0098] Furthermore, the conductive film in contact with the oxide semiconductor layers 404a and 404b contains a metal with high oxygen affinity. The material is preferable. Metals with high oxygen affinity include titanium (Ti) and manganese (Mn). Magnesium (Mg), Zirconium (Zr), Beryllium (Be), Thorium (Th) It is preferable that the material is selected from one or more of the following. In this embodiment, A tongue film is used.

[0099] When an oxide semiconductor layer and a conductive film with high oxygen affinity are formed in contact, the carrier density near the interface This increases the resistance, forming a low-resistance region and reducing the contact resistance between the oxide semiconductor layer and the conductive film. Yes, it is possible. This is because the highly oxygen-affinity conductive film extracts oxygen from the oxide semiconductor layer. Furthermore, at the interface between the oxide semiconductor layer and the conductive film, there is a layer with an excess of metal from the oxide semiconductor layer (also known as a composite layer). (This is called by the formation of either an oxidized conductive film or both.) For example, in a configuration where an In-Ga-Zn-O oxide semiconductor layer and a titanium film are in contact: Near the interface between the oxide semiconductor layer and the titanium film, there is a layer with an excess of indium and a titanium oxide layer. In some cases, indiu may be formed near the interface between the oxide semiconductor layer and the titanium film. In some cases, either an excess layer of ions or a titanium dioxide layer may be formed. In an O-based oxide semiconductor layer, a layer with an excess of oxygen-deficient indium has high electrical conductivity, and acid This makes it possible to reduce the contact resistance between the ionized semiconductor layer and the conductive film.

[0100] Furthermore, a titanium film or conductive titanium oxide film may be used as the conductive film in contact with the oxide semiconductor layer. A film may also be used. In that case, an In-Ga-Zn-O based oxide semiconductor layer and titanium dioxide may be used. In a configuration where the films are in contact, near the interface between the oxide semiconductor layer and the titanium oxide film, an indicator is present. In some cases, an excess layer of um may be generated.

[0101] Furthermore, a conductive material that is transparent to visible light can also be used as the conductive film. The conductive material that is transparent to visible light is indium, tin, or zinc. Transparent conductive oxides containing are preferred, for example, indium oxide (In2O3) and indium oxide. A tin oxide alloy (In2O3-SnO2, abbreviated as ITO) can be used. Alternatively, a material in which an insulating oxide such as silicon oxide is added to a transparent conductive oxide may be used. i. By using a transparent conductive oxide as a conductive film, the aperture ratio of the display device can be improved. It is possible.

[0102] Furthermore, methods for depositing conductive films include arc discharge ion plating and spraying. It may also be used. In addition, conductive nanopastes such as silver, gold, and copper can be screen printed, ink It may also be formed by extrusion and firing using methods such as the cudget method.

[0103] Next, a mask is formed on the conductive film by photolithography or inkjet printing. Then, the conductive film is etched using the mask to form the source electrode and drain electrode. (Figure 1(C)). In this embodiment, a conductive film with a thickness of 200n is formed by sputtering. A Ti film of m is formed, and using a resist mask, it is etched by wet etching or dry etching. The conductive film is selectively etched using the etching method and used as the source electrode and drain electrode. The second electrode layer 455a, the third electrode layer 455b, the second electrode layer 455c, and the third electrode layer 455a are capable of performing the function. An electrode layer 455d is formed.

[0104] The first, the second electrode layer 455a, the third electrode layer 455b, the second electrode layer 455c, and A second insulating layer covering electrode layer 455d and exposed oxide semiconductor layers 404a and 404b. Form 428 (Figure 1(D)). The thickness of the second insulating layer 428 is 50 nm to 250 nm. The following is preferable, wherein the second insulating layer 428 has an oxide insulating layer on the side in contact with the oxide semiconductor layer. The oxide insulating layer on the side of the second insulating layer 428 that is in contact with the oxide semiconductor layer is acid Silicon oxide layer, silicon oxide nitride layer, aluminum oxide layer, tantalum oxide layer, ytoxide An oxide insulating layer such as a lium layer or a hafnium oxide layer can be used.

[0105] The oxide insulating layer is created by methods such as sputtering, which introduces impurities such as water and hydrogen into the oxide insulating layer. It can be formed using any method as appropriate. In this embodiment, the sputtering method is used. Then, a silicon oxide film is formed as an oxide insulating layer. The substrate temperature during film formation is above room temperature and up to 300°C. The following is sufficient, and in this embodiment, it is set to 100°C. Here, during film formation, if water, hydrogen, etc. As a method to prevent contamination with pure substances, before film formation, the temperature is 150°C to 350°C under reduced pressure for 2 Perform a pre-bake for more than 10 minutes to form an oxide insulating layer without exposure to the atmosphere. It is desirable to do so. For silicon oxide film deposition by sputtering, a rare gas (typically, a) is used. Under an argon atmosphere, under an oxygen atmosphere, or under a mixture of a noble gas (typically argon) and oxygen. It can be carried out in an atmosphere. Also, a silicon oxide target or a silicon target can be used as the target. For example, using a silicon target, silicon oxide can be formed by sputtering in an oxygen and rare gas atmosphere. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer is formed while avoiding the inclusion of impurities such as moisture, hydrogen ions, and OH. For example, using a silicon target, silicon oxide can be formed by sputtering in an oxygen and rare gas atmosphere. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer is formed while avoiding the inclusion of impurities such as moisture, hydrogen ions, and OH. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer is formed while avoiding the inclusion of impurities such as moisture, hydrogen ions, and OH. - The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer is formed while avoiding the inclusion of impurities such as moisture, hydrogen ions, and OH. The oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer is formed while avoiding the inclusion of impurities such as moisture, hydrogen ions, and OH.

[0106] Also, an inorganic insulating film is laminated on the oxide insulating layer, and a configuration that suppresses the intrusion of impurities such as moisture, hydrogen ions, and OH from the outside into the oxide semiconductor layer is preferable. As the inorganic insulating film laminated on the oxide insulating layer of the second insulating layer 428, a silicon oxide layer, a silicon oxynitride layer, - Also, an inorganic insulating film is laminated on the oxide insulating layer, and a configuration that suppresses the intrusion of impurities such as moisture, hydrogen ions, and OH from the outside into the oxide semiconductor layer is preferable. As the inorganic insulating film laminated on the oxide insulating layer of the second insulating layer 428, a silicon oxide layer, a silicon oxynitride layer, Also, an inorganic insulating film is laminated on the oxide insulating layer, and a configuration that suppresses the intrusion of impurities such as moisture, hydrogen ions, and OH from the outside into the oxide semiconductor layer is preferable. As the inorganic insulating film laminated on the oxide insulating layer of the second insulating layer 428, a silicon oxide layer, a silicon oxynitride layer, a silicon oxynitride layer, a silicon nitride layer, an aluminum oxide layer, a tantalum oxide layer, etc. can be used. a silicon oxynitride layer, a silicon nitride layer, an aluminum oxide layer, a tantalum oxide layer, etc. can be used. a silicon oxynitride layer, a silicon nitride layer, an aluminum oxide layer, a tantalum oxide layer, etc. can be used.

[0107] In this embodiment, a silicon target with a purity of 6N and columnar polycrystalline B-doped (resistivity 0.01 Ω·cm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, the pressure is 0.4 Pa, a DC (DC) power supply of 6 kW, and a pulsed DC sputtering method is used in an oxygen (oxygen flow ratio 100%) atmosphere to form a film. The film thickness is 300 nm. Also, when forming the second insulating layer 428, the sputtering gas used is preferably a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to a concentration of about ppm or about ppb. the pressure is 0.4 Pa, a DC (DC) power supply of 6 kW, and a pulsed DC sputtering method is used in an oxygen (oxygen flow ratio 100%) atmosphere to form a film. The film thickness is 300 nm. Also, when forming the second insulating layer 428, the sputtering gas used is preferably a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to a concentration of about ppm or about ppb. the pressure is 0.4 Pa, a DC (DC) power supply of 6 kW, and a pulsed DC sputtering method is used in an oxygen (oxygen flow ratio 100%) atmosphere to form a film. The film thickness is 300 nm. Also, when forming the second insulating layer 428, the sputtering gas used is preferably a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to a concentration of about ppm or about ppb. the pressure is 0.4 Pa, a DC (DC) power supply of 6 kW, and a pulsed DC sputtering method is used in an oxygen (oxygen flow ratio 100%) atmosphere to form a film. The film thickness is 300 nm. Also, when forming the second insulating layer 428, the sputtering gas used is preferably a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to a concentration of about ppm or about ppb. the pressure is 0.4 Pa, a DC (DC) power supply of 6 kW, and a pulsed DC sputtering method is used in an oxygen (oxygen flow ratio 100%) atmosphere to form a film. The film thickness is 300 nm. Also, when forming the second insulating layer 428, the sputtering gas used is preferably a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to a concentration of about ppm or about ppb. the pressure is 0.4 Pa, a DC (DC) power supply of 6 kW, and a pulsed DC sputtering method is used in an oxygen (oxygen flow ratio 100%) atmosphere to form a film. The film thickness is 300 nm. Also, when forming the second insulating layer 428, the sputtering gas used is preferably a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to a concentration of about ppm or about ppb.

[0108] Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, in a nitrogen atmosphere Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. For example, in a nitrogen atmosphere Perform a second heat treatment at 250°C for 1 hour under reduced pressure. Or, perform a high-temperature rapid thermal annealing (RTA) treatment for a short time. When the second heat treatment is performed, the oxide insulating layer and the oxide semi- conductor layer are heated while in contact, and oxygen is supplied to the oxygen-deficient part of the oxide semiconductor layer that has been made low-resistance by the first heat treatment, enabling high-resistance (type-i) conversion.

[0109] In this embodiment, the second heat treatment is performed after forming the silicon oxide film. However, the timing of the heat treatment is not limited to immediately after forming the silicon oxide film, and there is no problem as long as it is after forming the silicon oxide film.

[0110] Next, perform a photolithography process to form a resist mask, and form a contact hole that reaches the second electrode layer 455d by etching the second insulating layer 428.

[0111] Next, after forming a conductive film on the second insulating layer 428, perform a photolithography process on the conductive film to form the fourth electrode layer 422a, the fourth electrode layer 422b, and a connection electrode layer 422c that is connected to the pixel electrode layer in a later process (Fig. 1(E)). As the conductive film, a film mainly composed of an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W can be used as a single film or a laminated film. However, when the third electrode layer 455d and the pixel electrode layer are directly connected, the connection electrode layer 422c may be omitted.

[0112] In this embodiment, the fourth electrode layer 422a of the transistor 440A is used as the main gate electrode of the transistor. Also, the potential of the first electrode layer 421a may be lower than the potential of the fourth electrode layer 42 2a, or may be in a GND, 0V, or floating state. ​​​​

[0113] Furthermore, the first electrode layer 421b of transistor 440B is the main gate of the transistor. It is used as an electrode. Furthermore, the potential of the fourth electrode layer 422b is greater than or equal to the potential of the first electrode layer 421b. It can be down, GND, 0V, or floating.

[0114] A pair of electrode layers are placed above and below the channel formation region of the oxide semiconductor layer via an insulating film, forming four ends. By using a substructure, the reliability of the transistor can be improved. Specifically, A bias-thermal stress test (hereinafter referred to as the BT test) was used to examine the reliability of the inverter. In this way, the change in the threshold voltage of the transistor before and after the BT test can be reduced. Cut.

[0115] Furthermore, as shown in Figure 2, a transistor that uses the first electrode layer as the main gate electrode is... A configuration without a fourth electrode layer is also acceptable.

[0116] Figure 2 shows an example of the cross-sectional structure of multiple transistors fabricated on a circuit board for a display device. As shown in Figure 2, transistor 440A has an insulating layer above and below the channel formation region of the oxide semiconductor layer. It is one of the four-terminal structures in which a pair of electrode layers are arranged via a border film, and transistor 450 is reverse It is a staggered type.

[0117] Furthermore, transistor 440A is part of the drive circuit located around the pixel area of ​​the display device. It is preferable that the transistor 450 is used in the pixel, as part of the drive circuit, or as part of the protection circuit. It is preferable that it be formed in a road.

[0118] The transistor 450 has a first electrode layer 421c on a substrate 400 having an insulating surface, and An insulating layer 402, an oxide semiconductor layer 404c including a crystalline region 405c, and a second electrode layer 455 e, and a third electrode layer 455f. Further, it has a second insulating layer 428 that covers the transistor 450 and contacts the crystalline region 40 5c. The first electrode layer 421c and the oxide semiconductor layer 40 4c overlap via the first insulating layer 402. Also, a part of the second electrode layer 455e and the third electrode layer 455f is formed to overlap above the oxide semiconductor layer 404c.

[0119] Note that a protective insulating layer may be formed to cover the transistors 440A and 440B. As the protective insulating layer, for example, a silicon nitride film, a silicon oxynitride film, or an aluminum nitride film, etc. is used.

[0120] Also, a planarizing insulating layer may be provided on the fourth electrode layer 422b in the pixel portion. As the planarizing insulating layer, heat-resistant organic materials such as acrylic, polyimide, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that a plurality of insulating layers formed of these materials may be laminated. Also, a color filter layer can be used as the planarizing insulating layer.

[0121] Also, a capacitance wiring that can be manufactured from the same material and in the same process as the first electrode layer 421b, and a capacitance electrode that can be manufactured from the same material and in the same process as the fourth electrode layer 422b are used to form a holding capacitor sandwiching a dielectric layer including the first insulating layer 402 or an oxide insulating layer on the same substrate. Pixels having the transistor 440B and the holding capacitor are arranged A substrate with a drive circuit having transistor 440A arranged around the pixel area is an active machine. It can be used as one of the substrates for fabricating a Trix-type display device.

[0122] Furthermore, when manufacturing a display device using transistors 440A and 440B, the drive transistor A power supply line is provided that is electrically connected to the source electrode layer of the zista, and this power supply line is connected to the gate It intersects with the wiring and is shaped using the same material and process as the connecting electrode layer 422c, which is made of a metal conductive film. Alternatively, the power supply line crosses the source wiring and is the same as the first electrode layer 421b. The same materials are used and formed using the same process.

[0123] Furthermore, when fabricating a light-emitting device, one electrode of the light-emitting element is connected to the source power of the driving transistor. It is electrically connected to the polar layer or drain electrode layer, and electrically connected to the other electrode of the light-emitting element. A common potential line is provided. This common potential line is connected to a connecting electrode layer 4 made of a metal conductive film. Formed using the same material and process as 22c. Alternatively, the common potential line is formed in the first electrode layer 421b. It is formed using the same materials and the same process.

[0124] As described above, the transistor having an oxide semiconductor layer with reduced hydrogen concentration is an off-electric transistor. The flow is extremely low, 1 × 10 -13 It has characteristics below A. As an inverter, for example, silicon carbide (e.g., 4H-SiC) is used. Iridescent semiconductors and 4H-SiC share several commonalities, one example being carrier density. Yes. Using the Fermi-Dirac distribution at room temperature, the minority carriers in oxide semiconductors are 1 0 -7 / cm 3 It is estimated to be around 6.7 × 10 in 4H-SiC.-1 1 / cm 3 Similarly, it is an extremely low value. The intrinsic carrier density of silicon is (1.4 × 10⁻⁶). 1 0 / cm 3 By comparing it to other levels, it becomes clear that its level is extraordinary. The energy band gap of oxide semiconductors is 3.0~3.5eV, and 4H-SiC Its energy band gap is 3.26 eV, so it is a wide-bandgap semiconductor. In this regard, oxide semiconductors and silicon carbide share commonalities.

[0125] On the other hand, there is a very significant difference between oxide semiconductors and silicon carbide. This is the process temperature. Semiconductor processes using silicon carbide generally operate at temperatures between 1500°C and 2000°C. The process involves activation heat treatment. At such high temperatures, semiconductor substrates and semiconductor elements can be destroyed. Therefore, an integrated circuit was formed using other semiconductor materials, and then a semiconductor was added using silicon carbide. It is difficult to form conductive elements. On the other hand, oxide semiconductors can be heated to 300-500°C (glass It can be manufactured by heat treatment below the transition temperature (maximum of about 700°C), unlike other semiconductors. After forming an integrated circuit using a conductive material, semiconductor elements are formed using oxide semiconductors. This becomes possible.

[0126] Furthermore, unlike with silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. It has the advantage of not requiring high-temperature heat treatment, compared to silicon carbide. This has the advantage of significantly reducing energy costs.

[0127] Furthermore, in oxide semiconductors, physical properties such as DOS (density of states) While much research has been done, these studies focus on the idea of ​​significantly reducing the use of DOS itself. It does not include. In one aspect of the disclosed invention, it may be a cause of DOS in the energy gap. By removing water and hydrogen from the oxide semiconductor, a highly purified oxide semiconductor is produced. This is based on the idea of ​​significantly reducing the use of DOS itself. This makes it possible to manufacture extremely high-quality industrial products.

[0128] Furthermore, it supplies oxygen to the unbonded metals that occur due to oxygen deficiency, and the oxygen vacancies By reducing DOS, an even higher purity (type i) oxide semiconductor can be achieved. This is also possible. For example, by forming an oxygen-rich oxide film in close proximity to the channel-forming region. By supplying oxygen from the oxide film, it is possible to reduce DOS caused by oxygen vacancies.

[0129] Defects in oxide semiconductors include levels below the conduction band of 0.1-0.2 eV due to excess hydrogen, and oxygen... These are believed to be caused by deep energy levels due to deficiencies, etc. In order to eliminate these defects, The technological concept of thoroughly removing hydrogen and supplying sufficient oxygen is likely correct.

[0130] Furthermore, although oxide semiconductors are generally considered to be n-type, in one aspect of the disclosed invention, impurities, In particular, the i-type is achieved by removing water and hydrogen. In this respect, unlike silicon, This approach involves a completely new technological concept, rather than simply adding pure substances to create a Type I product.

[0131] Transistors using oxide semiconductors have several characteristics. Here, regarding their conduction mechanism... This will be explained using Figures 23 to 26. However, the following explanation is merely one consideration, and this... It should be noted that the effectiveness of the invention is not negated based on this. I will explain that next.

[0132] Figure 23 shows a longitudinal cross-sectional view of an inverse staggered transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the electrode (GE1) via a gate insulating film (GI), A source electrode (S) and a drain electrode (D) are provided on top of it. Furthermore, an insulating layer is placed on top of it. A back gate (GE2) is provided via the margin layer.

[0133] Figure 24 shows the energy band diagram (schematic diagram) in the A-A' section shown in Figure 23. 24(A) ensures the voltage between the source and drain is at the same potential (V D The case where =0V is shown in the figure. 24(B) has a positive potential (V) between the source and the drain. D This shows the case where (>0) is added.

[0134] Figures 25 and 26 show the energy band diagram (schematic diagram) between B and B' in Figure 23. Figure 25 shows the state when the gate voltage is 0V. Figure 26(A) shows the gate (GE1) Positive potential (V G A state in which >0) is applied, and carriers (electrons) are between the source and drain. This shows the ON state where ) flows. Also, Figure 26(B) shows a negative potential at the gate (GE1). (V G When <0) is applied, and the state is off (minority carriers do not flow) This indicates that the oxide semiconductor has a thickness of about 50 nm, and that the oxide semiconductor has been made highly pure. The donor concentration is 1 × 10 18 / cm 3 If the following conditions are met, the depletion layer will oxidize in the off state. It spreads throughout the entire semiconductor material. In other words, it can be considered a completely depleted state.

[0135] Figure 27 shows the relationship between the vacuum level, the work function (φM) of the metal, and the electron affinity (χ) of the oxide semiconductor. This indicates.

[0136] Metals are degenerate, and the Fermi level is located within the conduction band. On the other hand, conventional oxide semiconductors are It is of type n, and its Fermi level (E f ) is the true Fermi located in the center of the band gap. Level (E i It is located away from the conduction band and closer to the conduction band. Furthermore, in oxide semiconductors, it is contained It is known that some of the hydrogen produced becomes a donor, which is one of the factors that causes it to become N-type.

[0137] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. Furthermore, by purifying the material to the point where it contains as few impurities as possible other than the main components of the oxide semiconductor, This involves making it true (type i), or attempting to make it true. That is, by adding impurities. Instead of converting it to type i, it is purified by removing as many impurities as possible, such as hydrogen and water. It is characterized by being a type i (intrinsic semiconductor) or approaching it. By doing so, Hermi level (E f ) is the true Fermi level (E i It can be brought up to the same level as ).

[0138] Band gap (E) of oxide semiconductors g If the voltage is 3.15 eV, then the electron affinity (χ) is It is said to be 4.3 eV. The titanium (Ti) that makes up the source electrode and drain electrode. The function is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, metal-oxide semiconductor At the body interface, no Schottky-type barrier is formed for electrons.

[0139] In other words, when the work function of the metal (φM) and the electron affinity (χ) of the oxide semiconductor are equal, When a person makes contact, an energy band diagram (schematic diagram) like the one shown in Figure 24(A) is displayed.

[0140] In Figure 24(B), the black circles (●) represent electrons, and a positive voltage (V) is applied to the drain. D >0) is applied Furthermore, if no voltage is applied to the gate (V G The value (=0) is shown with a dashed line, and a positive voltage is applied to the gate. (V G The solid line shows the case when a positive voltage (V) is applied to the gate. G When >0) is applied In addition, when a positive potential is applied to the drain, electrons cross the barrier (h) and enter the oxide semiconductor. It is drawn in and flows towards the drain. In this case, the height of the barrier (h) is determined by the gate voltage and the drain. It changes depending on the rain voltage, but a positive voltage (V) is applied to the gate. G Apply >0) and positive drain When voltage is applied, the barrier height, i.e., the band, is the same as in Figure 24(A) when no voltage is applied. The barrier height (h) will be less than half of the gap (Eg). If no potential is applied, carriers will not move from the electrode to the oxide semiconductor due to the high potential barrier. This indicates an off state where no electrons are injected and no current flows. On the other hand, when a positive voltage is applied to the gate... This reduces the potential barrier, causing it to enter an ON state where current flows.

[0141] At this time, the electrons injected into the oxide semiconductor move through the oxide semiconductor as shown in Figure 26(A). It flows. Also, in Figure 26(B), when a negative potential is applied to the gate electrode (GE1) Since the minority carriers, such as holes, are practically zero, the current is a value very close to zero. Yes.

[0142] This process aims to achieve high purity by minimizing the inclusion of impurities other than the main components of oxide semiconductors. By making it intrinsic (type i) or substantially intrinsic, the interface characteristics with the gate insulating film are improved. This becomes apparent and needs to be considered separately from the bulk properties. Therefore, the gate insulating film is oxidized. A material capable of forming a good interface with a semiconductor is needed. For example, in the VHF to microwave band. An insulating film, or a superfine film, fabricated by a CVD method using high-density plasma generated at a power supply frequency. It is preferable to use an insulating film fabricated by the puttering method.

[0143] To improve the purity of oxide semiconductors while maintaining a good interface between the oxide semiconductor and the gate insulating film. As a result, the channel width W of the transistor is 1 × 10⁻⁶ 4 Channel length in μm Even with a 3μm element, the off-current at room temperature is 10 -13 A or less, Subthreshold The gate swing value (S value) is 0.1 V / dec. (gate insulating film thickness 100 nm) To be waited for.

[0144] In this way, the purity is increased so that impurities other than the main components of the oxide semiconductor are included as little as possible. This allows for better operation of the transistor.

[0145] The transistor of this embodiment has a highly purified oxide semiconductor layer. The body layer has a dense crystalline region composed of nanocrystals on its surface, and the crystalline region is of high purity from the surface layer. This prevents the re-intrusion of moisture into the oxide semiconductor layer and the desorption of oxygen, which can lead to n-type conversion. A pair of electrode layers are placed above and below a highly purified oxide semiconductor layer, separated by an insulating film. The 4-terminal transistor has a positive threshold voltage and its off-current is extremely small and suppressed. It possesses certain characteristics.

[0146] Furthermore, when the fourth electrode layer is used as the main gate electrode, the second electrode of the oxide semiconductor layer The second insulating layer is sandwiched between the region in contact with the layer and the region in contact with the third electrode layer of the oxide semiconductor layer. A channel is formed in the region that is in contact with and overlaps with the fourth electrode layer. The resulting region is also a crystalline region of the oxide semiconductor, and is approximately perpendicular to the surface of the oxide semiconductor layer. It has crystal grains oriented along the c-axis in a perpendicular direction. For example, In-Ga-Zn- When using O-based oxide semiconductor materials, the c-axis is the substrate plane (or the oxide semiconductor layer surface). By arranging nanocrystals so that they are perpendicular to the plane, the transistor can be made The direction of the current is in the b-axis direction (or a-axis direction) of In2Ga2ZnO7. Therefore Transistors that use the fourth electrode layer as the main gate electrode have high dynamic characteristics (on-response and It exhibits frequency characteristics (also called f-characteristics), and is used, for example, in drive circuits where high-speed operation is required. It is suitable for use with transistors.

[0147] Furthermore, when the first electrode layer is used as the main gate electrode, the second electrode of the oxide semiconductor layer The first insulating layer is sandwiched between the region in contact with the layer and the region in contact with the third electrode layer of the oxide semiconductor layer. A channel is formed in the region that is in contact with and overlaps with the first electrode layer. Furthermore, to remove impurities By doing so, an i-type or substantially i-type oxide semiconductor layer (high-purity oxide semiconductor layer) is created. The carrier concentration is suppressed in the conductive layer. Furthermore, the channel formation region of the oxide semiconductor layer is On the opposite side, there is a dense crystalline region composed of nanocrystals, so moisture from the surface This prevents n-type conversion due to re-entry or oxygen desorption. Therefore, the first electrode layer is the main gate electrode The transistors used as polar layers have extremely low off-current and excellent reliability, for example. Therefore, it is suitable for transistors used in pixel sections where reduction of leakage current is required.

[0148] As described above, by selecting the gate electrode to be used as the primary electrode, a crystalline region can be obtained on the surface. A pair of electrode layers are placed above and below the channel formation region of the oxide semiconductor layer, separated by an insulating film. The electrical characteristics of the transistor can be selected based on its terminal structure.

[0149] Furthermore, an insulating film is placed above and below the channel formation region of an oxide semiconductor layer having a crystalline region on its surface. Multiple transistors with a 4-terminal structure, each having a pair of electrode layers, are provided on the same substrate, primarily By selecting the gate electrode to use, multiple transistors formed on the same substrate can be processed in different ways. It can be operated with certain characteristics.

[0150] Furthermore, it has a drive circuit capable of high-speed operation and a pixel section with reduced power consumption on the same substrate. It is possible to fabricate semiconductor devices.

[0151] In addition, in a transistor according to one aspect of the present invention, the gate electrode mainly used is the first electrode. It does not need to be fixed to either the layer or the fourth electrode layer, and the operation status of the circuit, It can be adjusted as needed depending on the workload.

[0152] Furthermore, this embodiment can be freely combined with other embodiments.

[0153] (Embodiment 2) In this embodiment, a pair of electrodes are placed above and below the channel formation region of the oxide semiconductor layer via an insulating film. The inverter circuit of the drive circuit is constructed using two 4-terminal transistors that arrange the polar layers. An example of this will be explained below using Figure 3. The transistor shown in Figure 3(A) is an embodiment. These are identical to transistors 440A and 440B shown in Figure 1(E) of 1. The same parts are explained using the same symbols.

[0154] The drive circuit for driving the pixel portion is, for example, located around the pixel portion and includes an inverter circuit. It is constructed using capacitance, resistance, etc. One embodiment of the inverter circuit has two n-channel inverters Some are formed by combining transistors. For example, enhancement transistors. A combination of a depletion-type transistor and a EDMOS circuit (hereinafter referred to as an EDMOS circuit) (This refers to) and those formed by enhancement transistors (hereinafter referred to as EEMOS transistors) There is a road.

[0155] Figure 3(A) shows the cross-sectional structure of the inverter circuit of the drive circuit. The first transistor is 440A. The second transistor 440B can be formed in the same manner as in Embodiment 1, so a detailed explanation is not provided. Omitted. After forming the contact hole 408 in the second insulating layer 428, the fourth electric A polar layer 422a and a fourth electrode layer 422b are provided, and the second electrode is connected via a contact hole 408. The second wiring 410b connected to the pole layer 455c and the fourth electrode layer 422b are directly connected. This is preferable. Because the number of contact holes required for connection is small, electrical resistance can be reduced. Not only does this reduce the area occupied by the contact hole, but it also reduces the overall area occupied by the contact hole.

[0156] First wiring 410 connected to the second electrode layer 455a of the first transistor 440A 'a' is a power line to which a negative voltage VDL is applied (negative power line). This power line is at ground potential. It can also be used as a power line (grounding power line).

[0157] Furthermore, a third wiring that connects to the third electrode layer 455d of the second transistor 440B 410c is a power line to which a positive voltage VDH is applied (positive power line).

[0158] Furthermore, a top view of the inverter circuit of the drive circuit is shown in Figure 3(C). In Figure 3(C), the chain The cross-section obtained by cutting along line Z1-Z2 corresponds to Figure 3(A).

[0159] Furthermore, the equivalent circuit of the EDMOS circuit is shown in Figure 3(B). The circuit connections shown in Figure 3(B) are as follows: This corresponds to 3(A), and the first transistor 440A is an enhancement-type n-channel transistor The second transistor, a 440B, is a depletion-type n-channel transistor. This is an example of using "zista".

[0160] In this embodiment, the thresholds of the first transistor 440A and the second transistor 440B To control the value, insulating films are applied above and below the channel formation region of the highly purified oxide semiconductor layer. The first electrode and the fourth electrode, which are provided via a first transistor 440, are used. Specifically, the first transistor 440 To make A an enhancement type and the second transistor 440B a depletion type, A voltage is applied to each of the first and fourth electrodes.

[0161] In Figures 3(A) and 3(C), the second wiring 410b is formed in the second insulating layer 428. This example shows a direct connection to the fourth electrode layer 422b via the formed contact hole 408. However, it is not particularly limited, and a connecting electrode is provided separately to the second wiring 410b and the fourth electrode layer 422 b may be electrically connected. Also, in this embodiment, the second transistor 440B We have explained the case in which the fourth electrode layer is used as the main gate electrode, but the second transistor The first electrode layer of ZISTA 440B may be used as the main gate electrode. In that case, There is no need to provide contact holes 408 in the second insulating layer 428, and the first insulating layer 402 A contact hole is formed to connect the second electrode layer 455c and the first electrode layer 421b.

[0162] As described above, a pair of electrode layers are placed above and below the channel formation region of the oxide semiconductor layer, separated by an insulating film. An inverter circuit can be constructed using two 4-terminal transistors. Controlling the transistor threshold using the first and fourth electrode layers of a Lugate structure. So, without differentiating between oxide semiconductor films, enhancement-type transistors and depletion-type transistors were created. Since transistors can be fabricated on the same substrate, the manufacturing process is simplified.

[0163] Furthermore, a transistor according to one aspect of the present invention, in which the fourth electrode layer is used as the main gate electrode, is also applicable. The inverter circuit used exhibits excellent dynamic characteristics.

[0164] Furthermore, this embodiment can be freely combined with other embodiments.

[0165] (Embodiment 3) In this embodiment, a pair of electrodes are placed above and below the channel formation region of the oxide semiconductor layer via an insulating film. A pulse output circuit was fabricated using two 4-terminal transistors with polar layers, and further Figures 4 and 5 show an example of configuring a shift register by connecting multiple such pulse output circuits. I will use it to explain.

[0166] A transistor is defined as having at least three terminals, including a gate, a drain, and a source. It is an element having a channel region between the drain region and the source region, and the drain Current can be passed through the input region, channel region, and source region. The difference between the drain and the source depends on the transistor's structure and operating conditions, so which one is the source? It is difficult to determine whether it is a source or a drain. Therefore, source and drain and The area that functions in this way is sometimes not called the source or drain. In that case, for example, In some cases, these are referred to as the first terminal and the second terminal, respectively.

[0167] Figure 4(A) shows the configuration of the shift register. The shift register is a first pulse output circuit 1 It has pulse output circuits 10_N (where N is a natural number greater than or equal to 3) from 0_1 to the Nth.

[0168] Furthermore, the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are connected to the first wiring 11, connected to the second wiring 12, the third wiring 13, and the fourth wiring 14, and the first wiring 1 The first clock signal CK1 is transmitted from wire 1, and the second clock signal CK2 is transmitted from wire 12. The third clock signal CK3 is transmitted from the third wire 13, and the fourth clock signal is transmitted from the fourth wire 14. Unit CK4 will be supplied.

[0169] The clock signal (CK) is raised to a high level (H signal, high power supply potential level) at regular intervals. This is a signal that alternates between L level (also called L signal or low power supply potential level). Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially 1 / 4 cycles. There is a delay of a certain period. In this embodiment, the first clock signal (CK1) to the fourth clock The signal (CK4) is used to control the drive of the pulse output circuit, etc. Depending on the input drive circuit, it may also be GCK or SCK, but here we will use CK. Then, explain.

[0170] Each of the first pulse output circuits 10_1 to the Nth pulse output circuits 10_N has a first input terminal Child 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal It has a child 25, a first output terminal 26, and a second output terminal 27 (see Figure 4(B)). Although not shown in the diagram, it is also connected to power lines 51, 52, and 53. .

[0171] The first input terminal 21, the second input terminal 22, and the third input terminal 23 of the pulse output circuit are It is electrically connected to one of the first wiring 11 to the fourth wiring 14. For example, Figure 4 ( In A), the first pulse output circuit 10_1 has a first input terminal 21 connected to the first wiring 11 The second input terminal 22 is electrically connected to the second wiring 12, and the third Input terminal 23 is electrically connected to the third wiring 13. Also, the second pulse output circuit 10_2 is such that the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. They are directly connected.

[0172] Also, in the first pulse output circuit 10_1, the start pulse SP1 from the fifth wiring 15 ( The first start pulse is input. Also, the nth pulse output circuit 10_n for the second stage and beyond. (where n is a natural number between 2 and N) the signal from the pulse output circuit one stage prior (previous stage signal) The input is OUT(n-1) (where n is a natural number greater than or equal to 2).

[0173] Furthermore, in the first pulse output circuit 10_1, from the second-stage third pulse output circuit 10_3 The following signal is input. Similarly, in the nth pulse output circuit 10_n from the second stage onward, The signal from the (n+2)th pulse output circuit 10_(n+2) of the stage (the subsequent stage signal OUT(n+ 2) is input. Therefore, from the pulse output circuit of each stage, the subsequent stage and / or two The first output signal (OUT(1)(SR)~OU) to be input to the preceding pulse output circuit. T(N)(SR)), a second output signal (OUT(1)~) electrically connected to another wire, etc. OUT(N)) is output.

[0174] That is, in the first pulse output circuit 10_1, the first cross is connected to the first input terminal 21. The clock signal CK1 is input, and the second clock signal CK2 is input to the second input terminal 22. The third clock signal CK3 is input to the third input terminal 23, and the fourth input terminal 24 is input to the station A pulse is input, and the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first The first output signal OUT(1)(SR) is output from output terminal 26, and the second output terminal 27 This indicates that the second output signal OUT(1) is being output.

[0175] Furthermore, as shown in Figure 4(A), the last two stages of the shift register (10_N-1, and Although the subsequent signal OUT(n+2) is not input to 10_N), one example is that, separately, The second start pulse SP2 is from wire 16 of 6, and the third start pulse is from wire 17 of 7. The configuration should involve inputting SP3 to each of the respective values. Alternatively, it can be generated internally within a separate shift register. It may be a generated signal. For example, the (N+1)th that does not contribute to the pulse output to the pixel area. The pulse output circuit 10_(N+1) and the (N+2) pulse output circuit 10_(N+2) A dummy stage is provided (also called a dummy stage), and a second start pulse (SP2) and a third start pulse are generated from this dummy stage. The system may also be configured to generate a signal corresponding to the start pulse (SP3).

[0176] Next, the configuration of a pulse output circuit according to one aspect of the present invention will be explained using Figure 4(C).

[0177] The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are connected to the power supply line 51 to the power supply. It is connected to line 53. Power line 51 is the first high power supply potential VDD, and power line 52 is the second The high power supply potential VCC is supplied by power line 53, and the low power supply potential VSS is supplied by power line 51. The relative magnitudes of the power supply potentials of power line 53 are as follows: the first high power supply potential VDD is equal to the second high power supply potential VC. It is equal to C or higher than the second high power supply potential VCC, and the second high power supply potential VCC is low It is assumed that the potential is higher than the power supply potential VSS. Also, the potential VCC of power line 52 is equal to that of power line 51 The potential may be equal to VDD, but lowering it below VDD will affect the operation. Without doing so, the potential applied to the gate electrode of the transistor can be kept low, This reduces the threshold shift of the DISTA and suppresses degradation.

[0178] The first clock signal (CK1) to the fourth clock signal (CK4) are transmitted at regular intervals. This is a signal that alternates between high and low levels, where VDD is at the high level and V is at the low level. Let's assume it's SS.

[0179] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is a first pulse It has transistors 31 to the 11th transistor 41 (see Figure 4(C)). In this configuration, two types of transistors are fabricated on the same substrate to form a pulse output circuit. Oh, the first pulse output circuit 10_1~ of the shift register illustrated in this embodiment Since the pulse output circuit 10_N of N has the same configuration, here the first pulse output The configuration and operation of circuit 10_1 will be explained.

[0180] The first pulse output circuit 10_1 consists of the first transistor 31 to the eleventh transistor 41. It has the following: The first transistor 31 to the eleventh transistor 41 are made of high-purity material. This is an n-channel transistor in which a channel is formed in an oxide semiconductor layer.

[0181] Furthermore, the highly purified oxide semiconductor layer according to one aspect of the present invention is composed of nanocrystals on its surface. It has a dense crystalline region, which prevents the re-intrusion of moisture from the surface and the desorption of oxygen, thus preventing N-type conversion. A pair of electrode layers are placed above and below such a highly purified oxide semiconductor layer, separated by an insulating film. The 4-terminal transistor has a positive threshold voltage and its off-current is suppressed to an extremely low level. It possesses certain characteristics.

[0182] In particular, the surface where the crystalline region is formed is considered the back channel side, and the substrate side is connected via the first insulating layer. A transistor that uses the first electrode layer positioned at the top as the main gate electrode has an extremely low It has off-current and excellent reliability. In this embodiment, the first electrode layer is the main gate current The transistors used as electrodes are the second transistor 32 and the fifth transistor 35. It is used for this purpose.

[0183] Furthermore, the pulse output circuit of this embodiment, and a configuration formed by connecting multiple such pulse output circuits. In a shift register, an external signal is input directly to the gate electrode of a transistor. A transistor that uses the first electrode layer as the main gate electrode is also preferable. For example, In the case of pulse output circuit 10_1, the fourth input terminal to which the start pulse is input from an external source. The first transistor 31 and the fifth transistor 35, which are connected to child 24, are examples of this. It can be listed that transistors that use the first electrode layer as the main gate electrode are gate The voltage resistance between the source and the gate, or between the gate and the drain, is high, and abnormal inputs such as static electricity are present. By applying force, it is possible to suppress the occurrence of failures such as fluctuations in the threshold values ​​of transistors that make up the circuit.

[0184] Furthermore, the surface on which the crystalline region is formed is used as the channel formation region, and the substrate is connected via a second insulating layer. A transistor that uses a fourth electrode layer, positioned on the opposite side, as the primary gate electrode, is high It has dynamic characteristics. In this embodiment, the fourth electrode layer is used as the main gate electrode. The transistors are the third transistor 33, the sixth transistor 36, and the tenth transistor. It is used for transistors 40 and 11, transistor 41.

[0185] Furthermore, a transistor that uses the fourth electrode layer as the main gate electrode, and the first electrode layer The transistor used as the main gate electrode is manufactured according to the method described in Embodiment 1. Since it can be manufactured, a detailed explanation is omitted in this embodiment.

[0186] Furthermore, the first transistor 31, the fourth transistor 34, the seventh transistor 37, and so on. The ninth transistor 39 is a transistor that uses the first electrode layer as the main gate electrode, for example. Which is better: a DISTRA, or a transistor that uses a fourth electrode layer as the primary gate electrode? Although it may be used, in this embodiment, the first electrode layer is used as the main gate electrode. ZISTA shall be applied.

[0187] In Figure 4(C), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is It is electrically connected to input terminal 24 of 4. The second transistor 32 has the first terminal electrically connected. It is electrically connected to the source line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. It is connected, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has its first terminal electrically connected to the first input terminal 21, and the second The terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is the first The terminal is electrically connected to the power line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power line 53, and its second terminal The terminals are connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. Electrically connected, the gate electrode is electrically connected to the fourth input terminal 24. The sixth The transistor 36 has its first terminal electrically connected to the power line 52, and its second terminal connected to the second transistor The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. The gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 37 The first terminal is electrically connected to the power line 52, and the second terminal is connected to the eighth transistor 38. It is electrically connected to terminal 2, and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal connected to the gate electrode of the second transistor 32 and the fourth The gate electrode of transistor 34 is electrically connected, and the gate electrode is connected to the second input terminal 22 It is electrically connected to the first transistor 39. The first terminal of the ninth transistor 39 is connected to the first transistor The second terminal of 31 and the second terminal of the second transistor 32 are electrically connected, and the second terminal is The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are electrically charged. The terminal is connected to the power line 52. The tenth transistor The terminal 40 has its first terminal electrically connected to the first input terminal 21, and its second terminal is connected to the second output terminal. It is electrically connected to child 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. It is connected. The 11th transistor 41 has its first terminal electrically connected to the power line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the second transistor The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. .

[0188] Note that in Figure 4(C), the gate electrode of the third transistor 33 and the tenth transistor The connection point between the gate electrode of transistor 40 and the second terminal of transistor 39 (number 9) is designated as node A. Also, the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 , the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the eighth transistor The connection point between the first terminal of transistor 38 and the gate electrode of transistor 41 (number 11) is not Let this be node B. Furthermore, in order to maintain the potential of node B, one electrode is electrically connected to node B. A separate capacitive element may be provided. Specifically, one electrode of the capacitive element may be connected to node B. One end can be connected electrically, and the other end electrically connected to the power line 53.

[0189] Next, refer to Figures 5(B), 6-8 for the operation of the pulse output circuit shown in Figure 5(A). Let me explain. Specifically, in the timing chart in Figure 5(B), the first period 61 The explanation will be divided into the second period 62, the third period 63, the fourth period 64, and the fifth period 65. In Figures 6 and 7, the transistors that are ON (conducting) during each period are shown by solid lines. A wavy line indicates a transistor in the OFF state.

[0190] Here, we will explain the output of the first pulse output circuit 10_1. The path 10_1 is the first distribution to which the first input terminal 21 supplies the first clock signal (CK1). The second input terminal 22 is electrically connected to line 11 and supplies the second clock signal (CK2). The second wiring 12 is electrically connected, and the third input terminal 23 receives the third clock signal (C It is electrically connected to a third wiring 13 that supplies K3).

[0191] In the following explanation, the first transistor 31 to the eleventh transistor 41 are N Assuming a channel-type transistor, the gate-source voltage (Vgs) is equal to the threshold voltage (Vt It is assumed that conduction occurs when the value exceeds h).

[0192] Furthermore, for the sake of simplicity in this explanation, we will assume VSS=0, but this is not the only option. Note that VD The difference between D and VCC, and the difference between VCC and VSS (if VDD > VCC) are... It is assumed that the voltage will be greater than the threshold voltage of the transistor, i.e., the transistor will be in the ON state. The circuit shall be made conductive. Furthermore, the potential of power line 52 shall be lower than the potential of power line 51. As a result, the second transistor 32, the fourth transistor 34, and the ninth transistor 3 9. The potential applied to the gate electrode of the 11th transistor 41 is kept low, and the pulse output The second transistor 32, the fourth transistor 34, and the ninth transistor 39 of the power circuit, This reduces the threshold shift of the 11th transistor 41 and suppresses degradation. ru.

[0193] During the first period 61, the first start pulse (SP1) becomes H level, and the first S The fourth input terminal 2 of the first pulse output circuit 10_1 to which the tart pulse (SP1) is input. The first transistor 31 and the fifth transistor 35, which are electrically connected to 4, enter a conductive state. Yes. Also, since the third clock signal (CK3) is at a high level, the seventh transistor 3 7 is also turned on. In addition, the gate of the ninth transistor 39 is marked with the second high power supply potential VCC. This is added, and the ninth transistor 39 is also turned on (see Figure 6(A)).

[0194] At this time, the first transistor 31 and the ninth transistor 39 are on, so the node The potential at A rises. Also, because the fifth transistor 35 is on, the potential at node B is It descends.

[0195] Furthermore, the potential of the second terminal of the first transistor 31 is the same as the potential of the second terminal of the first transistor 31 This serves as the source, and the threshold voltage of the first transistor 31 is determined from the potential of the first power line 51. Since it is the value obtained by subtracting VDD-Vth31 (Vth31 is the first transistor 31) The threshold voltage (Vth39) of the ninth transistor 39 and Vt In h31, if (VDD-Vth31) is greater than or equal to (VCC-Vth39), then no. The potential at node A becomes VCC-Vth39, and the 9th transistor 39 turns off, and node A It remains in a floating state while maintaining the potential (VCC-Vth39). Also, (VDD-Vth3 1) If (VCC - Vth39) is less than (VCC - Vth39), the 9th transistor 39 will turn off. Node A rises to the potential (VDD-Vth31).

[0196] In this embodiment, the first transistor 31 to the eleventh transistor 41 are all the same. Because it has a threshold voltage Vth0, the potential of node A becomes (VCC-Vth0). The ninth transistor 39 turns off, and node A maintains its potential (VCC-Vth0). It enters a state of floating.

[0197] Here, in the third transistor 33, the potential of the gate electrode is (VCC-Vth0) The voltage between the gate and source of the third transistor 33 exceeds its threshold. That is, VCC-Vth0>Vth33 (Vth33 is the third transistor 3 The threshold voltage is 3, which in this embodiment is Vth0, therefore the third transistor The TA33 is turned on.

[0198] During the second period 62, the first input terminal 21 of the first pulse output circuit 10_1 is first The clock signal (CK1) switches from low level to high level. The third transient has already occurred. Because sta33 is on, a current is generated between the source and drain and appears at output terminal 26. The potential of the output signal (OUT(1)(SR)), that is, the second potential of the third transistor 33. The potential of the electrode (in this case, the source electrode) begins to rise. The gate of the third transistor 33 and Capacitive coupling exists between the sources due to parasitic capacitance and channel capacitance, and the potential of the output terminal 26 As the voltage rises, the potential of the terminal terminal of the third transistor 33, which is in a floating state, increases. (Bootstrap operation). Ultimately, the gate electrode of the third transistor 33 The voltage level becomes higher than (VDD + Vth33), and the potential of output terminal 26 becomes equal to VDD. (See Figures 5(B) and 6(B)).

[0199] Also, at this time, the fourth input terminal 24 of the first pulse output circuit 10_1 is the first start Because the pulse (SP1) is at an H level, the fifth transistor 35 turns on and the node B is maintained at an L level. Therefore, the potential of output terminal 26 changes from an L level to an H level. When starting up, malfunctions caused by capacitive coupling between output terminal 26 and node B can be suppressed. ru.

[0200] Next, in the first half of the third period 63, the first start pulse (SP1) was at the L level and Then the first transistor 31 and the fifth transistor 35 turn off. Also, the second period 6 Following step 2, the first clock signal (CK1) maintains a high level, and the potential of node A also changes. To prevent this from happening, a high-level signal is supplied to the first electrode of the third transistor 33 (Figure See 6(C). In addition, during the first half of the third period 63, each transistor connected to node B When it turns off, node B becomes floating, but the potential of output terminal 26 also does not change, The impact of the capacitive coupling between B and output terminal 26 is almost negligible.

[0201] Furthermore, as shown in Figure 5(A), the ninth gate to which the second high power supply potential VCC is applied By installing the Rangista 39, the following occurs before and after the bootstrap operation: It has advantages like these.

[0202] If there is no ninth transistor 39 to which the second high power supply potential VCC is applied to the gate electrode, When the potential of node A rises due to the bootstrap operation, the first transistor 31 The potential of the two source terminals rises and becomes greater than the first high power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, to the power line 51 side. Therefore, in the first transistor 31, between the gate and source, and between the gate and drain, During this time, a large bias voltage is applied, causing significant stress on the transient. This could be a factor in the deterioration of the stamina.

[0203] Therefore, a ninth transistor 39 is provided to which a second high power supply potential VCC is applied to the gate electrode. By leaving it as is, although the potential of node A rises due to the bootstrap operation, This prevents an increase in the potential of the second terminal of transistor 31. By providing the ninth transistor 39, the gate and socket of the first transistor 31 are connected. The value of the negative bias voltage applied between the two can be reduced. Therefore, this implementation By using this circuit configuration, a mark is made between the gate and source of the first transistor 31. The applied negative bias voltage can also be reduced, thus reducing stress on the first transistor 31 This can suppress deterioration.

[0204] Furthermore, the location where the ninth transistor 39 is installed is the second transistor 31 The terminal is connected to the gate of the third transistor 33 via the first and second terminals. Any configuration that is set up in this manner is acceptable. Note that the pulse output circuit in this embodiment may be equipped with multiple pulse output circuits. In the case of a sub-register, the signal line drive circuit requires higher dynamic characteristics than the scan line drive circuit. The ninth transistor, 39, can be omitted, which has the advantage of reducing the number of transistors.

[0205] In the latter half of the third period 63, the third clock signal (CK3) switches to the H level. Then, the seventh transistor 37 turns on. Also, following the first half of the third period 63, the second The clock signal (CK2) remains at a high level, and the eighth transistor 38 is on. The potential at node B rises to VCC.

[0206] Because the potential of node B increased, the second transistor 32 and the fourth transistor 34 and The 11th transistor 41 turns on, and the potential of the output terminal 27 (OUT(1)) becomes L It becomes a bell.

[0207] Furthermore, in the latter half of the third period 63, the second transistor 32 turns on, and the ninth transistor Since an L-level signal is supplied to the first terminal of transistor 39, the ninth transistor 39 The device turns on, and the potential at node A drops.

[0208] Furthermore, when the fourth transistor 34 turns on, the potential of the output terminal 26 decreases. (See Figure 6(D)).

[0209] In the first half of the fourth period 64, the second clock signal (CK2) changes from a high level to a low level. Because it switches to this state, the 8th transistor 38 turns off. However, the 5th input terminal 25 ( By keeping OUT(3)) at a high level, the sixth transistor 36 is in the ON state. Therefore, node B will hold VCC. (See Figure 7(A)).

[0210] Subsequently, in the latter half of the fourth period 64, the fifth input terminal 25 of the first pulse output circuit 10_1 (OUT(3)) becomes low, and the sixth transistor 36 turns off (see Figure 7(B)). (Illuminate). At this time, node B changes from a state where it maintains the VCC level to a floating state. Furthermore, the second transistor 32, the fourth transistor 34, and the eleventh transistor 4 The state remains ON. However, as shown in Figure 5(B), the potential of node B is V The signal level will drop from the CC level due to factors such as the transistor's off-current.

[0211] Subsequently, the circuit repeats a periodic operation. This period is designated as the fifth period, 65. (Figure 7(C) ), (see (D)). A fifth period 65 during a period (second clock signal (CK2) and third When both clock signals (CK3) are at a high level, the seventh transistor 3 Transistors 7 and 8 (38) are turned on, and a VCC-level signal is periodically supplied to node B. (See Figure 7(D)).

[0212] Thus, the configuration is such that a VCC-level signal is periodically supplied to node B during the fifth period 65. This can suppress malfunctions in the pulse output circuit. Also, the seventh transistor By periodically switching transistor 37 and the eighth transistor 38 on or off, This makes it possible to reduce the threshold shift of the transistor.

[0213] Furthermore, during the fifth period 65, a VCC level signal is received at node B from the second power line 52. If the potential of node B drops while power is not supplied, a capacitive element should be installed at node B beforehand. A configuration that mitigates the decrease in potential at node B may also be used.

[0214] Furthermore, the connection between the second input terminal 22 and the gate electrode of the eighth transistor 38, and the third input By swapping the connections between terminal 23 and the gate electrode of the 7th transistor 37, the 8th transistor The clock signal that was supplied to the gate electrode of transistor 38 is now supplied to the gate electrode of the seventh transistor 37. The clock signal that was supplied to the pole and to the gate electrode of the 7th transistor 37 is now supplied to the 8th The same effect is achieved when supplied to the gate electrode of transistor 38.

[0215] In the pulse output circuit shown in Figure 5(A), the second input terminal 22 and the third input terminal 23 By controlling the potential, both the seventh transistor 37 and the eighth transistor 38 are turned ON. From this state, the seventh transistor 37 is off and the eighth transistor 38 is on. Subsequently, when both the seventh transistor 37 and the eighth transistor 38 are turned off, The potential of the gate electrode of the 7th transistor 37 decreases, and the gate electrode of the 8th transistor 38 decreases. The decrease in the potential of the electrode results in a decrease in the potential of node B occurring twice.

[0216] On the other hand, in the pulse output circuit shown in Figure 5(A), as shown in Figure 5(B), the seventh to When transistors 37 and 8 and 38 are both ON, the 7th transistor 37 is ON, and after passing through the state where the 8th transistor 38 is OFF, the 7th transistor 3 When transistors 7 and 8 38 are both turned off, the gate of transistor 8 38 A decrease in the potential of the electrode causes a decrease in the potential of node B only once, and the number of times the potential decreases The number of steps can be reduced to one.

[0217] In other words, the gate electrode of the seventh transistor 37 receives a clock signal from the third input terminal 23. The clock signal is supplied to the gate electrode of the eighth transistor 38 from the second input terminal 22. Supplying this reduces the potential fluctuations at node B, which in turn reduces noise, thus being preferable. It is suitable.

[0218] In this way, the period during which the potential of the first output terminal 26 and the second output terminal 27 is maintained at the L level In between, by configuring the system so that a VCC-level signal is periodically supplied to node B, This can suppress malfunctions in the output circuit.

[0219] Node B of the pulse output circuit described in this embodiment is VCC in the latter half of the fourth period 64. The bell transitions from a state of being held to a floating state. The potential of node B in the floating state is the fifth transient. There is a risk that the VCC level may drop due to the off-current of ST35, etc. However, in this implementation The fifth transistor 35 of the pulse output circuit in this configuration has an extremely low off-current. Because a transistor is used that uses the first electrode layer as the main gate electrode, floating The potential of node B in state is well maintained, with little drop from the VCC level. As a result, half Malfunctions in the conductive device are suppressed, improving reliability.

[0220] Furthermore, in order to suppress the off-current of the transistor, the gate electrode is made into a double-gate structure, Because it does not require a multi-gate structure such as a pull-gate structure, the transistor can be miniaturized. It is possible. Furthermore, the capacitive element required to maintain the potential of node B is either unnecessary or can be miniaturized. A pulse output circuit constructed using such miniaturized elements, or a miniaturized... By using a shift register configured with a pulse output circuit, a semiconductor device can be used. This will allow for overall miniaturization.

[0221] Furthermore, transistors that use the first electrode layer as the main gate electrode have extremely low off-current. Not only is it suppressed to a low level, but it also has a positive threshold voltage. Pulse output of this embodiment In the circuit, the second transistor 32 uses the first electrode layer as the main gate electrode. Because a zista is used, when raising the potential of node A through bootstrap operation, loss It can ascend quickly with minimal loss. As a result, malfunctions in semiconductor devices are suppressed, and reliability is improved. To rise.

[0222] Furthermore, in the pulse output circuit of this embodiment, the third transistor 33 and the sixth transistor Transistor 36, the 10th transistor 40, and the 11th transistor 41 are made of high-purity material. A fourth electrode layer using the crystalline region of the oxide semiconductor layer is used as the main gate electrode. A transistor is applied. A transistor that uses the fourth electrode layer as the main gate electrode is Because it has excellent f-characteristics and high field-effect mobility, the third transistor 33 and the sixth transistor The switches of transistor 36, the 10th transistor 40, and the 11th transistor 41 This allows for faster switching operations and enables miniaturization of the transistor.

[0223] A pulse output circuit configured using such high-speed elements, or a high-speed By using a shift register configured with a pulse output circuit, the entire semiconductor device This will enable faster processing.

[0224] Furthermore, the shift register shown in this embodiment, as shown in Figure 8(A), is the mth pulse The pulse output from the output circuit and the pulse output from the (m+1)th pulse output circuit It uses a drive method that overlaps by half (1 / 4 cycle). This is different from conventional shift registers. The pulse output from the mth pulse output circuit and the (m+1)th pulse output circuit Compared to a driving method where the output pulses do not overlap (see Figure 8(B)), this method charges the wiring. The time can be doubled. In this way, the pulse output from the mth pulse output circuit The pulses output from the (m+1) pulse output circuit overlap by half (1 / 4 period). By using this drive method, a large load can be applied and it can operate at a high frequency. It is possible to provide a pulse output circuit that can significantly change the operating conditions of the pulse output circuit. It is possible.

[0225] Note that the shift register and pulse output circuit shown in this embodiment are not included in other embodiments described herein. This can be implemented in combination with the configuration of the shift register and pulse output circuit shown in the implementation form. It is possible. Furthermore, the invention of this embodiment can also be applied to semiconductor devices. A semiconductor device is a device that functions by utilizing the properties of semiconductors.

[0226] (Embodiment 4) In this embodiment, above and below the channel formation region of the oxide semiconductor layer described in Embodiment 3 A Shift was fabricated using a 4-terminal transistor with a pair of electrode layers separated by an insulating film. A transistor with a highly purified oxide semiconductor layer is used as a resistor. This is an example of configuring a drive circuit for an active-matrix display device by combining various circuits. I will explain this using a block diagram. First, I will give an overview of the active matrix display device. Then, the signal line driving circuit and scan line that the display device has using a shift register will be explained, and then the signal line driving circuit and scan line Let's explain the drive circuit.

[0227] An example of a block diagram of an active-matrix display device is shown in Figure 9(A). On the plate 5300 are a pixel section 5301, a first scan line drive circuit 5302, and a second scan line drive It has a circuit 5303 and a signal line driving circuit 5304. The pixel section 5301 has multiple signal lines. Multiple scan lines are arranged extending from the signal line drive circuit 5304, and multiple scan lines are driven by the first scan line drive circuit 5 302, and the second scan line drive circuit 5303 are arranged as extensions. In the regions where the signal lines intersect, pixels, each containing a display element, are arranged in a matrix. Furthermore, the substrate 5300 of the display device is FPC (Flexible Printed Circuit). The timing control circuit 5305 (controller, control IC) is connected via a connection part such as cuit. It is connected to (also known as)

[0228] The transistors arranged in the pixel section 5301 are the transistors of one embodiment of the present invention described in Embodiment 1. A transistor can be applied. The transistor used in the pixel section 5301 is connected via the first insulating layer. A transistor that uses a first electrode layer located on the substrate side as the main gate electrode is particularly preferred. It seems so. Transistors that use the first electrode layer as the main gate electrode have a low off-current. Therefore, it not only increases the contrast of the displayed image, but also reduces the power consumption of the display device. .

[0229] Furthermore, since the transistor described in Embodiment 1 is an n-channel type transistor, Of the drive circuits, a portion of the drive circuit that can be constructed with n-channel transistors is the transistor of the pixel section. It is formed on the same substrate as the zista.

[0230] Figure 9(A) shows the first scan line drive circuit 5302, the second scan line drive circuit 5303, and the signal The line drive circuit 5304 is formed on the same substrate 5300 as the pixel section 5301. Therefore, Since the number of components such as drive circuits installed outside the display device is reduced, costs can be reduced. It is possible. Also, if a drive circuit is provided outside the circuit board 5300, it becomes necessary to extend the wiring. The number of connections between wires increases. If a drive circuit is provided on the same board 5300, the number of connections between those wires increases. The number of successors can be reduced, leading to improved reliability or yield.

[0231] The timing control circuit 5305 is, for example, related to the first scan line drive circuit 5302. The first scan line drive circuit start signal (GSP1), the scan line drive circuit clock signal (GCK1) is supplied. The timing control circuit 5305 also supplies the second scan line drive circuit For example, for 5303, the start signal (GSP2) for the second scan line drive circuit (start) It supplies the clock signal (GCK2) for the scan line drive circuit (also called a pulse). The drive circuit 5304 receives a start signal (SSP) for the signal line drive circuit and a crossover signal for the signal line drive circuit. SCK signal, video signal data (DATA) (also simply called video signal), A clock signal (LAT) shall be supplied. Each clock signal shall consist of multiple signals with different periods. It can be a clock signal, or it can be supplied along with an inverted clock signal (CKB). It may also be a first scan line drive circuit 5302 and a second scan line drive circuit 53 It is possible to omit either 03 or 03.

[0232] In Figure 9(B), a circuit with a relatively low drive frequency (for example, the first scan line drive circuit 5302) is shown. The second scan line drive circuit (5303) is formed on the same substrate (5300) as the pixel section (5301), and the drive is performed. A configuration in which a signal line driving circuit 5304 with a relatively high frequency is formed on a separate substrate from the pixel section 5301. This shows the characteristics. For example, using a transistor made of a single crystal semiconductor, the driving frequency The signal line drive circuit 5304, which has a relatively high frequency, can also be formed on a separate board. Therefore, This can lead to larger display devices, reduced processing steps, lower costs, or improved yield. can.

[0233] In this embodiment, the signal line drive circuit 5304, which has a relatively high drive frequency, is used in the pixel section 53 It shall be formed on the same substrate 5300 as 01. Furthermore, a drive circuit shall be provided on the substrate 5300. This reduces the number of connections between wires, improving reliability or yield. It is possible.

[0234] Next, we will discuss an example of the configuration and operation of a signal line drive circuit composed of n-channel transistors. This will be explained using Figures 10(A) and 10(B).

[0235] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. Switching circuit 5602 is a switching circuit 5602_1~5602_N (where N is natural). It has multiple circuits, each of which is called a number. Switching circuits 5602_1 to 5602_N are, , multiple transistors called transistors 5603_1 to 5603_k (where k is a natural number) It has. In this embodiment, transistors 5603_1 to 5603_k have n channels This section describes a configuration that applies a type 1 transistor.

[0236] Regarding the connection relationships of the signal line drive circuit, Figure 10 shows the switching circuit 5602_1 as an example. Let's explain using A). The first terminals of transistors 5603_1 to 5603_k are, respectively, Wiring 5604_1~5604_k is connected. Transistor 5603_1~5603_ The second terminal of transistor k is connected to signal lines S1 to Sk, respectively. Transistors 5603_1 to 5 The gate of 603_k is connected to wiring 5605_1.

[0237] The shift register 5601 sequentially supplies high levels (high signals) to the wiring 5605_1 to 5605_N. It outputs a signal at a high power supply potential level, also known as the switching circuit 5602_1~56 It has the function of sequentially selecting 02_N. Note that the shift register 5601 is in the embodiment Since it can be made using the method described in section 3, a detailed explanation will be omitted here.

[0238] Switching circuit 5602_1 consists of wiring 5604_1~5604_k and signal lines S1~Sk A function to control the conductivity state (conduction between the first terminal and the second terminal), i.e., wiring 5604_ It has a function to control whether or not to supply potentials between 1 and 5604k to signal lines S1 and Sk. Thus, the switching circuit 5602_1 functions as a selector. Rangings 5603_1 to 5603_k are connected to wiring 5604_1 to 5604_k respectively. A function to control the conductivity state with lines S1~Sk, i.e., the electrical conductivity of wiring 5604_1~5604_k It has the function of supplying power to signal lines S1~Sk. Thus, transistor 5603_1 Each of the ~5603_k units functions as a switch.

[0239] In this embodiment, the transistor used in the switching circuit 5602 is made highly pure. The crystalline region of the oxide semiconductor layer is used as the channel formation region, and the fourth electrode layer is used as the main gate. A transistor is used as an electrode. The fourth electrode layer is used as the main gate electrode. Transistors have excellent dynamic characteristics and fast switching operation. Therefore, they are suitable for high-resolution displays with a large number of pixels. It can handle the high-speed writing required by next-generation display devices. A transistor using a semiconductor layer as the channel formation region is manufactured by the method described in Embodiment 1. Since it can be manufactured, a detailed explanation will be omitted here.

[0240] Note that wiring 5604_1 to 5604_k each contain video signal data (DATA). The input is video signal data (DATA), which is image information or analog corresponding to the image signal. It is often a G signal.

[0241] Next, regarding the operation of the signal line drive circuit in Figure 10(A), see the timing chart in Figure 10(B). Refer to Figure 10(B) for explanation. Figure 10(B) shows signals Sout_1 to Sout_N, and signals An example of Vdata_1 to Vdata_k is shown. Signals Sout_1 to Sout_N are each The following is an example of the output signals of the shift register 5601, with signals Vdata_1 to Vdata _k represents an example of a signal input to wiring 5604_1~5604_k. One operating period of the signal line drive circuit corresponds to one gate selection period in the display device. The selection period is divided into, for example, periods T1 to TN. Periods T1 to TN are each , a period for writing video signal data (DATA) to pixels belonging to the selected row be.

[0242] Note that the signal waveform distortions, etc., of each configuration shown in the drawings, etc. of this embodiment are for clarity. The figures may be exaggerated for aesthetic reasons. Therefore, they are not necessarily limited to that scale. It should be noted that...

[0243] During periods T1 to TN, the shift register 5601 receives a high-level signal via wiring 560 Outputs are sent sequentially from 5_1 to 5605_N. For example, during period T1, shift register 5 601 outputs a high-level signal to wire 5605_1. Then transistor 56 Since 03_1~5603_k will be turned on, connect the wiring 5604_1~5604_k and the signal wire S1 to Sk become conductive. At this time, Da is connected to wiring 5604_1 to 5604_k. ta(S1)~Data(Sk) are input. Data(S1)~Data(Sk) are Each of the pixels belonging to the selected row is accessed via transistors 5603_1 to 5603_k. Of these, the pixels from the 1st to the kth column are written. In this way, during the period T1 to TN, the selected Video signal data (DATA) is written sequentially to the pixels belonging to the selected row, in k columns at a time. It can be done.

[0244] As described above, video signal data (DATA) is written to pixels in multiple columns. This allows for a reduction in the number of video signal data (DATA) or the number of wires. Therefore, the number of connections to external circuits can be reduced. Also, the video signal is displayed in multiple columns. By writing directly, the writing time can be extended, and the video signal can be written. This can prevent overcrowding and under-concentration.

[0245] Furthermore, the shift register 5601 of the drive circuit in this embodiment is as described in Embodiment 3. Because it uses a shift register, malfunctions are suppressed, resulting in high reliability. By using a miniaturized shift register, it becomes possible to miniaturize the entire drive circuit. ru.

[0246] Furthermore, the switching circuit 5602 of the drive circuit in this embodiment uses a highly purified oxide Because the crystalline region of the semiconductor layer is used as the channel formation region, the switching operation is fast. Therefore, the drive circuit illustrated in this embodiment enables high-speed writing to pixels, and the number of pixels It is suitable for numerous high-definition, next-generation display devices.

[0247] Furthermore, the shift register described in Embodiment 3 can also be applied to the scan line driving circuit. The drive circuit includes a shift register. In some cases, it may also include a level shifter or buffer. It may also have the following: In a scan line driving circuit, a clock signal (CL) is set to the shift register. A selection signal is generated when K) and the start pulse signal (SP) are input. The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The scan line is connected to the gate electrode of the transistor for one pixel line. Since the transistors for all the pixels in one line must be turned ON simultaneously, the buffer is large. A device capable of conducting a large current is used.

[0248] Furthermore, the active matrix display device and the external device described in this embodiment are connected via a terminal. They are connected in this way. Therefore, due to abnormal input from the outside (for example, static electricity), the transient To prevent malfunctions such as fluctuations in the threshold voltage, a protection circuit is provided within the drive circuit. Because of its high breakdown voltage between the gate and source, and between the gate and drain, it is used in protective circuits. As a transistor, one that uses the first electrode layer as the main gate electrode is preferable. ru.

[0249] (Embodiment 5) In this embodiment, Figure 22 shows an example of the configuration of the terminal section provided on the same substrate as the transistor. This is shown below. Note that in Figure 22, the same reference numerals are used to describe the same parts as in Figure 1.

[0250] Figures 22(A1) and 22(A2) show a cross-sectional view and a top view of the gate wiring terminal section, respectively. This is shown. Figure 22(A1) corresponds to a cross-sectional view along the line C1-C2 in Figure 22(A2). In Figure 22(A1), the conductive layer 415 formed on the second insulating layer 428 is input These are terminal electrodes for connection that function as terminals. Also, in Figure 22(A1), at the terminal section This includes a first terminal 411 formed from the same material as the gate wiring, and a first terminal 411 formed from the same material as the source wiring. The connecting electrode 412 is made to overlap with the first insulating layer 402 and make direct contact, thereby enabling electrical conductivity. Furthermore, the connecting electrode 412 and the conductive layer 415 are provided in the second insulating layer 428. It is connected and electrically conductive through a hole.

[0251] Furthermore, Figures 22(B1) and 22(B2) show a cross-sectional view and a top view of the source wiring terminal section. Each is illustrated. Also, Figure 22(B1) follows the line C3-C4 in Figure 22(B2). This corresponds to a cross-sectional view. In Figure 22(B1), a conductive layer is formed on the second insulating layer 428. Layer 418 is a terminal electrode for connection that functions as an input terminal. Also, in Figure 22(B1) In the terminal section, an electrode layer 416, formed from the same material as the gate wiring, is connected to the source wiring. The first insulating layer 402 is superimposed on the second terminal 414 which is electrically connected. It is formed below the second terminal 414. The electrode layer 416 is electrically connected to the second terminal 414. It is not done, and the electrode layer 416 is at a different potential from the second terminal 414, for example, floating, G Setting it to ND, 0V, etc. will provide capacitance for noise reduction or electrostatic discharge protection. It can be formed. Also, the second terminal 414 is connected to the conductive layer via the second insulating layer 428. It is electrically connected to 418.

[0252] Multiple gate lines, source lines, common potential lines, and power supply lines are provided according to the pixel density. Furthermore, at the terminal section, the first terminal is at the same potential as the gate wiring, and the source wiring is... The second terminal is at the same potential as the line, the third terminal is at the same potential as the power supply line, and the fourth terminal is at the same potential as the common potential line. Multiple terminals are arranged in a row. The number of each terminal can be set to any number. It is acceptable as long as it is done as it is appropriate, and the implementer should make the decision as appropriate.

[0253] This embodiment can be freely combined with other embodiments.

[0254] (Embodiment 6) A transistor as shown in Embodiment 1 is fabricated, and this transistor is used in the pixel section and further in the drive circuit. It can be used to fabricate semiconductor devices (also called display devices) that have a display function. Furthermore, the transistor shown in Embodiment 1 is driven by part or all of the circuit on the same substrate as the pixel section. It can be integrally formed on top to create a system-on-panel.

[0255] A display device includes display elements. Display elements include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements. A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electrical LEDs). This includes Luminescence, organic EL, etc. Also, electronic inks, etc. Display media in which contrast changes due to the effect can also be applied.

[0256] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. It includes a module on which ICs and the like are mounted. Furthermore, it is a device for manufacturing the display device. With respect to an element substrate that corresponds to one form before the display element is completed in the process, the element substrate is The element substrate is specifically provided with means for supplying current to the display element in each of the multiple pixels. This may be a state where only the pixel electrodes of the display element are formed, or a conductive film that will serve as the pixel electrode may be formed. This may be the state after the film has been formed but before etching to form the pixel electrodes. All forms apply.

[0257] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC (Flexible Printed Circuit). (inted circuit) or TAB (Tape Automated Bon) (ding) tape or TCP (Tape Carrier Package) Modules that have a printed circuit board attached to the end of the TAB tape or TCP. The display element or IC (integrated circuit board) is integrated using the COG (Chip On Glass) method. All modules in which the road is directly implemented are also included in the display device.

[0258] In this embodiment, the external appearance and cross-section of a liquid crystal display panel, which corresponds to one form of semiconductor device, are described below. This will be explained using Figure 11. Figure 11 shows an embodiment formed on the first substrate 4001. A highly reliable transient containing the In-Ga-Zn-O system film shown in 1 as an oxide semiconductor layer The components 4010, 4011, and the liquid crystal element 4013 are sealed between them and the second substrate 4006. This is a top view of the panel sealed with material 4005, and Figure 11(B) is a top view of Figure 11(A1). This corresponds to the cross-sectional view in MN of (A2).

[0259] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0260] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, etc. The ear bonding method or the TAB method can be used. Figure 11(A1) is C This is an example of implementing the signal line drive circuit 4003 using the OG method, and Figure 11(A2) shows the TAB method. This is an example of implementing the signal line drive circuit 4003 according to the law.

[0261] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple transistors, and in Figure 11(B), the transistors included in the pixel section 4002 The transistor 4010 and the transistor 4011 included in the scan line drive circuit 4004 are shown as examples. Insulating layers 4020 and 4021 are provided on transistors 4010 and 4011. ru.

[0262] Transistors 4010 and 4011 use an In-Ga-Zn-O system film as the oxide semiconductor layer. The transistor shown in the highly reliable embodiment 1 can be applied. In this configuration, transistors 4010 and 4011 are n-channel transistors.

[0263] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. It is connected to the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are formed on top of each other. The part that is made up corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode Layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films, and is insulating The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033. (Note: This is not shown in the diagram.) However, the color filter is provided on either the first substrate 4001 or the second substrate 4006. That's good too.

[0264] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically, glass). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Film can be used. Also, aluminum foil can be used with PVF film or polyester. It is also possible to use a sheet with a structure sandwiched between layers of film.

[0265] Furthermore, spacer 4035 is a columnar spacer obtained by selectively etching the insulating film. This controls the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. It is provided for this purpose. A spherical spacer may also be used. Furthermore, the counter electrode layer 4031 is electrically connected to a common potential line located on the same board as transistor 4010. It is done. Using a common connection part, the opposing electrode layer is connected via conductive particles placed between the pair of substrates. 4031 and the common potential line can be electrically connected. Note that the conductive particles are a sealing material. It will be included in 4005.

[0266] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs. c. The duration is short, less than 100 μsec, and is optically isotropic, so orientation treatment is unnecessary. It has little dependence on the field of view.

[0267] Although this embodiment is an example of a transmissive liquid crystal display device, the present invention can also be applied to a reflective liquid crystal display device. It can also be applied to semi-transmissive liquid crystal display devices.

[0268] Furthermore, in the liquid crystal display device of this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and on the inside An example is shown where the colored layer and the electrode layer used for the display element are arranged in that order, but the polarizing plate is placed on the inside of the substrate. It may also be done. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the polarizing plate and The coloring layer and the manufacturing process conditions should be set appropriately. A light-shielding film that functions in this way may be provided.

[0269] Furthermore, in this embodiment, in order to reduce surface irregularities caused by transistors, and transistors To improve the reliability of the transistor, the transistor obtained in Embodiment 1 is protected with a protective film or planar insulating film. The structure is covered with insulating layers (insulating layer 4020, insulating layer 4021) that function as a border film. Furthermore, the protective film prevents the intrusion of contaminants such as organic matter, metallic substances, and water vapor suspended in the atmosphere. The purpose is to prevent oxidation, and a dense film is preferred. The protective film is made using the sputtering method, which removes silicate oxide. Condenser film, silicon nitride film, silicon oxide nitride film, silicon oxide nitride film, aluminum oxide A film, an aluminum nitride film, an aluminum oxide nitride film, or a monolayer of an aluminum nitride oxide film. Alternatively, they may be formed by lamination. This embodiment shows an example in which the protective film is formed by sputtering. However, it is not particularly limited and can be formed in various ways.

[0270] Here, a laminated insulating layer 4020 is formed as a protective film. As the first layer of 0, a silicon oxide film is formed using the sputtering method. When using a recon film, the aluminum film used as the source electrode layer and drain electrode layer is It is effective in preventing lockout.

[0271] Furthermore, an insulating layer is formed as the second layer of the protective film. Here, the second layer of the insulating layer 4020 is Then, a silicon nitride film is formed using the sputtering method. The silicon nitride film is used as a protective film. Then, mobile ions such as sodium penetrate into the semiconductor region, affecting the electrical characteristics of the transistor. It is possible to suppress change.

[0272] Furthermore, after forming the protective film, the oxide semiconductor layer is annealed (300°C to 400°C). You may do so.

[0273] Furthermore, an insulating layer 4021 is formed as a planar insulating film. As the insulating layer 4021, acrylic Heat-resistant resins such as polyimide, benzocyclobutene resins, polyamides, epoxy resins, etc. Organic materials having properties can be used. In addition to the above organic materials, low dielectric constant materials (l (ow-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) Materials such as (S) can be used. Furthermore, multiple insulating films formed from these materials can be stacked. This may result in the formation of an insulating layer 4021.

[0274] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0275] The method for forming the insulating layer 4021 is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used. When forming the insulating layer 4021 using a material liquid, During the manufacturing process, the oxide semiconductor layer is simultaneously annealed (300°C to 400°C). This is also acceptable. By combining the firing process of the insulating layer 4021 and the annealing of the oxide semiconductor layer, efficiency can be improved. This makes it possible to manufacture semiconductor devices.

[0276] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon dioxide. Conductive materials can be used.

[0277] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrodes have a sheet resistance of 10,000 Ω / □ or less and a light transmittance at a wavelength of 550 nm. It is preferable that the ratio is 70% or more. Also, the resistance of the conductive polymer contained in the conductive composition The ratio is preferably 0.1 Ω·cm or less.

[0278] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0279] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0280] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. Formed from the same conductive film as 30, terminal electrode 4016 is made from transistors 4010, 4011 The source electrode layer and drain electrode layer are formed of the same conductive film.

[0281] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0282] Furthermore, in Figure 11, a signal line drive circuit 4003 is formed separately and implemented on the first substrate 4001. Although an example of the configuration is shown, this embodiment is not limited to this configuration. Scan line drive circuit Alternatively, it may be formed and implemented separately, or it may be part of the signal line drive circuit or part of the scan line drive circuit. It is also acceptable to form and implement the component separately.

[0283] Figure 12 shows a transistor substrate 26 fabricated by applying the transistor shown in Embodiment 1. This shows an example of configuring a liquid crystal display module as a semiconductor device using 00.

[0284] Figure 12 shows an example of a liquid crystal display module, consisting of a transistor substrate 2600 and a counter substrate 260. 1 is fixed by a sealing material 2602, and between them is a pixel section 2603 including a transistor, A display area is formed by providing a display element 2604 including a liquid crystal layer, a colored layer 2605, etc. The colored layer 2605 is necessary for color display; in the case of the RGB system, it contains red, green, and blue. A colored layer corresponding to each color is provided for each pixel. Transistor board 2600 On the outside of the opposing substrate 2601, polarizing plates 2606, 2607, and a diffuser plate 2613 are arranged. The light source consists of a cold cathode tube 2610 and a reflector 2611, and a circuit board 261 2 is the wiring circuit section 26 of the transistor board 2600 via the flexible wiring board 2609. It is connected to the 08 and incorporates external circuits such as control circuits and power supply circuits. The polarizing plate and the liquid crystal layer may be laminated with a phase difference plate between them.

[0285] The LCD display module has TN (Twisted Nematic) mode and IPS (I n-Plane-Switching) mode, FFS (Fringe Field Switching) (witching) mode, MVA (Multi-domain Vertical A) alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0286] Through the above process, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. ru.

[0287] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It will be possible to do so.

[0288] (Embodiment 7) In this embodiment, the semiconductor device to which the transistor shown in Embodiment 1 is applied is an electronic device Here is an example of a super.

[0289] Figure 13 shows an active-matrix electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the transistor shown in Embodiment 1. It is possible.

[0290] The electronic paper in Figure 13 is an example of a display device using a twist ball display method. The Toball display method is an electrode layer that uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer. This method of display is achieved by controlling the orientation of spherical particles by generating a phenomenon.

[0291] The transistor 581 sealed between substrate 580 and substrate 596 is a transistor according to one aspect of the present invention. It is an inverter, and the first electrode layer 587 is insulated by the source electrode layer or drain electrode layer. The first electrode layer 58 is electrically connected to the first electrode layer 58 through openings formed in layers 583 and 585. Between 7 and the second electrode layer 588 there is a black region 590a and a white region 590b, and around A spherical particle 589 is provided, which includes a cavity 594 filled with liquid, The area surrounding particle 589 is filled with a filler material 595 such as resin (see Figure 13). Spherical particle 5 The cavity 594 within 89 is filled with liquid, and the black region 590a and the white region Particles having 590b are present. In this embodiment, the first electrode layer 587 is The pixel electrode corresponds to the second electrode layer 588, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is It is electrically connected to a common potential line provided on the same board as transistor 581. Using one of the common connection parts shown in Embodiment 1, conductive particles are placed between a pair of substrates. The second electrode layer 588 and the common potential line can be electrically connected via this.

[0292] Alternatively, an electrophoretic element can be used instead of a twist ball. (Transparent liquid) And, positively charged white particles and negatively charged black particles are enclosed in a 2-inch container with a diameter of 10 μm or more. Microcapsules of approximately 00 μm or less are used. They are placed between the first electrode layer and the second electrode layer. The microcapsules being injected are subjected to an electric field by a first electrode layer and a second electrode layer. Then, the white particles and the black particles move in opposite directions to each other, resulting in either white or black being displayed. Yes, it is possible. An electrophoretic display element, commonly known as electronic paper, utilizes this principle. It is called that. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary It does not require a light, consumes little power, and the display can be seen even in dimly lit places. Furthermore, even if power is not supplied to the display unit, it retains the image that has been displayed. Because it is possible to do so, a semiconductor device with a display function (simply a display device, or Even when the semiconductor device (also called a semiconductor device equipped with a display device) is moved away, the displayed image It becomes possible to save it.

[0293] Through the above process, highly reliable electronic paper can be manufactured as a semiconductor device. .

[0294] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It will be possible to do so.

[0295] (Embodiment 8) In this embodiment, a semiconductor device to which the transistor shown in Embodiment 1 is applied is used, and the light emission surface An example of a display device is shown. The display element of the display device is, in this case, electroluminescent. This is demonstrated using a light-emitting element that utilizes electroluminescence. They are distinguished by whether the luminescent material is an organic compound or an inorganic compound, and generally, The latter is called an organic EL element, and the latter is called an inorganic EL element.

[0296] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each is injected into a layer containing a luminescent organic compound, and an electric current is passed through it. Through the recombination of electrons and holes, the luminescent organic compound forms an excited state. It emits light when the excited state returns to the ground state. From this mechanism, such emission Optical devices are called current-excited light-emitting devices.

[0297] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0298] Figure 14 shows an example of a semiconductor device to which the present invention is applied, which can be used to apply digital time-gradation driving. This figure shows an example of the basic configuration. Note that OS in the figure stands for Oxide Semiconductor. This indicates that it is a transistor using a conductor.

[0299] This section describes the pixel configuration and operation to which digital time-based gradation driving can be applied. This is the channel-shaped oxide semiconductor layer (In-Ga-Zn-O film) shown in Embodiment 1. This example shows how to use two n-channel transistors for the region, with each pixel utilizing this method.

[0300] Pixel 6400 consists of a switching transistor 6401, a driving transistor 6402, It has a light-emitting element 6404 and a capacitive element 6403. Switching transistor 64 01 has a gate connected to scan line 6406, and the first electrode (source electrode and drain electrode) The (side) is connected to signal line 6405, and the second electrode (the other of the source electrode and drain electrode) is driven It is connected to the gate of the drive transistor 6402. The drive transistor 6402 is The gate is connected to the power line 6407 via the capacitive element 6403, and the first electrode is connected to the power line 640 It is connected to 7, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is identical It is electrically connected to a common potential line formed on the substrate. If that connection point is called a common connection point... Yes.

[0301] Furthermore, a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential, and low power supply potentials include, for example, GND and 0V. It may be fixed. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404. Then, in order to pass current through the light-emitting element 6404 and make the light-emitting element 6404 emit light, a high power supply potential is used. The potential difference between the low power supply potential and the light-emitting element 6404 is set to be greater than or equal to the forward threshold voltage of the light-emitting element 6404. Set the potential for each.

[0302] Note that the capacitive element 6403 is omitted by substituting the gate capacitance of the drive transistor 6402. This is also possible. Regarding the gate capacitance of the drive transistor 6402, the channel region A capacitance may be formed between the gate electrode and the gate electrode.

[0303] In the case of a voltage input / voltage drive method, the gate of the drive transistor 6402 is: The drive transistor 6402 is either fully on or completely off. The video signal is input. In other words, the driver transistor 6402 is operated in the linear region. The driver transistor 6402 operates in the linear region, therefore the voltage of the power line 6407 is higher than A high voltage is applied to the gate of the drive transistor 6402. The signal line 6405 is connected to... Apply a voltage equal to or greater than (power line voltage + Vth of the drive transistor 6402).

[0304] Furthermore, when using analog gradation drive instead of digital time gradation drive, the signal input is different. By doing so, the same pixel configuration as in Figure 14 can be used.

[0305] When performing analog grayscale driving, the gate of the driving transistor 6402 is connected to the light-emitting element 6404 Apply a voltage equal to or greater than the forward voltage of the drive transistor 6402 + Vth. (Light-emitting element 64) The forward voltage of 04 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is Includes key voltage. Note that the drive transistor 6402 operates in the saturation region. By inputting an O signal, current can be supplied to the light-emitting element 6404. The drive transistor... To operate the 6402 in the saturation region, the potential of the power line 6407 is set to the drive transistor The gate potential of the TA6402 is set higher. By making the video signal analog, the light-emitting element... By supplying current to the 6404 according to the video signal, analog grayscale driving can be performed.

[0306] Note that the pixel configuration shown in Figure 14 is not limited to this. For example, if new pixels are added to the pixels shown in Figure 14... Switches, resistors, capacitives, transistors, or logic circuits may be added to it.

[0307] Next, the configuration of the light-emitting element will be explained using Figure 15. Here, the driving transistor The cross-sectional structure of a pixel will be explained using the case where the type is n as an example. Figure 15(A)(B)( Transistors 7001 and 701 are drive transistors used in the semiconductor device of C). 1. 7021 can be fabricated in the same manner as the transistor shown in Embodiment 1, and is made of In-Ga-Zn - This is a highly reliable transistor that includes an O-based film as an oxide semiconductor layer.

[0308] A light-emitting element only needs to have at least one of its electrodes, either the anode or the cathode, transparent in order to extract light. Then, a transistor and a light-emitting element are formed on the substrate, and light is extracted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and emission from both the substrate side and the opposite side of the substrate. There is a light-emitting element with a double-sided emission structure that extracts light from a surface, and the pixel configuration of the present invention is which emission structure It can also be applied to light-emitting elements.

[0309] The light-emitting element with a bottom-extrusion structure will be explained using Figure 15(A).

[0310] The driving transistor 7011 is of the n type, and the light emitted from the light-emitting element 7012 is the first electrode. Figure 15(A) shows a cross-sectional view of the pixel when ejected to the 7013 side. A conductive material that is transparent to visible light and electrically connected to the drain electrode layer of ST7011. A first electrode 7013 of the light-emitting element 7012 is formed on the film 7017, and the first electrode An EL layer 7014 and a second electrode 7015 are stacked sequentially on top of 7013.

[0311] As a conductive film 7017 that is transparent to visible light, an indi containing tungsten oxide is used. Indium oxide, indium zinc oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium oxide, titanium oxide-containing indium tin oxide, indium tin oxide, indium zinc Indium tin oxide with added silicon dioxide has transparency to visible light. A conductive film can be used.

[0312] Furthermore, the first electrode 7013 of the light-emitting element can be made of various materials. For example, the first When using electrode 7013 as the cathode, a material with a small work function is used, specifically, for example For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and In addition to alloys containing these elements (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are also preferred. It seems so. In Figure 15(A), the film thickness of the first electrode 7013 is such that it transmits visible light (preferably... Or, it should be about 5 nm to 30 nm. For example, an aluminum film with a thickness of 20 nm. This is used as the first electrode 7013.

[0313] Furthermore, after laminating a conductive film that is transparent to visible light and an aluminum film, selectively Etched to form a conductive film 7017 that is transparent to visible light and a first electrode 7013 It may be formed, and in this case, etching can be done using the same mask, so it is preferred. It's nice.

[0314] Furthermore, the partition wall 7019 is formed in the protective insulating layer 7035 and the insulating layer 7032, and Dre It is placed on the contact hole that reaches the in electrode layer via the conductive film 7017. The peripheral edge of electrode 7013 may be covered with a partition wall. The partition wall 7019 may be made of polyimide, acrylic acid Organic resin films such as yl resin, polyamide, epoxy resin, inorganic insulating film, or organic polysilicone It is formed using a sieve. The partition wall 7019 is made of a photosensitive resin material in particular, and the first electrode 70 An opening is formed on 13, and the side walls of the opening are inclined surfaces formed with a continuous curvature. It is preferable to form it in such a way. When a photosensitive resin material is used as the partition wall 7019. This eliminates the need to form a resist mask.

[0315] Furthermore, the EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least It is sufficient to include a light-emitting layer, and even if it consists of a single layer, it can be configured so that multiple layers are stacked on top of each other. Either way is fine. If the EL layer 7014 is composed of multiple layers, the cathode is... An electron injection layer, electron transport layer, light emission layer, hole transport layer, and hole are placed on the first electrode 7013 which functions. The layers are stacked in the order of the injection-treated layers. Note that it is not necessary to provide all of these layers.

[0316] Furthermore, the stacking order is not limited to the above, and the first electrode 7013 can function as an anode, and the first electrode A hole injection layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer are stacked on top of 7013 in that order. This is also acceptable. However, when comparing power consumption, the first electrode 7013 is used as the cathode. On the first electrode 7013, there is an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole injection layer. Stacking the layers in the order they are placed inside out can suppress the voltage rise in the drive circuit and reduce power consumption. Therefore, it is preferable.

[0317] Furthermore, various materials can be used for the second electrode 7015 formed on the EL layer 7014. This is possible. For example, when the second electrode 7015 is used as the anode, the work function is large ( Specifically, materials with a voltage of 4.0 eV or higher, such as ZrN, Ti, W, Ni, Pt, Cr, etc. Transparent conductive materials such as ITO, IZO, and ZnO are preferred. Also, on the second electrode 7015 A shielding film 7016, such as a light-blocking metal or a light-reflecting metal, is used. In this configuration, an ITO film is used as the second electrode 7015, and a Ti film is used as the shielding film 7016. ru.

[0318] The first electrode 7013 and the second electrode 7015 sandwich the EL layer 7014 which includes the light-emitting layer. The region corresponds to the light-emitting element 7012. In the element structure shown in Figure 15(A), The light emitted from 7012 is directed toward the first electrode 7013, as indicated by the arrow.

[0319] In Figure 15(A), the light emitted from the light-emitting element 7012 is directed to the color filter layer. It passes through 7033, insulating layer 7032, oxide insulating layer 7031, gate insulating layer 7030, and It is then ejected through substrate 7010.

[0320] The color filter layer 7033 is used in droplet ejection methods such as inkjet printing, as well as in photolithography. These are formed using etching methods employing graphic technology.

[0321] Furthermore, the color filter layer 7033 is covered with an overcoat layer 7034, providing additional protective insulation. It is covered by layer 7035. Note that in Figure 15(A), the overcoat layer 7034 is a thin film. As shown in the diagram, the overcoat layer 7034 uses a resin material such as acrylic resin, and - It has the function of flattening the irregularities caused by the filter layer 7033.

[0322] Next, a light-emitting element with a double-sided injection structure will be explained using Figure 15(B).

[0323] Figure 15(B) shows the drain electrode layer of the drive transistor 7021 and the electrically connected The first electrode 70 of the light-emitting element 7022 is placed on a conductive film 7027 that is transparent to visible light. 23 is formed, and an EL layer 7024 and a second electrode 7025 are formed on the first electrode 7023. They are stacked in order.

[0324] As a conductive film 7027 that is transparent to visible light, an indi containing tungsten oxide is used. Indium oxide, indium zinc oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium oxide, titanium oxide-containing indium tin oxide, indium tin oxide, indium zinc Indium tin oxide with added silicon dioxide has transparency to visible light. A conductive film can be used.

[0325] Furthermore, the first electrode 7023 can be made of various materials. For example, the first electrode 70 When using 23 as the cathode, use a material with a small work function (specifically, 3.8 eV or less), for example. For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, In addition to alloys containing these (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are also included. Preferred. In this embodiment, the first electrode 7023 is used as the cathode, and its film thickness is visible. The film thickness should be such that it transmits light (preferably around 5 nm to 30 nm). For example, a film thickness of 20 nm. An aluminum film having [a certain characteristic] is used as the cathode.

[0326] Furthermore, after laminating a conductive film that is transparent to visible light and an aluminum film, selectively Etched to form a conductive film 7027 that is transparent to visible light and a first electrode 7023 It may be formed in this way, and in this case, etching can be done using the same mask, which is preferable.

[0327] Furthermore, the partition wall 7029 is formed in the protective insulating layer 7045 and the insulating layer 7042, and Dre It is placed on the contact hole that reaches the in electrode layer via the conductive film 7027. The peripheral edge of electrode 7023 may be covered with a partition wall. The partition wall 7029 may be made of polyimide, acrylic acid Organic resin films such as yl resin, polyamide, epoxy resin, inorganic insulating film, or organic polysilicone It is formed using Sun. The partition wall 7029 is made of a photosensitive resin material in particular, and the first electrode 70 An opening is formed on 23, and the side walls of the opening are inclined surfaces formed with a continuous curvature. It is preferable to form it in such a way. When a photosensitive resin material is used as the partition wall 7029. This eliminates the need to form a resist mask.

[0328] Furthermore, the EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It is fine as long as it is composed of a single layer, or multiple layers stacked on top of each other. Either is fine. If the EL layer 7024 consists of multiple layers, it functions as a cathode. On the first electrode 7023, there is an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole injection layer. The layers are stacked in this order. Note that it is not necessary to include all of these layers.

[0329] Furthermore, the stacking order is not limited to the above, and the first electrode 7023 may be used as the anode, with holes placed on the anode. The layers may be stacked in the order of injection layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer. When comparing power consumption, the first electrode 7023 is used as the cathode, and an electron injection layer is placed on the cathode. Stacking the electron transport layer, light-emitting layer, hole transport layer, and hole injection layer in that order consumes less power. It is preferable because it does not exist.

[0330] Furthermore, various materials can be used for the second electrode 7025 formed on the EL layer 7024. This is possible. For example, when the second electrode 7025 is used as the anode, a material with a large work function can be used. Materials such as transparent conductive materials like ITO, IZO, and ZnO can preferably be used. In this embodiment, the second electrode 7025 is used as the anode, and an ITO film containing silicon oxide is used. It forms.

[0331] The first electrode 7023 and the second electrode 7025 sandwich the EL layer 7024 which includes the light-emitting layer. The region corresponds to the light-emitting element 7022. In the device structure shown in Figure 15(B), The light emitted from 7022 is directed towards the second electrode 7025 and the first electrode 70, as indicated by the arrows. It is injected on both sides of the 23 side.

[0332] In Figure 15(B), the light emitted from the light-emitting element 7022 toward the first electrode 7023 is One light passes through the color filter layer 7043, then through the insulating layer 7042, and the oxide insulating layer 704 1. The material is ejected through the gate insulating layer 7040 and the substrate 7020.

[0333] The color filter layer 7043 is used in droplet ejection methods such as inkjet printing, as well as in photolithography. These are formed using etching methods employing graphic technology.

[0334] Furthermore, the color filter layer 7043 is covered with an overcoat layer 7044, providing additional protection and insulation. It is covered by layer 7045.

[0335] However, when using a double-sided injection-type light-emitting element and both display surfaces are to display in full color, Since the light from the second electrode 7025 does not pass through the color filter layer 7043, a separate color filter is required. - It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0336] Next, the light-emitting element with an upper surface injection structure will be explained using Figure 15(C).

[0337] Figure 15(C) shows that the driving transistor, transistor 7001, is of n type, and the light-emitting element 7 This shows a cross-sectional view of the pixel when the light emitted from 002 passes through to the second electrode 7005. In Figure 15(C), the drain electrode layer of the drive transistor 7001 is electrically connected. A first electrode 7003 of the light-emitting element 7002 is formed on the first electrode 7003, and E The L layer 7004 and the second electrode 7005 are stacked in that order.

[0338] Furthermore, the first electrode 7003 can be made of various materials. For example, the first electrode 70 When using O3 as the cathode, materials with a low work function are preferred, specifically, for example, Li or Cs. Alkali metals such as Mg, Ca, Sr, and other alkaline earth metals, and alloys containing these. In addition to (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0339] Furthermore, the partition wall 7009 is formed in the protective insulating layer 7052 and the insulating layer 7055, and Dre The first electrode 7003 is placed on the contact hole that reaches the in electrode layer. The periphery of the first electrode 7003 may be covered with a partition wall. The partition wall 7009 is made of polyimide. Organic resin films such as acrylic resin, polyamide, epoxy resin, inorganic insulating film, or organic poly It is formed using roxane. The partition wall 7009 is made using a photosensitive resin material in particular, and the first electrode An opening is formed on 7003, and the side walls of the opening are formed with a continuous curvature. It is preferable to form it into a surface. A photosensitive resin material is used as the partition wall 7009. In this case, the step of forming a resist mask can be omitted.

[0340] Furthermore, the EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is at least It is sufficient to include a light-emitting layer, and even if it consists of a single layer, it can be configured so that multiple layers are stacked on top of each other. Either way is fine. If the EL layer 7004 is composed of multiple layers, the cathode is On the first electrode 7003 used, an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole layer are placed. The layers are stacked in the order of injection. Note that it is not necessary to provide all of these layers.

[0341] Furthermore, the stacking order is not limited to the above, and a hole injection layer is placed on the first electrode 7003 used as the anode. Alternatively, the layers may be stacked in the order of a hole transport layer, an emissive layer, an electron transport layer, and an electron injection layer.

[0342] Figure 15(C) shows a layered film consisting of a Ti film, an aluminum film, and another Ti film, onto which a hole injection is applied. The layers are stacked in the following order: indentation layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer, with Mg:A on top of them. A layer is formed between a g alloy thin film and ITO.

[0343] However, if transistor 7001 is n-type, an electron injection layer is placed on the first electrode 7003, electron Stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer in that order is preferable in the drive circuit. This is preferable because it can suppress voltage rise and reduce power consumption.

[0344] The second electrode 7005 is formed using a conductive material that is transparent to visible light, for example. For example, indium oxide containing tungsten oxide, indium zinc containing tungsten oxide. Oxides, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, Indium tin oxide, indium zinc oxide, indium tin oxide with added silicon oxide Any conductive film with transparency to visible light may be used.

[0345] The EL layer 7004, which includes the light-emitting layer, is sandwiched between the first electrode 7003 and the second electrode 7005. The region corresponds to the light-emitting element 7002. In the case of the pixel shown in Figure 15(C), the light-emitting element 700 The light emitted from 2 is directed toward the second electrode 7005, as indicated by the arrow.

[0346] Furthermore, in Figure 15(C), the drain electrode layer of transistor 7001 is an oxide insulating layer. Through contact holes provided in 7051, protective insulating layer 7052 and insulating layer 7055 The first electrode 7003 is electrically connected to the first electrode 7053. The planar insulating layer 7053 is made of polyimide, acrylic Resin materials such as yl resin, benzocyclobutene, polyamide, and epoxy resin can be used. Yes, it is possible. In addition to the resin materials mentioned above, low dielectric constant materials (low-k materials) and siloxane-based resins are also possible. PSG (phosphorus glass), BPSG (phosphorus boron glass), etc., can be used. By stacking multiple insulating films formed from these materials, a planar insulating layer 7053 is formed. It may be done. The method for forming the planar insulating layer 7053 is not particularly limited and depends on the material. Sputtering, SOG method, spin coating, dip coating, spray coating, droplet ejection (inkjet) (Printing methods such as inkjet, screen printing, offset printing, etc.), doctor knife, roll coater, etc. A tumbler, knife coater, etc., can be used.

[0347] Furthermore, in the structure shown in Figure 15(C), when full-color display is performed, for example, the light-emitting element 70 02 is a green light-emitting element, one of the adjacent light-emitting elements is a red light-emitting element, and the other is The light-emitting element will be a blue light-emitting element. In addition to the three types of light-emitting elements, a white element will be added, making it a four-element system. A light-emitting display device capable of full-color display may be manufactured using various types of light-emitting elements.

[0348] Furthermore, in the structure shown in Figure 15(C), all of the multiple light-emitting elements to be arranged are white light-emitting elements. The configuration involves placing a sealing substrate having a color filter or the like above the light-emitting element 7002. A light-emitting device capable of full-color display may be manufactured. By forming a material and combining it with color filters and color conversion layers, full-color display is achieved. It is possible.

[0349] Of course, single-color illumination may also be used. For example, a lighting device can be formed using white light. Alternatively, a monochromatic light emission may be used to form an area-color type light-emitting device.

[0350] Furthermore, if necessary, optical films such as polarizing films, including circular polarizers, may be provided.

[0351] Here, we have discussed organic EL elements as light-emitting elements, but inorganic EL elements can also be used as light-emitting elements. It is also possible to incorporate an L element.

[0352] Furthermore, the transistor that controls the driving of the light-emitting element (driving transistor) and the light-emitting element are electrically connected. An example of a direct connection was shown, but a current control transistor is used between the driving transistor and the light-emitting element. A configuration in which a transistor is connected is also acceptable.

[0353] The semiconductor device shown in this embodiment is not limited to the configuration shown in Figure 15. Various modifications are possible based on the technical concept of this invention.

[0354] Next, a light-emitting surface corresponding to one form of semiconductor device to which the transistor shown in Embodiment 1 is applied. The appearance and cross-section of the display panel (also called a light-emitting panel) will be explained using Figure 16. 16(A) provides a transistor and light-emitting element formed on a first substrate, and a second substrate. Figure 16(B) is a top view of the panel, which is sealed with a sealant in between. This corresponds to a cross-sectional view in HI.

[0355] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0356] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple transistors. In Figure 16(B), the transistor 4510 included in the pixel unit 4502 and the signal line drive The example shows transistor 4509 included in circuit 4503a.

[0357] Transistors 4509 and 4510 use an In-Ga-Zn-O system film as the oxide semiconductor layer. The transistor shown in the highly reliable embodiment 1 can be applied. In this configuration, transistors 4509 and 4510 are n-channel transistors.

[0358] On the insulating layer 4544, the channel of the oxide semiconductor layer of the transistor 4509 for the drive circuit A conductive layer 4540 is provided in a position that overlaps with the layer formation region. The conductive layer 4540 is made of oxide semiconductor By placing it in a position that overlaps with the channel formation region of the conductor layer, the BT test can be performed before and after the test. The change in threshold voltage of the transistor 4509 can be reduced. Also, the conductive layer 45 40 may have the same potential as the gate electrode layer of transistor 4509, or it may be different. It can also function as a second gate electrode layer. Furthermore, the potential of the conductive layer 4540... It may be GND, 0V, or in a floating state.

[0359] Furthermore, 4511 corresponds to a light-emitting element, and the first electrode is a pixel electrode of the light-emitting element 4511. Layer 4517 is electrically connected to the source electrode layer or drain electrode layer of transistor 4510. It is continued. The configuration of the light-emitting element 4511 is a first electrode layer 4517 and an electroluminescent layer 45 12. The stacked structure of the second electrode layer 4513 is not limited to the configuration shown in this embodiment. No. The configuration of the light-emitting element 4511 is adjusted according to the direction of the light extracted from the light-emitting element 4511. This can be changed as needed.

[0360] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side wall of the opening It is preferable to form it so that it becomes an inclined surface with a continuous curvature.

[0361] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0362] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on 4513 and the partition wall 4520. The protective film may be silicon nitride. It can form films, silicon nitride films, DLC films, and the like.

[0363] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0364] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light-emitting element 4511. Formed from the same conductive film as 517, terminal electrode 4516 is made from transistors 4509, 451 It is formed from the same conductive film as the source electrode layer and drain electrode layer of 0.

[0365] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0366] The substrate located in the direction of light extraction from the light-emitting element 4511 has light transmittance to visible light. It must be there. In that case, glass plate, plastic plate, polyester film Alternatively, a material that is transparent to visible light, such as acrylic film, can be used.

[0367] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as a filler. I used a prime element.

[0368] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0369] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and this embodiment is configured as shown in Figure 16. Not limited.

[0370] Through the above process, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0371] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It will be possible to do so.

[0372] (Embodiment 9) The semiconductor device using the transistor shown in Embodiment 1 is used as electronic paper. It is possible. Electronic paper can be used in electronic devices in all fields as long as they display information. It is possible to use it. For example, electronic paper can be used to create ebooks (electronic books), Stars, advertisements inside trains and other vehicles, displays on various cards such as credit cards, etc. It can be applied to [the following]. Examples of electronic devices are shown in Figures 17 and 18.

[0373] Figure 17(A) shows poster 2631 made with electronic paper. In the case of printed materials, advertisements are changed manually, but with electronic paper... It allows you to change the ad display in a short amount of time. Furthermore, the display remains stable without any distortion. This can be obtained. Furthermore, the poster may be configured to transmit and receive information wirelessly.

[0374] Figure 17(B) also shows in-vehicle advertisements 2632 on trains and other vehicles. In the case of printed paper, advertisements are changed manually, but using electronic paper... This allows you to change the ad display quickly without requiring a lot of manpower. Also, the display will not break down. A stable image can be obtained without any issues. Furthermore, the in-car advertisements are configured to transmit and receive information wirelessly. That is also acceptable.

[0375] Figure 18 also shows an example of an e-book. For example, the e-book 2700 has a casing 27 It consists of two enclosures, 01 and enclosure 2703. Enclosures 2701 and 2703 are It is integrated with the shaft portion 2711, and the shaft portion 2711 is used as the axis for opening and closing operations. This configuration allows it to function like a physical book.

[0376] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are also configured to display a continuation screen. Yes, or you can configure it to display different screens. For example, text is displayed in the right-hand display unit (display unit 2705 in Figure 18), and the left-hand display unit ( In Figure 18, an image can be displayed on the display unit 2707).

[0377] Furthermore, Figure 18 shows an example in which the housing 2701 is equipped with an operating unit, etc. For example, housing 2 Unit 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, and the like. The page can be turned using operation key 2723. Note that the key is located on the same side as the display unit of the casing. It may also be configured to include a board or pointing device. Furthermore, the back of the enclosure or On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB cable). The configuration includes terminals that can connect to various cables such as cables, a recording medium insertion section, and more. It is also permissible to do so. Furthermore, the eBook 2700 is configured to have the functionality of an electronic dictionary. That's good too.

[0378] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0379] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It will be possible to do so.

[0380] (Embodiment 10) The semiconductor device using the transistor shown in Embodiment 1 can be used in various electronic devices (including amusement machines). It can be applied to (including) electronic devices. For example, television equipment (television). (Also called a television receiver), monitors for computers, digital cameras , digital video camera, digital photo frame, mobile phone (mobile phone, mobile phone accessories) (Also called a portable game console), portable game console, portable information terminal, sound playback device, large game such as pachinko machines Examples include airsoft guns.

[0381] Figure 19(A) shows an example of a television system. The television system 9600 is, The display unit 9603 is integrated into the housing 9601. The display unit 9603 displays video. It is possible to do so. In addition, here the stand 9605 supports the housing 9601. This shows the configuration.

[0382] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys The 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0383] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0384] Figure 19(B) shows an example of a digital photo frame. For example, a digital photo Frame 9700 has a display unit 9703 integrated into the housing 9701. Display unit 970 3 is capable of displaying various images, such as images taken with a digital camera. By displaying data, it can function just like a regular picture frame.

[0385] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It is desirable to include it as it improves the design. For example, the recording medium of a digital photo frame. A memory device containing image data captured by a digital camera is inserted into the body insertion site. The system can capture data and display the captured image data on the display unit 9703.

[0386] Furthermore, the digital photo frame 9700 may be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0387] Figure 20(A) shows a portable gaming machine, which consists of two cabinets, cabinet 9881 and cabinet 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display unit The 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. The portable gaming machine shown in 20(A) also includes a speaker section 9884 and a recording medium insertion section 988 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with a function to measure motion, odor, or infrared radiation, a microphone (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least the present invention includes Any configuration that includes such semiconductor equipment is acceptable, and other auxiliary equipment may be provided as appropriate. This is possible. The portable gaming machine shown in Figure 20(A) has a program recorded on the recording medium. It has functions to read data and display it on the display unit, and to communicate wirelessly with other portable gaming machines. It has the function of sharing information. The functions of the portable gaming machine shown in Figure 20(A) are It is not limited to this and can have a variety of functions.

[0388] Figure 20(B) shows an example of a slot machine, which is a large-scale gaming machine. Slot machine 9 The 900 has a display unit 9903 integrated into the casing 9901. Also, slot machine 9 The 900 also includes other features such as a start lever, stop switch, coin slot, It is equipped with speakers, etc. Of course, the configuration of the slot machine 9900 is not limited to those mentioned above. It is not specified, and any configuration that includes at least the semiconductor device according to the present invention is sufficient, and other accessories The configuration can be configured with appropriate equipment provided.

[0389] Figure 21(A) shows an example of a mobile phone. The mobile phone 1000 has a housing 1001 In addition to the display unit 1002 incorporated into it, there are operation buttons 1003, an external connection port 1004, and It is equipped with a speaker (Peaker 1005), microphone (Microphone 1006), etc.

[0390] The mobile phone 1000 shown in Figure 21(A) allows you to touch the display unit 1002 with your finger or the like to receive information. You can enter information. You can also perform operations such as making phone calls or composing emails. This can be done by touching the display unit 1002 with a finger or the like.

[0391] The display unit 1002 has three main modes. The first is a display that primarily displays images. The first mode is display mode, the second is input mode which is mainly for inputting information such as characters. The third is display mode. This is a display + input mode, which is a combination of two modes: display mode and input mode.

[0392] For example, when making a phone call or composing an email, the display unit 1002 is used for text input. In this case, the primary text input mode should be used, and you should perform the input operation for the characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. It seems so.

[0393] Furthermore, the mobile phone 1000 contains sensors that detect tilt, such as a gyroscope and an accelerometer. By providing a detection device, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the display The display on the display unit 1002 can be automatically switched.

[0394] Furthermore, the screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating button 1003. Also, the type of image displayed on display unit 1002 Therefore, it is also possible to switch between them. For example, the image signal displayed on the display unit is a video signal. Switch to display mode if it's data, or to input mode if it's text data.

[0395] Furthermore, in input mode, the signal detected by the optical sensor of the display unit 1002 is detected and displayed If there is no input via touch operation on unit 1002 for a certain period of time, the screen mode will be changed to input mode. You may also control the system to switch from that display mode to a different mode.

[0396] The display unit 1002 can also function as an image sensor. For example, the display unit 10 By touching device 02 with the palm or fingers, the user can be authenticated by capturing images of their palm print, fingerprints, etc. Furthermore, the display unit may have a backlight that emits near-infrared light or a sensing light that emits near-infrared light. Using the appropriate source, it is also possible to image finger veins, palmar veins, and other veins.

[0397] Figure 21(B) is also an example of a mobile phone. The mobile phone in Figure 21(B) has a housing 9411. The display device 9410 includes a display unit 9412 and an operation button 9413, and the housing 9401 Operation buttons 9402, external input terminal 9403, microphone 9404, speaker 9405, and It has a communication device 9400 which includes a light-emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 is detachable from the communication device 9400, which has telephone functionality, in two directions indicated by the arrows. Yes. Therefore, it is also possible to attach the short axes of the display device 9410 and the communication device 9400 together. The long axes of the display device 9410 and the communication device 9400 can also be mounted together. If only the function is required, remove the display device 9410 from the communication device 9400, and the display device The 9410 can also be used independently. The communication device 9400 and the display device 9410 are connected wirelessly. Images or input information can be sent and received via wireless or wired communication, and each has a rechargeable battery. Close Terry.

[0398] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It will be possible to do so. [Explanation of Symbols]

[0399] 10. Pulse output circuit 11 First Wiring 12 Second Wiring 13 Third Wiring 14. Fourth Wiring 15. Fifth Wiring 16. The sixth wiring 17. The 7th Wiring 21 First input terminal 22 Second input terminal 23 Third input terminal 24. Fourth input terminal 25. Fifth input terminal 26 First output terminal 27 Second output terminal 31. The first transistor 32 Second Transistor 33. The third transistor 34. The fourth transistor 35. The fifth transistor 36. The sixth transistor 37 The 7th Transistor 38. The 8th transistor 39. The 9th Transistor 40 The 10th transistor 41 The 11th transistor 51 Power line 52 Power line 53 Power line 61 The first period 62 Second period 63 Third Period 64 The fourth period 65 The fifth period 400 circuit boards 402 First insulating layer 403 Oxide semiconductor film 404a oxide semiconductor layer 404b oxide semiconductor layer 404c oxide semiconductor layer 405a Crystal region 405b Crystal region 405c crystal region 408 Contact Hole 410a First wiring 410b Second wiring 410c Third Wiring 411 First terminal 412 Connecting electrodes 414 Second terminal 415 Conductive layer 416 Electrode layer 418 Conductive layer 421a First electrode layer 421b First electrode layer 421c First electrode layer 422a Fourth electrode layer 422b Fourth electrode layer 422c connecting electrode layer 428 Second insulating layer 440A Transistor 440B transistor 450 transistors 455a Second electrode layer 455b Third electrode layer 455c Second electrode layer 455d Third electrode layer 455e Second electrode layer 455f Third electrode layer 580 circuit boards 581 transistors 583 Insulating layer 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 circuit boards 1000 mobile phones 1001 enclosure 1002 Display section 1003 Operation Buttons 1004 External connection port 1005 Speaker 1006 Mike 2600 Transistor Board 2601 Opposing substrate 2602 Sealant 2603 pixel section 2604 display elements 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible Wiring Board 2610 cold cathode tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2631 Poster 2632 In-car advertisement 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speaker 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4040 conductive layer 4042 Conductive layer 4501 circuit board 4502 pixel section 4503a Signal Line Drive Circuit 4503b Signal line drive circuit 4504a Scan line drive circuit 4504b Scan line drive circuit 4505 Sealant 4506 circuit board 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulating layer 5300 circuit boards 5301 pixel section 5302 Scan line drive circuit 5303 Scan line drive circuit 5304 Signal Line Drive Circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching Transistor 6402 drive transistor 6403 Capacitive element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7000 circuit boards 7001 Driver Transistor 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7010 circuit board 7011 Driver Transistor 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7020 circuit board 7021 Driver Transistor 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7027 Conductive film 7029 Bulkhead 7030 Gate Insulation Layer 7031 Oxide insulating layer 7032 Insulating layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulating layer 7040 Gate Insulation Layer 7041 Oxide insulating layer 7042 Insulating layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulating layer 7051 Oxide Insulating Layer 7052 Protective insulating layer 7053 Planarized insulating layer 7055 Insulating layer 9400 Communication equipment 9401 enclosure 9402 Operation Buttons 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 cabinet 9412 Display section 9413 Operation Buttons 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand 9607 Display section 9609 Operation Keys 9610 Remote Control Unit 9700 Digital Photo Frame 9701 enclosure 9703 Display section 9881 cabinet 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 cabinet 9893 Connection section 9900 slot machines 9901 cabinet 9903 Display section

Claims

1. A light-emitting device comprising a color filter layer and a light-emitting element having a region disposed above the color filter layer, A first conductive layer having the function of the first gate electrode of a transistor, An oxide semiconductor layer having a region positioned above the first conductive layer and having a channel formation region for the transistor, A second conductive layer having a region positioned above the oxide semiconductor layer and functioning as the second gate electrode of the transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as either the source electrode or the drain electrode of the transistor, An insulating layer having a region positioned above the second conductive layer and a region positioned above the third conductive layer, The color filter layer having a region positioned above the insulating layer, A first resin layer having a region positioned above the color filter layer, A pixel electrode of the light-emitting element having a region positioned above the first resin layer, A second resin layer having a region positioned above the first resin layer and a region positioned above the pixel electrode, The pixel electrode has a region that does not overlap with the second resin layer, The light emitted from the light-emitting element passes through the color filter layer and is emitted. The first resin layer has a region that is in contact with the upper surface of the insulating layer in a region that does not overlap with the color filter layer. The first resin layer has a first contact hole in a region that does not overlap with the color filter layer. The insulating layer has a second contact hole that overlaps with the first contact hole in a region that does not overlap with the color filter layer. The upper surface of the insulating layer has a region that overlaps with the third conductive layer, is not in contact with the first resin layer, and is not in contact with the color filter layer. The pixel electrode is electrically connected to the third conductive layer via a region where the first contact hole and the second contact hole overlap. The second resin layer has a region in which the first contact hole and the second contact hole overlap, and a region in contact with the upper surface of the pixel electrode. Light-emitting device.

2. A light-emitting device comprising a color filter layer and a light-emitting element having a region disposed above the color filter layer, A first conductive layer having the function of the first gate electrode of a transistor, An oxide semiconductor layer having a region positioned above the first conductive layer and having a channel formation region for the transistor, A second conductive layer having a region positioned above the oxide semiconductor layer and functioning as the second gate electrode of the transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as either the source electrode or the drain electrode of the transistor, An insulating layer having a region positioned above the second conductive layer and a region positioned above the third conductive layer, The color filter layer having a region positioned above the insulating layer, A first resin layer having a region positioned above the color filter layer, A pixel electrode of the light-emitting element having a region positioned above the first resin layer, A second resin layer having a region positioned above the first resin layer and a region positioned above the pixel electrode, The pixel electrode has a region that does not overlap with the second resin layer, The light emitted from the light-emitting element passes through the color filter layer and is emitted. The first resin layer has a region that is in contact with the upper surface of the insulating layer in a region that does not overlap with the color filter layer. The first resin layer has a first contact hole in a region that does not overlap with the color filter layer. The insulating layer has a second contact hole that overlaps with the first contact hole in a region that does not overlap with the color filter layer. The upper surface of the insulating layer has a region that overlaps with the third conductive layer, is not in contact with the first resin layer, and is not in contact with the color filter layer. The pixel electrode is electrically connected to the third conductive layer via a region where the first contact hole and the second contact hole overlap. The second resin layer has a region that overlaps with the third conductive layer in the region where the first contact hole and the second contact hole overlap. Light-emitting device.

3. A light-emitting device comprising a color filter layer and a light-emitting element having a region disposed above the color filter layer, A first conductive layer having the function of the first gate electrode of a transistor, An oxide semiconductor layer having a region positioned above the first conductive layer and having a channel formation region for the transistor, A second conductive layer having a region positioned above the oxide semiconductor layer and functioning as the second gate electrode of the transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as either the source electrode or the drain electrode of the transistor, An insulating layer having a region positioned above the second conductive layer and a region positioned above the third conductive layer, The color filter layer having a region positioned above the insulating layer, A first resin layer having a region positioned above the color filter layer, A pixel electrode of the light-emitting element having a region positioned above the first resin layer, A second resin layer having a region positioned above the first resin layer and a region positioned above the pixel electrode, The oxide semiconductor layer has a region that overlaps with the color filter layer, The pixel electrode has a region that does not overlap with the second resin layer, The light emitted from the light-emitting element passes through the color filter layer and is emitted. The first resin layer has a region that is in contact with the upper surface of the insulating layer in a region that does not overlap with the color filter layer. The first resin layer has a first contact hole in a region that does not overlap with the color filter layer. The insulating layer has a second contact hole that overlaps with the first contact hole in a region that does not overlap with the color filter layer. The upper surface of the insulating layer has a region that overlaps with the third conductive layer, is not in contact with the first resin layer, and is not in contact with the color filter layer. The pixel electrode is electrically connected to the third conductive layer via a region where the first contact hole and the second contact hole overlap. The second resin layer has a region in which the first contact hole and the second contact hole overlap, and a region in contact with the upper surface of the pixel electrode. Light-emitting device.

4. A light-emitting device comprising a color filter layer and a light-emitting element having a region disposed above the color filter layer, A first conductive layer having the function of the first gate electrode of a transistor, An oxide semiconductor layer having a region positioned above the first conductive layer and having a channel formation region for the transistor, A second conductive layer having a region positioned above the oxide semiconductor layer and functioning as the second gate electrode of the transistor, A third conductive layer is electrically connected to the oxide semiconductor layer and functions as either the source electrode or the drain electrode of the transistor, An insulating layer having a region positioned above the second conductive layer and a region positioned above the third conductive layer, The color filter layer having a region positioned above the insulating layer, A first resin layer having a region positioned above the color filter layer, A pixel electrode of the light-emitting element having a region positioned above the first resin layer, A second resin layer having a region positioned above the first resin layer and a region positioned above the pixel electrode, The oxide semiconductor layer has a region that overlaps with the color filter layer, The pixel electrode has a region that does not overlap with the second resin layer, The light emitted from the light-emitting element passes through the color filter layer and is emitted. The first resin layer has a region that is in contact with the upper surface of the insulating layer in a region that does not overlap with the color filter layer. The first resin layer has a first contact hole in a region that does not overlap with the color filter layer. The insulating layer has a second contact hole that overlaps with the first contact hole in a region that does not overlap with the color filter layer. The upper surface of the insulating layer has a region that overlaps with the third conductive layer, is not in contact with the first resin layer, and is not in contact with the color filter layer. The pixel electrode is electrically connected to the third conductive layer via a region where the first contact hole and the second contact hole overlap. The second resin layer has a region that overlaps with the third conductive layer in the region where the first contact hole and the second contact hole overlap. Light-emitting device.

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