Addition method

Abstract

The present invention provides an addition method for suppressing overflow, a semiconductor device, and an electronic device. [Solution] An addition method in an adder circuit having first memories M1 to fourth memories M4, comprising: step ST11 providing a first data having a sign to the first memory; step ST12 providing the second memory with the first data having a positive sign stored in the first memory, and providing the third memory with the first data having a negative sign stored in the second memory; and step ST13 generating second data by adding the first data having a positive sign stored in the second memory and the first data having a negative sign stored in the third memory, and storing it in the fourth memory, wherein if the second data stored in the fourth memory is all second data having a positive sign or all second data having a negative sign, all the second data stored in the fourth memory are added together.

Description

[Technical Field]

[0001] One aspect of the present invention relates to an addition method, a semiconductor device, and an electronic device.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to products, programs, methods, or methods of manufacture. One aspect of the invention relates to semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, and their driving methods. Relating to laws or methods for manufacturing them.

[0003] In this specification, a semiconductor device is defined as an element that can function by utilizing semiconductor properties. This refers to a component, circuit, or device. Examples include semiconductor components such as transistors and diodes. The child is a semiconductor device. Another example is a circuit having semiconductor elements, which is a semiconductor device. Another example is a device equipped with a circuit having semiconductor elements, which is a semiconductor device. be. [Background technology]

[0004] IoT (Internet of Things), AI (Artificial I) Due to advancements in information technology such as intelligence, the amount of data handled tends to increase. This indicates that for electronic devices to utilize information technologies such as IoT and AI, a large amount of data is needed. The ability to process data is required. Furthermore, in order to use electronic devices comfortably, To achieve low power consumption, there is a need for semiconductor devices that reduce the amount of computation required.

[0005] Patent Document 1 describes how to use low-precision adders in parallel to create an adder with a specific precision. This document discloses an addition method that operates in this manner, as well as the configuration of an adder.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] An electronic device that combines IoT and AI has a problem of power reduction. In addition, semiconductor devices used in electronic devices are required to be miniaturized so that they can be housed in a narrow space. Therefore, the semiconductor device has a problem of reducing the circuit scale without reducing the arithmetic processing ability.

[0008] <000T00089>In AI, especially, for example, in deep learning, features can be extracted from various information (images, voices, big data, etc.) by using machine learning. AI has a neural network, and the neural network has a plurality of neurons. A neuron is known for performing a sum-of-products operation that mimics the function of a synapse. A circuit having the function of sum-of-products operation is known to calculate the sum of the results obtained by multiplying a plurality of input signals by weight coefficients. Since the sum-of-products operation processes signed floating-point data by digital arithmetic, there is a problem that the logic scale becomes large. The power consumption has a problem of increasing in proportion to the size of the logic scale. <T

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[0026] [Figure 1] <0One of the objectives is to provide a solution. Alternatively, one aspect of the present invention provides a solution that enables low-power computation of neurons. One objective is to provide a semiconductor device that can be powered. Alternatively, one aspect of the present invention is a new One of the objectives is to provide a standard program. Alternatively, one aspect of the present invention is to provide a novel program. One objective is to provide a calculation method. Alternatively, one aspect of the present invention relates to a novel semiconductor device. One of the objectives is to provide a novel semiconductor device. Alternatively, one aspect of the present invention relates to the driving of a novel semiconductor device. One of the objectives is to provide a method.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title will become clear from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the drawings, claims, etc.

[0011] The problems addressed by one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other issues. These other issues are described in the following section. This is an issue not mentioned in the specification. Any issues not mentioned in this section should be considered by someone skilled in the art. These can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention addresses at least one of the above-listed issues and / or other problems. At the very least, it solves one problem. [Means for solving the problem]

[0012] One aspect of the present invention comprises a first memory, a second memory, a third memory, and a fourth memory. The first memory is given first data having a sign, and the second memory is given This involves the step of providing a first data having a positive sign stored in a first memory, and the third The first step is to provide the memory with first data having a negative sign, which is stored in the first memory. The process includes a step where, if the first data is zero, it is discarded. The data is then stored in the second memory. A first data with a positive sign, and a first data with a negative sign stored in the third memory. The process includes the step of adding the first and second data to generate the second data. The fourth memory contains the second Step 2: Data is stored, and second data having a positive sign is stored in the fourth memory. In either case, when it is not stored, or when a second data with a negative sign is not stored. The addition includes a step of adding all the second data stored in the fourth memory. It is a method.

[0013] In each of the above configurations, the first data and the second data are signed integer data. An addition method is preferred.

[0014] In each of the above configurations, an addition method is preferred in which the second data is stored in the first memory.

[0015] First memory, second memory, third memory, selector circuit, first adder circuit, second adder circuit, and has a counter circuit. The counter circuit has a first counter, a second counter, It has a first memory which is electrically connected to a first adder circuit and a selector circuit. The rectangle circuit is electrically connected to the second memory and the third memory, and the second adder circuit is connected to the second The counter circuit is electrically connected to the first memory and the third memory, and the counter circuit is connected to the first memory and the first adder. It is electrically connected to the circuit. The first memory is given first data which has a sign. It has the function of providing initial values ​​to the first and second counters. The second memory has the function of outputting the first underflow flag when there is no stored data. The third memory has a second underflow flag which outputs when there is no stored data. It has the function of providing the first data to the first memory and the counter circuit. The underpass circuit is given either the first underflow flag or the second underflow flag. Sometimes, it has a function to determine the value of the first counter or the second counter, and the first counter, Alternatively, if either of the second counters is at its initial value, the first adder circuit is stored in the first memory. This is a semiconductor device that has the function of adding the first data.

[0016] In each of the above configurations, the selector circuit has a positive sign stored in the first memory. A device that distributes the first data to the second memory, and the first data with a negative sign to the third memory. The second adder circuit has the ability to take the first data having a positive sign stored in the second memory and the second A machine that adds a first data with a negative sign stored in memory to generate a second data. The second data is provided to the first memory and the counter circuit, and the counter circuit is Given the first underflow flag and the second underflow flag, the first It has the function of determining the value of the counter or the second counter, and the first counter or the second counter If either of the values ​​is an initial value, the first adder circuit will use the second data stored in the first memory. A semiconductor device having a function to add values ​​is preferred.

[0017] In each of the above configurations, the second memory and the third memory are first-in-first-a A semiconductor device having an output function is preferred.

[0018] In each of the above configurations, the semiconductor device includes a first zero insertion circuit and a second zero insertion circuit. It has a control circuit and a first underflow flag output and a second underflow - When the flow flag is not output, instead of the first data which has a positive sign, the first It has the function of providing a zero value by the zero insertion circuit, and second underflow When the flag is output and the first underflow flag is not output, the negative sign is Instead of the first data, a value of zero is given by the second zero insertion circuit. A semiconductor device having the function of [doing something] is preferred.

[0019] A semiconductor device having a neural network, wherein the neural network is an integral It has an addition circuit, and the sum-of-accumulate circuit has multiple multiplication circuits and suppresses overflow due to addition. It has a first circuit that controls, and the first circuit has a first memory, a second memory, a third memory, The circuit also has a first adder circuit, and the output data of the multiplier circuit is given to the first memory as first data. Furthermore, the second and third memories have a first-in, first-out function. The second memory is given the first data with a positive sign that the first memory stores. Then, the third memory is given the first data having a negative sign that the first memory stores, and 1. The adder circuit reads a first data with a positive sign from the second memory and a third memory. By adding the first data, which has a negative sign and was read out, an overflow due to addition occurs. This is a semiconductor device that suppresses low-power components.

[0020] In each of the above configurations, a semiconductor device having an addition method and a housing in which the semiconductor device is housed Electronic devices having the above features are preferred.

[0021] A semiconductor device having a neural network, wherein the neural network is multiplied It has an arithmetic circuit, and the multiplication circuit has a first to fourth transistor. A multiplier circuit outputs the result of multiplication as an output current by applying weight potentials and data potentials. It has the function of applying a first potential to the gate of the first transistor. The second transistor has the function of conducting the first current, and the second transistor has the function of the second transistor's gate The third transistor has the function of conducting a second current when a second potential is applied to it, and the third transistor is the third The transistor has the function of passing a third current when a third potential is applied to its gate, and the fourth current A transistor allows a fourth current to flow when a fourth potential is applied to the gate of the fourth transistor. The multiplication circuit has the function of subtracting the second and third currents from the first current, and the first current This semiconductor device obtains an output current by adding a fourth current to it.

[0022] In each of the above configurations, the first potential is the sum of the reference potential, the weighted potential, and the data potential. The first potential is generated by adding the reference potential and the data potential, and the second potential is generated by adding the reference potential and the data potential. The third potential is generated by adding the reference potential and the weighted potential, and the fourth potential is generated by adding the reference potential. The given semiconductor device is preferred.

[0023] In each of the above configurations, the multiplication circuit is a memory cell, a reference cell, and a first programming The memory cell has a first transistor and a second programming cell. The reference cell has a second transistor, and the first programming cell has a third transistor. The second programming cell has a transistor, and the memory cell has a fourth transistor. The first potential, corresponding to the first current, is maintained, and the reference cell has a potential corresponding to the second current. The second potential is maintained, and the first programming cell maintains the third potential, which corresponds to the third current. The second programming cell is a semiconductor device that holds a fourth potential corresponding to the fourth current. It is preferable to place it there. [Effects of the Invention]

[0024] One aspect of the present invention can provide a method for adding signed integers. One embodiment of the invention provides a semiconductor device having a signed integer addition method. Alternatively, one aspect of the present invention provides a semiconductor device that reduces the power consumption of neuronal computations. This can be done. Alternatively, one aspect of the present invention can provide a novel program. Alternatively, one aspect of the present invention can provide a novel calculation method. The embodiment can provide a novel semiconductor device. Alternatively, one embodiment of the present invention provides a novel A method for driving semiconductor devices can be provided.

[0025] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be understood by those skilled in the art from the specification. These can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. Furthermore, one aspect of the present invention includes, at least, the effects listed above and / or other effects. It has at least one effect. Therefore, one aspect of the present invention may, in some cases, It may not always have the effects listed above. [Brief explanation of the drawing]

[0026] [Figure 1] A diagram illustrating the addition method. [Figure 2] A circuit diagram illustrating a semiconductor device. [Figure 3] (A) Diagram illustrating the addition method. (B) Circuit diagram illustrating the semiconductor device. [Figure 4] A diagram illustrating the addition method. [Figure 5] A block diagram illustrating a semiconductor device. [Figure 6] A block diagram illustrating a semiconductor device. [Figure 7] A circuit diagram illustrating a semiconductor device. [Figure 8] A circuit diagram illustrating a semiconductor device. [Figure 9] A circuit diagram illustrating a semiconductor device. [Figure 10] A circuit diagram illustrating a semiconductor device. [Figure 11] A circuit diagram illustrating a semiconductor device. [Figure 12] A circuit diagram illustrating a semiconductor device. [Figure 13] A block diagram illustrating a semiconductor device. [Figure 14] A circuit diagram showing an example of a memory device configuration. [Figure 15] Schematic diagram of a semiconductor device. [Figure 16] A schematic diagram of a memory device. [Figure 17] A diagram showing electronic equipment. [Figure 18] A diagram showing an example configuration of a semiconductor device. [Figure 19] A diagram showing an example of a transistor configuration. [Figure 20] A diagram showing an example of a transistor configuration. [Modes for carrying out the invention]

[0027] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. It will be readily apparent to those skilled in the art that the form and details can be varied in various ways. Therefore The present invention is not limited to the descriptions of the following embodiments. The content described in one embodiment (even a part of it) is described in that embodiment. Other content (even partial content) and / or one or more other embodiments Apply, combine, or replace the content described therein (even if only a part of it). This can be done. Note that the figures (even partial ones) described in one embodiment are: Another part of that figure, another figure (even if only a part of it) described in that embodiment, and / or In one or more other embodiments, the figures (even partially) described are combined By combining them, even more diagrams can be constructed.

[0028] Furthermore, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. This may be the case. Therefore, it is not necessarily limited to that scale. Note that the drawing is an ideal example. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings.

[0029] Furthermore, the ordinal numbers "1st," "2nd," and "3rd" used in this specification refer to the constituent elements. This note is added to avoid confusion and does not imply any numerical limitation.

[0030] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. The positional relationships are used for convenience in explaining them by referring to the drawings. The relationship changes as appropriate depending on the direction in which each component is described. Therefore, the description in the specification is not applicable. The vocabulary is not limited to the explicitly stated terms; it can be appropriately rephrased depending on the situation.

[0031] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, drain (drain terminal, drain Between the drain region (or drain electrode) and the source (source terminal, source region, or source electrode) It has a channel region, and current flows between the source and drain through the channel-forming region. It is capable of carrying current. In this specification, the channel region is defined as the current It refers primarily to the area in which water flows.

[0032] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when the circuit The direction of the current may change during operation, which can cause the current to switch positions. In detailed documents, the terms "source" and "drain" may be used interchangeably. ru.

[0033] Furthermore, in this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "has some electrical effect The term "of" is not particularly limited as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes and wiring, as well as transistors. Switching elements such as resistors, inductors, capacitors, and other various functional elements are available. This includes elements such as [specific components].

[0034] Furthermore, in this specification, "parallel" means that two straight lines have an angle of -10° or more and 10° or less. This refers to a state where objects are arranged in degrees. Therefore, it also includes cases where the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, this includes cases where the angle is between 85° and 95°.

[0035] Furthermore, in this specification, the terms "membrane" and "layer" are interchangeable. It is possible to change the term. For example, the term "conductive layer" can be changed to the term "conductive film." It may be possible to change it. Or, for example, change the term "insulating film" to "insulating layer". In some cases, it may be possible to change the terminology to this.

[0036] Furthermore, unless otherwise specified in this specification, off-current refers to the current when the transistor is turned off. This refers to the drain current when the device is in a state (also called a non-conductive state or an interrupted state). Unless otherwise specified, in an n-channel transistor, the voltage between the gate and source is V When gs is lower than the threshold voltage Vth, in a p-channel transistor, the gate and socket are... This refers to a state where the voltage Vgs between channels is higher than the threshold voltage Vth. For example, n channels. The off-current of a transistor is defined as the voltage between the gate and source (Vgs) and the threshold voltage (Vt). Sometimes, this refers to the drain current when it is lower than h.

[0037] The off-current of a transistor may depend on Vgs. Therefore, the transistor The off-current of the transistor is less than or equal to I, which means that the value of Vgs at which the off-current of the transistor is less than or equal to I. It sometimes means that it exists. The off-current of a transistor is the off-current at a given Vgs. The off current may refer to the off state at a certain state, Vgs within a predetermined range, or the off state at Vgs where a sufficiently reduced off current is obtained. There are cases where it refers to the off current in an off state such as this.

[0038] As an example, assume an n-channel transistor where the threshold voltage Vth is 0.5V, the drain current at Vgs = 0.5V is 1×10 A, the drain current at Vgs = 0.1V is 1×10 -9 A, the drain current at Vgs = -0.5V is 1×10 -1 3 A, and the drain current at Vgs = -0.8V is 1×10 -19 A, and Vg s is such that the drain current at Vgs = -0.8V is 1×10 -22 A. Since the drain current of this transistor is 1×10 A or less at Vgs = -0.5V or in the range of Vgs from -0.5V to -0.8V, there are cases where the off current of this transistor is said to be 1×10 -19 A or less. Since there exists a Vgs at which the drain current of this transistor becomes 1×10 A or less, -19 there are cases where the off current of this transistor is said to be 1×10 A or less. -22 Since there exists a Vgs at which the drain current of this transistor becomes 1×10 A or less, -22 there are cases where the off current of this transistor is said to be 1×10

[0039] Also, in this specification and the like, the off current of a transistor having a channel width W may be represented by the current value flowing per channel width W. Or it may be represented by the current value flowing through a predetermined channel width (for example, 1μm). In the latter case, the unit of the off current may be represented by a unit having a unit of current / length (for example, A / μm). The off current of a transistor may depend on temperature. In this specification, the off current

[0040] The off current of a transistor may depend on temperature. In this specification, the off current Unless otherwise specified, the device is turned off at room temperature, 60°C, 85°C, 95°C, or 125°C. It may represent electric current. Alternatively, it may indicate that the reliability of the semiconductor device containing the transistor is maintained. The temperature at which the transistor is proven, or the temperature at which the semiconductor device containing the transistor is used (e.g.) For example, it may represent the off-current at any one temperature between 5°C and 35°C. The off-current of the inverter is less than or equal to I, meaning that at room temperature, 60°C, 85°C, 95°C, and 125°C, The temperature at which the reliability of the semiconductor device, etc., containing the transistor is guaranteed, or the transistor The operating temperature of semiconductor devices containing radiators (for example, any temperature between 5°C and 35°C) There exists a value of Vgs such that the transistor's off-current at temperature 1 is less than or equal to I. It may refer to something else.

[0041] The off-current of a transistor may depend on the voltage Vds between the drain and source. In this specification, unless otherwise specified, the off-current is defined as Vds = 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, and This may represent the off-current at 20V. Or, the semiconductor containing the transistor in question. The reliability of the device, etc., is guaranteed by Vds, or the semiconductor device containing the transistor in question. It may represent the off-current at Vds used in applications such as transistor off-voltage. The current is less than or equal to I, meaning that Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V, the transistor in question The reliability of the semiconductor device, etc., is guaranteed by Vds, or the semiconductor containing the transistor. The off-current of the transistor at Vds used in conductive devices, etc., is less than or equal to I. This can sometimes refer to the existence of a Vgs value.

[0042] In the above explanation of off-current, drain may be read as source. The term "current" can also refer to the current flowing through the source of a transistor when it is in the off state.

[0043] Furthermore, in this specification, the term "leakage current" may be used interchangeably with "off-current." Furthermore, in this specification, off-current refers to, for example, when a transistor is in the off state. It can also refer to the current flowing between the source and the drain.

[0044] Voltage refers to the potential difference between two points, while electric potential refers to the electrostatic field at a given point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge within a given object. Furthermore, generally speaking, the potential difference between the potential at a certain point and a reference potential (for example, the ground potential) This is simply called electric potential or voltage, and the terms electric potential and voltage are often used as synonyms. Therefore, unless otherwise specified in this specification, potential may be read as voltage. You may substitute "voltage" with "potential."

[0045] (Embodiment 1) In this embodiment, an addition method that suppresses overflow and a function having the same addition method The semiconductor device will be explained using Figures 1 to 4.

[0046] AI, for example, deep learning, uses machine learning to achieve various results. Features can be learned from information (images, audio, big data, etc.). However, learning To do this, it is necessary to perform calculations such as multiplication, addition, and subtraction on a large amount of data. Therefore, in AI, computation is performed using a semiconductor device that has a neural network. , is preferable in terms of learning speed or power consumption. For example, a neural network is It is known to have neurons that mimic those in the human brain. The function of these neurons is, It can be replaced with the sum-of-products operation. In other words, in order to realize the function of a neuron, It is preferable to use an OR operation circuit. However, part of the operation may be performed by software (program). It may also be calculated by ).

[0047] A multiply-accumulate circuit adds multiple multiplication circuits to the result of those multiplications, which are either positive or negative integers. It has an addition circuit. An example of a sum-of-accumulate circuit is an addition circuit using signed floating-point numbers. A circuit that performs calculations, or a circuit that performs operations with signed integers, is preferred. However, signed By using floating-point arithmetic, it is possible to extract more accurate information features. However, the size of the multiply-accumulate circuit increases, and so does the power consumption. (Signed integer operations) Therefore, the configuration of the multiply-accumulate circuit can be made smaller. As a result, semiconductor devices with multiply-accumulate circuits can be made smaller, and power consumption can be reduced. .

[0048] In arithmetic operations with signed integers, when adding positive or negative integers, the order of addition is determined by the order of addition. Therefore, an adder circuit may overflow. However, the order of addition Depending on the number of steps, an overflow may not occur, and the solution can be obtained within the range of the number of digits in the adder circuit. In other words, in adder circuits that handle large amounts of data, overflow suppression is essential for obtaining the correct calculation result. This is important for that purpose. In this embodiment, an addition method that suppresses overflow, and the addition method This document describes semiconductor devices that utilize the law and their programs (software).

[0049] First, we will explain the addition method that suppresses overflow using Figure 1(A). Figure 1 (A) for example has memory M1, memory M2, memory M3, and memory M4 Here, for the sake of explanation, we will use memory M4, but instead of memory M4, Memory M1 may be reused. Alternatively, registers can be used instead of memory M1 and memory M4. It is also acceptable. Note that memory M1, memory M2, memory M3, or memory M4 are each They may be located on separate memory chips, or at least two may be on the same memory chip. It may be provided in memory M1, memory M2, memory M3, and memory The M4s are located on the same memory chip, but each is assigned to a different storage area. It's fine if you do that.

[0050] As shown in Figure 1(A), it has steps ST1 to ST5. First, Figure 1 In step ST1 of (A), memory M1 contains a sensor, output circuit, or CPU. This shows an example where data group 1 is given as input data IN1 to IN9. Now, let's explain Data Group 1. It is preferable that Data Group 1 can be classified into multiple ranges. For example, range A is the value 0 (zero), range B is the value of a positive integer, and range C This is a negative integer value.

[0051] The value of one of the data items in the data group 1 provided to memory M1 is, for example, "A" is zero. This represents a positive value, with "B1" representing a positive value and "C1" representing a negative value. Positive integers are numbers whose values ​​are within the range B, such as "B1", "B2", "B3". As shown above, the letter "B" is added to the beginning. The number after "B" represents the value. Rather, it represents a sign used to distinguish data. Similarly, negative integers are within the range C. These are numbers that have values ​​within a certain range, such as "C1", "C2", "C3", "C4", etc. The initial letter "C" is added to indicate this. The number following "C" is a symbol used to distinguish the data. It represents the number.

[0052] Next, in step ST2, the positive sign stored in memory M1 is stored in memory M2. The data within range B is saved. For example, the data in range B is "B1" and "B2". And, “B3” is saved in memory M2. Memory M3 contains the data saved in memory M1. Data within range C that has a negative sign is stored. For example, data within range C is "C 1", "C2", "C3", and "C4" are stored in memory M3. However, If there are zero data points in data group 1 stored in Mori M1, you can discard that data. That's fine. Alternatively, you could put the data into either memory M2 or memory M3. Furthermore, after data group 1 has been saved to memory M2 and memory M3, memory M1 will be... It is preferable to initialize with data in range A. Therefore, memory M1 has a reset function. It is preferable that this is done. For example, if memory M1 is a register structure, reset It is easy to implement the function. However, when new data is saved to memory M1 If the value can be overwritten, memory M1 does not necessarily need to have a reset function. stomach.

[0053] Next, in step ST3, memory M2 where data with a positive sign is stored, Alternatively, data is read from each memory location in memory M3 where data with a negative sign is stored. Add the excess.

[0054] For example, read the data for "B1" from memory M2 and the data for "C1" from memory M3. Then add them together. Therefore, "B1" which has a positive sign and "C1" which has a negative sign Add the values ​​together. The result of the addition will be a number closer to zero than either "B1" or "C1". In other words, the absolute value of the addition result will be less than "B1". Or, the absolute value of the addition result will be , it becomes smaller than the absolute value of "C1". For example, the absolute value of the data in "B1" is smaller than the absolute value of "C1". If it is greater than the absolute value of the data, the addition result will be "B11" which has a positive sign. It becomes data.

[0055] Now, let's explain "B11". "B11" is a positive value stored in memory M2. The result of adding the integer "B1" and the negative integer "C1" stored in memory M3 is within range B. This indicates that the value is within a range, such as "B11", "B12", "B13", etc. The two-digit number following the "B" represents a code used to distinguish the data.

[0056] Furthermore, when you add "B2", which has a positive sign, and "C2", which has a negative sign, The calculation result will be a number closer to zero than "B2" or "C2". In other words, addition. The absolute value of the result will be less than "B2". Or, the absolute value of the addition result will be less than "C2". It will be smaller than the absolute value. For example, if the magnitude of the absolute values ​​of each data point is the same, The summation result is zero, resulting in data "A". Also, there is "B3" which has a positive sign, and a negative sign. When you add "C3", which has a sign, to B3, the result of the addition is greater than "C3". This results in a value closer to zero. In other words, the absolute value of the addition result will be smaller than "B3". Alternatively, the absolute value of the sum will be smaller than the absolute value of "C3". For example, "C3" If the absolute value of the data in "B3" is greater than the absolute value of the data in "B3", the result of the addition will be: This will be data with a negative sign, "C11". Also, memory M3 will contain data with a "C4" sign. Despite this, there is no data to add to memory M2. If it is not available, substitute the data of "A" and add "A" and "C4". Calculate. Therefore, the result of the addition will be the data in "C4". Or, the data to be added. If there is no data, the data in "C4" will be used as the summation result.

[0057] Now, let's explain "C11". "C11" is a positive value stored in memory M2. The result of adding the integer "B3" and the negative integer "C3" stored in memory M3 is within range C. This indicates that the number has a value within a range, such as "C11", "C12", "C13", etc. The two-digit number following the "C" represents a code used to distinguish the data.

[0058] Thus, the addition result is stored in memory M4 as data group 2. The data group 2 may be stored in memory M1. By storing it in memory M1, the circuit size can be reduced. It can be made smaller and consume less power. Note that it is stored in memory M1. In this case, the number of data points is less than in step ST1. Therefore, As mentioned above, before saving data to memory M1, the data in memory M1 is initialized. It is preferable to do so.

[0059] Dataset 2 contains data with a positive sign, data with a negative sign, and data with a zero sign. It includes and. When saving data to memory M4, the number of data with a positive sign and It is preferable to count the number of data points with a negative sign and the number of data points with a negative sign. The counter CNP counts the number of data points with a positive sign, and the counter CNM counts the number of data points with a negative sign. Count the number of data points that have the value CNP. For example, in ST3, the count value is counter CNP. =1, counter CNM=2. Note that counter CNP and counter CNM can be any number It is preferable that the system can be initialized with timing and initial values.

[0060] When data is saved from memory M2 or memory M3 to memory M4, counter C Determine the counter value of NP, or counter CNM. If any of the CNM values ​​remain unchanged from their initial values, the data stored in memory M4 All elements in group 2 can be added together. In that case, after adding them all together, the calculation process is performed. The discussion ends here.

[0061] If counters CNP and CNM have been updated, proceed to the next step, ST4. In this case, for the data group 2 stored in memory M4, the data with a positive sign is stored in memory Data with a negative sign can be stored in M2 and M3. For example, memory M2 can store The data "B11", which has a positive sign and is part of the data in range B, is saved. In M3, the data in range C are “C11” and “C4”, which are negatively signed data. It is stored there. Note that in the diagram it is stored in memory M2, but it can also be stored in another memory, for example, It may also be saved in memory M5. Similarly, although it is saved in memory M3 in the diagram, another memory Mori, for example, may be saved to memory M6. Note that if it is saved to memory M2, The amount of data is less than in step ST2. Therefore, the data is stored in memory M2. It is preferable to initialize the data in memory M2 before saving the data. It is preferable to initialize the data of the M3.

[0062] Next, in step ST5, the data for “B11” is taken from memory M2, and from memory M3 Read the data from “C11” and add it. That is, “B11” has a positive sign and negative Add "C11" which has the sign of B11. The result of the addition is either "B11" or "C11". Furthermore, the value will be even closer to zero. In other words, the absolute value of the addition result will be smaller than "B11". It becomes smaller. Or, the absolute value of the addition result becomes smaller than the absolute value of "C11". For example, If the absolute value of the data in "C11" is greater than the absolute value of the data in "B11", The addition result is data with a negative sign, "C111". Next, in memory M3, When there is data in "C4" but no data to add to memory M2. Then, substitute the data for "A" as the alternative data, and add "A" and "C4". Alternatively, “C4” will be used as the sum result. Therefore, the sum result will be the data in “C4”. Yes.

[0063] Now, let's explain "C111". "C111" is stored in memory M2. The result of adding the positive integer "B11" and the negative integer "C11" stored in memory M3 is This indicates that the value is within the range C, such as "C111", "C112", "C The three-digit number following "C," such as "113," is a identifier used to distinguish data. This represents the number. Although not illustrated in Figure 1(A), the positive sign stored in memory M2 is The result of adding the data you have and the negatively signed data stored in memory M3 is, For numbers whose values ​​fall within the range B, such as "B111", "B112", "B113", etc. The notation is as shown, and the three-digit number after "B" represents a code to distinguish the data. They are doing it.

[0064] The addition result is stored in memory M4 as data group 3. At this time, data group 3 is memoized. It may also be saved to memory M1. Note that if you save to memory M1, the data in memory M1 will be saved to memory M1. It is preferable to initialize it. By saving it to memory M1, the size of the circuit can be reduced. This allows for reduced power consumption. Note that when saving to memory M4... In this case, the number of data points is smaller than in the case of step ST3. Therefore, as mentioned above... Therefore, before saving data to memory M4, initialize the data in memory M4. It is preferable.

[0065] For example, in ST5, the count values ​​will be counter CNP=0 and counter CNM=2. Therefore, since the counter CNP remains at its initial value and has not been updated, the data stored in memory M4 All values ​​in group 3 are added together, and the calculation process is complete.

[0066] By using the addition method described above, when adding multiple signed data, the problem that occurs is resolved. This can suppress overflow. By suppressing overflow, the addition process This can suppress data degradation caused by [the process]. Note that in Figure 1(A), step ST As in step 2 and step ST4, the data was temporarily saved to memory M2 and memory M3, One aspect of the present invention is not limited thereto. For example, input from memory M1 or memory M4 Select data from the force range B data and the input range C data, add them together, and make a note. You can save it as an M4 file.

[0067] Figure 1(B) shows the addition method explained in Figure 1(A) (steps ST1 to ST5) This shows an example where actual numbers are given to ). First, in step ST11, memory M Figure 1 shows an example where data group 1 is given from IN1 to IN9. Memory M1 contains For example, "-1", "-3", "2", "3", "0", "0", "-3", "- Given 1'' and ''1'', although not explained in Figure 1(A), the counter CNP, The count value may be managed using a UNTCM. For example, step ST in Figure 1(B) In 11, counter CNP=3 and counter CNM=4.

[0068] For example, range B is given as positive integers from 1 to 3, and range C is given as negative integers. A range of -1 to -3 is given. That is, if it exceeds range B or range C, then (-3 A value less than (and greater than 3) is considered an overflow. For example, memory M When "-1" and "-3" are added to the data stored in 1 in order, the result of the addition is " This would result in -4" and an overflow. However, as shown in Figures 1(A) and 1(B) In the method of adding an integer with a positive sign and an integer with a negative sign, As the calculation result approaches zero, the occurrence of overflow can be suppressed.

[0069] Next, in step ST12, memory M2 receives the positive sign stored in memory M1. Data having the negative sign is stored in memory M3. The data is saved. In other words, memory M2 stores "2", "3", and "1". Additionally, memory M3 stores "-1", "-3", "-3", and "-1".

[0070] Next, in step ST13, memory M2, in which data having a positive sign is stored, Alternatively, data from each memory in memory M3 where data with a negative sign is stored. Read and add. That is, the "2" stored in memory M2 and the value stored in memory M3 -1 is added to it. The result of the addition, 1, is stored in memory M4. Next, memory The value "3" stored in memory M2 and the value "-3" stored in memory M3 are added together. The result "0" is saved in memory M4. Next, the "1" saved in memory M2, and memory The value "-3" stored in M3 is added to the result "-2", which is then stored in memory M4. Next, since there is no data stored in memory M2, zero is given instead, The value "-1" stored in Mori M3 is added to it. Alternatively, the value "-" stored in Memory M3 is added to it. The value "1" is output as is. The summation result "-1" is stored in memory M4. If the result is "0", it is not necessary to save it to memory M4.

[0071] In this case, the counter value for integers with a positive sign is counter CNP=1, and for integers with a negative sign... The integer counter value indicates counter CNM=2. Therefore, to add again... Therefore, the data is distributed and saved from memory M4 to memory M2 and memory M3.

[0072] Next, in step ST14, "1" is stored in memory M2, and in memory M3 For this, "-2" and "-1" are preserved.

[0073] Next, in step ST15, the "1" stored in memory M2 and the stored in memory M3 The stored "-2" is added. The result of the addition, "-1", is stored in memory M4. Since there is no data stored in memory M2, zero is assigned to it instead, and memory M3 is assigned to The saved "-1" is added to it. Alternatively, the "-1" saved in memory M3 is added to it. The output is displayed as is. The addition result "-1" is saved in memory M4.

[0074] In ST15, the count values ​​become counter CNP=0 and counter CNM=2. Because the counter CNP has not been updated and remains at its initial value, all the data stored in memory M4 has been lost. Then add them together. As a result, we can calculate the sum "-2". Therefore, the positive sign By sequentially combining integers with a sign and integers with a negative sign and adding them together, over This addition method suppresses data degradation due to the flow and can calculate the correct solution.

[0075] Figure 2(A) illustrates the addition circuit 10 that has the function of the addition method shown in Figure 1(A). This is a circuit diagram. The adder circuit 10 consists of a selector 20, memory 21, counter 22, and control circuit. Path 23, Selector 24, Memory 24a, Memory 24b, Control circuit 25, Zero insertion Adding circuit 26a, zero insertion circuit 26b, adding circuit 27, adding circuit 28, and It has a circuit 29. The counter 22 is counter CNP22a and counter C It has NM22b. The adder circuit 10 also has signal line DI, signal line DR, signal line DA, Signal line DA1, signal line DA2, signal line DAP, signal line DAM, signal line FO1, signal line FO 2, Signal line FOUT1, Signal line FOUT2, Signal line DO, Signal line SEL1, Signal line SEL 2, Signal line WEP, Signal line WEM, Signal line UFP, Signal line UFM, Signal line REP, Signal line REM, signal line WER, signal line FC, signal line DUF, signal line MB1, signal line MB2, signal It has line WE, signal line IRQ, and signal line ACK.

[0076] The selector 20 is electrically connected to the memory 21 via the signal line DA. Rectifier 20 is electrically connected to counter 22 via signal line DI, and further connected via signal line SE It is electrically connected to the gate circuit 29 via L1.

[0077] Memory 21 is electrically connected to selector 24 via signal line DA1. T24 is electrically connected to memory 24a via signal line DAP, and further connected to signal line DAM It is electrically connected to memory 24b via [a certain device].

[0078] The control circuit 23 is electrically connected to the memory 21 via the signal line DA1. The control circuit 23 is electrically connected to the selector 24 via the signal line SEL2. The control circuit 23 is electrically connected to the memory 24a via the signal line WEP, and further signals It is electrically connected to memory 24b via the WEM line.

[0079] Memory 24a is electrically connected to zero insertion circuit 26a via signal line FO1. Memory 24b is connected to the zero insertion circuit 26b via the signal line FO2. They are connected by energy.

[0080] The control circuit 25 electrically connects to the memory 24a via signal line UFP and signal line REP. It is connected and further electrically connected to memory 24b via signal lines UFM and REM. The control circuit 25 connects to the zero insertion circuit 26a via the signal line MB1. Electrically connected, and further connected to the zero insertion circuit 26b via signal line MB2. The control circuit 25 is connected to the signal line DUF and is electrically connected to the counter 22. Furthermore, it is electrically connected to the adder circuit 27 and the gate circuit 29 via the signal line WER. Yes, they are.

[0081] The adder circuit 27 is electrically connected to the zero insertion circuit 26a via the signal line FOUT1. It is connected and further electrically connected to the zero insertion circuit 26b via the signal line FOUT2. The addition circuit 27 is connected to the selector 20 and counter 22 via the signal line DR. It connects to the target.

[0082] The signal line IRQ is electrically connected to the counter 22 and the control circuit 23. The calculation circuit 10 outputs signal lines ACK and DO.

[0083] Next, we will explain the functions of each. Selector 20 is the signal that is given to signal line SEL1. Depending on the number, either the input data DI or the output DR of the summing circuit 27 is selected and the signal line It can output to DA. The signal given to signal line SEL1 is written to memory 21. The signal line WE or the signal line WER for writing the output DR of the adder circuit 27 is generated. Memory 21 corresponds to memory M1 in Figure 1.

[0084] Memory 21 is DRAM (Dynamic Random Access Memory) y), or SRAM (Static Random Access Memory), etc. A storage circuit may be used, or it may be composed of registers. Memory 21 It is preferable that it has a reset function or a read reset function. The reset function allows you to reset all data stored in memory to any initial value at any time. It is possible to do this. Also, read reset means reading the data at the accessed memory address. If data is lost, this function initializes the data after it has been read.

[0085] Counter 22 receives data from signal line DI or signal line DR. For each of these, a counter CNP22a counts integers with a positive sign, and a counter counts integers with a negative sign. It has a counter CNM22b that counts integers having a number, and counter 22 is It is preferable that it has a reset function and an enable function. Also, the signal line DUF It is preferable that the counter 22 is reset by the given signal. Also, the signal line IR The signal given to Q enables counter 22, and counter 22 is enabled. The count-up begins when the condition is met.

[0086] The control circuit 23 receives data stored in memory 21 via the selector 24 into memory 24. It can be moved to a and memory 24b. The control circuit 23 provides to the signal line SEL2 The signal indicates that the data stored in memory 21 is transferred to memory 24a or memory 24b. It can be distributed. For example, the control circuit 23 determines that the data to be moved from memory 21 is correct. If it has the sign, it can be stored in memory 24a via the signal line DAP. The control circuit 23, if the data being moved from memory 21 has a negative sign, will signal line DA It can be saved to memory 24b via M. Also, the control circuit 23 controls the signal line DA1 It is preferable that the system has a function to discard zero data when the data is zero.

[0087] Memory 21, memory 24a, and memory 24b are first-in, first-out. It is preferable that the memory 21, memory 24a, and memory 24b have the following functions. It can output an underflow flag when there is no data. The fast-out function adds a read-reset function. In Figure 2, Memory 24a and memory 24b have a fast-in, fast-out function. Let's proceed with the explanation assuming that... Also, memory 21, memory 24a, and memory 24b The size can be determined as appropriate, but memory 21 is larger than memory 24a and memory 24b. A larger size is preferable. Note that memory 24a corresponds to memory M2 in Figure 1, and memory 24b This corresponds to memory M3 in Figure 1.

[0088] The control circuit 25 outputs an underflow flag to the signal line UFP from memory 24a and It is possible to monitor the state of the underflow flag output by memory 24b to signal line UFM. It can also read data from memory 24a and memory 24b and supply it to the adder circuit 27. It can be added. However, memory 24a has an underflow error on signal line UFP. If a value is output, the zero insertion circuit 26a outputs zero as alternative data. Similarly, if memory 24b outputs an underflow flag to signal line UFM. The zero insertion circuit 26b then provides zero as alternative data.

[0089] The result of the adder circuit is stored in memory 21 via signal line DR. If the addition result has a positive sign, then counter CNP22a is incremented. If the summation result has a negative sign, increment counter CNM22b. (Note) When both memory 24a and memory 24b output an underflow flag, control circuit 25 The signal is output to the signal line DUF. Counter 22 receives the signal on the signal line DUF. Therefore, counters CNP22a and CNM22b are stopped and evaluated. The determination result is notified to the control circuit 23 and the adder circuit 28 via the signal line FC. The determination result is either counter CNP22a or counter CNM2 as the first result. Either one of 2b underflowed, or the second result did not underflow. It is preferable that it be the count value of the counter.

[0090] Counter 22 is determined by the first occurrence of either counter CNP22a or counter CNM22b. If the value remains unchanged, the data stored in memory 21 will have the same sign (including zero). It can be determined by either counter CNP22a or counter CNM22b. When the initial value is set, the adder circuit 28 reads the data via the signal line DA2 and adds it. After the calculation is complete, the adder circuit 28 signals the completion of the calculation to the signal line ACK. This can notify the CPU, etc. At this time, the addition result is output to the signal line DO. However, it is preferable to latch the information in order to retain it. Furthermore, signal line DO, signal Line ACK preferably has a read-reset function.

[0091] If counter CNP22a and counter CNM22b are counting up Therefore, it can be determined that data with different codes is stored in memory 21. In this case, the control circuit 23 performs the addition operation again.

[0092] Therefore, peripheral circuits such as the CPU memorize the multiple data to be added to the adder circuit 10. The data is saved in line 21, and a signal is then applied to the signal line IRQ to open the calculation process of the adder circuit 10. The addition circuit 10 initiates the process by sending a signal to the ACK signal line when the calculation is complete. It notifies peripheral circuits such as the processor that the calculation is complete. In other words, it sets the data and executes the calculation command. By doing so, the calculation result can be obtained. During the period when the adder circuit 10 is performing calculations, the CPU These peripheral circuits can perform different processes. Furthermore, they can add positive and negative integers. This prevents overflow by performing calculations and discards data where the calculation result is zero. This semiconductor device has an adder circuit 10 that has an addition method that can reduce the amount of computation. .

[0093] Figure 2(B) shows the zero insertion circuit 26 (zero insertion circuits 26a and 26b This is a circuit diagram that explains the zero insertion circuit 26 in detail. It has 6c and switches SW0 and SW1. The gate circuit 26c has two inputs It has a power terminal and one output terminal. The output terminal of gate circuit 26c is the signal line FOU It is electrically connected to one of the T[n:0]. Also, one of the gate circuits 26c The input terminal is electrically connected to one of the signal lines FO[n:0]. The other input The terminals are electrically connected to one electrode of switch SW0 and one electrode of switch SW1. The other electrode of switch SW0 is electrically connected to wiring Vdd, and wiring V It is preferable that the dd is supplied with the high power supply voltage of the adder circuit 10. The other electrode of 1 is electrically connected to the wiring Vss, and the wiring Vss is connected to the lower end of the summing circuit 10. It is preferable that a power supply voltage, such as GND, is provided.

[0094] Switches SW0 and SW1 are controlled by the signal supplied to signal line MB. Furthermore, it is preferable that switches SW0 and SW1 operate exclusively. The gate circuit 26c turns on switch SW0 based on the signal applied to signal line MB. And, the switch SW1 can be turned off for the same period of time. The same signal as the one specified can be output to the output terminal. Also, the gate circuit 26c is connected to the signal line M The signal given to B turns switch SW0 to the OFF state, and for the same period, switch SW1 is turned OFF. It can be turned on. Therefore, zero is assigned to the signal line FOUT. The gate circuit 26c can convert any data given to the signal line FO to zero. can.

[0095] One aspect of the present invention is not limited to the summing circuit described above. For example, using a program, It may be expressed by software rather than hardware, one aspect of the present invention. The following addition method may be used.

[0096] Figure 3(A) shows an addition method that suppresses overflow, which has a different configuration from Figure 1(A). This is a diagram that explains the matter.

[0097] Figure 3(A) differs from Figure 1(A) in that it has memory M5 and memory M6. Unlike Figure 1(A), the input data, or the calculated data, is further divided into multiple ranges. The difference lies in the fact that they can be classified into categories. For example, the range in which positive integers are classified is the range It can be divided into B and range BB. Range BB has values ​​that are greater than range B. Furthermore, the range in which negative integers are classified can be divided into range C and range CC. The range CC has smaller values ​​than the range C. This indicates that there is a finer classification. Therefore, when adding, it is possible to make the result of the addition a smaller value. This further suppresses the occurrence of overflow when adding.

[0098] Figure 3(B) is a circuit diagram illustrating a semiconductor device with a different configuration from that shown in Figure 2(A). The adder circuit 10a includes the control circuit 30, selector 31, memory 31a to memory 31d, and control Circuit 32, zero insertion circuit 33a, zero insertion circuit 33b are included. This differs from the addition circuit 10 in that respect. Due to space limitations, memory 31b and memory 31c are not shown. The part is omitted. Also, the summing circuit 10a has signal line DAP1, signal line DAP2, and signal line DA M1, signal line DAM2, signal line FO1, signal line FO2, signal line FO3, signal line FO4, signal line Line WEP1, signal line WEP2, signal line WEM1, signal line WEM2, signal line UFP1, signal Line UFP2, signal line UFM1, line UFM2, signal line REP1, signal line REP2, signal The fact that it has line REM1 and signal line REM2 is different from addition circuit 10.

[0099] Control circuit 30 is different from control circuit 23 in that it corresponds to memories 31a to 31d (memories 31b and 31c are not shown). Selector 31 is different from selector 24 in that it corresponds to memories 31a to memory 31d. Memory 31a stores data within the range of range BB, memory 31b stores data within the range of range B, memory 31c stores data within the range of range C, and memory 31d stores data within the range of range CC. Control circuit 32 is different from control circuit 25 in that it corresponds to memories 31a to 31d. Zero insertion circuit 33a is different from zero insertion circuit 26a in that it corresponds to signal lines FO1 and FO2. Zero insertion circuit 33b is different from zero insertion circuit 26 b in that it corresponds to signal lines FO3 and FO4. As shown in FIG. 3(B), in the addition process, in order to further suppress overflow, it is preferable to add a memory that finely manages the input range. Since overflow is suppressed,

[0100] more accurate calculations can be performed.

[0101] FIG. 4(A) is a diagram for explaining an addition method for suppressing overflow having a configuration different from that of FIG. 1(A). <000^915>FIG. 4(A) shows an example from step ST31 to step ST33. In FIG. 1(A), integers with a positive sign and integers with a negative sign are classified. This was being done. Meanwhile, in Figure 4(A), in step ST32, an integer with a positive sign was used. This system not only classifies numbers and integers with negative signs, but also sorts them in descending order of their absolute value. This can be done by adding values ​​with different signs in descending order of absolute value. The sum of the values ​​approaches zero. As a result, the calculation precision is reduced due to overflow. Addition can be performed faster without any delays.

[0102] Note that in Figure 4(A), the data is stored separately in memory M2 and memory M3, but in the present invention... One aspect of this is not limited to this. For example, an integer with a positive sign and an integer with a negative sign Integers may be stored without classification. For example, in memory M2, the values ​​from largest to smallest... You may save up to a certain value. For example, as shown in Figure 4(B), “3”, “2”, “1 In the order of ", "0", "0", "-1", "-1", "-3", "-3", memory M2 You can store it there. Then, add the largest value and the smallest value in order. For example Add "3" and "-3", then add "2" and "-3", and then "1" and Add "-1" to it, then add "0" and "-1" together. This is the process. As a result, the number of integers with a positive sign and the number of integers with a negative sign are large. Even in cases where the results are different, processing can be done quickly. Note that in Figure 4(B), After saving the data to Mori M2, it is added, but one aspect of the present invention is not limited thereto. For example, take an appropriate number from memory M1 and sequentially find the largest value and the smallest value. You may add the values ​​together.

[0103] Furthermore, in cases like Figure 4(B), even when adding unsigned integers, This reduces the decrease in calculation accuracy due to bar flow. In other words, it reduces the loss of calculation accuracy due to positive sign integers. Numbers only (may include zero), or integers only with a negative sign (may include zero). In the case where (it may be), similar to Figure 4(B), from the largest value to the smallest value You can save the values ​​and then add the largest and smallest values ​​in order. In this case, the data is stored in memory M2 and then added; however, one aspect of the present invention is not limited to this. It is not fixed. For example, take an appropriate number from memory M1 and sequentially find the largest value and You may add it to the smallest value.

[0104] Note that step ST5 in Figure 1(A), step ST15 in Figure 1(B), and step S in Figure 3(A) In devices such as the ST25, unsigned integers are added using a method similar to that shown in Figure 4(B). This is possible. As a different example, when adding only integers with a positive sign, or when adding only negative integers Even when adding only signed integers, the same method as in Figure 4(B) can be used for unsigned integers. Integers can be added together.

[0105] This embodiment involves changes, additions, modifications, and deletions of some or all of the other embodiments. This corresponds to an application, a higher-level conceptualization, or a lower-level conceptualization. Therefore, this embodiment You may freely combine some or all of this with some or all of other embodiments, or It can be implemented by replacing it.

[0106] (Embodiment 2) In this embodiment, a semiconductor device having an adder circuit that can suppress overflow The details will be explained using Figures 5 to 13.

[0107] FIG. 5(A) is a block diagram showing a semiconductor device 80 including a neural network. The semiconductor device 80 includes, as an example, a CPU 81, a memory 82, an imaging device 83, a neural network 84, a display controller 85a, a display device 85b, and an input / output bus 86. The CPU 81, the memory 82, the imaging device 83, the neural network 84, and the display controller 85a are connected via the input / output bus 86. However, the imaging device 83 may be electrically connected to the neural network 84 without going through the input / output bus 86, and the neural network 84 may be electrically connected to the display controller 85a without going through the input / output bus 86.

[0108] FIG. 5(B) shows a configuration example in which, as an example, the imaging device 83 is connected to the neural network 84, and the neural network 84 outputs data to the CPU 81. The neural network 84 includes a multiplication cell block 84a and a driver 84d. The multiplication cell block 84a includes a plurality of neurons 84b. Each neuron 84b includes, as an example, a plurality of multiplication cells 11, a plurality of reference cells 12, an arithmetic circuit 13, and the addition circuit 10 described in FIG. 2(A). When adding by software or a program, the addition circuit 10 may

[0109] not be provided. FIG. 5(C) is a diagram for explaining the neuron 84b. The neuron 84b includes, as an example, a multiplication circuit 40 and a conversion circuit 15. The conversion The conversion circuit 15 is electrically connected to the adder circuit 10. In other words, neuron 8 4b has a multiply-add operation circuit consisting of a multiplier circuit 40 and an adder circuit 10.

[0110] Figure 6(A) shows the transistors in the multiplication cell 11. Then, by applying a weight coefficient ΔW and data ΔV to the gate of the transistor, ΔW × Δ This explains how to perform multiplication by V. The current Id flowing through the transistor is the current when the transistor saturates. When operating within a domain, it can be represented by Equation 1.

[0111] Ids = k × (Vgs - Vth) 2 (Formula 1)

[0112] The current Ids changes with Vgs. A reference voltage Vref is applied to the gate of the transistor, and Given the coefficient ΔW and the data ΔV, the current Ids is given by equation 2 and equation 1's Vg. It is necessary to substitute into s and perform the calculation. The Vgs to be substituted at this time will be Vgs1, and the calculation will be performed. Let the current Ids be denoted as current I1.

[0113] Vgs1 = Vref + ΔW + ΔV (Equation 2)

[0114] To obtain ΔW × ΔV as the multiplication result, we expand equation 1 with equation 2 substituted in. A term of ΔW × ΔV can be obtained within 5.

[0115] I1 = k × (Vref + ΔW + ΔV - Vth) 2 (Formula 3)

[0116] When the coefficient A = Vref + Vth

[0117] I1 = k × (ΔW + ΔV + A) 2 (Formula 4)

[0118] I1 = k × (A 2 +2 × A × ΔW + ΔW 2 +2 × A × ΔV + ΔV 2 (+2 × ΔW × ΔV) (Formula 5)

[0119] Similarly, if we substitute Vgs² = Vref + ΔV for Vgs in Equation 1, we can obtain the current I2. It is possible.

[0120] Furthermore, if we substitute Vgs3 = Vref + ΔW for Vgs in Equation 1, we can obtain the current I3. can.

[0121] Substituting Vgs4 = Vref for Vgs in Equation 1, we can obtain the current I4.

[0122] A obtained from equation 5 2 +2 × A × ΔW + ΔW 2 This is obtained when Vgs3 is substituted. This corresponds to current I3.

[0123] The result obtained from Equation 5 is 2 × A × ΔV + ΔV 2 This is the current I obtained when Vgs2 is substituted. It can be obtained by subtracting the current I4 obtained when Vgs4 is substituted into 2.

[0124] Therefore, in order to obtain the result of multiplication ΔW × ΔV from equation 5, the following equation 6 must hold. This is the result. In this case, I5 does not depend on the transistor's Vth.

[0125] I5=2×k×ΔW×ΔV (Formula 6)

[0126] Equation 7 holds when ΔV > 0 and ΔW > 0, or ΔV < 0 and ΔW < 0.

[0127] I1 + I4 - I2 - I3 - I5 = 0 (Equation 7)

[0128] In addition, equation 8 holds true in the cases where ΔV<0, ΔW>0, or ΔV<0, ΔW>0. To stand.

[0129] I1 + I4 - I2 - I3 + I5 = 0 (Equation 8)

[0130] In other words, to obtain the result of multiplication by ΔW × ΔV using a transistor, the current I1 to the current It can be calculated by calculating the flow rate I4.

[0131] Figure 6(B) shows currents I1 to I5 as an example. I5(7) is given by Equation 7 The direction of the current is shown, and I5(8) indicates the direction of the current in equation 8.

[0132] Figure 7(A) is a circuit diagram illustrating the multiplication circuit 40 of a sum-of-accumulate operation circuit as an example. The multiplication circuit 40, as an example, consists of a multiplication cell 11, a reference cell 12, and an arithmetic circuit 13. It has a current signal and a conversion circuit 15. An example of the conversion circuit 15 is a current signal to a voltage signal It has the function of converting to . Alternatively, as an example of the conversion circuit 15, it converts an analog signal to . It has a function to convert to a digital signal. Alternatively, an example of the conversion circuit 15 is the output signal It has a function to remove noise components. As an example of the arithmetic circuit 13, a switch S1 has a first programming cell and a second programming cell. Multiplication cell 11. Each of the reference cells 12 has a memory cell. Also, one of the multiplication circuits 40 Examples include wiring Vdd, wiring Vss, signal line SL, signal line SLR, signal line WL1, and It has a signal line WD.

[0133] Examples of memory cells in the multiplication cell 11 include transistor 41 and transistor 4 2, and a capacitive element 43. An example of a memory cell in a reference cell 12. It includes transistors 44 and 45, and a capacitive element 46. An example of the calculation circuit 13 is a transistor 47 that forms a current mirror, and a transistor It has 48. Furthermore, an example of a first programming cell is transistor 49. It has a capacitive element 50 and a switch S2. Furthermore, the second programming cell One example includes a transistor 51, a capacitive element 52, and a switch S3.

[0134] Transistors 47 through 49 are p-channel type transistors, and The other transistors are n-channel transistors.

[0135] The multiply-accumulate circuit is a transistor that contains silicon (such as single-crystal silicon) in the channel formation region. It may be constructed using a Si transistor (hereinafter also called a Si transistor), or a channel formation region It is composed of transistors containing oxide semiconductors (hereinafter also called OS transistors). This is also possible. In particular, because OS transistors have an extremely small off-current, they can hold voltage. It is suitable as a transistor. Furthermore, both Si transistors and OS transistors can be used. A sum-of-accumulate circuit may be constructed. In Figure 7(A), as an example, switch S2, switch It is preferable that transistor S3, transistor 41, or transistor 44 are OS transistors. It seems so.

[0136] Either the source or drain of transistor 41 is electrically connected to the signal line SL. The source or drain of transistor 41 is connected to the gate of transistor 42, and It is electrically connected to one of the electrodes of the capacitive element 43. Source or dot of transistor 42 One side of the rain is electrically connected to the wiring Vss. Transistor 42 source or do The other side of the rain is one electrode of switch S1, one electrode of switch S2, and the transistor Electrically connected to either the source or drain of the switch 49. The electrodes of switch S2 The other side is electrically connected to the gate of transistor 49 and one of the electrodes of capacitive element 50. The source or drain of transistor 49 is connected to the wiring Vdd, and the other is connected to the capacitive element 50. It is electrically connected to the other electrode of switch S1. The other electrode of switch S1 is connected to the input of conversion circuit 15. Power terminal, either the source or drain of transistor 51, one of the electrodes of switch S3, and is electrically connected to either the source or drain of transistor 48. The gate of the switch 51 is connected to the other electrode of the switch S3 and to one electrode of the capacitive element 52. Connected electrically. The source or drain of transistor 51 is connected to the other wire Vss, capacity The other electrode of the quantitative element 52 and one of the source or drain of the transistor 45 are electrically connected. They are connected precisely. The source or drain of transistor 48 is connected to the other wire Vdd, and It is electrically connected to either the source or drain of transistor 47. The gate of transistor 48 is the gate of transistor 47, or the source or drain of transistor 47. The other end is electrically connected to the other end of the transistor 45, and to the other end of the source or drain. The gate of transistor 45 is connected to either the source or the drain of transistor 44, and One electrode of the capacitive element 46 is electrically connected. The other electrode of the capacitive element 46 is connected to wiring W. It is electrically connected to D. The source or drain of transistor 44 is connected to the other wire SL. It is electrically connected to R.

[0137] Node FN10 is either the source or the drain of transistor 41, the other side of transistor 4 It is formed by connecting the gate of 2 and one of the electrodes of the capacitive element 43. Node FN 20 is either the source or drain of transistor 44, and the gate of transistor 45. and is formed by being connected to one of the electrodes of the capacitive element 46. Node FN30 is a The other electrode of transistor S2, the gate of transistor 49, and one electrode of capacitive element 50 It is connected and formed. Node FN40 is the other electrode of switch S3, the transistor It is formed by connecting the gate of the TA 51 and one of the electrodes of the capacitive element 52.

[0138] Here, the conversion circuit 15 will be explained using Figures 7(C), (D), and (E). An example of path 15 is that it includes an IV conversion circuit 15a and an amplification circuit 15b. The conversion circuit 15a can use resistive elements, capacitive elements, diodes, and the like. The IV conversion circuit 15a can convert current to voltage. As a result, the output signal The output can be easily extracted. Then, the output is converted to a voltage by the amplification circuit 15b. The signal can be output appropriately. An example of an amplification circuit 15b is an operational amplifier, saw A follower circuit, a common-source circuit, or a voltage follower circuit can be used. Furthermore, as shown in Figure 7(D) or Figure 7(E), the IV conversion circuit 15a is used as the operator. It can also be constructed using an amplifier and passive elements (for example, resistive or capacitive elements). Yes, it is possible. Figure 7(D) shows an IV conversion circuit using an operational amplifier and a resistor, and Figure 7(E Figure 7(D) or Figure 7(E) shows an integrating circuit using an operational amplifier and a capacitive element. As shown, by using an operational amplifier, the effect of the virtual ground is utilized, This is preferable because it allows control of the potential of the input terminal.

[0139] Next, an example of the operation of the multiplication circuit 40 will be explained using Figures 7(A) and 7(B).

[0140] First, let's explain Figure 7(A). Node FN10 has a connection to Vgs via wiring SL. 3 (=Vref+ΔW) is written, and current I3 flows through transistor 42. In FN30, a potential equivalent to the current I3 flowing through transistor 49 is transmitted via switch S2. It is given as follows. At the same time, node FN20 has Vgs4 (=Vre) via wiring SLR. f) is written, and current I4 flows through transistor 45. Current I4 is current million The node FN is copied by transistors 47 and 48, which form the r. At point 40, a potential equivalent to the current I4 flowing through transistor 51 is supplied via switch S3. It can be obtained.

[0141] Next, Figure 7(B) will be explained. Switches S2 and S3 are turned off. Then, the potential applied to node FN30 or node FN40 is stored.

[0142] Next, by varying the potential of the signal line WD by the data ΔV, node FN10 has a capacity The data ΔV is given via the quantitative element 43. That is, the potential of node FN10 is Vgs It changes from 3 to Vgs1 (=Vref+ΔW+ΔV). At the same time, node FN20, The data ΔV is supplied via the capacitive element 46. In other words, the potential of node FN10 is Vg The current changes from s4 to Vgs2 (=Vref+ΔV). The current I2 forms a current mirror. This is copied by transistors 47 and 48. Therefore, transistor 4 A current I2 can flow through 8.

[0143] Transistor 42 carries current I1, transistor 49 carries current I3, and transistor Transistor 48 can carry current I2, and transistor 51 can carry current I4. Here, By turning on switch S1, a current I5 can be supplied to the conversion circuit 15. Therefore, the result of multiplying ΔW × ΔV can be obtained as I5.

[0144] Figure 8 shows a multiplication cell 11 having multiple memory cells, and a reference cell having multiple memory cells. The difference from Figure 7(A) is that it has memory cells 12. In other words, it has multiple memory cells. Multiple currents output from the multiplication cell 11 having the following are calculated based on Kirchhoff's current law: They can be added together. Also, signal line NSEL2 is electrically connected to switch S2. Therefore, signal line NSEL3 is electrically connected to switch S3. However, multiplication cell 1 It is preferable that the number of memory cells in cell 1 and the reference cell 12 are the same. Switch S1 may use a transistor, but more preferably an analog switch. It is better to use it. Using an analog switch allows for more accurate multiplication.

[0145] Another difference is that transistor 49a of the first programming cell is connected to multiplier cell 11 It is preferable to increase the channel width of the transistor in proportion to the number of stages. When n stages of memory cells are connected in the calculation cell 11, the channel of transistor 49a The width is preferably n times the channel width of transistor 42a. It is better to make it larger than n times the channel width of transistor 42a.

[0146] The transistor 51a of the second programming cell corresponds to the number of stages of the reference cell 12. Therefore, it is preferable to increase the channel width of the transistor. When n-stage memory cells are connected in 12, the channel width of transistor 51a is Preferably, the channel width of transistor 45a is n times the channel width. More preferably, It is better to make it larger than n times the channel width of the Rangitta 45a.

[0147] Figure 9 is a circuit diagram illustrating a different arithmetic circuit 13a from Figure 8. The calculation circuit 13a further includes transistors 47a, 48a, and 4 9b, capacitive element 50a, switch S2a, transistor 51b, capacitive element 52a, and It has a switch S3a.

[0148] By using the circuit configuration shown in Figure 9, the saturation characteristics of the transistor used for the addition process can be adjusted. This allows for a flat characteristic. Therefore, the current can be copied using a current mirror, etc. In some cases, even more accurate current can be handled. Therefore, the calculation circuit 13a is used. This improves the precision of addition operations.

[0149] Figure 10(A) is a circuit diagram illustrating a multiplication circuit 40a that differs from that shown in Figure 7(A). Figure 10(A) shows that the main transistors are n-channel type transistors. Furthermore, if the switch is also constructed with n-channel transistors, all transistors are It can be constructed using only n-channel type components. In that case, the process steps can be simplified. It can be abbreviated.

[0150] An example of a multiplication circuit 40a is a multiplication cell 11a, a reference cell 12a, and an arithmetic circuit. It has 13b and a conversion circuit 15. An example of the arithmetic circuit 13b is a switch S 1. It has a first programming cell and a second programming cell. Multiplication cell 1 Cells 1a and 12a each have memory cells. Also, the multiplication circuit 40a Examples include wiring Vdd, wiring Vss, signal line SL, signal line SLR, signal line WL1, It also has a signal line WD.

[0151] An example of a memory cell in the multiplication cell 11a is transistor 61, transistor It has 62 and a capacitive element 63. An example of a reference cell 12a is a tra It has an radiator 64, a transistor 65, and a capacitive element 66. For example, transistor 72, capacitive element 73, transistor 74, capacitive element 75, It includes a transistor 76, a capacitive element 77, and switches S7 to S15. Furthermore, an example of a first programming cell is a transistor 67, a capacitive element 68, and It has a switch S4. Furthermore, as an example of a second programming cell, Transistor 69, capacitive element 70, transistor 71, switch S5, and switch S6 I have it.

[0152] In Figure 10(A), switches S4, S5, S12, and S14 are shown. Switch S15, transistor 61, or transistor 64, for example, OS Transistor It is preferable that it be a t. OS transistors have an extremely small off-current, so they can maintain the voltage. It is suitable as a transistor.

[0153] The multiply-accumulate circuit may be constructed using Si transistors, or OS transistors. This configuration is also possible. In particular, OS transistors have an extremely small off-current, so multiply-accumulate operations It is suitable as a transistor for constituting the memory of the circuit. Note that Si transistors and OS A sum-of-accumulate circuit may be constructed using both transistors.

[0154] Either the source or the drain of transistor 61 is electrically connected to the signal line SL. The source or drain of transistor 61 is connected to the gate of transistor 62, and It is electrically connected to one of the electrodes of the capacitive element 63. The source or drive of transistor 62 One side of the rain is electrically connected to the wiring Vss. Transistor 62's source or do The other end of the rain is one electrode of the capacitive element 68, or the source or drain of transistor 67. On the other hand, one electrode of switch S1, one electrode of switch S6, and switch S10 It is electrically connected to one of the electrodes of the transistor 67. The gate of transistor 67 is connected to the electrode of the capacitive element 68. On the other hand, it is electrically connected to one of the electrodes of switch S4. The other end of the drain is electrically connected to the other electrode of switch S4 and the wiring Vdd. It is being done.

[0155] The other electrode of switch S1 is electrically connected to conversion circuit 15. Transistor 64 Either the source or drain of the transistor 64 is electrically connected to the SLR wiring. The other end of the source or drain is the gate of transistor 65 and the power of capacitive element 66. It is electrically connected to one of the poles. Either the source or the drain of transistor 65 is connected It is electrically connected to the line Vss. The source or drain of transistor 65 is connected to the other side. It is electrically connected to one electrode of switch S7 and to one electrode of switch S9. The other electrode of switch S7 is either the source or drain of transistor 72, and the capacitive element 7 One electrode of 3 and one electrode of switch S8 are electrically connected. Transistor The other end of the 72 source or drain is connected to one of the electrodes of switch S15, and the wiring Vdd It is electrically connected to the other electrode of the capacitive element 73. It is electrically connected to the other electrode of the switch S15.

[0156] The other electrode of switch S9 is connected to either the source or drain of transistor 74, and is a capacitance. One electrode of element 75 and one electrode of switch S11 are electrically connected. The source or drain of the converter 74 is connected to one of the electrodes of the switch S14, and the other is connected to the source or drain of the converter 74. It is electrically connected to line Vdd. The gate of transistor 74 is connected to the electrodes of capacitive element 75. One side is electrically connected to the other electrode of switch S14. The electrode of switch S11 The other side refers to the other electrode of switch S10, the one electrode of capacitive element 77, and the transistor. It is electrically connected to either the source or drain of transistor 76. The other end of the drain is electrically connected to one of the electrodes of switch S12. The gate of TA76 is connected to the other electrode of the capacitive element 77 and to one electrode of the switch S13. They are electrically connected. The other electrode of switch S12 is connected to the other electrode of switch S13, and The wiring Vdd is electrically connected. The other electrode of switch S8 is connected to transistor 71. It is electrically connected to either the source or the drain, and to one of the electrodes of switch S5. The gate of transistor 71 is connected to one electrode of capacitive element 70 and the other electrode of switch S5. and is electrically connected to the gate of transistor 69. The source of transistor 69 also One side of the drain is electrically connected to the other electrode of switch S6. Transistor 7 The other end of the source or drain of 1 is the other end of the electrode of the capacitive element 70, and the other end of the transistor 69 is the source It is electrically connected to the other end of the drain or the wiring Vss.

[0157] Node FN50 is either the source or the drain of transistor 61, the other side of transistor 6 It is formed by connecting the gate of 2 and one of the electrodes of the capacitive element 63. Node FN 60 is the source or drain of transistor 64, and the gate of transistor 65. and is formed by being connected to one of the electrodes of the capacitive element 66. Node FN70 is a tra The gate of the inverter 67, the other electrode of the capacitive element 68, and one electrode of the switch S4 It is formed by being connected. Node FN80 is the gate of transistor 71, and capacitive element 7 One electrode of 0, the other electrode of switch S5, and the gate of transistor 69 are connected. It is formed by being formed.

[0158] Next, using Figures 10(A), 10(B), and 11, we will explain the operation of the multiplication circuit 40a. Let me give you an example.

[0159] First, let's explain Figure 10(A). Switch S4, switch S7, and switch Turn on switch S15. Connect Vgs3 (=Vre) to node FN50 via wiring SL. f + ΔW) is written, and current I3 flows through transistor 62. The potential corresponding to the current I3 flowing through transistor 67 is supplied via switch S4. At the same time, Vgs4 (=Vref) is written to node FN60 via wiring SLR. Occasionally, current I4 flows through transistor 65. Current I4 flows through switch S7. Current also flows through the transistor 72. Therefore, the capacitive element 73 has a potential equivalent to the current I4. It is given via S15.

[0160] Next, switch S4, switch S7, and switch S15 are turned off, and node F The potentials applied to N70 and the capacitive element 73 are stored.

[0161] Next, Figure 10(B) will be explained. Switches S5 and S8 are set to the ON position. Node FN80 is given a potential equivalent to the current I4 flowing through transistor 71. It can be done.

[0162] Next, by varying the potential of the signal line WD by the data ΔV, node FN50 becomes a capacitance. The data ΔV is supplied via element 63. In other words, the potential of node FN50 is Vgs3 It changes from Vgs1 (=Vref+ΔW+ΔV). At the same time, node FN60 changes the capacity The data ΔV is supplied via element 66. That is, the potential of node FN60 is Vgs4 It changes from Vgs2 (=Vref+ΔV).

[0163] Next, turn on switches S9, S11, S13, and S14. To achieve this state, a potential equivalent to the current I2 flowing through transistor 74 is applied to the capacitive element 75. Because switches S13 and S14 are ON, the capacitive element 77 is charged. The same potential as the capacitance element 75 is applied. Therefore, the switch S14 and the capacitance element 75 are provided. It is not necessary; instead, the gate and source of transistor 74 are also available. Alternatively, the same operation can be achieved even if the other end of the drain is connected to wiring Vdd.

[0164] Next, Figure 11 will be explained. Switch S9, Switch S11, Switch S13, Switch S14 is turned off. Node FN80 stores the given potential. Next, switch S6, switch S10, and switch S12 are turned ON.

[0165] Transistor 62 carries current I1, transistor 67 carries current I3, and the transistor Transistor 76 can conduct current I2, and transistor 69 can conduct current I4. Here, By turning on switch S1, a current I5 can be supplied to the conversion circuit 15. Therefore, the result of multiplying ΔW × ΔV can be obtained as I5.

[0166] Figure 12 shows a multiplication cell 11a having multiple memory cells, and a lift cell having multiple memory cells. It differs from Figure 8 in that it has a logic cell 12a and an arithmetic circuit 13b. Line NSEL4 is electrically connected to switch S4, and signal line NSEL5 is connected to switch S 7, and electrically connected to switch S15, the signal line NSEL6 is connected to switch S9, The switch S11 and switch S13 are electrically connected, and the signal line NSEL7 is connected to the switch. The signal line NSEL8 is electrically connected to switch S5 and switch S8, It is electrically connected to switches S6, S10, and S12. Line NSEL4 and signal line NSEL5 may be treated as a single signal line.

[0167] However, the number of memory cells in the multiplication cell 11a and the reference cell 12a are the same. It is preferable that there be a transistor. Also, a transistor may be used for switch S1, but it is more preferable. It is better to use an analog switch. Using an analog switch will result in greater accuracy. Multiplication is possible.

[0168] Another difference is that transistor 67a of the first programming cell is connected to multiplication cell 11 It is preferable to increase the channel width of the transistor in proportion to the number of stages a. Therefore, When n stages of memory cells are connected in the multiplication cell 11a, the chain of transistor 67a Preferably, the channel width is n times the channel width of transistor 62a. More preferably... It is preferable that the value of the channel width of transistor 62a be greater than n times the channel width of transistor 62a.

[0169] The transistor 69a of the second programming cell corresponds to the number of stages of the reference cell 12a. Therefore, it is preferable to increase the channel width of the transistor. When n stages of memory cells are connected in cell 12a, the channel of transistor 69a The width is preferably n times the channel width of transistor 65a. It is preferable to make it larger than n times the channel width of transistor 65a.

[0170] Similarly, transistors 71a, 72a, 74a, and The channel width of transistor 76a is greater than n times the channel width of transistor 65a. It is preferable to do so.

[0171] Figure 13 shows a different neural network 84c from the block diagram shown in Figure 5(B). The difference from Figure 5 is that in the neurons shown in Figure 13, the reference cell 12 and The difference lies in the fact that they share the same arithmetic circuit 13. Each neuron's memory cell is the target of the calculation. The memory cells are connected via one of the switches 90(1) to 90(i). This is possible. By sharing the reference cell 12 and the arithmetic circuit 13, the neurons Implementation density is improved, allowing for more calculations to be performed.

[0172] This embodiment involves changes, additions, modifications, and deletions of some or all of the other embodiments. This corresponds to an application, a higher-level conceptualization, or a lower-level conceptualization. Therefore, this embodiment You may freely combine some or all of this with some or all of other embodiments, or It can be implemented by replacing it.

[0173] (Embodiment 3) In this embodiment, using Figure 14, an aspect of the present invention is shown in which an oxide is used as a semiconductor. Memory devices to which transistors (OS transistors) and capacitive elements are applied (hereinafter, This section will explain the OS memory device, which is sometimes called the OS memory device. This is a memory device having a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. Because the off-current of the S transistor is extremely small, the OS memory device has excellent retention characteristics. It can function as non-volatile memory.

[0174] <Example of a storage device configuration>

[0175] Figure 14 shows the memories M1 to M3 described in Embodiment 1, and the memory described in Embodiment 2. This section describes an example configuration of a memory cell (MC) that can be applied to a multiplication circuit.

[0176] [DOSRAM] Figures 14(A) to (C) show examples of circuit configurations for memory cells (MC) of DRAM. In the above, DRAM using a 1OS transistor 1 capacitance element type memory cell is used in DOS RAM(Dynamic Oxide Semiconductor Random A It is sometimes called a success memory. Figure 14(A) shows memory cell 147 Device 1 has a transistor T1 and a capacitive element CA. Note that transistor T1 is a ge It has a tailgate (sometimes called a front gate) and a back gate.

[0177] The first terminal of transistor T1 is connected to the first terminal of capacitive element CA, and transistor T The second terminal of 1 is connected to wiring BIL, and the gate of transistor T1 is connected to wiring WOL. Next, the back gate of transistor T1 is connected to wiring BGL. Capacitive element C The second terminal of A is connected to wiring CAL.

[0178] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, a low-level potential is applied to the wiring CAL. It is preferable to do so. Wiring BGL applies potential to the back gate of transistor T1. It functions as a wiring. By applying an arbitrary potential to wiring BGL, the transient The threshold voltage of T1 can be increased or decreased.

[0179] Furthermore, the memory cell MC is not limited to memory cell 1471, and the circuit configuration can be changed. This is possible. For example, a memory cell MC is like the memory cell 1472 shown in Figure 14(B). In this configuration, the back gate of transistor T1 is connected to the WOL wiring instead of the BGL wiring. It may also be made into a memory cell MC, as shown in Figure 14(C). As shown in 73, a single-gate transistor, that is, a transistor without a back gate, A memory cell composed of ZISTA T1 may also be used.

[0180] By using an OS transistor as transistor T1, the transistor T1 The leakage current can be made very low. In other words, the data written to the transistor T Because it can be retained for a long time by method 1, the frequency of refreshing the memory cell is reduced. This can be done. Furthermore, it eliminates the need for memory cell refresh operations. Furthermore, because the leakage current is very low, memory cell 1471, memory cell 1472, memory cell For the 1473, it can hold multi-level data or analog data.

[0181] Furthermore, in DOSRAM, although not shown in the diagram, there is a layer overlapping memory cell 1471. By using a configuration that includes a sense amplifier, the bit line can be shortened. This reduces the bit line capacity, thereby lowering the memory cell retention capacity.

[0182] [NOSRAM] Figures 14(D) to (H) show a gain cell type memory cell with two transistors and one capacitance element. An example of a circuit configuration is shown. As shown in Figure 14(D), the memory cell 1474 is connected to transistor T2, It has a transistor T3 and a capacitive element CB. Transistor T2 is the front It has a gate (sometimes simply called a gate) and a back gate. In this configuration, transistor T2 has a gain cell type memory cell using an OS transistor. The memory device is NOSRAM (Nonvolatile Oxide Semiconductor). It is sometimes referred to as `uctor RAM`.

[0183] The first terminal of transistor T2 is connected to the first terminal of the capacitive element CB, and transistor T The second terminal of 2 is connected to the wiring WBL, and the gate of transistor T2 is connected to the wiring WOL. Next, the back gate of transistor T2 is connected to wiring BGL. Capacitive element C The second terminal of B is connected to wiring CAL. The first terminal of transistor T3 is connected to wiring R. The second terminal of transistor T3 is connected to BL and the wiring SL is connected to transistor T The gate of 3 is connected to the first terminal of the capacitive element CB.

[0184] Wiring WBL functions as the write bit line, and wiring RBL functions as the read bit line. The wiring WOL functions as a word line. The wiring CAL is the second of the capacitive element CB. It functions as wiring to apply a predetermined potential to the terminal. When writing data, data retention During the process, when reading data, a low-level potential is applied to the wiring CAL. Preferred. Wiring BGL is wiring for applying potential to the back gate of transistor T2. It functions as follows: By applying an arbitrary potential to the wiring BGL, the transistor T2 The threshold voltage can be increased or decreased.

[0185] Furthermore, the memory cell MC is not limited to memory cell 1474, and the circuit configuration can be changed as appropriate. This is possible. For example, the memory cell MC is the memory cell 1475 shown in Figure 14(E) Therefore, the back gate of transistor T2 is connected to the WOL wiring instead of the BGL wiring. It may also be configured as follows. For example, the memory cell MC is the memory cell shown in Figure 14(F). Like the 1476, it is a single-gate transistor, meaning it does not have a back gate. A memory cell composed of transistor T2 may also be used. Alternatively, for example, a memory cell MC As shown in Figure 14(G), memory cell 1477 has wiring WBL and wiring RBL connected to a single unit. It is also acceptable to configure it as a wiring BIL (Building Inspection Unit).

[0186] When the semiconductor device shown in the above embodiment is used as a memory cell 1474, etc., a transistor Transistor 41 is used as T2, and transistor 42 is used as transistor T3. Capacitive element 43 can be used as the capacitive element CB. Transistor T2 can be OS By using a transistor, the leakage current of transistor T2 can be made very low. This allows the written data to be held for a long time by transistor T2. This allows for a reduction in the frequency of memory cell refresh. This eliminates the need for refreshing the Morisel. Furthermore, it offers extremely low leakage current. Therefore, the memory cell 1474 can store multi-level data or analog data. The same applies to memory cells 1475 to 1477.

[0187] Note that transistor T3 may also be a Si transistor. The transistor type may be n-channel or p-channel. In some cases, the field-effect mobility may be higher than that of an OS transistor. Therefore, readout transistor A Si transistor may be used as transistor T3, which functions as an inverter. Furthermore, by using a Si transistor for transistor T3, stacking is performed on top of transistor T3. By providing transistor T2, the occupied area of ​​the memory cell can be reduced, and storage This allows for a higher level of integration of the device.

[0188] Also, transistor T3 may be an OS transistor. Transistors T2, M3 When an OS transistor is used, memory cells 1474 to 1477 are n-type transistors. It can be constructed using only transistors.

[0189] Furthermore, Figure 14(H) shows an example of a gain cell type memory cell with 3 transistors and 1 capacitance element. As shown in Figure 14(H), the memory cell 1478 consists of transistors T4 to T6, and It has a capacitance element CC. Capacitance elements CC are provided as appropriate. Memory cell 1478 is connected to wiring BI Electrically connected to L, RWL, WWL, BGL, and GNDL. Wiring GNDL This is a wiring that provides a low-level potential. Furthermore, memory cell 1478 is replaced with wiring BIL. The wiring may also be electrically connected to RBL and WBL.

[0190] Transistor T4 is an OS transistor with a back gate, and the back gate is It is electrically connected to wiring BGL. Note that the back gate and gate of transistor T4 They may be electrically connected to each other. Alternatively, transistor T4 may have a back gate. It's not necessary.

[0191] Note that transistors T5 and T6 are either n-channel Si transistors or p-channel Si transistors, respectively. A channel-type Si transistor is also acceptable. Alternatively, transistors T4 to T6 can be OS transistors. A zista would also be acceptable; in this case, the memory cell 1478 is constructed using only n-type transistors. It is possible.

[0192] The configuration of memory cells 1471 to 1478, etc., shown in this embodiment is as follows: The above is not limited to these circuits, and the wiring and circuits connected to them. The arrangement or function of elements, etc., may be changed, deleted, or added as necessary.

[0193] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. This is possible.

[0194] This embodiment involves changes, additions, modifications, and deletions of some or all of the other embodiments. This corresponds to an application, a higher-level conceptualization, or a lower-level conceptualization. Therefore, this embodiment You may freely combine some or all of this with some or all of other embodiments, or It can be implemented by replacing it.

[0195] (Embodiment 4) In this embodiment, Figure 15 shows a chip 1200 on which the semiconductor device of the present invention is mounted. Here is an example. Chip 1200 has multiple circuits (systems) mounted on it. Uni, the technology of integrating multiple circuits (systems) onto a single chip is called system-on-chip ( It is sometimes referred to as a System on Chip (SoC).

[0196] As shown in Figure 15(A), the chip 1200 is a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing Unit) 1212, or analog processing unit 1213, memory controller 1214, The GPU has an interface 1215 or a network circuit 1216, etc. It is preferable to have a holistic network.

[0197] The chip 1200 is provided with bumps (not shown), as shown in Figure 15(B), The first part of Printed Circuit Board (PCB) 1201 It connects to the surface. Also, on the back surface of the first surface of PCB1201, there are multiple bumps 1202. It is provided and connects to the motherboard 1203.

[0198] Motherboard 1203 includes memory devices such as DRAM 1221 and flash memory 1222. A place may be provided. For example, the DOSR shown in the previous embodiment may be placed in the DRAM1221. AM can be used. Also, for example, in the flash memory 1222, the above embodiment The NOSRAM shown can be used.

[0199] CPU1211 preferably has multiple CPU cores. Also, GPU1212 It is preferable that it has multiple GPU cores. Also, CPU1211 and GPU1 Each of 212 may have memory to temporarily store data. Or, CP The memory common to both U1211 and GPU1212 is provided on chip 1200. Alternatively, the aforementioned NOSRAM or DOSRAM can be used for this memory. Furthermore, the GPU1212 is suitable for parallel computation of large amounts of data, and is ideal for image processing and multiply-accumulate operations. It can be used. The GPU1212 can be used with an image processing circuit using the oxide semiconductor of the present invention. By providing a multiply-accumulate circuit, image processing and multiply-accumulate operations can be performed with low power consumption. This will become possible.

[0200] Furthermore, because the CPU1211 and GPU1212 are located on the same chip, The wiring between CPU1211 and GPU1212 can be shortened, and CPU1211 or Data transfer to GPU1212, and notes held by CPU1211 and GPU1212. Data transfer between the two systems, and after calculations on GPU1212, data transfer from GPU1212 to CPU12 The transfer of calculation results to 11 can be done at high speed.

[0201] The analog processing unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital / digital) conversion circuit. It has one or both of the digital / analog conversion circuits. Also, analog arithmetic unit 1213 The above-mentioned sum-of-accumulate circuit may be provided.

[0202] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. It also has a circuit that functions as an interface for the flash memory 1222.

[0203] Interface 1215 is for display devices, speakers, microphones, cameras, and controllers. It has an interface circuit for connecting to external devices such as a torpedo. A controller is a motor This includes mice, keyboards, game controllers, etc. USB (Universal Serial Bus), HDMI (registered trademark) (H (using igh-Definition Multimedia Interface, etc.) It is possible to be there.

[0204] The network circuit 1216 is a LAN (Local Area Network), etc. It has a network circuit. It may also have a circuit for network security. stomach.

[0205] The above circuit (system) can be formed on chip 1200 using the same manufacturing process. It is possible. Therefore, even if the number of circuits required for chip 1200 increases, the manufacturing process does not need to be increased. This eliminates the need for additional processing, allowing for the low-cost manufacturing of the Chip 1200.

[0206] PCB1201 equipped with chip 1200 having GPU1212, DRAM122 1, and the motherboard 1203 equipped with flash memory 1222, GPU module It can be called Lure 1204.

[0207] The GPU module 1204 has a chip 1200 that uses SoC technology, Its size can be reduced. Also, because it excels at image processing, smart Phones, tablet devices, laptop PCs, portable (take-out) game consoles, etc. It is suitable for use in portable electronic devices. Also, a multiply-accumulate circuit using the GPU1212. This leads to the development of deep neural networks (DNNs) and convolutional neural networks. (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can perform calculations such as those for machine learning (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is the AI ​​chip, or the GPU module 1204 is the AI ​​system module. It can be used as a joule.

[0208] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0209] (Embodiment 5) In this embodiment, regarding the application example of a memory device using the semiconductor device shown in the previous embodiment, Let me explain. The semiconductor device shown in the above embodiment is, for example, used in various electronic devices (for example, information Terminals, computers, smartphones, e-readers, digital cameras (including video cameras) This can be applied to storage devices (including recording and playback devices, navigation systems, etc.). Secondly, computers include tablet computers, notebook computers, and This includes not only desktop computers but also large computers such as server systems. Alternatively, the semiconductor device shown in the previous embodiment may be a memory card (for example, S Various types of removable media such as D cards, USB memory sticks, and SSDs (Solid State Drives) This applies to bubble storage devices. Figure 16 schematically shows several configuration examples of removable storage devices. As shown above, for example, the semiconductor device shown in the above embodiment is a packaged memory chip It is processed into plastic and used in various storage devices and removable memory.

[0210] Figure 16(A) is a schematic diagram of a USB memory device. The USB memory device 1100 is housed in a casing 1101 It has a cap 1102, a USB connector 1103, and a circuit board 1104. Circuit board 110 4 is housed in the casing 1101. For example, the circuit board 1104 contains the memory chip 110 5. Controller chip 1106 is installed. Memory chip 1 on board 1104 The semiconductor device shown in the above embodiment can be incorporated into 105, etc.

[0211] Figure 16(B) is a schematic diagram of the external appearance of an SD card, and Figure 16(C) shows the internal structure of an SD card. This is a schematic diagram of the structure. The SD card 1110 consists of a housing 1111, a connector 1112 and a base It has a board 1113. The circuit board 1113 is housed in the housing 1111. For example, circuit board 11 The memory chip 1114 and the controller chip 1115 are mounted on component 13. By also providing a memory chip 1114 on the back side of the circuit board 1113, the SD card 1110 The capacity can be increased. Also, a wireless chip with wireless communication capabilities is provided on the circuit board 1113. This may be done. This allows wireless communication between the host device and the SD card 1110 to be performed. The memory on board 1113 can be read from and written to the Mori chip 1114. The semiconductor device shown in the above embodiment can be incorporated into chip 1114 or the like.

[0212] Figure 16(D) is a schematic diagram of the external appearance of an SSD, and Figure 16(E) is a schematic diagram of the internal structure of an SSD. This is a diagram of the equation. The SSD1150 consists of a housing 1151, a connector 1152, and a circuit board 1153. It has. The circuit board 1153 is housed in the casing 1151. For example, the circuit board 1153 has The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is the work memory of the controller chip 1156. For example, a DOSRAM chip can be used. There is also a memory chip 11 on the back side of the circuit board 1153. By adding 54, the capacity of SSD1150 can be increased. (Note on board 1153) The semiconductor device shown in the above embodiment can be incorporated into a rechip 1154 or the like.

[0213] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. This is possible.

[0214] (Embodiment 6) <Electronic equipment> A semiconductor device according to one aspect of the present invention can be used in various electronic devices. Figure 17 shows A specific example of an electronic device using a semiconductor device according to one aspect of the present invention is shown.

[0215] Figure 17(A) shows the monitor 830. The monitor 830 consists of a display unit 831, a housing 832, It has a speaker 833, etc. Furthermore, it has an LED lamp, operation keys (power switch, or operation key). It may include a switch, connection terminals, various sensors, a microphone, etc. The monitor 830 can also be operated using the remote control unit 834.

[0216] Furthermore, the monitor 830 can receive broadcast signals and function as a television device. Cut.

[0217] The broadcast signals that Monitor 830 can receive include those transmitted from terrestrial or satellite sources. These are some examples. Furthermore, there are analog broadcasts, digital broadcasts, and other types of broadcast signals. This includes broadcasts with video and audio, or audio only. For example, in the UHF band (300MHz and above). Specific frequencies within the 3GHz or VHF band (30MHz to 300MHz) It can receive broadcast radio waves transmitted in multiple frequency bands. Also, for example, in multiple frequency bands By using multiple received data sets, the transfer rate can be increased, allowing for more information to be transmitted. This allows us to obtain information. This enables us to display video with a resolution exceeding Full HD. The display unit 831 can display the following: for example, 4K-2K, 8K-4K, 16K-8K. It can display video with a resolution of , or higher.

[0218] Also, the internet, LAN (Local Area Network), and Wi-Fi It is transmitted via data transmission technologies over computer networks such as i(registered trademark). The configuration may also involve using the broadcast data to generate an image to be displayed on the display unit 831. In that case, the monitor 830 does not need to have a tuner.

[0219] Furthermore, the monitor 830 can be connected to a computer and used as a computer monitor. This is possible. Furthermore, the monitor 830 connected to the computer can be viewed by multiple people simultaneously. This allows it to be used in a conference system. Furthermore, it can be used with computers via a network. By displaying information and connecting the monitor 830 itself to the network, the monitor 830 can be telecommunicated. It can be used in video conferencing systems.

[0220] Furthermore, the Monitor 830 can also be used as digital signage.

[0221] For example, it can be used in a drive circuit for a display unit or an image processing unit of a semiconductor device according to one aspect of the present invention. This can be done. One embodiment of the present invention can be used in a drive circuit for a display unit or in an image processing unit of a semiconductor device. This enables high-speed operation and signal processing with low power consumption.

[0222] Furthermore, an AI system using a semiconductor device according to one aspect of the present invention is provided in the image processing unit of monitor 830. By using it, image processing such as noise reduction, gradation conversion, color correction, and brightness correction can be performed. It can perform image processing. It can also perform pixel interpolation processing associated with resolution upconversion, It can perform inter-frame interpolation processing associated with upconverting frame frequencies. Furthermore, the grayscale conversion process not only converts the number of grayscale levels in an image, but also increases the number of grayscale levels. It can interpolate the tonal values ​​of the combination. It can also widen the dynamic range, such as high-dynamics. High Dynamic Range (HDR) processing is also included in the grayscale conversion process.

[0223] The video camera 2940 shown in Figure 17(B) consists of a housing 2941, a housing 2942, and a display unit 2 It has 943, an operating switch 2944, a lens 2945, and a connecting part 2946, etc. The switch 2944 and lens 2945 are provided on the housing 2941, and the display unit 29 43 is located in the housing 2942. Also, the video camera 2940 is located in the housing 2941. It has an antenna, battery, etc. inside. And housings 2941 and 2942 are connected. They are connected by part 2946, and the angle between housing 2941 and housing 2942 is the connection part 2 The structure can be changed by 946. Casing 2941 vs. Casing 2942 Depending on the angle, the orientation of the image displayed on the display unit 2943 can be changed, and the image can be shown or hidden. It is possible to switch between these.

[0224] For example, it can be used in a drive circuit for a display unit or an image processing unit of a semiconductor device according to one aspect of the present invention. This can be done. One embodiment of the present invention can be used in a drive circuit for a display unit or in an image processing unit of a semiconductor device. This enables high-speed operation and signal processing with low power consumption.

[0225] Furthermore, an AI system using a semiconductor device according to one aspect of the present invention is used to capture the image of a video camera 2940. By using it in the image processing unit, the video camera 2940 can capture images according to the surrounding environment. Specifically, it allows you to take photos with the optimal exposure depending on the ambient light. Also, in backlit situations... When shooting in different lighting conditions, such as indoors and outdoors, or when shooting in various locations, high-dip ray is used. It can perform high-resolution (HDR) shooting.

[0226] Furthermore, the AI ​​system can learn the photographer's habits and assist them during shooting. Physically, it learns the photographer's camera shake habits and corrects camera shake during shooting, thus improving the image quality of the captured image. The image can be made to contain as little image distortion due to camera shake as possible. Also, during shooting When using the zoom function, adjust the lens orientation so that the subject is always in the center of the image. It can control things like that.

[0227] The information terminal 2910 shown in Figure 17(C) consists of a housing 2911, a display unit 2912, and a microphone 29 17. Speaker unit 2914, camera 2913, external connection unit 2916, and operation switch It has 2915, etc. The display unit 2912 has a display panel and a flexible substrate. It is equipped with a touchscreen. In addition, the information terminal 2910 has an antenna inside the housing 2911. It is equipped with a battery, etc. The information terminal 2910 is, for example, a smartphone, mobile phone, tablet. Used as a redline information terminal, tablet personal computer, e-book reader, etc. It is possible.

[0228] For example, a storage device using a semiconductor device according to one aspect of the present invention is the information terminal 2910 described above. It can retain control information and control programs for extended periods.

[0229] Furthermore, an AI system using a semiconductor device according to one aspect of the present invention is used in the image processing of an information terminal 2910. By using it in the chemistry department, it can perform noise reduction, grayscale conversion, color correction, brightness correction, etc. It can perform image processing. It can also perform pixel interpolation processing associated with resolution upconversion. This can involve performing inter-frame interpolation processing associated with upconverting frame frequencies. Yes, it is possible. Furthermore, the grayscale conversion process not only converts the number of grayscale levels in an image, but also increases the number of grayscale levels. It can interpolate gradation values ​​in cases where the dynamic range is widened. Dynamic Range (HDR) processing is also included in the grayscale conversion process.

[0230] Furthermore, the AI ​​system learns the user's habits and assists in operating the information terminal 2910. It can do this. The information terminal 2910 equipped with an AI system can track the user's finger movements and It can predict touch input based on eye movements and other factors.

[0231] The laptop personal computer 2920 shown in Figure 17(D) has a casing 2921 It includes a display unit 2922, a keyboard 2923, and a pointing device 2924, etc. In addition, the laptop personal computer 2920 is located inside the case 2921. It is equipped with an antenna, battery, etc.

[0232] For example, a memory device using a semiconductor device according to one aspect of the present invention is a laptop-type personal The control information and control programs of the computer 2920 can be stored for a long period of time. .

[0233] Furthermore, an AI system using a semiconductor device according to one aspect of the present invention can be installed on a laptop computer. By using it in the image processing unit of computer 2920, noise reduction processing, grayscale conversion processing, and color It can perform image processing such as tone correction and brightness correction. It can also upsize the resolution. Inter-pixel interpolation processing associated with conversion, and inter-frame interpolation associated with frame frequency upconversion. Interpolation processing can be performed. Additionally, grayscale conversion processing converts the number of grayscale levels in an image. Furthermore, it can interpolate gradation values ​​when increasing the number of gradations. High dynamic range (HDR) processing, which expands the dynamic range, is also included in the gradation conversion process. It can be done.

[0234] Furthermore, the AI ​​system learns the user's habits and uses a laptop-type personal computer. It can assist in the operation of the Ta2920. A laptop equipped with an AI system. The personal computer 2920 displays information based on the user's finger movements and gaze. It can predict touch input to 22. Also, in text input, past It predicts input based on text input information, as well as surrounding text and images such as photos, and assists in conversion. Perform a test. This will minimize input errors and conversion errors.

[0235] Figure 17(E) is an external view showing an example of an automobile, and Figure 17(F) shows the navigation device 8 It shows 60. The car 2980 consists of the body 2981, wheels 2982, and dashboard 2 It has 983 and lights 2984, etc. Also, automobile 2980 has an antenna, battery It is equipped with a display unit 861, operation buttons 862, and It is equipped with an external input terminal 863. The automobile 2980 and the navigation device 860 are They could be independent, but the navigation system 860 is integrated into the automobile 2980. It is preferable to have a configuration where the components function in conjunction with each other.

[0236] For example, a memory device using a semiconductor device according to one aspect of the present invention can be used in automobiles 2980 and navigation systems. The control information and control programs of the control device 860 can be stored for a long period of time. Furthermore, an AI system using a semiconductor device according to one aspect of the present invention can be used as a control device for an automobile 2980, etc. By using this system, the AI ​​system learns the driver's driving skills and habits, and assists in safe driving. This includes assisting with driving by efficiently utilizing fuels such as gasoline and batteries. Yes, it is possible. As an assist for safe driving, it not only learns the driver's driving skills and habits, but also , the behavior of the automobile 2980, such as its speed and method of movement, and the navigation system 860 By comprehensively learning from stored road information and other data, the system prevents the vehicle from deviating from its lane while driving, and also... This enables collision avoidance with vehicles, pedestrians, structures, etc. Specifically, it enables collision avoidance with sudden forces in the direction of travel. If a road exists, the navigation device 860 transmits the road information to the vehicle 2980. It can control the speed of the vehicle (2980) and assist with steering.

[0237] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. This is possible.

[0238] (Embodiment 7)

[0239] In this embodiment, it can be used with the GPU or computer described in the above embodiment. A capable semiconductor device, and an example configuration of an OS transistor that can be used in said semiconductor device. I will explain this.

[0240] <Example of semiconductor device configuration> The semiconductor device shown in Figure 18 includes transistor 300, transistor 200, and a capacitance element. It has a child 100. Figure 19(A) is a cross-sectional view of transistor 200 in the channel length direction. Yes, Figure 19(B) is a cross-sectional view of transistor 200 in the channel width direction, and Figure 19(C) ) is a cross-sectional view of transistor 300 in the channel width direction.

[0241] Transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. It is a transistor. Transistor 200 is used in semiconductor devices because it has a small off-current. This makes it possible to retain memory content for a long period of time. In other words, refresh Because it does not require operation, or because the refresh operation is performed very infrequently, semiconductor devices This can significantly reduce power consumption.

[0242] In the semiconductor device shown in Figure 18, wiring 1001 is the source and source of transistor 300. Connected to one side of the rain, wiring 1002 is the source and drain of transistor 300. It is connected to the other side. Also, wiring 1003 is the source and slave of transistor 200. One side is connected to the top gate of transistor 200, and wiring 1004 is connected to the top gate of transistor 200. Line 1006 is connected to the bottom gate of transistor 200. And the transistor The gate of transistor 300, and the other of the source and drain of transistor 200, are capacitive elements. The wiring 1005 is connected to one electrode of the sub-element 100, and the wiring 1005 is connected to the other electrode of the capacitive element 100. It is being done.

[0243] In this case, when the memory cell shown in Embodiment 3 is used, the semiconductor device shown in this embodiment is used. Transistor T2 becomes transistor 200, and transistor T3 becomes transistor 300. Capacitive element CB corresponds to capacitive element 100. Also, wiring SL is connected to wiring 1001. RBL is connected to wire 1002, WBL is connected to wire 1003, and WOL is connected to wire 100 In section 4, wiring CAL corresponds to wiring 1005, and wiring BGL corresponds to wiring 1006.

[0244] Furthermore, when the semiconductor device shown in this embodiment is used in the calculation circuit shown in Embodiment 2, For example, transistor 42 is connected to transistor 300, and transistor 41 is connected to transistor At 200, the capacitive element 43 corresponds to the capacitive element 100.

[0245] Furthermore, when using the semiconductor device shown in this embodiment for both the memory cell and the arithmetic circuit, Transistor T3 and transistor 42, transistor T2 and transistor 41, capacitive element C B and the capacitive element 43 can be formed in the same process. This allows the manufacturing process This can be simplified and costs reduced.

[0246] A semiconductor device according to one aspect of the present invention, as shown in Figure 18, has a transistor 300, and a transistor It has transistor 200 and a capacitive element 100. Transistor 200 is located above transistor 300. The capacitive element 100 is provided above transistors 300 and 200. It is being done.

[0247] The transistor 300 is mounted on the substrate 311 and consists of a conductor 316, an insulator 315, and substrate 3 A semiconductor region 313 consisting of part of 11, and a region that functions as a source region or drain region. It has a low-resistance region 314a and a low-resistance region 314b.

[0248] As shown in Figure 19(C), transistor 300 is located on the upper surface of semiconductor region 313 and the channel The side surface in the width direction of the panel is covered by the conductor 316 via the insulator 315. In this way, By making the Rangista 300 a Fin type, the effective channel width is increased. This improves the on-characteristics of transistor 300. Also, the electric field of the gate electrode Because the contribution can be increased, the off-characteristics of transistor 300 can be improved. Cut.

[0249] Note that transistor 300 can be either a p-channel or n-channel type.

[0250] The region where the channel of the semiconductor region 313 is formed, the region near it, the source region, or the do In the low-resistance region 314a and low-resistance region 314b, which are rain regions, silico It is preferable that the semiconductor contains semiconductors such as silicon-based semiconductors, and it is preferable that it contains single-crystal silicon. Alternatively, Ge (germanium), SiGe (silicon germanium), GaAs (galvanium) It may also be formed from materials containing arginine, GaAlAs (gallium aluminum arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, silicon with controlled effective mass is produced. The configuration used may also be used. Alternatively, by using GaAs and GaAlAs, etc., the transient TA300 is HEMT (High Electron Mobility Transit) You can also use "tor)".

[0251] Low-resistance regions 314a and 314b are semiconductor regions applied to semiconductor region 313. In addition to the main material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron. It contains elements that impart conductivity.

[0252] The conductor 316, which functions as a gate electrode, is a component that imparts n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon containing elements that impart p-type conductivity, such as boron or other elements. Conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0253] Furthermore, since the work function is determined by the material of the conductor, by changing the material of the conductor, The Vth of the transistor can be adjusted. Specifically, titanium nitride or titanium nitride can be used as the conductor. It is preferable to use materials such as tar. Furthermore, in order to achieve both conductivity and embedding properties It is preferable to use a laminate of metal materials such as tungsten or aluminum as the conductive material. In particular, the use of tungsten is preferable in terms of heat resistance.

[0254] Note that the transistor 300 shown in Figure 18 is just one example, and its structure is not limited to that of the circuit configuration. A suitable transistor can be used depending on the driving method. For example, transistor 200 and Similarly, the transistor 300 may be configured to use an oxide semiconductor.

[0255] The transistor 300 is covered by insulators 320, 322, 324, and insulation. The bodies 326 are arranged in a series of stacked units.

[0256] As insulators 320, 322, 324, and 326, for example, oxidative Silicon, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, acid Aluminum nitride, aluminum nitride oxide, aluminum nitride, etc., can be used.

[0257] The insulator 322 smooths out the step created by the transistor 300 and the like located below it. It functions as a planarizing film that flattens the surface. For example, the upper surface of the insulator 322 is used to improve flatness. It may also be planarized by a planarization treatment using chemical mechanical polishing (CMP) or the like.

[0258] Furthermore, the insulator 324 receives transistors from the substrate 311 or transistors 300, etc. A barrier film is used in the region where the TA200 is provided to prevent the diffusion of hydrogen and impurities. It is preferable that they be present.

[0259] As an example of a film that has barrier properties against hydrogen, for example, silica nitride formed by CVD. A semiconductor having an oxide semiconductor, such as transistor 200, can be used. The diffusion of hydrogen into the element may degrade the characteristics of the semiconductor element. Therefore, A film that suppresses hydrogen diffusion is used between transistor 200 and transistor 300. It is preferable to have one. Specifically, a membrane that suppresses hydrogen diffusion is one that minimizes hydrogen desorption. It will form a membrane.

[0260] The amount of hydrogen desorbed can be measured, for example, by thermal desorption gas analysis (TDS). Analysis can be performed using methods such as spectroscopy. For example, The amount of hydrogen desorption from insulator 324 was determined by TDS analysis when the film surface temperature ranged from 50°C to 500°C. Within the range of °C, the amount of desorption converted to hydrogen atoms is, when converted to the area of ​​insulator 324, , 10×10 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0261] Furthermore, it is preferable that the dielectric constant of the insulator 326 is lower than that of the insulator 324. For example, insulation The relative permittivity of body 326 is preferably less than 4, and more preferably less than 3. Also, for example, insulator 3 The relative permittivity of 26 is preferably 0.7 times or less the relative permittivity of the insulator 324, and preferably 0.6 times or less. More preferable. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. It is possible.

[0262] Furthermore, insulators 320, 322, 324, and 326 contain capacitive elements 1 00, or conductors 328 and 330 connected to transistor 200 are embedded. It is embedded. Note that conductors 328 and 330 are used as plugs or wiring. It is possible. Also, a conductor that functions as a plug or wiring combines multiple structures into one. Symbols may be assigned. Also, in this specification, etc., wiring and plugs connected to the wiring are used. The two may be a single unit. That is, when a part of the conductor functions as wiring, and In some cases, a portion of the conductive material may function as a plug.

[0263] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal materials. Conductive materials such as materials, alloy materials, metal nitride materials, or metal oxide materials are used in a single layer or It can be used in a layered configuration. Materials such as tungsten and molybdenum offer both heat resistance and conductivity. It is preferable to use a high melting point material, and it is preferable to use tungsten. Alternatively, It is preferable to form it with a low-resistance conductive material such as aluminum or copper. Low-resistance conductive material By using this method, wiring resistance can be reduced.

[0264] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, as shown in Figure 18. The insulator 350, insulator 352, and insulator 354 are arranged in a stacked manner. Furthermore, a conductor 356 is formed in insulators 350, 352, and 354. Conductor 356 functions as a plug or wire connecting to transistor 300. The conductor 356 is constructed using the same material as conductors 328 and 330. It is possible to do so.

[0265] For example, insulator 350 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 356 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 350 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, Transistor 300 and transistor 200 can be separated by a barrier layer, This can suppress the diffusion of hydrogen from transistor 300 to transistor 200.

[0266] For example, tantalum nitride can be used as a conductor that has barrier properties against hydrogen. This is good. Also, by laminating tantalum nitride and highly conductive tungsten, the wiring can be This allows for the suppression of hydrogen diffusion from transistor 300 while maintaining conductivity. In this case, the tantalum nitride layer having barrier properties against hydrogen provides a barrier against hydrogen. It is preferable that the structure is in contact with the insulator 350.

[0267] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, as shown in Figure 18. Insulators 360, 362, and 364 are arranged in a stacked manner. Furthermore, a conductor 366 is formed on insulators 360, 362, and 364. Conductor 366 functions as a plug or wiring. It can be provided using the same material as the electric element 328 and the conductor 330.

[0268] For example, insulator 360 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 366 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 360 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, Transistor 300 and transistor 200 can be separated by a barrier layer, This can suppress the diffusion of hydrogen from transistor 300 to transistor 200.

[0269] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, as shown in Figure 18. Insulators 370, 372, and 374 are arranged in a stacked manner. Furthermore, a conductor 376 is formed in insulators 370, 372, and 374. Conductor 376 functions as a plug or wiring. It can be provided using the same material as the electric element 328 and the conductor 330.

[0270] For example, insulator 370 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 376 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 370 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, Transistor 300 and transistor 200 can be separated by a barrier layer, This can suppress the diffusion of hydrogen from transistor 300 to transistor 200.

[0271] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, as shown in Figure 18 The insulators 380, 382, ​​and 384 are arranged in a stacked manner. Furthermore, a conductor 386 is formed on insulators 380, 382, ​​and 384. Conductor 386 functions as a plug or wiring. It can be provided using the same material as the electric element 328 and the conductor 330.

[0272] For example, insulator 380 has a barrier property against hydrogen, similar to insulator 324. It is preferable to use an insulator. Furthermore, the conductor 386 has barrier properties against hydrogen. It is preferable that it contains a conductor. In particular, the insulator 380 having barrier properties against hydrogen is preferable. A conductor having a barrier property against hydrogen is formed in the opening. With this configuration, Transistor 300 and transistor 200 can be separated by a barrier layer, This can suppress the diffusion of hydrogen from transistor 300 to transistor 200.

[0273] In the above, a wiring layer containing a conductor 356, a wiring layer containing a conductor 366, and a conductor 376 Although the wiring layer including the conductive 386 has been described, this embodiment is not applicable. The semiconductor device is not limited to this. A wiring layer similar to a wiring layer containing conductor 356 The number of layers may be three or less, or the wiring layers similar to the wiring layer containing the conductor 356 may be made five or more layers. That's good too.

[0274] Insulators 210, 212, 214, and 216 are located on insulator 384. They are arranged in a stack in order. Insulator 210, insulator 212, insulator 214, and insulator It is preferable that one of the surrounding bodies 216 is made of a material that has barrier properties against oxygen and hydrogen. stomach.

[0275] For example, the insulator 210 and the insulator 214 have, for example, a substrate 311 or a transient From the area where transistor 300 is installed, hydrogen and impurities are present in the area where transistor 200 is installed. It is preferable to use a film that has barrier properties to prevent diffusion. Therefore, insulator 32 The same materials as in 4 can be used.

[0276] As an example of a film with hydrogen barrier properties, silicon nitride formed by CVD is used. This can be done. Here, a semiconductor device having an oxide semiconductor such as transistor 200, Hydrogen diffusion can degrade the properties of the semiconductor device. Therefore, A film that suppresses hydrogen diffusion is used between transistor 200 and transistor 300. This is preferable. Specifically, a membrane that suppresses hydrogen diffusion is a membrane that releases less hydrogen. .

[0277] Furthermore, as films having barrier properties against hydrogen, for example, insulator 210 and insulator 2 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0278] In particular, aluminum oxide is a source of oxygen and hydrogen, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both water and other impurities from passing through the film. Aluminum oxide is susceptible to hydrogen, moisture, and other elements during and after the transistor fabrication process. This prevents impurities from entering transistor 200. This can suppress the release of oxygen from the oxides that make up the transistor. It is suitable for use as a protective film against 200.

[0279] Furthermore, for example, the same material as the insulator 320 is used for insulators 212 and 216. It is possible to have it there. Also, by using a material with a relatively low dielectric constant as the interlayer film, it can prevent the formation of a barrier between the wiring. This can reduce parasitic capacitance. For example, as insulator 212 and insulator 216 Silicon oxide films and silicon oxide nitride films can be used.

[0280] Furthermore, insulators 210, 212, 214, and 216 contain conductor 2 18, and the conductor (conductor 203) etc. that constitute the transistor 200 are embedded. The conductor 218 is connected to the capacitive element 100 or the transistor 300. It functions as a wire or a conductor. Conductor 218 is connected to conductor 328 and conductor 3 It can be provided using the same materials as in 30.

[0281] In particular, the conductor 218 in the region in contact with the insulator 210 and the insulator 214 is oxygen, hydrogen, And preferably it is a conductor that has barrier properties against water. With this configuration, Transistor 300 and Transistor 200 have barrier properties against oxygen, hydrogen, and water. In the layer, it can be separated, and hydrogen from transistor 300 to transistor 200 It can suppress diffusion.

[0282] A transistor 200 is provided above the insulator 216.

[0283] As shown in Figures 19(A) and (B), the transistor 200 is an insulator 214 and an insulator A conductor 203 is positioned to be embedded in 216, and the insulator 216 and the conductor 203 An insulator 220 positioned on top, an insulator 222 positioned on top of the insulator 220, and an insulator An insulator 224 placed on top of 222, and an oxide 230a placed on top of the insulator 224. And, oxide 230b is placed on oxide 230a, and on oxide 230b, apart from each other. Conductors 242a and 242b are arranged in such manner, and conductors 242a and conductors It is positioned on 242b and superimposed between conductor 242a and conductor 242b to form an opening. The insulator 280, the conductor 260 placed in the opening, the oxide 230b, and the conductor 24 2a, conductor 242b, and insulating material placed between the insulator 280 and the conductor 260. Body 250, oxide 230b, conductor 242a, conductor 242b, and insulator 280 It has an insulator 250 and an oxide 230c disposed between them. Also, Figure 19(A) As shown in (B), oxide 230a, oxide 230b, conductor 242a, and conductive It is preferable that the insulator 244 is placed between the body 242b and the insulator 280. As shown in 19(A) and (B), the conductor 260 is a conductor provided inside the insulator 250. The conductive body 260a and the conductive body 260b are provided so as to be embedded inside the conductive body 260a. It is preferable to have the above. Also, as shown in Figures 19(A) and (B), the insulator 280 It is preferable that the insulator 274 is placed on top of the conductor 260 and the insulator 250.

[0284] In the following, oxides 230a, 230b, and 230c are grouped together. In some cases, oxide 230 is used. Also, conductors 242a and conductors 242b are combined. In some cases, it is referred to as conductor 242.

[0285] Furthermore, in transistor 200, oxidation occurs in the region where the channel is formed and in its vicinity. The following describes a configuration in which three layers of material 230a, oxide 230b, and oxide 230c are laminated. However, the present invention is not limited thereto. For example, a single layer of oxide 230b, oxidation Two-layer structure of substance 230b and oxide 230a, two-layer structure of oxide 230b and oxide 230c, Alternatively, a configuration with a stacked structure of four or more layers may be used. Furthermore, in transistor 200, Although the conductor 260 is shown as a two-layer laminated structure, the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a laminated structure of three or more layers. This is also fine. Furthermore, the transistor 200 shown in Figures 18 and 19(A)(B) is just one example, and The structure is not limited to this; an appropriate transistor can be used depending on the circuit configuration and driving method.

[0286] Here, conductor 260 functions as the gate electrode of the transistor, and conductor 242a and The conductor 242b functions as either a source electrode or a drain electrode, respectively. The conductor 260 is located at the opening of the insulator 280, and between conductors 242a and 242b. It is formed so as to be embedded in the sandwiched region. Conductor 260, Conductor 242a and Conductor The arrangement of the electric element 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. In transistor 200, the gate electrode is placed between the source electrode and the drain electrode, self They can be arranged in a consistent manner. Therefore, the conductor 260 is provided with a margin for alignment. Since it can be formed without any additional steps, the occupied area of ​​the transistor 200 can be reduced. This makes it possible to miniaturize and highly integrate semiconductor devices.

[0287] Furthermore, the conductor 260 is formed in a self-aligned manner in the region between conductor 242a and conductor 242b. Therefore, the conductor 260 has a region that overlaps with conductor 242a or conductor 242b. It does not have. As a result, a shape is formed between the conductor 260 and the conductors 242a and 242b. The resulting parasitic capacitance can be reduced. Therefore, the switching of transistor 200 This allows for increased speed and improved frequency response.

[0288] The conductor 260 may function as the first gate (also called the top gate) electrode. Furthermore, the conductor 203 functions as a second gate (also called a bottom gate) electrode. In some cases, the potential applied to conductor 203 may be changed to the potential applied to conductor 260. By changing it independently, without linking it to the other parameters, we can control the Vth of transistor 200. This can be done. In particular, by applying a negative potential to the conductor 203, the transistor 200 By making Vth greater than 0V, it becomes possible to reduce the off-current. Therefore, conductivity Applying a negative potential to body 203 is more effective than not applying one to conductor 260. The drain current when the potential is 0V can be reduced.

[0289] The conductor 203 is positioned to overlap with the oxide 230 and the conductor 260. Therefore, when a potential is applied to the conductor 260 and the conductor 203, the conductor 260 generates The electric field generated by the conductor 203 connects with the electric field generated by the conductor 203, forming a chain in the oxide 230. It can cover the flannel-forming region. In this specification, the first gate electrode and the second The electric field of the gate electrode electrically surrounds the channel formation region, thus creating the structure of the transistor. This is called a surrounded channel (S-channel) structure.

[0290] Furthermore, the conductor 203 has the same configuration as the conductor 218, and the insulator 214 and insulator 2 A conductor 203a is formed in contact with the inner wall of the 16 openings, and a conductor 203b is formed further inside. It has been done.

[0291] Insulators 220, 222, 224, and 250 are gate insulators. It has the function of being functional.

[0292] Here, the insulator 224 in contact with the oxide 230 is more than the oxygen that satisfies the stoichiometric composition. It is preferable to use an insulator containing oxygen. In other words, the insulator 224 contains excess oxygen. It is preferable that such an insulator containing excess oxygen is brought into contact with the oxide 230. By providing this, oxygen deficiencies in the oxide 230 are reduced, and the reliability of the transistor 200 is improved. It can improve sexual performance.

[0293] As an insulator having an excess oxygen region, specifically, an oxidative material in which some oxygen is removed by heating. It is preferable to use a material. Oxides that desorb oxygen upon heating can be identified by TDS analysis. The amount of oxygen removed, converted to oxygen atoms, is 1.0 × 10⁻⁶.18 atoms / cm 3 The above is preferred Or 1.0 × 10 19 atoms / cm 3 More preferably 2.0 × 10 19 a toms / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The oxide film described above The surface temperature of the film during the above TDS analysis is between 100°C and 700°C. A temperature range of 100°C to 400°C is preferred.

[0294] Furthermore, if the insulator 224 has an excess oxygen region, the insulator 222 will have oxygen (for example, acid It has the function of suppressing the diffusion of at least one of the following: elementary atoms, oxygen molecules, etc. (the above oxygen permeates) It is difficult to do. ) is preferable.

[0295] The insulator 222 has the function of suppressing the diffusion of oxygen and impurities, so the oxide 230 has The oxygen does not diffuse toward the insulator 220, which is preferable. Also, the conductor 203 This suppresses the reaction between the insulator 224 and the oxygen present in the oxide 230.

[0296] Insulator 222 can be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or zircon oxide. Conium, lead zirconate titanate (PZT), strontium titanate (SrTiO3) Alternatively, an insulator containing (Ba,Sr)TiO3 (BST) or similar material can be used in a single layer or multilayer configuration. This is preferable. As transistors become smaller and more integrated, the gate insulator becomes thinner. This can lead to problems such as leakage current. An insulator that functions as a gate insulator. By using high-k material, the physical film thickness is maintained while the gate during transistor operation is maintained. This makes it possible to reduce the potential.

[0297] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the above oxygen does not easily permeate). ) An insulating material containing an oxide of either or both aluminum and hafnium. It is preferable to use an edge material. An insulating material containing an oxide of either or both aluminum and hafnium. The marginal material includes aluminum oxide, hafnium oxide, aluminum, and hafnium. It is preferable to use an oxide (hafnium aluminate), etc. When an insulator 222 is formed, the insulator 222 prevents the release of oxygen from the oxide 230 and This layer suppresses the incorporation of impurities such as hydrogen from the periphery of the lampistor 200 into the oxide 230. It functions.

[0298] Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, germanium oxide. M, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, acid Zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxide-nitride, or silicon nitride may be used as an insulator in a laminated form.

[0299] Furthermore, it is preferable that the insulator 220 is thermally stable. For example, silicon oxide and Silicon oxide nitride is suitable because it is thermally stable. Also, high-k material By combining an insulator with silicon oxide or silicon oxide-nitride, thermal stability can be achieved. This makes it possible to obtain an insulator 220 with a multilayer structure and a high relative permittivity.

[0300] Furthermore, the insulators 220, 222, and 224 have a laminated structure of two or more layers. It is also acceptable to have a laminated structure made of the same material, or a structure made of different materials. A layered structure is also acceptable.

[0301] The transistor 200 is formed in the oxide 230 including the channel formation region as an oxide semiconductor. It is preferable to use a metal oxide that can perform the function. For example, as oxide 230, In-MZ n oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium) Um, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, rancid Tan, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use one or more metal oxides selected from the above. Also, oxide 2 For 30, In-Ga oxide or In-Zn oxide may be used.

[0302] In oxide 230, the metal oxide that functions as a channel-forming region has a band gap It is preferable to use one with a voltage of 2 eV or higher, preferably 2.5 eV or higher. By using a metal oxide with a large gap, the off-current of the transistor can be reduced. It is possible.

[0303] Oxide 230 has oxide 230a beneath oxide 230b, so oxide 230a Furthermore, it is possible to suppress the diffusion of impurities from the structure formed below to oxide 230b. It can. Also, by having oxide 230c on oxide 230b, oxide 230c is better than The diffusion of impurities from the structure formed above to oxide 230b can be suppressed. .

[0304] Furthermore, oxide 230 has a layered structure due to oxides with different atomic ratios of each metal atom. This is preferable. Specifically, in the metal oxide used for oxide 230a, among the constituent elements The atomic ratio of element M in the metal oxide used in oxide 230b is the element among the constituent elements. It is preferable that the atomic ratio of M is greater than the atomic ratio of M. Also, the metal oxide used in oxide 230a In this context, the atomic ratio of element M to In is the same as that of the metal oxide used in oxide 230b. It is preferable that the atomic ratio of element M to In is greater than that of In. Also, when used in oxide 230b In the metal oxides, the atomic ratio of In to element M is the same as that of the gold used in oxide 230a. In the group oxide, the atomic ratio of In to element M is preferably greater. Oxide 230c is a metal oxide that can be used as oxide 230a or oxide 230b. It can be used.

[0305] Furthermore, the energy at the lower end of the conduction band of oxide 230a and oxide 230c is It is preferable that the energy of b is higher than the energy of the lower end of the conduction band. In other words, oxide The electron affinity of 230a and oxide 230c is smaller than the electron affinity of oxide 230b. It is preferable.

[0306] Here, at the joint of oxide 230a, oxide 230b, and oxide 230c, The energy levels at the lower end of the guide band change smoothly. In other words, oxide 230a, oxide The energy levels at the lower end of the conduction band at the junction of 230b and oxide 230c are continuous. It can also be said that it undergoes a gradual change or continuous bonding. In order to do this, oxide 2 At the interface between 30a and oxide 230b, and at the interface between oxide 230b and oxide 230c It is desirable to lower the defect level density of the mixed layer that is formed.

[0307] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than the primary element (which is the main component), a mixed layer with a low defect level density is formed. It can be done. For example, if oxide 230b is In-Ga-Zn oxide, As 230a and oxide 230c, In-Ga-Zn oxide, Ga-Zn oxide, acid Gallium oxide or similar materials are suitable.

[0308] In this case, the main carrier pathway is oxide 230b. Oxide 230a, oxide 23 By configuring 0c as described above, the interface between oxide 230a and oxide 230b, and oxidation The defect level density at the interface between material 230b and oxide 230c can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is reduced, and transistor 200 has high On-current can be obtained.

[0309] On the oxide 230b, there is a conductor 242 that functions as a source electrode and a drain electrode. Conductors 242a and 242b are provided. As for the conductor 242, aluminum nium, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tung Stainless steel, hafnium, vanadium, niobium, manganese, magnesium, zirconium, be Selected from lylium, indium, ruthenium, iridium, strontium, and lanthanum. A metal element, or an alloy containing the above-mentioned metal elements, or a combination of the above-mentioned metal elements It is preferable to use alloys such as tantalum nitride, titanium nitride, and tungsten. , nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, lutein oxide nium, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum and nickel It is preferable to use oxides containing tar. Also, tantalum nitride, titanium nitride, titanium Nitrides containing aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, Ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Oxides are conductive materials that are resistant to oxidation, or materials that maintain their conductivity even when absorbing oxygen. Therefore, it is preferable.

[0310] Furthermore, as shown in Figure 19(A), at the interface of the oxide 230 with the conductor 242 and in its vicinity As a low-resistance region, region 243 (region 243a and region 243b) is formed. In some cases, region 243a functions as either the source region or the drain region. Furthermore, region 243b functions as either the source region or the drain region. A channel-forming region is formed in the area sandwiched between region 43a and region 243b.

[0311] By providing the conductor 242 in contact with the oxide 230, the oxygen concentration in region 243 It may be reduced. Also, in region 243, the metal contained in the conductor 242 and the oxide 230 A metal compound layer containing the components of the following may be formed. In such cases, region 243 As the carrier density increases, region 243 becomes a low-resistance region.

[0312] The insulator 244 is provided so as to cover the conductor 242, thereby suppressing oxidation of the conductor 242. At this time, the insulator 244 covers the side surface of the oxide 230 and is arranged to be in contact with the insulator 224. I don't mind being kicked.

[0313] Insulator 244 includes hafnium, aluminum, gallium, yttrium, and zirconium. Tungsten, titanium, tantalum, nickel, germanium, or magnesium One or more metal oxides selected from the above can be used.

[0314] In particular, as the insulator 244, an oxide of either or both aluminum and hafnium is used. The insulators include aluminum oxide, hafnium oxide, aluminum, and hafnium It is preferable to use an oxide containing (hafnium aluminate), etc. In particular, hafnium Mualuminate has higher heat resistance than hafnium oxide film. Therefore, heat in subsequent processes In processing, it is preferable because it is less prone to crystallization. Furthermore, the conductor 242 is an oxidation-resistant material. If the conductivity does not significantly decrease even when absorbed with a substance or oxygen, the insulator 244 is essential. It's not about the configuration. You should design it appropriately based on the desired transistor characteristics.

[0315] Insulator 250 functions as a gate insulator. Insulator 250 is inside oxide 230c It is preferable that they be arranged in contact (top and side surfaces). The insulator 250 is heated by oxygen It is preferable to form it using the emitted insulator. For example, in TDS analysis, oxygen atoms The amount of oxygen removed when converted to this is 1.0 × 10⁻⁶. 18 atoms / cm 3 The above, preferably 1. 0 x 10 19 atoms / cm 3 More preferably 2.0 × 10 19 atom / cm 3 Above, or 3.0 × 10 20 atoms / cm 3 The above describes the oxide film. The surface temperature of the film during the above TDS analysis is in the range of 100°C to 700°C. preferable.

[0316] Specifically, silicon oxide, silicon oxide nitride, silicon nitride oxide, and silicon oxide containing excess oxygen. Silicon oxide, fluorinated silicon oxide, carbon-added silicon oxide, carbon and Nitrogen-added silicon oxide and porous silicon oxide can be used. In particular, Silicon oxide and silicon oxide-nitride are preferred because they are stable to heat.

[0317] An insulator that releases oxygen upon heating is designated as insulator 250 and is brought into contact with the upper surface of oxide 230c. By providing this, the oxide 230b can be transmitted from the insulator 250 through the oxide 230c. This allows for effective oxygen supply to the channel-forming region. Furthermore, similar to insulator 224... Preferably, the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The thickness of the edge body 250 is preferably between 1 nm and 20 nm.

[0318] Furthermore, in order to efficiently supply excess oxygen from the insulator 250 to the oxide 230, A metal oxide may be provided between the body 250 and the conductor 260. The metal oxide is an insulator. It is preferable to suppress oxygen diffusion from 250 to the conductor 260. By providing a metal oxide, the diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. This means that the decrease in the amount of excess oxygen supplied to oxide 230 can be suppressed. This can suppress the oxidation of the conductor 260 due to excess oxygen. The metal oxide in question is Any material suitable for use as the insulator 244 may be used.

[0319] The conductor 260, which functions as the first gate electrode, has a two-layer structure in Figures 19(A) and (B). As shown, it may be a single-layer structure or a laminated structure of three or more layers.

[0320] Conductor 260a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules. Conductive properties that suppress the diffusion of impurities such as N2O, NO, NO2, and copper atoms. It is preferable to use a material. Alternatively, oxygen (for example, oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material that has the function of suppressing the diffusion of (1). Conductor 26 Because 0a has the function of suppressing oxygen diffusion, the oxygen contained in the insulator 250 This can suppress the oxidation of the conductor 260b and the resulting decrease in conductivity. Oxygen diffusion Examples of conductive materials that have the function of suppressing this include tantalum, tantalum nitride, and ruthenium. It is preferable to use um or ruthenium oxide.

[0321] Furthermore, the conductor 260b is a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable to use the material. Also, since the conductor 260b also functions as wiring, It is preferable to use a highly conductive material. For example, tungsten, copper, or aluminum. A conductive material mainly composed of um can be used. In addition, the conductor 260b has a laminated structure. This may also be the case, for example, a laminated structure of titanium, titanium nitride and the above-mentioned conductive material. .

[0322] The insulator 280 is provided on the conductor 242 via the insulator 244. It is preferable to have an excess oxygen region. For example, as the insulator 280, silicon oxide, Silicon oxide nitride, silicon nitride, silicon nitride, fluorine-added silicon oxide, Carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, porous acids It is preferable to have silicon oxide or resin. In particular, silicon oxide and nitrile oxide Silicon oxides are preferred because they are thermally stable. In particular, silicon oxide and porous silicon oxides are preferred. Silicon is preferred because it can easily form an excess oxygen region in a later process.

[0323] The insulator 280 preferably has an excess oxygen region. By providing the edge 280 in contact with the oxide 230c, the oxygen in the insulator 280 is removed from the oxide Through 230c, the oxide 230 can be efficiently supplied to region 243. Preferably, the concentration of impurities such as water or hydrogen in the insulator 280 is reduced.

[0324] The opening in the insulator 280 is formed superimposed on the region between the conductor 242a and the conductor 242b. As a result, the conductor 260 has an opening in the insulator 280, and the conductor 242a and the conductor It is formed in a way that it is embedded in the region sandwiched between 242b.

[0325] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but the conductor 26 It is necessary to prevent the conductivity of 0 from decreasing. To achieve this, the film thickness of conductor 260 is increased. As a result, the conductor 260 may have a shape with a high aspect ratio. In this embodiment, the conductor Since the conductor 260 is to be embedded in the opening of the insulator 280, the aspect ratio of the conductor 260 Even with a highly shaped form, the conductive material 260 can be formed without collapsing during the process. ru.

[0326] The insulator 274 is located on the upper surface of the insulator 280, the upper surface of the conductor 260, and the upper surface of the insulator 250. It is preferable that it be provided in contact with the insulator 274. This allows for the creation of excess oxygen regions in the insulators 250 and 280. Oxygen can be supplied to the oxide 230 from the excess oxygen region.

[0327] For example, as insulator 274, hafnium, aluminum, gallium, yttrium, and Titanium, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more selected metals, such as cium, can be used. ru.

[0328] In particular, aluminum oxide has high barrier properties, and in thin films of 0.5 nm to 3.0 nm... However, the diffusion of hydrogen and nitrogen can be suppressed. Therefore, the sputtering method The aluminum oxide film formed using this method serves as both an oxygen source and a barrier against impurities such as hydrogen. It can also function as a membrane.

[0329] Furthermore, it is preferable to provide an insulator 281 that functions as an interlayer film on top of the insulator 274. The insulator 281, like the insulator 224, has an impurity concentration of water or hydrogen in the film. It is preferable that it be reduced.

[0330] Furthermore, openings formed in insulators 281, 274, 280, and 244 Conductors 240a and 240b are placed in the opening. 40b is provided opposite the conductor 260, with the conductor 240a and conductor 240b in between. This has the same configuration as conductors 246 and 248, which will be described later.

[0331] An insulator 282 is provided on the insulator 281. The insulator 282 is resistant to oxygen and hydrogen. Therefore, it is preferable to use a barrier material. The same material as body 214 can be used. For example, insulator 282 can be made of aluminum oxide. It is preferable to use metal oxides such as um, hafnium oxide, and tantalum oxide.

[0332] In particular, aluminum oxide is a source of oxygen and hydrogen, which can cause variations in the electrical properties of transistors. It has a high barrier effect that prevents both water and other impurities from passing through the film. Aluminum oxide is susceptible to hydrogen, moisture, and other elements during and after the transistor fabrication process. This prevents impurities from entering transistor 200. This can suppress the release of oxygen from the oxides that make up the transistor. It is suitable for use as a protective film against 200.

[0333] Furthermore, an insulator 286 is provided on the insulator 282. The insulator 286 is insulator 3 The same materials as in 20 can be used. Additionally, a material with a relatively low dielectric constant can be used as the interlayer film. This reduces parasitic capacitance between wires. For example, as insulator 286 Silicon oxide films and silicon oxide nitride films can be used.

[0334] Also, insulator 220, insulator 222, insulator 224, insulator 244, insulator 280, insulation Body 274, insulator 281, insulator 282, and insulator 286 contain conductor 246, and Conductors such as 248 are embedded within it.

[0335] Conductors 246 and 248 are connected to the capacitive element 100, the transistor 200, or It functions as a plug or wiring to connect to the Rangista 300. Conductor 246, and Conductor 248 may be provided using the same material as conductors 328 and 330. can.

[0336] Next, a capacitive element 100 is provided above the transistor 200. 00 comprises a conductor 110, a conductor 120, and an insulator 130.

[0337] Furthermore, a conductor 112 may be provided on the conductor 246 and the conductor 248. Conductor 1 12 functions as a plug or wire connecting to transistor 200. Conductive Body 110 functions as an electrode for the capacitive element 100. Note that the conductor 112 and The conductor 110 can be formed simultaneously.

[0338] Conductors 112 and 110 contain molybdenum, titanium, tantalum, and tungsten. A metal film containing elements selected from aluminum, copper, chromium, neodymium, and scandium. Alternatively, metal nitride films containing the above-mentioned elements (tantalum nitride film, titanium nitride film, monoxide nitride film) A ribdenum film, tungsten nitride film, etc., can be used. Alternatively, indium tin oxide can be used. Indium oxide containing tungsten oxide, indium zinc containing tungsten oxide Oxides, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, Conductive materials such as indium zinc oxide and indium tin oxide with added silicon oxide are applied. It is also possible.

[0339] In Figure 18, the conductors 112 and 110 are shown as having a single-layer structure, but the configuration is not limited to this. It is not limited to a single layer, and a laminated structure of two or more layers is also acceptable. For example, a conductor with barrier properties and a highly conductive material. A conductor with barrier properties and a conductor with high conductivity have good adhesion to each other. A highly conductive material may be formed.

[0340] The conductor 120 is provided so as to overlap the conductor 110 via the insulator 130. The conductor 120 uses a conductive material such as a metal material, an alloy material, or a metal oxide material. This is possible. High-melting-point materials such as tungsten and molybdenum that offer both heat resistance and conductivity. It is preferable to use a conductive material, and it is particularly preferable to use tungsten. When forming it simultaneously with other structures, low-resistance metallic materials such as Cu (copper) or Al (aluminium) are used. You can use (Mu), etc.

[0341] An insulator 150 is provided on the conductor 120 and the insulator 130. 0 can be provided using the same material as insulator 320. Also, insulator 150 is It may also function as a flattening film that covers the uneven surface below it.

[0342] By using this structure, in semiconductor devices using transistors having oxide semiconductors This can suppress fluctuations in electrical characteristics and improve reliability. Or, on A transistor having an oxide semiconductor with a high current can be provided. Or, off It is possible to provide a transistor having an oxide semiconductor with a low current. Or, A semiconductor device with reduced power consumption can be provided. Alternatively, a device having an oxide semiconductor can be provided. In semiconductor devices using transistors, miniaturization or high integration can be achieved.

[0343] <Transistor Configuration Example 1> In Figures 18 and 19, the conductor 242, which functions as a source electrode or drain electrode, Although we have described an example of a configuration formed in contact with oxide 230, the OS transistor The configuration is not limited to this. For example, the conductor 242 may be omitted, and the oxide 230 may be selectively made low-resistance. By anti-oxidizing, a configuration is used in which the oxide 230b is provided with a source region or a drain region. It is also possible to have such a transistor configuration. An example of this transistor configuration is shown in Figure 20.

[0344] Figure 20(A) is a cross-sectional view of transistor 200A in the channel length direction, and Figure 20(B) is This is a cross-sectional view of transistor 200A in the channel width direction. Note that the transistor shown in Figure 20 Transistor 200A is a modified version of transistor 200 shown in Figure 19. Therefore, the explanation is repeated. To prevent misunderstandings, we will primarily explain the differences between this transistor and the 200.

[0345] Transistor 200A, like transistor 200, contains an oxide containing a channel formation region. For 230, a metal oxide that functions as an oxide semiconductor can be used.

[0346] Oxide 230 is modified by adding elements that form oxygen vacancies or elements that bond with oxygen vacancies. This can increase carrier density and lower resistance. Typical elements include boron and phosphorus. Also, hydrogen, carbon, and nitrogen. Fluorine, sulfur, chlorine, titanium, noble gases, etc. may also be used. Typical examples of noble gases include fluorine, sulfur, chlorine, titanium, and noble gases. Examples include lium, neon, argon, krypton, and xenon.

[0347] The concentrations of the above elements were determined by secondary ion mass spectrometry (SIMS). Measurements can be taken using methods such as mass spectrometry.

[0348] In particular, boron and phosphorus are used in the production of amorphous silicon or low-temperature polysilicon. It is preferable because the equipment of the production line can be used. This allows for a reduction in capital investment.

[0349] As shown in Figure 20, region 243 (regions 243a and 243b) is oxide 230b. This is the region to which the above elements are added. Region 243 can be defined, for example, by using a dummy gate. It can be formed with.

[0350] For example, a dummy gate is provided on oxide 230b, and the dummy gate is used as a mask. It is preferable to add an element that reduces the resistance of the above oxide 230b. In other words, oxide 230 is The element is added to the region not overlapping with the dummy gate, forming region 243. Furthermore, the method of adding the element involves adding it by mass separation of the ionized raw material gas. On-injection method, ion doping method in which ionized source gas is added without mass separation, Methods such as raspmymerization ion implantation can be used.

[0351] Next, oxide 230b and an insulating film which will become an insulator 244 are placed on the dummy gate, An insulating film that will become the insulator 245 may be formed. As will be described later, before removing the dummy gate An insulating film that will become insulator 244 and an insulating film that will become insulator 245 are laminated on the dummy gate. By providing this, the side walls of the opening after the dummy gate has been removed are insulator 244 and insulator 2 A 45-layer film is formed. The intersection of insulator 244 and insulator 245 formed on the dummy gate. An element that reduces the resistance of oxide 230b is added from the layer film. Region 243 is a dummy gate. As it extends to the lower part, region 243, oxide 230c, and insulator 250 are superimposed. A region can be created.

[0352] Specifically, an insulating film that will become an insulating film 245 is provided on an insulating film that will become an insulating film 280, and then insulation The insulating film that forms part 280 is CMP (Chemical Mechanical Pollicate). By performing the (hing) process, a portion of the insulating film that becomes the insulator 280 is removed, and a dummy gate is created. This exposes the insulator 244 that is in contact with the dummy gate when removing it. It is also advisable to remove a portion of it. Therefore, on the side of the opening provided in the insulator 280, 245 and the insulator 244 are exposed, and the bottom surface of the opening is provided in oxide 230b A portion of the exposed region 243 is exposed. Next, an oxide film which will become oxide 230c is applied to the opening, and an insulating film is applied. After sequentially forming an insulating film that will become the edge 250 and a conductive film that will become the conductor 260, the insulator 2 The oxide film becomes oxide 230c and the insulator 250 through CMP treatment, etc., until 80 is exposed. By removing the insulating film and a portion of the conductive film that forms the conductor 260, as shown in Figure 20, It is possible to form a transistor.

[0353] Note that insulators 244 and 245 are not essential components. The design should be adjusted according to the specific requirements.

[0354] The transistor 200A shown in Figure 20 can be repurposed from existing equipment, and furthermore, Unlike the radiator 200, it does not have a conductor 242, thus reducing costs. ru. [Explanation of Symbols]

[0355] DA1: Signal line, DA2: Signal line, DAM1: Signal line, DAM2: Signal line, DAP1: Signal line Line number, DAP2: signal line, FN10: node, FN20: node, FN30: node, F N40: Node, FN50: Node, FN60: Node, FN70: Node, FN80: Node, FO1: signal line, FO2: signal line, FO3: signal line, FO4: signal line, FOUT 1: Signal line, FOUT2: Signal line, I1: Current, I2: Current, I3: Current, I4: Current, I5: Current, M1: Memory, M2: Memory, M3: Memory, M4: Memory, M5: Memory M6: Memory, 21: Memory, 24a: Memory, 24b: Memory, 31a: Memory, 3 1b: Memory, 31c: Memory, 31d: Memory, MB1: Signal line, MB2: Signal line, R EM1: signal line, REM2: signal line, REP1: signal line, REP2: signal line, S1: switch S2: Switch, S3: Switch, S4: Switch, S5: Switch, S6: Switch Switch, S7: Switch, S8: Switch, S9: Switch, S10: Switch, S11: Switch, S12: Switch, S13: Switch, S14: Switch, S15: Switch SW0: Switch, SW1: Switch, UFM1: Signal line, UFM2: Signal line, UFP 1: Signal line, UFP2: Signal line, WEM1: Signal line, WEM2: Signal line, WEP1: Signal Line, WEP2: signal line, WL1: signal line, 10: adder circuit, 10a: adder circuit, 11: multiplication Calculation cell, 11a: Multiplication cell, 12: Reference cell, 12a: Reference cell, 13 : Arithmetic circuit, 13a: Arithmetic circuit, 15: Conversion circuit, 15a: IV conversion circuit, 15b: Amplification Circuit, 20: Selector, 22: Counter, 22a: CNP, 22b: CNM, 23: Control Circuit, 24: Selector, 25: Control circuit, 26: Zero insertion circuit, 26a: Zero Insertion circuit, 26b: Zero insertion circuit, 26c: Gate circuit, 27: Addition circuit 28: Adding circuits, 29: Gate circuits, 30: Control circuits, 31: Selectors, 32: Control circuit, 33a: Zero insertion circuit, 33b: Zero insertion circuit, 40: Multiplier circuit, 40a: Multiplier circuit, 41: Transistor, 42: Transistor, 42a: Transistor Transistor, 43: Capacitive element, 44: Transistor, 45: Transistor, 45a: Transistor 46: Capacitive element, 47: Transistor, 48: Transistor, 49: Transistor Ta, 49a: transistor, 50: capacitive element, 51: transistor, 51a: transceiver T, 52: Capacitive element, 61: Transistor, 62: Transistor, 62a: Transistor , 63: Capacitive element, 64: Transistor, 65: Transistor, 65a: Transistor, 66: Capacitive element, 67: Transistor, 67a: Transistor, 68: Capacitive element, 69: Transistor, 69a: Transistor, 70: Capacitive element, 71: Transistor, 71a: Transistor, 72: Transistor, 72a: Transistor, 73: Capacitive element, 74: Ranjista, 74a: Transistor, 75: Capacitive element, 76: Transistor, 76a: Rangitar, 77: Capacitive element, 80: Semiconductor device, 81: CPU, 82: Memory, 83: Imaging device, 84: neural network, 84a: multiplication cell block, 84b: New Ron, 84c: Neural network, 85a: Display controller, 85b: Display device, 86: Input / Output bus, 90: Switch

Claims

[Claim 1] It has a first memory, a second memory, a third memory, and a fourth memory, The first memory is provided with first data having a sign, The second memory is provided with the first data having a positive sign that is stored in the first memory, The third memory is provided with the first data having a negative sign that is stored in the first memory, If the first data is zero, the step of discarding it is performed. A step of generating second data by adding the first data having a positive sign stored in the second memory and the first data having a negative sign stored in the third memory, The fourth memory includes the step of storing the second data, An addition method comprising the step of adding all the second data stored in the fourth memory when no second data having a positive sign is stored in the fourth memory, or when no second data having a negative sign is stored in the fourth memory.

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