Semiconductor equipment

Abstract

The present invention provides a semiconductor device with improved voltage resistance in a structure equipped with a sealing conductor. [Solution] The semiconductor device 5 includes a semiconductor chip 41 having a main surface 42, an insulating layer 51 formed on the main surface 42, functional devices 45, 60 formed on at least one of the semiconductor chip 41 and the insulating layer 51, at least one terminal 11, 12 formed on the insulating layer 51 and electrically connected to the functional devices 45, 60, and a sealing conductor 61 which includes a first portion 64 that separates the region containing the functional devices 45, 60 and at least one terminal 11, 12 from other regions in a plan view, and a plurality of second portions 65 located between the semiconductor chip 41 and the first portion 64 and arranged adjacent to each other in a plan view, with each of their widths in a plan view being smaller than that of the first portion 64.

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a seal conductor.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, active elements, a plurality of interlayer insulating layers, a plurality of metal electrodes, and a moisture-resistant ring (seal conductor). The active elements are formed on the semiconductor substrate. The plurality of interlayer insulating layers are stacked on the semiconductor substrate. The plurality of metal electrodes are formed on the uppermost interlayer insulating layer. The moisture-resistant ring is embedded in the plurality of interlayer insulating layers so as to surround the active elements and the plurality of metal electrodes in a plan view. The moisture-resistant ring is grounded to the semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] In the semiconductor device according to Patent Document 1, due to the structure in which the seal conductor is grounded to the semiconductor substrate, when a voltage is applied to the plurality of metal electrodes, undesired conduction may occur between the plurality of metal electrodes and the seal conductor. The withstand voltage of the semiconductor device decreases due to this type of conduction. Examples of the mode of undesired conduction include leakage and discharge.

[0005] One embodiment of the present invention provides a semiconductor device capable of improving the withstand voltage in a structure including a seal conductor.

[0006] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low-potential terminal formed on the insulating layer and electrically connected to the functional device; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the functional device; and a sealing conductor embedded in the insulating layer in a wall-like manner so as to demarcate the region including the functional device, the low-potential terminal and the high-potential terminal from other regions in a plan view, and electrically isolated from the semiconductor chip, the functional device, the low-potential terminal and the high-potential terminal.

[0007] This semiconductor device can suppress unwanted conduction between the high-potential terminal and the sealing conductor when voltage is applied to the low-potential and high-potential terminals. It can also suppress unwanted conduction between the low-potential terminal and the sealing conductor. Furthermore, it can suppress unwanted conduction between the functional device and the sealing conductor. Therefore, the withstand voltage can be improved.

[0008] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a low-potential pattern formed within the insulating layer; a high-potential pattern formed within the insulating layer so as to face the low-potential pattern in the direction normal to the main surface; a dummy pattern formed within the insulating layer around the high-potential pattern, containing a conductor, and shielding the electric field between the low-potential pattern and the high-potential pattern; a low-potential terminal formed on the insulating layer and electrically connected to the low-potential pattern; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the high-potential pattern; and a sealing conductor embedded in the insulating layer in a wall-like manner so as to demarcate the region including the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal and the high-potential terminal from other regions in a plan view, and electrically disconnected from the semiconductor chip, the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal and the high-potential terminal.

[0009] This semiconductor device allows for the suppression of electric field concentration on high-potential patterns by a dummy pattern when voltage is applied to low-potential and high-potential terminals. Furthermore, this semiconductor device can suppress unwanted conduction between high-potential patterns (high-potential terminals) and sealing conductors when voltage is applied to low-potential and high-potential terminals. It can also suppress unwanted conduction between low-potential patterns (low-potential terminals) and sealing conductors. Additionally, it can suppress unwanted conduction between dummy patterns and sealing conductors. Therefore, the withstand voltage can be improved.

[0010] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; at least one terminal formed on the insulating layer and electrically connected to the functional device; and a sealing conductor comprising a first portion and a plurality of second portions located between the semiconductor chip and the first portion, arranged adjacent to each other in a plan view, with each second portion having a width smaller than that of the first portion in a plan view.

[0011] The above-mentioned, or further, objectives, features, and effects of the present invention will be made clearer by the following description of embodiments with reference to the accompanying drawings. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a plan view of a semiconductor module incorporating a semiconductor device according to the first embodiment of the present invention. [Figure 2] Figure 2 is a diagram illustrating the operation of the semiconductor module shown in Figure 1. [Figure 3] Figure 3 is the voltage waveform diagram used to explain Figure 2. [Figure 4] Figure 4 is a perspective view showing the semiconductor device shown in Figure 1. [Figure 5]FIG. 5 is a plan view of the semiconductor device shown in FIG. 4. [Figure 6] FIG. 6 is a plan view showing a layer in which a low-potential coil is formed in the semiconductor device shown in FIG. 4. [Figure 7] FIG. 7 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device shown in FIG. 4. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 7. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. 7. [Figure 10] FIG. 10 is an enlarged view of region X shown in FIG. 7. [Figure 11] FIG. 11 is an enlarged view of region XI shown in FIG. 7. [Figure 12] FIG. 12 is an enlarged view of region XII shown in FIG. 7. [Figure 13] FIG. 13 is an enlarged view of region XIII shown in FIG. 8, and is a view showing a separation structure according to the first exemplary embodiment. [Figure 14A] FIG. 14A is an enlarged view of region XIII shown in FIG. 8, and is a view showing a separation structure according to the second exemplary embodiment. [Figure 14B] FIG. 14B is an enlarged view of region XIII shown in FIG. 8, and is a view showing a separation structure according to the third exemplary embodiment. [Figure 14C] FIG. 14C is an enlarged view of region XIII shown in FIG. 8, and is a view showing a separation structure according to the fourth exemplary embodiment. [Figure 14D] FIG. 14D is an enlarged view of region XIII shown in FIG. 8, and is a view showing a separation structure according to the fifth exemplary embodiment. [Figure 15] FIG. 15 is a graph showing the average instantaneous breakdown voltage. [Figure 16] FIG. 16 is a view obtained by simulating the electric field distribution in the vicinity of the high-potential coil. [Figure 17] FIG. 17 is a view obtained by simulating the electric field distribution of the first high-potential dummy pattern. [Figure 18]FIG. 18 is a diagram showing the electric field distribution of the floating dummy pattern investigated by simulation. [Figure 19] FIG. 19 is a plan view corresponding to FIG. 7, showing a plan view of a semiconductor device according to the second embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX shown in FIG. 19. [Figure 21] FIG. 21 is a cross-sectional view of a region corresponding to FIG. 8, showing a cross-sectional view of a semiconductor device according to the third embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0013] FIG. 1 is a plan view of a semiconductor module 1 incorporating a semiconductor device 5 according to the first embodiment of the present invention. In FIG. 1, the central part of the package body 2 is shown transparently for clarity of the internal structure.

[0014] Referring to FIG. 1, in this embodiment, the semiconductor module 1 is of the SOP (Small Outline Package) type. The semiconductor module 1 is not limited to the SOP, and may be of the QFN (Quad Flat No-Lead Package), DFP (Dual Flat Package), DIP (Dual In-line Package), QFP (Quad Flat Package), SIP (Single In-line Package), or SOJ (Small Outline J-leaded Package), or various packages similar thereto.

[0015] In this embodiment, the semiconductor module 1 is a composite module including a plurality of devices. The semiconductor module 1 includes a package body 2, a plurality of die pads 3, a plurality of lead terminals 4, a semiconductor device 5, a controller IC 6, a driver IC 7, and a plurality of conducting wires 17 to 20.

[0016] The semiconductor device 5 is a transformer chip that boosts the input electrical signal and outputs it. The controller IC 6 is an IC chip that drives and controls the semiconductor device 5. The driver IC 7 is an IC chip that generates an electrical signal in response to the electrical signal from the semiconductor device 5 and drives and controls a load (e.g., a switching device). The controller IC 6 is a low-potential device relative to the semiconductor device 5. The driver IC 7 is a high-potential device relative to the semiconductor device 5.

[0017] The package body 2 includes a molding resin. The molding resin may also include an epoxy resin. The package body 2 is formed in a rectangular parallelepiped shape. The package body 2 has a non-mounting surface 8 on one side, a mounting surface 9 on the other side, and side walls 10A to 10D connecting the non-mounting surface 8 and the mounting surface 9. The non-mounting surface 8 and the mounting surface 9 are formed in a rectangular shape in a plan view taken from their normal direction Z. The mounting surface 9 is the surface facing the connection target when the semiconductor module 1 is mounted on the connection target. Examples of connection targets include circuit boards such as PCBs (printed circuit boards).

[0018] The side walls 10A to 10D include the first side wall 10A, the second side wall 10B, the third side wall 10C, and the fourth side wall 10D. The first side wall 10A and the second side wall 10B extend along the first direction X and face the second direction Y which is perpendicular to the first direction X. The third side wall 10C and the fourth side wall 10D extend in the second direction Y and face the first direction X.

[0019] Multiple die pads 3 are arranged inside the package body 2. In this configuration, each of the multiple die pads 3 is formed in a rectangular parallelepiped shape. The multiple die pads 3 include a first die pad 3A and a second die pad 3B. The first die pad 3A is located on the side of the first side wall 10A. The second die pad 3B is located on the side of the second side wall 10B, spaced apart from the first die pad 3A.

[0020] Multiple lead terminals 4 are provided on the first side wall 10A and the second side wall 10B of the package body 2, respectively. Each lead terminal 4 has one end located inside the package body 2 and the other end located outside the package body 2. The other end of each lead terminal 4 is formed as an external connection part that is connected to the object to be connected.

[0021] The semiconductor device 5 is positioned on the first die pad 3A within the package body 2. In this configuration, the semiconductor device 5 is formed in a rectangular shape in plan view. The semiconductor device 5 is positioned on the first die pad 3A with its long side facing the first side wall 10A (second side wall 10B).

[0022] The semiconductor device 5 includes a plurality of low-potential terminals 11 and a plurality of high-potential terminals 12. The plurality of low-potential terminals 11 are arranged at intervals along the long side on the first side wall 10A side of the semiconductor device 5. The plurality of high-potential terminals 12 are arranged at intervals along the long side on the second side wall 10B side of the semiconductor device 5.

[0023] The controller IC 6 is located on the first die pad 3A within the package body 2. Specifically, the controller IC 6 is located on the first die pad 3A with a gap between it and the semiconductor device 5 towards the first side wall 10A. In this configuration, the controller IC 6 is formed in a rectangular shape in plan view. The controller IC 6 is located on the first die pad 3A with its longer side facing the first side wall 10A (second side wall 10B).

[0024] The controller IC 6 includes a plurality of first input pads 13 and a plurality of first output pads 14. The plurality of first input pads 13 are arranged at intervals along the long side of the first side wall 10A in the controller IC 6. The plurality of first output pads 14 are arranged at intervals along the long side of the second side wall 10B in the controller IC 6.

[0025] The driver IC 7 is located on the second die pad 3B within the package body 2. In this configuration, the driver IC 7 is rectangular in shape when viewed from above. The driver IC 7 is located on the second die pad 3B with its longer side facing the first side wall 10A (second side wall 10B).

[0026] The driver IC 7 includes a plurality of second input pads 15 and a plurality of second output pads 16. The plurality of second input pads 15 are spaced apart along the long side of the first side wall 10A on the driver IC 7. The plurality of second output pads 16 are spaced apart along the long side of the second side wall 10B on the driver IC 7.

[0027] Multiple conductors 17-20 selectively connect multiple lead terminals 4, semiconductor device 5, controller IC 6, and driver IC 7 within the package body 2. Each of the multiple conductors 17-20 consists of a bonding wire. Each of the multiple conductors 17-20 includes at least one of copper wire, gold wire, and aluminum wire.

[0028] The multiple conductors 17-20 include the first conductor 17, the second conductor 18, the third conductor 19, and the fourth conductor 20. The first conductor 17 is connected to the lead terminal 4 on the first side wall 10A side and the first input pad 13 of the controller IC 6. The second conductor 18 is connected to the low-potential terminal 11 of the semiconductor device 5 and the first output pad 14 of the controller IC 6. The third conductor 19 is connected to the high-potential terminal 12 of the semiconductor device 5 and the second input pad 15 of the driver IC 7. The fourth conductor 20 is connected to the second output pad 16 of the driver IC 7 and the lead terminal 4 on the second side wall 10B side.

[0029] Figure 2 is a diagram illustrating the operation of the semiconductor module 1 shown in Figure 1. Figure 3 is a voltage waveform diagram used to illustrate Figure 2.

[0030] Referring to Figure 2, the semiconductor device 5 includes a transformer 21. The transformer 21 includes a primary low-potential coil 22 (low-potential conductor pattern) and a secondary high-potential coil 23 (high-potential conductor pattern) that are opposed to each other in the vertical direction. The high-potential coil 23 is positioned above the low-potential coil 22 and faces the low-potential coil 22.

[0031] The high-potential coil 23 is AC-connected to the low-potential coil 22 by magnetic coupling, while simultaneously being DC-isolated from the low-potential coil 22. In other words, the driver IC 7 is AC-connected to the controller IC 6 via the semiconductor device 5, while simultaneously being DC-isolated from the controller IC 6 by the semiconductor device 5.

[0032] The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 spirally routed between the first inner end 24 and the first outer end 25. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 spirally routed between the second inner end 27 and the second outer end 28.

[0033] The semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34. The first low-potential wiring 31 connects the first inner end 24 of the low-potential coil 22 to the corresponding low-potential terminal 11. The second low-potential wiring 32 connects the first outer end 25 of the low-potential coil 22 to the corresponding low-potential terminal 11. The first high-potential wiring 33 connects the second inner end 27 of the high-potential coil 23 to the corresponding high-potential terminal 12. The second high-potential wiring 34 connects the second outer end 28 of the high-potential coil 23 to the corresponding high-potential terminal 12.

[0034] The controller IC 6 includes a first wire 35 and a second wire 36. The first wire 35 is connected to the corresponding first input pad 13 and first output pad 14. The second wire 36 is connected to the corresponding first input pad 13 and first output pad 14. The controller IC 6 further includes a first switching device Sw1 and a second switching device Sw2. The first switching device Sw1 and the second switching device Sw2 consist of transistors, respectively.

[0035] The first switching device Sw1 is interposed in the first wiring 35. The first switching device Sw1 controls the conduction and interruption of electrical signals transmitted to the first wiring 35. The second switching device Sw2 is interposed in the second wiring 36. The second switching device Sw2 controls the conduction and interruption of electrical signals transmitted to the second wiring 36.

[0036] The first input pad 13 on the first wiring 35 side is connected to ground via the first conductor 17. The first output pad 14 on the first wiring 35 side is electrically connected to the low-potential terminal 11 on the first inner end 24 side via the second conductor 18. The first input pad 13 on the second wiring 36 side is electrically connected to the power supply 37 via the first conductor 17. The power supply 37 applies a voltage of, for example, 5V to the controller IC 6. The first output pad 14 on the second wiring 36 side is electrically connected to the low-potential terminal 11 on the first outer end 25 side via the second conductor 18.

[0037] The driver IC 7 is electrically connected to the semiconductor device 5 via multiple third conductors 19. Specifically, the second input pad 15 of the driver IC 7 is electrically connected to the high-potential terminal 12 on the second inner end 27 side via the third conductors 19. In addition, the second input pad 15 of the driver IC 7 is electrically connected to the high-potential terminal 12 on the second outer end 28 side via the third conductors 19.

[0038] The driver IC 7 is connected to a reference voltage power supply 38, a power supply 39, and a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of a load. The reference voltage power supply 38 applies a reference voltage of, for example, 1200V to the driver IC 7. This reference voltage is also applied to the high-potential coil 23 via the driver IC 7. The power supply 39 applies a voltage of, for example, 15V to the driver IC 7. The driver IC 7 drives and controls the SiC-MISFET using 1200V as the reference voltage.

[0039] Referring to Figure 3, the controller IC 6 controls the on / off state of the first switching device Sw1 and the second switching device Sw2 in a predetermined switching pattern to generate a pulse signal PS. In this example, the predetermined switching pattern includes a first applied state (Sw1 on, Sw2 off) and a second applied state (Sw1 off, Sw2 on). Figure 3 shows an example in which a 5V pulse signal PS is generated with respect to 0V (ground potential).

[0040] The pulse signal PS generated by the controller IC 6 is input to the semiconductor device 5. The semiconductor device 5 transmits the pulse signal PS from the low-potential coil 22 to the high-potential coil 23. As a result, the pulse signal PS is boosted by an amount corresponding to the winding ratio (voltage transformation ratio) of the low-potential coil 22 and the high-potential coil 23. Figure 3 shows an example where the pulse signal PS is boosted to 15V.

[0041] The boosted pulse signal PS is input to the driver IC7. The driver IC7 generates an electrical signal corresponding to the boosted pulse signal PS and drives and controls the SiC-MISFET. The values ​​shown in Figures 2 and 3 are merely examples. For example, the reference voltage on the secondary side (high potential side) may be between 500V and 4000V.

[0042] Figure 4 is a perspective view showing the semiconductor device 5 shown in Figure 1. Figure 5 is a plan view of the semiconductor device 5 shown in Figure 4. Figure 6 is a plan view showing the layer in the semiconductor device 5 shown in Figure 4 on which the low-potential coil 22 is formed. Figure 7 is a plan view showing the layer in the semiconductor device 5 shown in Figure 4 on which the high-potential coil 23 is formed. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 7. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 7. Figure 10 is an enlarged view of region X shown in Figure 7. Figure 11 is an enlarged view of region XI shown in Figure 7. Figure 12 is an enlarged view of region XII shown in Figure 7. Figure 13 is an enlarged view of region XIII shown in Figure 8, showing the separation structure 130 according to the first embodiment.

[0043] Referring to Figures 4 to 8, the semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0044] Wide-bandgap semiconductors consist of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide-bandgap semiconductor is preferably 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0045] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a laminated structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0046] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a rectangular shape (in this form, a rectangular shape) when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").

[0047] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and face a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in a second direction Y and face a first direction X. The chip sidewalls 44A to 44D consist of a ground surface.

[0048] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that aligns with the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0049] The insulating sidewalls 53A to 53D include the first insulating sidewall 53A, the second insulating sidewall 53B, the third insulating sidewall 53C, and the fourth insulating sidewall 53D. The insulating sidewalls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A to 44D. Specifically, the insulating sidewalls 53A to 53D are formed flush with the chip sidewalls 44A to 44D. The insulating sidewalls 53A to 53D form a ground surface that is flush with the chip sidewalls 44A to 44D.

[0050] The insulating layer 51 consists of a multilayer insulating laminate structure including a bottom insulating layer 55, an upper insulating layer 56, and a plurality (11 layers in this embodiment) of interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the upper insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the thickness of the upper insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0051] Each of the multiple interlayer insulating layers 57 has a laminated structure including a first insulating layer 58 on the bottom insulating layer 55 side and a second insulating layer 59 on the top insulating layer 56 side. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, about 0.3 μm).

[0052] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0053] The total thickness DT of the insulating layer 51 may be between 5 μm and 50 μm. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the dielectric breakdown voltage (dielectric breakdown withstand voltage) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layer 57 are arbitrary and are not limited to any specific insulating material.

[0054] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, more) transformers 21. In other words, the semiconductor device 5 consists of a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed in the inner part of the insulating layer 51, spaced apart from the insulating side walls 53A to 53D. The multiple transformers 21 are formed spaced apart in a first direction X.

[0055] The multiple transformers 21 specifically include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating sidewall 53C to the insulating sidewall 53D in a plan view. The multiple transformers 21A to 21D each have a similar structure. The structure of the first transformer 21A will be used as an example below. The explanation of the structures of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D will be omitted, as the explanation of the structure of the first transformer 21A will be applied mutatis mutandis.

[0056] Referring to Figures 6 to 9, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within the insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between the bottom insulating layer 55 and the top insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0057] The low-potential coil 22 is formed within the insulating layer 51 on the side of the bottom insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 on the side of the top insulating layer 56 (main insulating surface 52) relative to the low-potential coil 22. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The placement of the low-potential coil 22 and the high-potential coil 23 is arbitrary. Furthermore, the high-potential coil 23 only needs to face the low-potential coil 22 with one or more interlayer insulating layers 57 in between.

[0058] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulating layer 57) is adjusted as appropriate according to the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this configuration, the low-potential coil 22 is formed in the third interlayer insulating layer 57 counting from the bottom insulating layer 55. In this configuration, the high-potential coil 23 is formed in the first interlayer insulating layer 57 counting from the top insulating layer 56.

[0059] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 that is spirally routed between the first inner end 24 and the first outer end 25. The first helical portion 26 is spirally routed in an elliptical (oval) shape in plan view. The portion forming the innermost periphery of the first helical portion 26 defines an elliptical first inner region 66 in plan view.

[0060] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first helical portion 26 is 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction perpendicular to the helical direction. The first turn pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. Preferably, the first turn pitch is 1 μm or more and 3 μm or less. The first turn pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction perpendicular to the helical direction.

[0061] The winding shape of the first helical portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the forms shown in Figure 6, etc. The first helical portion 26 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The first inner region 66 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the first helical portion 26.

[0062] The low-potential coil 22 may contain at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a laminated structure including a barrier layer and a main body layer. The barrier layer partitions a recess space within the interlayer insulating layer 57. The main body layer is embedded in the recess space partitioned by the barrier layer. The barrier layer may contain at least one of titanium and titanium nitride. The main body layer may contain at least one of copper, aluminum, and tungsten.

[0063] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 that is spirally routed between the second inner end 27 and the second outer end 28. The second helical portion 29 is spirally routed in an elliptical (oval) shape in plan view. The portion forming the innermost periphery of the second helical portion 29 defines an elliptical second inner region 67 in plan view in this embodiment. The second inner region 67 of the second helical portion 29 faces the first inner region 66 of the first helical portion 26 in the normal direction Z.

[0064] The number of turns of the second helical section 29 may be between 5 and 30. The number of turns of the second helical section 29 relative to the number of turns of the first helical section 26 is adjusted according to the voltage value to be boosted. It is preferable that the number of turns of the second helical section 29 exceeds the number of turns of the first helical section 26. Of course, the number of turns of the second helical section 29 may be less than the number of turns of the first helical section 26, or it may be equal to the number of turns of the first helical section 26.

[0065] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction perpendicular to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0066] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions in the second helical portion 29 in a direction perpendicular to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0067] The winding shape of the second helical portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the forms shown in Figure 7, etc. The second helical portion 29 may be wound in a polygonal shape such as a triangle or a square, or in a circular shape in a plan view. The second inner region 67 may be divided into a polygonal shape such as a triangle or a square, or in a circular shape in a plan view, depending on the winding shape of the second helical portion 29.

[0068] It is preferable that the high-potential coil 23 is formed from the same conductive material as the low-potential coil 22. In other words, it is preferable that the high-potential coil 23 includes a barrier layer and a main body layer, similar to the low-potential coil 22.

[0069] Referring to Figure 5, the semiconductor device 5 includes a plurality (12 in this configuration) of low-potential terminals 11 and a plurality (12 in this configuration) of high-potential terminals 12. The plurality of low-potential terminals 11 are each electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D. The plurality of high-potential terminals 12 are each electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D.

[0070] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed in the region on the insulating side wall 53B side, spaced apart in the second direction Y from the multiple transformers 21A to 21D, and are arranged with spacing in the first direction X.

[0071] The multiple low-potential terminals 11 include a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this configuration, two of each of the multiple low-potential terminals 11A to 11F are formed. The number of multiple low-potential terminals 11A to 11F is arbitrary.

[0072] The first low-potential terminal 11A faces the first transformer 21A in the second direction Y in a plan view. The second low-potential terminal 11B faces the second transformer 21B in the second direction Y in a plan view. The third low-potential terminal 11C faces the third transformer 21C in the second direction Y in a plan view. The fourth low-potential terminal 11D faces the fourth transformer 21D in the second direction Y in a plan view. The fifth low-potential terminal 11E is formed in the region between the first low-potential terminal 11A and the second low-potential terminal 11B in a plan view. The sixth low-potential terminal 11F is formed in the region between the third low-potential terminal 11C and the fourth low-potential terminal 11D in a plan view.

[0073] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0074] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0075] Multiple high-potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51, spaced apart from multiple low-potential terminals 11. Specifically, the multiple high-potential terminals 12 are formed in the region on the insulating side wall 53A side, spaced apart in the second direction Y from the multiple low-potential terminals 11, and are arranged with spacing in the first direction X.

[0076] Multiple high-potential terminals 12 are each formed in a region adjacent to the corresponding transformers 21A to 21D in a plan view. The proximity of the high-potential terminals 12 to the transformers 21A to 21D means that, in a plan view, the distance between the high-potential terminals 12 and the transformer 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0077] Specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D in a plan view. More specifically, the multiple high-potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high-potential coil 23 and in the region between adjacent high-potential coils 23 in a plan view. As a result, the multiple high-potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0078] The multiple high-potential terminals 12 include a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this configuration, two of each of the multiple high-potential terminals 12A to 12F are formed. The number of multiple high-potential terminals 12A to 12F is arbitrary.

[0079] The first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23) in a plan view. The second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23) in a plan view. The third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23) in a plan view. The fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23) in a plan view. The fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0080] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0081] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0082] Referring to Figures 6 to 9, the semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, each formed within the insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0083] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this configuration, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0084] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this configuration, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0085] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A to 11D and the first inner ends 24 of the corresponding transformers 21A to 21D (low-potential coils 22), respectively. Multiple first low-potential wirings 31 have similar structures. Below, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. For descriptions of the structures of other first low-potential wirings 31, the description of the structure of the first low-potential wiring 31 connected to the first transformer 21A will be applied mutatis mutandis, and the description will be omitted.

[0086] The first low-potential wiring 31 includes a through-wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0087] It is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, it is preferable that the through-wiring 71, low-potential connection wiring 72, lead-out wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0088] The through-wiring 71 penetrates multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this configuration, the through-wiring 71 is formed in the region between the lowest insulating layer 55 and the uppermost insulating layer 56 in the insulating layer 51. The through-wiring 71 has an upper end on the side of the uppermost insulating layer 56 and a lower end on the side of the lowest insulating layer 55. The upper end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through-wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0089] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0090] The first electrode layer 78 forms the upper end of the through-wiring 71. The second electrode layer 79 forms the lower end of the through-wiring 71. The first electrode layer 78 is formed in an island shape and faces the low-potential terminal 11 (first low-potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0091] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the bottom insulating layer 55 to the top insulating layer 56 so as to be electrically connected to each other, and also electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0092] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this configuration, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the multiple interlayer insulating layers 57.

[0093] The low-potential connection wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) within the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connection wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. It is preferable that the low-potential connection wiring 72 has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0094] The lead wire 73 is formed in the region between the semiconductor chip 41 and the through-wiring 71 within the interlayer insulating layer 57. In this embodiment, the lead wire 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead wire 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first and second ends. The first end of the lead wire 73 is located in the region between the semiconductor chip 41 and the lower end of the through-wiring 71. The second end of the lead wire 73 is located in the region between the semiconductor chip 41 and the low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip-like manner in the region between the first and second ends.

[0095] The first connecting plug electrode 74 is formed in the region between the through-wiring 71 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the first ends of the through-wiring 71 and the lead-out wiring 73. The second connecting plug electrode 75 is formed in the region between the low-potential connecting wiring 72 and the lead-out wiring 73 within the interlayer insulating layer 57 and is electrically connected to the second ends of the low-potential connecting wiring 72 and the lead-out wiring 73.

[0096] Multiple pad plug electrodes 76 are formed in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through-wiring 71 within the uppermost insulating layer 56, and are electrically connected to the upper ends of the low-potential terminal 11 and the through-wiring 71, respectively. Multiple substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the lead-out wiring 73 within the lowermost insulating layer 55. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first end of the lead-out wiring 73, and are electrically connected to the first end of the semiconductor chip 41 and the lead-out wiring 73, respectively.

[0097] Referring to Figure 9, the multiple second low-potential wirings 32 are electrically connected to the corresponding low-potential terminals 11E, 11F and the first outer ends 25 of the low-potential coils 22 of the corresponding transformers 21A to 21D, respectively. Each of the multiple second low-potential wirings 32 has a similar structure. Below, the structure of the second low-potential wiring 32 connected to the fifth low-potential terminal 11E and the first transformer 21A (second transformer 21B) will be described as an example. For descriptions of the structures of the other second low-potential wirings 32, the description of the structure of the second low-potential wiring 32 connected to the first transformer 21A (second transformer 21B) will be applied mutatis mutandis, and the descriptions will be omitted.

[0098] The second low-potential wiring 32, like the first low-potential wiring 31, includes through wiring 71, low-potential connection wiring 72, lead wiring 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77. The second low-potential wiring 32 has the same structure as the first low-potential wiring 31, except that the low-potential connection wiring 72 is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22).

[0099] The low-potential connection wiring 72 of the second low-potential wiring 32 is formed around the low-potential coil 22 within the same interlayer insulating layer 57 as the low-potential coil 22. Specifically, the low-potential connection wiring 72 is formed in the region between two adjacent low-potential coils 22 in a plan view. The pad plug electrode 76 is formed in the region between the low-potential terminal 11 (fifth low-potential terminal 11E) and the low-potential connection wiring 72 within the uppermost insulating layer 56 and is electrically connected to the low-potential terminal 11 and the low-potential connection wiring 72.

[0100] Referring to Figure 8, the multiple first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A to 12D and the second inner ends 27 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple first high-potential wirings 33 each have a similar structure. Below, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. For descriptions of the structures of the other first high-potential wirings 33, the description of the structure of the first high-potential wiring 33 connected to the first transformer 21A will be applied mutatis mutandis, and the descriptions will be omitted.

[0101] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, more) pad plug electrodes 82. Preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 are formed of the same conductive material as the low-potential coil 22, etc. That is, preferably, the high-potential connection wiring 81 and the pad plug electrodes 82 include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0102] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In a plan view, the high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the dielectric strength of the insulating layer 51 is enhanced.

[0103] Multiple pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulating layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. Each of the multiple pad plug electrodes 82 has a planar area less than the planar area of ​​the high-potential connection wiring 81 in a plan view.

[0104] Referring to Figure 9, the multiple second high-potential wirings 34 are electrically connected to the corresponding high-potential terminals 12E and 12F and the second outer ends 28 of the corresponding transformers 21A to 21D (high-potential coils 23), respectively. The multiple second high-potential wirings 34 each have a similar structure. Below, the structure of the second high-potential wiring 34 connected to the fifth high-potential terminal 12E and the first transformer 21A (second transformer 21B) will be described as an example. For descriptions of the structures of other second high-potential wirings 34, the description of the structure of the second high-potential wiring 34 connected to the first transformer 21A (second transformer 21B) will be applied mutatis mutandis, and the descriptions will be omitted.

[0105] The second high-potential wiring 34 includes a high-potential connection wiring 81 and a pad plug electrode 82, similar to the first high-potential wiring 33. The second high-potential wiring 34 has the same structure as the first high-potential wiring 33, except that the high-potential connection wiring 81 is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23).

[0106] The high-potential connection wiring 81 of the second high-potential wiring 34 is formed around the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in the region between two adjacent high-potential coils 23 in a plan view and faces the high-potential terminal 12 (fifth high-potential terminal 12E) in the normal direction Z. The high-potential connection wiring 81 is formed at a distance from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z.

[0107] Multiple pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (fifth high-potential terminal 12E) and the high-potential connection wiring 81 within the uppermost insulating layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively.

[0108] Referring to FIGS. 8 and 9, the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 preferably exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the insulation breakdown voltage to be achieved.

[0109] Referring to FIGS. 7 to 12, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. In FIGS. 10 to 12, the dummy pattern 85 is shown by hatching. The dummy pattern 85 includes a conductor. The dummy pattern 85 is preferably formed of the same conductive material as the low-potential coil 22 or the like. That is, the dummy pattern 85 preferably includes a barrier layer and a main body layer, similar to the low-potential coil 22 or the like.

[0110] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration on the high-potential coil 23.

[0111] In this embodiment, the dummy pattern 85 is routed in a dense linear fashion so as to partially cover and partially expose the area around one or more high-potential coils 23 in a plan view. In this embodiment, the dummy pattern 85 is routed at a line density equal to that of the high-potential coils 23 per unit area. The line density of the dummy pattern 85 being equal to that of the high-potential coils 23 means that the line density of the dummy pattern 85 falls within ±20% of the line density of the high-potential coils 23.

[0112] It is preferable that the dummy pattern 85 is formed in a region that is close to the high-potential coil 23 relative to the low-potential terminal 11 in a plan view. In a plan view, the dummy pattern 85 being close to the high-potential coil 23 means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential terminal 11.

[0113] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the dummy pattern 85 is formed in a region adjacent to the high-potential coil 23 with respect to the low-potential coil 22 with respect to the normal direction Z. Adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 is less than the distance between the dummy pattern 85 and the low-potential coil 22 with respect to the normal direction Z.

[0114] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively.

[0115] It is preferable that the dummy pattern 85 is formed around the multiple high-potential coils 23 so as to be interposed in the region between adjacent high-potential coils 23 in a plan view. In this case, the region between adjacent high-potential coils 23 can be used to suppress unwanted electric field concentration on the multiple high-potential coils 23.

[0116] It is preferable that the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23 can be suppressed. It is preferable that the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential terminal 12 caused by electric field concentration in the high-potential coil 23 can be suppressed.

[0117] In this configuration, the dummy pattern 85 is formed along the multiple high-potential coils 23 in a plan view and interposed in the region between adjacent high-potential coils 23. Furthermore, the dummy pattern 85 collectively surrounds the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12 in a plan view. Additionally, the dummy pattern 85 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential coils 23 in a plan view. Furthermore, the dummy pattern 85 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential terminals 12A-12F in a plan view.

[0118] Referring to Figures 7 to 12, the dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 includes a high-potential dummy pattern 86. The high-potential dummy pattern 86 is formed within the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. The high-potential dummy pattern 86 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. In other words, the high-potential dummy pattern 86 does not function as a transformer 21A to 21D.

[0119] In this embodiment, the high-potential dummy pattern 86 is routed in a dense linear pattern such that, in a plan view, it partially covers and partially exposes the area surrounding the high-potential coil 23. In this embodiment, the high-potential dummy pattern 86 is routed at a line density equal to that of the high-potential coil 23 per unit area. The line density of the high-potential dummy pattern 86 being equal to that of the high-potential coil 23 means that the line density of the high-potential dummy pattern 86 falls within ±20% of the line density of the high-potential coil 23.

[0120] The high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in transformers 21A to 21D, suppressing electric field concentration on the high-potential coil 23. Specifically, the high-potential dummy pattern 86 shields the electric field between the low-potential coil 22 and the high-potential coil 23, thereby keeping the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23 caused by the electric field leaking above the high-potential coil 23.

[0121] A voltage exceeding the voltage applied to the low-potential coil 22 is applied to the high-potential dummy pattern 86. This suppresses the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby suppressing electric field concentration on the high-potential coil 23. Preferably, the voltage applied to the high-potential dummy pattern 86 is the same voltage applied to the high-potential coil 23. In other words, it is preferable that the high-potential dummy pattern 86 is fixed at the same potential as the high-potential coil 23. This reliably suppresses the voltage drop between the high-potential coil 23 and the high-potential dummy pattern 86, thereby appropriately suppressing electric field concentration on the high-potential coil 23.

[0122] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the high-potential dummy pattern 86 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z relative to the low-potential coil 22. The high-potential dummy pattern 86 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22 with respect to the normal direction Z.

[0123] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. With respect to the normal direction Z, the smaller the distance between the high-potential dummy pattern 86 and the high-potential coil 23, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the high-potential dummy pattern 86 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively.

[0124] The high-potential dummy pattern 86 is preferably formed in a region that is close to the high-potential coil 23 relative to the low-potential terminal 11 in a plan view. In a plan view, the high-potential dummy pattern 86 being close to the high-potential coil 23 means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 is less than the distance between the high-potential dummy pattern 86 and the low-potential terminal 11.

[0125] It is preferable that the high-potential dummy pattern 86 is formed around the multiple high-potential coils 23 so as to be interposed in the region between adjacent high-potential coils 23 in a plan view. In this case, the region between adjacent high-potential coils 23 can be used to suppress unwanted electric field concentration on the multiple high-potential coils 23.

[0126] The high-potential dummy pattern 86 is preferably interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential coil 23 due to electric field concentration of the high-potential coil 23 can be suppressed. The high-potential dummy pattern 86 is preferably interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential terminal 12 due to electric field concentration of the high-potential coil 23 can be suppressed.

[0127] In this configuration, the high-potential dummy pattern 86 is formed along the multiple high-potential coils 23 in a plan view and interposed in the region between adjacent high-potential coils 23. Furthermore, the high-potential dummy pattern 86 collectively surrounds the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12 in a plan view. Additionally, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential coils 23 in a plan view. Furthermore, the high-potential dummy pattern 86 is interposed in the region between the multiple low-potential terminals 11A-11F and the multiple high-potential terminals 12A-12F in a plan view.

[0128] The high-potential dummy pattern 86 is routed around the high-potential terminals 12E and 12F such that, in a plan view, it exposes the area directly beneath the high-potential terminals 12E and 12F in the region between adjacent high-potential coils 23. A portion of the high-potential dummy pattern 86 may face the high-potential terminals 12A to 12F in the normal direction Z. In this case, the high-potential terminals 12E and 12F, like the high-potential dummy pattern 86, suppress the electric field leaking above the high-potential coils 23 by shielding the electric field. In other words, the high-potential terminals 12E and 12F are formed together with the high-potential dummy pattern 86 as a shielding conductor layer that suppresses electric field concentration on the high-potential coils 23.

[0129] It is preferable that the high-potential dummy pattern 86 is formed with ends. In this case, the formation of a current loop circuit (closed circuit) in the high-potential dummy pattern 86 can be suppressed. This suppresses noise caused by the current flowing through the high-potential dummy pattern 86. As a result, unwanted electric field concentration caused by noise can be suppressed, and at the same time, fluctuations in the electrical characteristics of transformers 21A to 21D can be suppressed.

[0130] The high-potential dummy pattern 86 specifically includes a first high-potential dummy pattern 87 and a second high-potential dummy pattern 88. The first high-potential dummy pattern 87 is formed in the region between a plurality of adjacent transformers 21A to 21D (a plurality of high-potential coils 23) in a plan view. The second high-potential dummy pattern 88 is formed in the region outside the region between the plurality of adjacent transformers 21A to 21D (a plurality of high-potential coils 23) in a plan view.

[0131] In the following, the region between the adjacent first transformer 21A (high-potential coil 23) and second transformer 21B (high-potential coil 23) will be referred to as the first region 89. The region between the second transformer 21B (high-potential coil 23) and the third transformer 21C (high-potential coil 23) will be referred to as the second region 90. The region between the third transformer 21C (high-potential coil 23) and the fourth transformer 21D (high-potential coil 23) will be referred to as the third region 91.

[0132] In this configuration, the first high-potential dummy pattern 87 is electrically connected to the high-potential terminal 12 (fifth high-potential terminal 12E) via the second high-potential wiring 34. Specifically, the first high-potential dummy pattern 87 includes a first connection 92 connected to the second high-potential wiring 34. The position of the first connection 92 is arbitrary. This fixes the first high-potential dummy pattern 87 at the same potential as the multiple high-potential coils 23.

[0133] The first high-potential dummy pattern 87 specifically includes a first pattern 93 formed in the first region 89, a second pattern 94 formed in the second region 90, and a third pattern 95 formed in the third region 91. As a result, the first high-potential dummy pattern 87 suppresses the electric field leaking above the high-potential coil 23 in the first region 89, the second region 90, and the third region 91, thereby suppressing electric field concentration for multiple adjacent high-potential coils 23.

[0134] In this embodiment, the first pattern 93, the second pattern 94, and the third pattern 95 are integrally formed and fixed at the same potential. The first pattern 93, the second pattern 94, and the third pattern 95 may be separated, as long as they are fixed at the same potential.

[0135] Referring to Figures 7 and 10, the first pattern 93 is connected to the second high-potential wiring 34 via the first connection part 92. The first pattern 93 is routed in a dense line pattern so as to cover a portion of the first region 89 in a plan view. In a plan view, the first pattern 93 is formed in the first region 89 at a distance from the high-potential terminal 12 (fifth high-potential terminal 12E) and does not face the high-potential terminal 12 in the normal direction Z. Also, in a plan view, the first pattern 93 is formed at a distance from the low-potential connection wiring 72 and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the first pattern 93 and the low-potential connection wiring 72 is increased, and the dielectric strength of the insulating layer 51 is enhanced.

[0136] The first pattern 93 includes a first outer perimeter line 96, a second outer perimeter line 97, and a plurality of first intermediate lines 98. The first outer perimeter line 96 extends in a band shape around the high-potential coil 23 of the first transformer 21A. In this embodiment, the first outer perimeter line 96 is formed in a ring shape with an open end in a first region 89 in plan view. The width of the open end of the first outer perimeter line 96 is less than the width along the second direction Y of the high-potential coil 23.

[0137] The width of the first outer perimeter line 96 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first outer perimeter line 96 is 1 μm or more and 3 μm or less. The width of the first outer perimeter line 96 is defined by the width in the direction perpendicular to the direction in which the first outer perimeter line 96 extends. Preferably, the width of the first outer perimeter line 96 is equal to the width of the high-potential coil 23. The width of the first outer perimeter line 96 being equal to the width of the high-potential coil 23 means that the width of the first outer perimeter line 96 falls within ±20% of the width of the high-potential coil 23.

[0138] The first pitch between the first outer circumference line 96 and the high-potential coil 23 (first transformer 21A) may be 0.1 μm or more and 5 μm or less. Preferably, the first pitch is 1 μm or more and 3 μm or less. Preferably, the first pitch is equal to the second winding pitch of the high-potential coil 23. For the first pitch to be equal to the first winding pitch means that the first pitch is within ±20% of the first winding pitch.

[0139] The second outer perimeter line 97 extends in a band-like manner around the high-potential coil 23 of the second transformer 21B. In this embodiment, the second outer perimeter line 97 is formed in a ring shape with an open end in the first region 89 in a plan view. The width of the open end of the second outer perimeter line 97 is less than the width of the high-potential coil 23 along the second direction Y. The open end of the second outer perimeter line 97 faces the open end of the first outer perimeter line 96 along the first direction X.

[0140] The width of the second outer perimeter line 97 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second outer perimeter line 97 is 1 μm or more and 3 μm or less. The width of the second outer perimeter line 97 is defined by the width in the direction perpendicular to the direction in which the second outer perimeter line 97 extends. Preferably, the width of the second outer perimeter line 97 is equal to the width of the high-potential coil 23. The width of the second outer perimeter line 97 being equal to the width of the high-potential coil 23 means that the width of the second outer perimeter line 97 falls within a range of ±20% of the width of the high-potential coil 23.

[0141] The second pitch between the second outer circumference line 97 and the high-potential coil 23 (second transformer 21B) may be 0.1 μm or more and 5 μm or less. Preferably, the second pitch is 1 μm or more and 3 μm or less. Preferably, the second pitch is equal to the second winding pitch of the high-potential coil 23. When the second pitch is equal to the second winding pitch, it means that the second pitch is within ±20% of the second winding pitch.

[0142] Multiple first intermediate lines 98 extend in a strip-like manner in the region between the first outer perimeter line 96 and the second outer perimeter line 97 in the first region 89. Each of the multiple first intermediate lines 98 includes at least one (one in this embodiment) first connecting line 99 that electrically connects the first outer perimeter line 96 and the second outer perimeter line 97.

[0143] From the viewpoint of preventing the formation of current loop circuits, it is preferable that the plurality of first intermediate lines 98 include only one first connection line 99. The position of the first connection line 99 is arbitrary. At least one of the plurality of first intermediate lines 98 has a slit 100 formed therein to interrupt the current loop circuit. The position of the slit 100 is appropriately adjusted depending on the design of the plurality of first intermediate lines 98.

[0144] Preferably, the multiple first intermediate lines 98 are formed in a strip shape extending along the opposing directions of the multiple high-potential coils 23. In this embodiment, each of the multiple first intermediate lines 98 is formed in a strip shape extending in a first direction X and is formed with gaps in the second direction Y. In a plan view, the multiple first intermediate lines 98 as a whole are formed in a stripe shape extending in the first direction X.

[0145] The multiple first intermediate lines 98 specifically include multiple first lead-out sections 101 and multiple second lead-out sections 102. The multiple first lead-out sections 101 are drawn out in a stripe pattern from the first outer peripheral line 96 toward the second outer peripheral line 97. The tips of the multiple first lead-out sections 101 are formed with a gap between them and the second outer peripheral line 97 side from the first outer peripheral line 96.

[0146] Multiple second extensions 102 are drawn out in a stripe pattern from the second outer circumference line 97 toward the first outer circumference line 96. The tips of the multiple second extensions 102 are formed with a gap between them and the first outer circumference line 96 from the second outer circumference line 97. In this configuration, the multiple second extensions 102 are formed alternately with the multiple first extensions 101 in the second direction Y, sandwiching one first extension 101.

[0147] Multiple second lead portions 102 may sandwich multiple first lead portions 101. Furthermore, a group including multiple second lead portions 102 may be formed adjacent to a group including multiple first lead portions 101. The slit 100, the multiple first lead portions 101, and the multiple second lead portions 102 suppress the formation of current loop circuits in the first pattern 93.

[0148] With respect to the second direction Y, the width of the first intermediate line 98 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the first intermediate line 98 is 1 μm or more and 3 μm or less. Preferably, the width of the first intermediate line 98 is equal to the width of the high-potential coil 23. The width of the first intermediate line 98 being equal to the width of the high-potential coil 23 means that the width of the first intermediate line 98 is within ±20% of the width of the high-potential coil 23.

[0149] The third pitch of two adjacent first intermediate lines 98 may be 0.1 μm or more and 5 μm or less. Preferably, the third pitch is 1 μm or more and 3 μm or less. The third pitch is defined by the distance between a plurality of adjacent first intermediate lines 98 with respect to the second direction Y. Preferably, the third pitches are equal to each other. Equal third pitches mean that the third pitches fall within a range of ±20% of the third pitch. Preferably, the third pitch is equal to the second winding pitch of the high-potential coil 23. Equal third pitches mean that the third pitch falls within a range of ±20% of the second winding pitch.

[0150] Referring to Figures 7 and 11, the second pattern 94 is electrically connected to the high-potential terminal 12 via the first high-potential wiring 33. In this embodiment, the second pattern 94 is electrically connected to the second high-potential wiring 34 (fifth high-potential terminal 12E) via the second outer periphery line 97 of the first pattern 93. The second pattern 94 is routed in a dense linear fashion so as to cover the second region 90.

[0151] The second pattern 94 includes the aforementioned second outer perimeter line 97, third outer perimeter line 103, and a plurality of second intermediate lines 104. The third outer perimeter line 103 extends in a band shape around the high-potential coil 23 of the third transformer 21C. In this embodiment, the third outer perimeter line 103 is formed in a ring shape with an open end in the third region 91 in plan view. The width of the open end of the third outer perimeter line 103 is less than the width along the second direction Y of the high-potential coil 23 of the third transformer 21C.

[0152] The width of the third outer perimeter line 103 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the third outer perimeter line 103 is 1 μm or more and 3 μm or less. The width of the third outer perimeter line 103 is defined by the width in the direction perpendicular to the direction in which the third outer perimeter line 103 extends. Preferably, the width of the third outer perimeter line 103 is equal to the width of the high-potential coil 23. The width of the third outer perimeter line 103 being equal to the width of the high-potential coil 23 means that the width of the third outer perimeter line 103 falls within ±20% of the width of the high-potential coil 23.

[0153] The fourth pitch between the third outer circumference line 103 and the high-potential coil 23 (third transformer 21C) may be 0.1 μm or more and 5 μm or less. Preferably, the fourth pitch is 1 μm or more and 3 μm or less. Preferably, the fourth pitch is equal to the second winding pitch of the high-potential coil 23. Equal to the second winding pitch means that the fourth pitch is within ±20% of the second winding pitch.

[0154] The multiple second intermediate lines 104 extend in a strip-like manner in the region between the second outer perimeter line 97 and the third outer perimeter line 103 in the second region 90. The multiple second intermediate lines 104 include at least one (one in this embodiment) second connecting line 105 that electrically connects the second outer perimeter line 97 and the third outer perimeter line 103.

[0155] From the viewpoint of preventing the formation of current loop circuits, it is preferable that the plurality of second intermediate lines 104 include only one second connecting line 105. The second connecting line 105 may have a width exceeding the width of the other second intermediate lines 104. The position of the second connecting line 105 is arbitrary. At least one of the plurality of second intermediate lines 104 has a slit 106 formed therein to interrupt the current loop circuit. The position of the slit 106 is appropriately adjusted depending on the design of the plurality of second intermediate lines 104.

[0156] Preferably, the multiple second intermediate lines 104 are formed in a strip shape extending along the opposing directions of the multiple high-potential coils 23. In this embodiment, each of the multiple second intermediate lines 104 is formed in a strip shape extending in the first direction X and is formed with gaps in the second direction Y. In a plan view, the multiple second intermediate lines 104 as a whole are formed in a stripe shape extending in the first direction X.

[0157] The multiple second intermediate lines 104 specifically include multiple third lead sections 107 and multiple fourth lead sections 108. The multiple third lead sections 107 are drawn out in a stripe pattern from the second outer perimeter line 97 toward the third outer perimeter line 103. The tips of the multiple third lead sections 107 are formed with a gap between the third outer perimeter line 103 and the second outer perimeter line 97.

[0158] Multiple fourth extensions 108 are drawn out in a stripe pattern from the third outer circumference line 103 toward the second outer circumference line 97. The tips of the multiple fourth extensions 108 are formed with a gap between them and the third outer circumference line 103 from the second outer circumference line 97. In this configuration, the multiple fourth extensions 108 are formed alternately with the multiple third extensions 107 in the second direction Y, sandwiching one third extension 107.

[0159] Multiple fourth lead sections 108 may sandwich multiple third lead sections 107. Furthermore, a group including multiple fourth lead sections 108 may be formed adjacent to a group including multiple third lead sections 107. The slit 106, the multiple third lead sections 107, and the multiple fourth lead sections 108 suppress the formation of current loop circuits in the second pattern 94.

[0160] With respect to the second direction Y, the width of the second intermediate line 104 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the second intermediate line 104 is 1 μm or more and 3 μm or less. Preferably, the width of the second intermediate line 104 is equal to the width of the high-potential coil 23. When the width of the second intermediate line 104 is equal to the width of the high-potential coil 23, it means that the width of the second intermediate line 104 is within ±20% of the width of the high-potential coil 23.

[0161] The fifth pitch of two adjacent second intermediate lines 104 may be 0.1 μm or more and 5 μm or less. Preferably, the fifth pitch is 1 μm or more and 3 μm or less. The fifth pitch is defined by the distance between a plurality of adjacent second intermediate lines 104 with respect to the second direction Y. Preferably, the fifth pitches are equal to each other. Equal fifth pitches mean that the fifth pitch falls within a range of ±20% of the fifth pitch. Preferably, the fifth pitch is equal to the second winding pitch of the high-potential coil 23. Equal fifth pitches mean that the fifth pitch falls within a range of ±20% of the second winding pitch.

[0162] Referring to Figures 7 and 12, the third pattern 95 is electrically connected to the second high-potential wiring 34. In this embodiment, the third pattern 95 is electrically connected to the second high-potential wiring 34 via the second pattern 94 and the first pattern 93. The third pattern 95 is routed in a dense line pattern so as to cover a portion of the third region 91. In a plan view, the third pattern 95 is formed in the third region 91 at a distance from the high-potential terminal 12 (sixth high-potential terminal 12F) and does not face the high-potential terminal 12 in the normal direction Z.

[0163] The third pattern 95 is formed at a distance from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. As a result, the insulation distance between the third pattern 95 and the low-potential connection wiring 72 is increased in the normal direction Z, and the dielectric strength of the insulating layer 51 is increased.

[0164] The third pattern 95 includes the aforementioned third outer perimeter line 103, fourth outer perimeter line 109, and a plurality of third intermediate lines 110. The fourth outer perimeter line 109 extends in a band shape around the high-potential coil 23 of the fourth transformer 21D. In this embodiment, the fourth outer perimeter line 109 is formed in a ring shape with an open end in the third region 91 in plan view. The width of the open end of the fourth outer perimeter line 109 is less than the width along the second direction Y of the high-potential coil 23 of the fourth transformer 21D. The open end of the fourth outer perimeter line 109 faces the open end of the third outer perimeter line 103 along the first direction X.

[0165] The width of the fourth outer perimeter line 109 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the fourth outer perimeter line 109 is 1 μm or more and 3 μm or less. The width of the fourth outer perimeter line 109 is defined by the width in the direction perpendicular to the direction in which the fourth outer perimeter line 109 extends. Preferably, the width of the fourth outer perimeter line 109 is equal to the width of the high-potential coil 23. When the width of the fourth outer perimeter line 109 is equal to the width of the high-potential coil 23, it means that the width of the fourth outer perimeter line 109 falls within a range of ±20% of the width of the high-potential coil 23.

[0166] The sixth pitch between the fourth outer circumference line 109 and the high-potential coil 23 (fourth transformer 21D) may be 0.1 μm or more and 5 μm or less. Preferably, the sixth pitch is 1 μm or more and 3 μm or less. Preferably, the sixth pitch is equal to the second winding pitch of the high-potential coil 23. Equal to the second winding pitch means that the sixth pitch is within ±20% of the second winding pitch.

[0167] The multiple third intermediate lines 110 extend in a strip-like manner in the third region 91 between the third outer perimeter line 103 and the fourth outer perimeter line 109. The multiple third intermediate lines 110 include at least one (one in this embodiment) third connecting line 111 that electrically connects the third outer perimeter line 103 and the fourth outer perimeter line 109.

[0168] From the viewpoint of preventing the formation of current loop circuits, it is preferable that the plurality of third intermediate lines 110 include only one third connecting line 111. The position of the third connecting line 111 is arbitrary. At least one of the plurality of third intermediate lines 110 has a slit 112 formed therein to interrupt the current loop circuit. The position of the slit 112 is appropriately adjusted depending on the design of the plurality of third intermediate lines 110.

[0169] Preferably, the multiple third intermediate lines 110 are formed in a strip shape extending along the opposing directions of the multiple high-potential coils 23. In this embodiment, each of the multiple third intermediate lines 110 is formed in a strip shape extending in the first direction X and is formed with gaps in the second direction Y. The multiple third intermediate lines 110 are formed in a stripe shape as a whole in a plan view.

[0170] In this embodiment, the multiple third intermediate lines 110 include multiple fifth lead sections 113 and multiple sixth lead sections 114. The multiple fifth lead sections 113 are drawn out in a stripe pattern from the third outer perimeter line 103 toward the fourth outer perimeter line 109. The ends of the multiple fifth lead sections 113 are formed with a gap between the fourth outer perimeter line 109 and the third outer perimeter line 103.

[0171] Multiple sixth extension sections 114 are drawn out in a stripe pattern from the fourth outer circumference line 109 toward the third outer circumference line 103. The tips of the multiple sixth extension sections 114 are formed with a gap between them, from the third outer circumference line 103 toward the fourth outer circumference line 109. In this configuration, the multiple sixth extension sections 114 are formed alternately with the multiple fifth extension sections 113 in the second direction Y, sandwiching one fifth extension section 113.

[0172] Multiple sixth lead sections 114 may sandwich multiple fifth lead sections 113. Furthermore, a group including multiple sixth lead sections 114 may be formed adjacent to a group including multiple fifth lead sections 113. The slit 112, the multiple fifth lead sections 113, and the multiple sixth lead sections 114 suppress the formation of current loop circuits in the third pattern 95.

[0173] With respect to the second direction Y, the width of the third intermediate line 110 may be 0.1 μm or more and 5 μm or less. Preferably, the width of the third intermediate line 110 is 1 μm or more and 3 μm or less. Preferably, the width of the third intermediate line 110 is equal to the width of the high-potential coil 23. When the width of the third intermediate line 110 is equal to the width of the high-potential coil 23, it means that the width of the third intermediate line 110 is within ±20% of the width of the high-potential coil 23.

[0174] The seventh pitch of two adjacent third intermediate lines 110 may be 0.1 μm or more and 5 μm or less. Preferably, the seventh pitch is 1 μm or more and 3 μm or less. The seventh pitch is defined by the distance between a plurality of adjacent third intermediate lines 110 with respect to the second direction Y. Preferably, the seventh pitches are equal to each other. Equal seventh pitches mean that the seventh pitch falls within a range of ±20% of the seventh pitch. Preferably, the seventh pitch is equal to the second winding pitch of the high-potential coil 23. Equal seventh pitch means that the seventh pitch falls within a range of ±20% of the second winding pitch.

[0175] Referring to Figures 7 to 12, the second high-potential dummy pattern 88 is electrically connected to the high-potential terminal 12 via the first high-potential dummy pattern 87 in this configuration. Specifically, the second high-potential dummy pattern 88 includes a second connection 115 connected to the first high-potential dummy pattern 87. The position of the second connection 115 is arbitrary. This fixes the second high-potential dummy pattern 88 at the same potential as the multiple high-potential coils 23.

[0176] The second high-potential dummy pattern 88 suppresses the electric field leaking above the high-potential coil 23 in the regions outside the first region 89, the second region 90, and the third region 91, thereby suppressing electric field concentration on the multiple high-potential coils 23. In this configuration, the second high-potential dummy pattern 88 collectively surrounds the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12A to 12F in a plan view. In this configuration, the second high-potential dummy pattern 88 is formed in an oval (elliptical) shape in a plan view.

[0177] As a result, the second high-potential dummy pattern 88 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential coils 23 in a plan view. Furthermore, the second high-potential dummy pattern 88 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential terminals 12A to 12F in a plan view.

[0178] The second high-potential dummy pattern 88 includes several (six in this configuration) high-potential lines 116A, 116B, 116C, 116D, 116E, and 116F. The number of high-potential lines is adjusted according to the electric field to be mitigated. The multiple high-potential lines 116A to 116F are formed in this order, spaced apart, in the direction away from the multiple high-potential coils 23.

[0179] Multiple high-potential lines 116A to 116F collectively surround multiple high-potential coils 23 in a plan view. Specifically, multiple high-potential lines 116A to 116F collectively surround the region containing multiple high-potential coils 23 and multiple high-potential terminals 12A to 12F in a plan view. In this configuration, multiple high-potential lines 116A to 116F are formed in an oval (elliptical) shape in a plan view.

[0180] Each of the multiple high-potential lines 116A to 116F includes a slit 117 that interrupts the current loop circuit. The position of the slit 117 is adjusted as appropriate depending on the design of the multiple high-potential lines 116A to 116F.

[0181] The width of the high-potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. Preferably, the width of the high-potential lines 116A to 116F is 1 μm or more and 3 μm or less. The width of the high-potential lines 116A to 116F is defined by the width in the direction perpendicular to the direction in which the high-potential lines 116A to 116F extend. Preferably, the width of the high-potential lines 116A to 116F is equal to the width of the high-potential coil 23. When the width of the high-potential lines 116A to 116F is equal to the width of the high-potential coil 23, it means that the width of the high-potential lines 116A to 116F falls within ±20% of the width of the high-potential coil 23.

[0182] The eighth pitch of two adjacent high-potential lines 116A to 116F may be 0.1 μm or more and 5 μm or less. Preferably, the eighth pitch is 1 μm or more and 3 μm or less. Preferably, the eighth pitches are equal to each other. Equal eighth pitches mean that the eighth pitches fall within a range of ±20% of the eighth pitch of that eighth pitch.

[0183] The ninth pitch between adjacent first high-potential dummy patterns 87 and second high-potential dummy patterns 88 may be 0.1 μm or more and 5 μm or less. Preferably, the ninth pitch is 1 μm or more and 3 μm or less. Preferably, the ninth pitch is equal to the second winding pitch of the high-potential coil 23. Equaling the ninth pitch to the second winding pitch means that the ninth pitch falls within a range of ±20% of the second winding pitch. The number, width, pitch, etc. of the multiple high-potential lines 116A to 116F are arbitrary and are adjusted according to the electric field to be mitigated.

[0184] Referring to Figures 7 to 12, the dummy pattern 85 includes a floating dummy pattern 121 that is electrically floating within the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view. The floating dummy pattern 121 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22 and is independent of the transformers 21A to 21D. In other words, the floating dummy pattern 121 does not function as a transformer 21A to 21D.

[0185] In this embodiment, the floating dummy pattern 121 is routed in a dense linear fashion so as to partially cover and partially expose the area surrounding the high-potential coil 23 in a plan view. The floating dummy pattern 121 may be formed with ends or as an endless pattern.

[0186] The floating dummy pattern 121 is routed at a line density equal to that of the high-potential coil 23 per unit area. The line density of the floating dummy pattern 121 being equal to that of the high-potential coil 23 means that the line density of the floating dummy pattern 121 falls within ±20% of the line density of the high-potential coil 23.

[0187] Furthermore, the floating dummy pattern 121 is routed with a line density equal to that of the high-potential dummy pattern 86 per unit area. The line density of the floating dummy pattern 121 being equal to that of the high-potential dummy pattern 86 means that the line density of the floating dummy pattern 121 falls within ±20% of the line density of the high-potential dummy pattern 86.

[0188] The floating dummy pattern 121 shields the electric field between the low-potential coil 22 and the high-potential coil 23 in transformers 21A to 21D, suppressing electric field concentration on the high-potential coil 23. Specifically, the floating dummy pattern 121 disperses the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23.

[0189] Furthermore, the floating dummy pattern 121 disperses the electric field leaking above the high-potential dummy pattern 86 in a direction away from the high-potential coil 23 and the high-potential dummy pattern 86. This suppresses electric field concentration on the high-potential dummy pattern 86 while also appropriately suppressing electric field concentration on the high-potential coil 23.

[0190] The depth position of the floating dummy pattern 121 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the floating dummy pattern 121 is formed in a region adjacent to the high-potential coil 23 with respect to the normal direction Z, relative to the low-potential coil 22. The floating dummy pattern 121 being adjacent to the high-potential coil 23 with respect to the normal direction Z means that the distance between the floating dummy pattern 121 and the high-potential coil 23 is less than the distance between the floating dummy pattern 121 and the low-potential coil 22, with respect to the normal direction Z.

[0191] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the floating dummy pattern 121 and the high-potential coil 23 with respect to the normal direction Z, the more effectively electric field concentration on the high-potential coil 23 can be suppressed. It is preferable that the floating dummy pattern 121 is formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be suppressed even more effectively.

[0192] The floating dummy pattern 121 is preferably interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23 can be suppressed. The floating dummy pattern 121 is preferably interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. In this case, unwanted conduction between the low-potential terminal 11 and the high-potential terminal 12 caused by electric field concentration in the high-potential coil 23 can be suppressed.

[0193] In this embodiment, the floating dummy pattern 121 is formed along a plurality of high-potential coils 23 in a plan view. Specifically, the floating dummy pattern 121 collectively surrounds an area containing a plurality of high-potential coils 23 and a plurality of high-potential terminals 12 in a plan view. In this embodiment, the floating dummy pattern 121 collectively surrounds an area containing a plurality of high-potential coils 23 and a plurality of high-potential terminals 12, with the high-potential dummy pattern 86 (second high-potential dummy pattern 88) in between, in a plan view.

[0194] As a result, the floating dummy pattern 121 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential coils 23 in a plan view. Furthermore, the floating dummy pattern 121 is interposed in the region between the multiple low-potential terminals 11A to 11F and the multiple high-potential terminals 12A to 12F in a plan view.

[0195] The number of floating lines is arbitrary and is adjusted according to the electric field to be mitigated. In this configuration, the floating dummy pattern 121 includes several (six in this configuration) floating lines 122A, 122B, 122C, 122D, 122E, and 122F. The floating lines 122A to 122F are formed in this order, spaced apart, in the direction away from the multiple high-potential coils 23.

[0196] The multiple floating lines 122A to 122F collectively surround the multiple high-potential coils 23 in a plan view. Specifically, the multiple floating lines 122A to 122F collectively surround the region containing the multiple high-potential coils 23 and the multiple high-potential terminals 12A to 12F, with the high-potential dummy pattern 86 in between, in a plan view. In this configuration, the multiple floating lines 122A to 122F are formed in an oval (elliptical) shape in a plan view.

[0197] The width of the floating lines 122A to 122F may be 0.1 μm or more and 5 μm or less. Preferably, the width of the floating lines 122A to 122F is 1 μm or more and 3 μm or less. The width of the floating lines 122A to 122F is defined by the width in the direction perpendicular to the direction in which the floating lines 122A to 122F extend.

[0198] The tenth pitch between two adjacent floating lines 122A to 122F may be 0.1 μm or more and 5 μm or less. Preferably, the tenth pitch is 1 μm or more and 3 μm or less. Preferably, the width of the floating lines 122A to 122F is equal to the width of the high-potential coil 23. The width of the floating lines 122A to 122F being equal to the width of the high-potential coil 23 means that the width of the floating lines 122A to 122F is within ±20% of the width of the high-potential coil 23.

[0199] The 11th pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 (second high-potential dummy pattern 88) may be 0.1 μm or more and 5 μm or less. Preferably, the 11th pitch is 1 μm or more and 3 μm or less. Preferably, the 11th pitches are equal to each other. Equal to each other means that the 11th pitches fall within a range of ±20% of the given 11th pitch.

[0200] The 11th pitch is preferably equal to the second winding pitch of the high-potential coil 23. The 11th pitch between the floating lines 122A to 122F being equal to the second winding pitch means that the 11th pitch falls within ±20% of the second winding pitch. Figures 10 to 12 show examples where the 11th pitch exceeds the second winding pitch for clarity.

[0201] The 12th pitch between the floating dummy pattern 121 and the high-potential dummy pattern 86 is preferably equal to the second winding pitch. The 12th pitch being equal to the second winding pitch means that the 12th pitch falls within a range of ±20% of the second winding pitch. The number, width, pitch, etc., of the multiple floating lines 122A to 122F are adjusted according to the electric field to be mitigated and are not limited to specific values.

[0202] Referring to Figures 8 and 9, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using the surface layer of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (bottom insulating layer 55). In Figures 8 and 9, the second functional device 60 is simplified by dashed lines shown on the surface layer of the first main surface 42.

[0203] The second functional device 60 is electrically connected to the low-potential terminal 11 via low-potential wiring and to the high-potential terminal 12 via high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 to connect to the second functional device 60. A detailed explanation of the low-potential and high-potential wiring related to the second functional device 60 is omitted.

[0204] The second functional device 60 may include at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more devices from among the passive device, semiconductor rectifier device, and semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0205] Passive devices may include semiconductor passive devices. Passive devices may include either a resistor or a capacitor, or both. Semiconductor rectifier devices may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. Semiconductor switching devices may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0206] Referring to Figures 8 and 9, the semiconductor device 5 further includes a sealing conductor 61 embedded in the insulating layer 51. In a plan view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating side walls 53A to 53D, and divides the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 suppresses the intrusion of moisture and cracks from the outer region 63 into the device region 62.

[0207] The device region 62 is the region that includes the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. The outer region 63 is the region outside the device region 62.

[0208] The sealing conductor 61 is electrically isolated from the device region 62. Specifically, the sealing conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealing conductor 61 is electrically suspended. The sealing conductor 61 does not form a current path that connects to the device region 62.

[0209] The sealing conductor 61 is formed in a strip shape along the insulating side walls 53-53D in a plan view. In this configuration, the sealing conductor 61 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. As a result, the sealing conductor 61 demarcates a rectangular (specifically, rectangular) device region 62 in a plan view. Furthermore, the sealing conductor 61 demarcates the outer rectangular ring (specifically, a rectangular ring shape) region 63 surrounding the device region 62 in a plan view.

[0210] Specifically, the seal conductor 61 has an upper end on the insulating main surface 52 side, a lower end on the semiconductor chip 41 side, and a wall portion extending wall-like between the upper end and the lower end. In this embodiment, the upper end of the seal conductor 61 is formed with a gap from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed with a gap from the semiconductor chip 41 toward the upper end side.

[0211] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side relative to the multiple low-potential terminals 11 and the multiple high-potential terminals 12. Furthermore, within the insulating layer 51, the sealing conductor 61 faces the first functional device 45 (multiple transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Within the insulating layer 51, the sealing conductor 61 may also face a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0212] The seal conductor 61 includes a plurality of seal plug conductors (first portion) 64 and one or more (in this embodiment, multiple) seal via conductors (second portion) 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 of the plurality of seal plug conductors 64 forms the upper end of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end of the seal conductor 61. It is preferable that the seal plug conductors 64 and seal via conductors 65 are made of the same conductive material as the low-potential coil 22. That is, it is preferable that the seal plug conductors 64 and seal via conductors 65 include a barrier layer and a body layer, similar to the low-potential coil 22, etc.

[0213] Multiple seal plug conductors 64 are embedded in multiple interlayer insulating layers 57, and in a plan view, they are each formed in a rectangular ring (specifically, a rectangular ring) surrounding the device region 62. Multiple seal plug conductors 64 are stacked from the bottom insulating layer 55 toward the top insulating layer 56 so as to be connected to each other. The number of stacked seal plug conductors 64 corresponds to the number of stacked interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0214] If a single annular seal conductor 61 is formed by an assembly of multiple seal plug conductors 64, it is not necessary for all of the multiple seal plug conductors 64 to be formed in an annular shape. For example, at least one of the multiple seal plug conductors 64 may be formed with ends. Alternatively, at least one of the multiple seal plug conductors 64 may be divided into multiple end-shaped strips. However, considering the risk of moisture and cracks entering the device region 62, it is preferable that the multiple seal plug conductors 64 be formed in an endless (annular) shape.

[0215] Multiple seal via conductors 65 are formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the bottom insulating layer 55. The multiple seal via conductors 65 are formed at intervals from the semiconductor chip 41 and connected to the seal plug conductor 64. The multiple seal via conductors 65 have a planar area less than the planar area of ​​the seal plug conductor 64. If a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area greater than or equal to the planar area of ​​the seal plug conductor 64.

[0216] The width of the seal conductor 61 may be 0.1 μm or more and 10 μm or less. Preferably, the width of the seal conductor 61 is 1 μm or more and 5 μm or less. The width of the seal conductor 61 is defined by the width in the direction perpendicular to the direction in which the seal conductor 61 extends.

[0217] Referring to Figures 8, 9, and 13, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the sealing conductor 61, electrically isolating the sealing conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 consists of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0218] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 consists of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0219] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the seal conductor 61 in a plan view. In this embodiment, the isolation structure 130 is formed in a rectangular ring shape (specifically, a rectangular ring shape) in a plan view. The isolation structure 130 has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion to which the lower end (seal via conductor 65) of the seal conductor 61 bites toward the semiconductor chip 41 side. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0220] The separation structure 130 includes an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. The inner end portion 130A demarcates the region where the second functional device 60 is formed (i.e., the device region 62) in a plan view. The inner end portion 130A may be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0221] The outer end portion 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. Specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may be formed within the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0222] The main body portion 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body portion 130C has a connection portion 132 to which the lower end (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in the main body portion 130C at a distance from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms, as shown in Figures 14A to 14D, in addition to the field insulating film 131.

[0223] Figure 14A is an enlarged view of region XIII shown in Figure 8, and shows the separation structure 130 according to the second embodiment. Referring to Figure 14A, the separation structure 130 may have a laminated structure including an insulating film 133 formed on the first main surface 42 and a conductive film 134 formed on the insulating film 133. In this case, either or both of the insulating film 133 and the conductive film 134 may be exposed from the chip sidewalls 44A to 44D.

[0224] The insulating film 133 may contain silicon oxide or silicon nitride. The insulating film 133 may also be a field insulating film 131. The thickness of the insulating film 133 may be 0.1 μm or more and 5 μm or less. The conductive film 134 contains polysilicon or metal and is formed in an electrically floating state. The thickness of the conductive film 134 may be 0.1 μm or more and 5 μm or less. The connection portion 132 with the seal conductor 61 is formed in the conductive film 134.

[0225] Figure 14B is an enlarged view of region XIII shown in Figure 8, and shows the separation structure 130 according to the third embodiment. Referring to Figure 14B, the separation structure 130 includes a trench 135 formed in the first main surface 42, and an embedded body 136 embedded in the trench 135. In this case, the trench 135 and the embedded body 136 are exposed from the chip sidewalls 44A to 44D. The embedded body 136 is embedded in the trench 135 so as to be electrically isolated from the semiconductor chip 41. Specifically, the embedded body 136 is embedded in the trench 135 so as to be electrically floating.

[0226] In this embodiment, the buried body 136 consists of an insulator 137. That is, the isolation structure 130 consists of a trench insulation structure. The trench insulation structure may be STI (shallow trench isolation). The depth of the trench 135 may be 0.1 μm or more and 5 μm or less. The buried body 136 may contain silicon oxide or silicon nitride. The buried body 136 may have a main surface that protrudes above the first main surface 42. The buried body 136 may have a main surface that is located on the bottom wall side of the trench 135 than the first main surface 42. The buried body 136 may have a main surface that is connected to the first main surface 42. The connection portion 132 with the seal conductor 61 is formed in the buried body 136.

[0227] Figure 14C is an enlarged view of region XIII shown in Figure 8, and shows the separation structure 130 according to the fourth embodiment. Referring to Figure 14C, the separation structure 130 includes a trench 135 formed in the first main surface 42, and an embedded body 136 embedded in the trench 135. In this case, the trench 135 and the embedded body 136 are exposed from the chip sidewalls 44A to 44D. The embedded body 136 is embedded in the trench 135 so as to be electrically isolated from the semiconductor chip 41. Specifically, the embedded body 136 is embedded in the trench 135 so as to be electrically floating.

[0228] In this embodiment, the embedded body 136 includes an insulating film 138 formed on the wall surface of the trench 135, and a conductor 139 embedded in the trench 135 with the insulating film 138 in between. The conductor 139 is electrically insulated from the semiconductor chip 41 by the insulating film 138 and is embedded in an electrically floating state. In other words, the isolation structure 130 consists of a trench insulating structure. The trench insulating structure may also be an STI.

[0229] The depth of the trench 135 may be between 0.1 μm and 5 μm. The insulating film 138 may contain silicon oxide or silicon nitride. The thickness of the insulating film 138 may be between 0.1 μm and 2 μm. The conductor 139 contains polysilicon or metal and is embedded in an electrically floating state. The conductor 139 may have a main surface that protrudes above the first main surface 42. The conductor 139 may have a main surface that is located on the bottom wall side of the trench 135 above the first main surface 42. The conductor 139 may have a main surface that is connected to the first main surface 42. The connection portion 132 with the seal conductor 61 is formed in the conductor 139.

[0230] Figure 14D is an enlarged view of region XIII shown in Figure 8, and shows the separation structure 130 according to the fifth embodiment. Referring to Figure 14D, the separation structure 130 consists of a part of the insulating layer 51. The separation structure 130 may include the bottom insulating layer 55 and one or more interlayer insulating layers 57. In this embodiment, the separation structure 130 consists of the bottom insulating layer 55. In this embodiment, the seal conductor 61 does not have a seal via conductor 65 and has a lower end consisting of a seal plug conductor 64. The connection portion 132 of the separation structure 130 consists of the connection portion between the insulating layer 51 (bottom insulating layer 55) and the lower end of the seal conductor 61 (seal plug conductor 64).

[0231] Referring to Figures 8 and 9, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating main surface 52.

[0232] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. Preferably, the first inorganic insulating layer 141 contains USG (undoped siliconcate glass), which is silicon oxide without impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength on the high-potential coil 23 can be increased.

[0233] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the dielectric breakdown voltage (V / cm) of USG exceeds the dielectric breakdown voltage (V / cm) of silicon nitride. Therefore, when thickening the inorganic insulating layer 140, it is preferable to form the first inorganic insulating layer 141 which is thicker than the second inorganic insulating layer 142.

[0234] The first inorganic insulating layer 141 may contain at least one of BPSG (borondopedphosphorsilicateglass) and PSG (phosphorussilicateglass) as examples of silicon oxide. However, in this case, since impurities (boron and phosphorus) are contained in the silicon oxide, it is particularly preferable that the first inorganic insulating layer 141 be made of USG in order to increase the dielectric strength on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure consisting of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0235] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed in the area outside the seal conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11, respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that ride up over the periphery of the high-potential terminals 12.

[0236] The semiconductor device 5 further includes an organic insulating layer 145 formed on an inorganic insulating layer 140. The organic insulating layer 145 may contain a photosensitive resin. The organic insulating layer 145 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0237] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than or equal to the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Also, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. With these structures, the thickness of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, and at the same time, the dielectric strength on the high-potential coil 23 can be appropriately increased by the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0238] The organic insulating layer 145 includes a first portion 146 that covers the low-potential region and a second portion 147 that covers the high-potential region. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 in between. The first portion 146 has a plurality of low-potential terminal openings 148 that expose a plurality of low-potential terminals 11 (low-potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have overlapping portions that ride up on the periphery (overlap portion) of the low-potential pad openings 143.

[0239] The second portion 147 is formed at a distance from the first portion 146, exposing the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149, each exposing a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may have overlapping portions that rise over the periphery (overlap portion) of the high-potential pad openings 144.

[0240] The second section 147 covers the transformers 21A to 21D and the dummy pattern 85 together. Specifically, the second section 147 covers the multiple high-potential coils 23, the multiple high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121 together.

[0241] If the organic insulating layer 145 is not formed, damage may occur to multiple high-potential coils 23, multiple high-potential terminals 12, sealing conductors 61, first high-potential dummy pattern 87, second high-potential dummy pattern 88, and floating dummy pattern 121 due to fillers contained in the package body 2 (molding resin). This type of damage is called filler attack.

[0242] The organic insulating layer 145 protects the multiple high-potential coils 23, multiple high-potential terminals 12, sealing conductors 61, first high-potential dummy pattern 87, second high-potential dummy pattern 88, and floating dummy pattern 121 from fillers contained in the package body 2 (molded resin). The slit between the first part 146 and the second part 147 functions as an anchor to the package body 2 (molded resin).

[0243] A portion of the package body 2 (molded resin) enters the slit between the first portion 146 and the second portion 147 and connects to the inorganic insulating layer 140. This increases the adhesion of the package body 2 (molded resin) to the semiconductor device 5. Of course, the first portion 146 and the second portion 147 may be formed integrally. Also, the organic insulating layer 145 may consist of only one of the first portion 146 and the second portion 147. However, in this case, attention must be paid to filler attack.

[0244] Figure 15 is a graph showing the average instantaneous dielectric breakdown voltage. In Figure 15, the vertical axis represents the average instantaneous dielectric breakdown voltage [kV·rms], and the horizontal axis represents the item. A higher average instantaneous dielectric breakdown voltage indicates a higher withstand voltage of the insulating layer 51. Figure 15 shows the first bar graph G1, the second bar graph G2, the third bar graph G3, and the fourth bar graph G4.

[0245] The first bar graph G1 shows the average instantaneous dielectric breakdown voltage of the semiconductor device 5 according to the first structure. In the semiconductor device 5 according to the first structure, no dummy pattern 85 is formed. The second bar graph G2 shows the average instantaneous dielectric breakdown voltage of the semiconductor device 5 according to the second structure. In the semiconductor device 5 according to the second structure, a dummy pattern 85 is formed that includes only the second high-potential dummy pattern 88.

[0246] The third bar graph G3 shows the average instantaneous dielectric breakdown voltage of the semiconductor device 5 relating to the third structure. In the semiconductor device 5 relating to the third structure, a dummy pattern 85 is formed that includes only a floating dummy pattern 121 and a second high-potential dummy pattern 88. The fourth bar graph G4 shows the average instantaneous dielectric breakdown voltage of the semiconductor device 5 relating to the fourth structure. In the semiconductor device 5 relating to the fourth structure, a dummy pattern 85 is formed that includes a first high-potential dummy pattern 87, a second high-potential dummy pattern 88, and a floating dummy pattern 121.

[0247] Referring to the first bar graph G1 and the second bar graph G2, the average instantaneous dielectric breakdown voltage increased by 11.2% by forming the second high-potential dummy pattern 88. Referring to the second bar graph G2 and the third bar graph G3, the average instantaneous dielectric breakdown voltage increased by 13.2% by forming a floating dummy pattern 121 in addition to the second high-potential dummy pattern 88.

[0248] Referring to the third bar graph G3 and the fourth bar graph G4, the average instantaneous dielectric breakdown voltage increased by 6.2% by forming the first high-potential dummy pattern 87 in addition to the second high-potential dummy pattern 88 and the floating dummy pattern 121. Referring to the first bar graph G1 and the fourth bar graph G4, the average instantaneous dielectric breakdown voltage increased by 13.37% by forming the first high-potential dummy pattern 87, the second high-potential dummy pattern 88 and the floating dummy pattern 121.

[0249] Figure 16 shows the equipotential lines (electric field distribution) near the high-potential coil 23, as investigated by simulation. Figure 16 shows the electric field distribution of the semiconductor device 5 according to the first structure described above. Referring to Figure 16, in the case of the semiconductor device 5 according to the first structure, the equipotential lines wrap around to the upper side of the high-potential coil 23 and are concentrated around the periphery of the high-potential coil 23. In other words, in the case of the semiconductor device 5 according to the first structure, it can be seen that the electric field is concentrated around the periphery of the high-potential coil 23. The average instantaneous dielectric breakdown voltage decreases due to this type of electric field concentration.

[0250] Figure 17 shows the equipotential lines (electric field distribution) near the first high-potential dummy pattern 87, as investigated by simulation. Figure 17 shows the electric field distribution of the semiconductor device 5 according to the fourth structure described above. Referring to Figure 17, in the case of the semiconductor device 5 according to the fourth structure, the equipotential lines bypass the high-potential coil 23 and the first high-potential dummy pattern 87 and leak out to the upper side of the first high-potential dummy pattern 87. In other words, in the case of the semiconductor device 5 according to the fourth structure, the electric field is not concentrated in the high-potential coil 23. This makes it possible to increase the average instantaneous dielectric breakdown voltage.

[0251] Although a detailed illustration is omitted, the second high-potential dummy pattern 88 has the same effect as the first high-potential dummy pattern 87. That is, in the vicinity of the second high-potential dummy pattern 88, equipotential lines bypass the high-potential coil 23 and the second high-potential dummy pattern 88 and leak out to the upper side of the second high-potential dummy pattern 88. This suppresses electric field concentration on the high-potential coil 23, thereby increasing the average instantaneous dielectric breakdown voltage.

[0252] Figure 18 shows the electric field distribution near the floating dummy pattern 121, as investigated by simulation. Figure 18 shows the electric field distribution of the semiconductor device 5 according to the fourth structure described above. Referring to Figure 18, in the case of the semiconductor device 5 according to the fourth structure, equipotential lines leak out from the region between adjacent floating dummy patterns 121 to the upper side of the high-potential coil 23. In other words, in the case of the semiconductor device 5 according to the fourth structure, the electric field leaking out to the upper side of the high-potential coil 23 is thinned out by the floating dummy pattern 121. This suppresses electric field concentration on the high-potential coil 23, and therefore the average instantaneous dielectric breakdown voltage can be increased.

[0253] Specifically, equipotential lines leak out from the region between adjacent floating dummy patterns 121 to the upper side of the high-potential dummy pattern 86. In other words, in the case of the semiconductor device 5 relating to the fourth structure, the electric field leaking to the upper side of the high-potential dummy pattern 86 is thinned out by the floating dummy patterns 121.

[0254] In the dummy pattern 85, which includes a high-potential dummy pattern 86 and a floating dummy pattern 121, the high-potential dummy pattern 86 keeps the electric field leaking above the high-potential coil 23 away from the high-potential coil 23. On the other hand, the floating dummy pattern 121, in a region away from the high-potential coil 23, disperses the electric field leaking above the high-potential dummy pattern 86 in a direction away from both the high-potential coil 23 and the high-potential dummy pattern 86. As a result, electric field concentration on the high-potential coil 23 can be appropriately suppressed, and the average instantaneous dielectric breakdown voltage can be appropriately increased.

[0255] Thus, it was found that by forming a dummy pattern 85 including the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121, electric field concentration on the high-potential coil 23 can be suppressed and the average instantaneous dielectric breakdown voltage can be improved. Furthermore, from the results in Figures 16, 17, and 18, it was found that the dummy pattern 85 only needs to include at least one of the first high-potential dummy pattern 87, the floating dummy pattern 121, and the second high-potential dummy pattern 88.

[0256] As described above, the semiconductor device 5 includes a semiconductor chip 41, an insulating layer 51, a first functional device 45, a low-potential terminal 11, a high-potential terminal 12, and a sealing conductor 61. The insulating layer 51 is formed on the first main surface 42 of the semiconductor chip 41. The first functional device 45 is formed within the insulating layer 51. The low-potential terminal 11 is formed on the insulating layer 51 and is electrically connected to the first functional device 45.

[0257] The high-potential terminal 12 is formed on the insulating layer 51 at a distance from the low-potential terminal 11 and is electrically connected to the first functional device 45. The sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner so as to demarcate the region including the first functional device 45, the low-potential terminal 11, and the high-potential terminal 12 from other regions in a plan view, and is electrically isolated from the semiconductor chip 41, the first functional device 45, the low-potential terminal 11, and the high-potential terminal 12.

[0258] This structure allows for the suppression of unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 when voltage is applied to the low-potential terminal 11 and the high-potential terminal 12. It also suppresses unwanted conduction between the low-potential terminal 11 and the sealing conductor 61. Furthermore, it suppresses unwanted conduction between the first functional device 45 and the sealing conductor 61. Therefore, the withstand voltage can be improved.

[0259] In this structure, it is preferable that the sealing conductor 61 is fixed in an electrically floating state. This structure reliably prevents the sealing conductor 61 from forming a current path. Therefore, unwanted conduction of the sealing conductor 61 can be appropriately suppressed.

[0260] Preferably, the sealing conductor 61 is embedded in the insulating layer 51 at a distance from the first main surface 42 of the semiconductor chip 41 in the normal direction Z. This structure allows for proper electrical isolation of the sealing conductor 61 from the semiconductor chip 41. Therefore, electrical conductivity between the semiconductor chip 41 and the sealing conductor 61 can be properly suppressed.

[0261] Preferably, the semiconductor device 5 further includes an isolation structure 130 interposed between the semiconductor chip 41 and the seal conductor 61, which electrically isolates the semiconductor chip 41 and the seal conductor 61. With this structure, the isolation structure 130 can properly electrically isolate the seal conductor 61 from the semiconductor chip 41.

[0262] The isolation structure 130 may include a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41. The isolation structure 130 may also include a trench 135 formed on the first main surface 42 and an embedded body 136 embedded in the trench 135. The embedded body 136 is embedded in the trench 135 so as to be electrically isolated from the semiconductor chip 41. Specifically, the embedded body 136 is embedded in the trench 135 so as to be electrically floating. The isolation structure 130 may be formed using a portion of the insulating layer 51.

[0263] The separation structure 130 is preferably exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41. With this structure, even if the seal conductor 61 is formed offset toward the chip sidewalls 44A to 44D, the separation structure 130 is formed on the periphery of the first main surface 42, exposing it from the chip sidewalls 44A to 44D, so the seal conductor 61 can be properly connected to the separation structure 130.

[0264] Preferably, the insulating sidewalls 53A to 53D of the insulating layer 51 are connected to the chip sidewalls 44A to 44D of the semiconductor chip 41. Furthermore, preferably, the insulating layer 51 is connected to the outer end portion 130B of the separation structure 130. With this structure, the insulating layer 51 and the separation structure 130 can properly insulate the seal conductor 61.

[0265] The sealing conductor 61 is preferably formed in an annular shape that surrounds the first functional device 45, the low-potential terminal 11, and the high-potential terminal 12 in a plan view. This structure allows the sealing conductor 61 to adequately protect the first functional device 45, the low-potential terminal 11, and the high-potential terminal 12.

[0266] The semiconductor device 5 includes an inorganic insulating layer 140 covering the seal conductor 61 on top of the insulating layer 51. The inorganic insulating layer 140 has low-potential pad openings 143 and high-potential pad openings 144 formed in the region outside the seal conductor 61. The low-potential pad openings 143 expose the low-potential terminals 11, and the high-potential pad openings 144 expose the high-potential terminals 12. This structure allows the inorganic insulating layer 140 to protect the seal conductor 61 while simultaneously increasing the insulation of the seal conductor 61 from the outside.

[0267] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140 so as to cover the sealing conductor 61 with the inorganic insulating layer 140 in between. With this structure, the sealing conductor 61 can be protected by the organic insulating layer 145, and at the same time, the insulating properties of the sealing conductor 61 from the outside can be further enhanced.

[0268] The first functional device 45 may include a transformer 21 (passive device) formed within the insulating layer 51. The transformer 21 includes a low-potential coil 22 (low-potential pattern) formed within the insulating layer 51, and a high-potential coil 23 (high-potential pattern) formed within the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. The high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 in between. The low-potential coil 22 is electrically connected to the low-potential terminal 11, and the high-potential coil 23 is electrically connected to the high-potential terminal 12.

[0269] This structure makes it possible to suppress unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 when a voltage is applied to the transformer 21 via the low-potential terminal 11 and the high-potential terminal 12. Furthermore, it makes it possible to suppress unwanted conduction between the low-potential terminal 11 and the sealing conductor 61 when a voltage is applied to the transformer 21 via the low-potential terminal 11 and the high-potential terminal 12. Furthermore, it makes it possible to suppress unwanted conduction between the transformer 21 and the sealing conductor 61 when a voltage is applied to the transformer 21 via the low-potential terminal 11 and the high-potential terminal 12.

[0270] The semiconductor device 5 further includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 covers the second functional device 60. The low-potential terminal 11 and the high-potential terminal 12 are electrically connected to the second functional device 60. The sealing conductor 61 demarcates the region containing the second functional device 60 from other regions in a plan view and is electrically isolated from the second functional device 60.

[0271] This structure makes it possible to suppress unwanted conduction between the second functional device 60 and the sealing conductor 61 when a voltage is applied to the low-potential terminal 11 and the high-potential terminal 12. Therefore, the semiconductor device 5 can achieve the same effect between the second functional device 60 and the sealing conductor 61 as the effect between the first functional device 45 and the sealing conductor 61.

[0272] Furthermore, the semiconductor device 5 includes a dummy pattern 85 formed within the insulating layer 51 so as to be located around the high-potential coil 23 in a plan view. The dummy pattern 85 shields the electric field formed between the low-potential coil 22 and the high-potential coil 23, suppressing electric field concentration on the high-potential coil 23. This suppresses electric field concentration on the high-potential coil 23 and improves the dielectric breakdown voltage (average instantaneous dielectric breakdown voltage). Moreover, the semiconductor device 5 can suppress unwanted conduction between the dummy pattern 85 and the sealing conductor 61 when a voltage is applied to the low-potential terminal 11 and the high-potential terminal 12. Thus, the dielectric breakdown voltage improvement effect of the dummy pattern 85 and the sealing conductor 61 can be appropriately realized.

[0273] In this configuration, the dummy pattern 85 is interposed in the region between multiple adjacent high-potential coils 23 in a plan view. This allows for the suppression of electric field concentration on the multiple high-potential coils 23 by utilizing the region between the adjacent high-potential coils 23.

[0274] In this embodiment, the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. This suppresses unwanted conduction between the low-potential terminal 11 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23.

[0275] In this configuration, the dummy pattern 85 is interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view. This suppresses unwanted conduction between the low-potential terminal 11 and the high-potential terminal 12 caused by electric field concentration in the high-potential coil 23.

[0276] In this embodiment, the dummy pattern 85 is interposed in the region between the sealing conductor 61 and the high-potential coil 23 in a plan view. This suppresses unwanted conduction between the sealing conductor 61 and the high-potential coil 23 caused by electric field concentration in the high-potential coil 23.

[0277] In this form, the dummy pattern 85 is interposed in the region between the seal conductor 61 and the high-potential terminal 12 in a plan view. Thereby, the undesired conduction between the seal conductor 61 and the high-potential terminal 12 due to the electric field concentration of the high-potential coil 23 can be suppressed.

[0278] In this form, the dummy pattern 85 includes a high-potential dummy pattern 86 formed around the high-potential coil 23 in a plan view. The high-potential dummy pattern 86 suppresses the electric field leaking to the upper side of the high-potential coil 23 in the region around the high-potential coil 23. Thereby, the electric field concentration on the high-potential coil 23 can be appropriately suppressed in the region around the high-potential coil 23.

[0279] The dummy pattern 85 includes a first high-potential dummy pattern 87 interposed in the region between a plurality of adjacent high-potential coils 23 in a plan view. The first high-potential dummy pattern 87 suppresses the electric field leaking to the upper side of the plurality of high-potential coils 23 in the region between the plurality of adjacent high-potential coils 23. Thereby, the electric field concentration on the plurality of high-potential coils 23 can be appropriately suppressed in the region between the plurality of adjacent high-potential coils 23.

[0280] Further, the dummy pattern 85 includes a second high-potential dummy pattern 88 located in a region outside the region between a plurality of adjacent high-potential coils 23 in a plan view. The second high-potential dummy pattern 88 suppresses the electric field leaking to the upper side of the plurality of high-potential coils 23 in the region outside the region between the plurality of adjacent high-potential coils 23. Thereby, the electric field concentration on the plurality of high-potential coils 23 can be appropriately suppressed in the region outside the region between the plurality of adjacent high-potential coils 23.

[0281] Further, the dummy pattern 85 includes a floating dummy pattern 121 formed in an electrically floating state around the high-potential coil 23 in a plan view. The floating dummy pattern 121 shields the electric field between the low-potential coil 22 and the high-potential coil 23 so as to disperse the electric field leaking to the upper side of the high-potential coil 23. Thereby, the electric field concentration on the high-potential coil 23 can be suppressed.

[0282] In addition, the floating dummy pattern 121 disperses the electric field leaking above the high-potential dummy pattern 86 around the high-potential dummy pattern 86. Thereby, while the electric field concentration on the high-potential dummy pattern 86 can be suppressed, the electric field concentration on the high-potential coil 23 can also be appropriately suppressed. In this structure, it is preferable that the sealing conductor 61 in an electrically floating state is formed. In this case, the sealing conductor 61 does not cause a voltage drop between the floating dummy pattern 121. Therefore, the undesired conduction between the dummy pattern 85 and the sealing conductor 61 can be appropriately suppressed.

[0283] As understood from FIG. 16, the dummy pattern 85 preferably includes all of the first high-potential dummy pattern 87, the floating dummy pattern 121, and the second high-potential dummy pattern 88. However, the average instantaneous breakdown voltage can also be improved by the dummy pattern 85 including any one or two of the first high-potential dummy pattern 87, the floating dummy pattern 121, and the second high-potential dummy pattern 88.

[0284] That is, the dummy pattern 85 having only the first high-potential dummy pattern 87 may be adopted. Also, the dummy pattern 85 having only the second high-potential dummy pattern 88 may be adopted. Also, the dummy pattern 85 having only the floating dummy pattern 121 may be adopted.

[0285] Also, the dummy pattern 85 having only the first high-potential dummy pattern 87 and the second high-potential dummy pattern 88 may be adopted. Also, the dummy pattern 85 having only the first high-potential dummy pattern 87 and the floating dummy pattern 121 may be adopted. Also, the dummy pattern 85 having only the second high-potential dummy pattern 88 and the floating dummy pattern 121 may be adopted.

[0286] Furthermore, the first high-potential dummy pattern 87 may be changed to a floating dummy pattern 121. Also, the first high-potential dummy pattern 87 and the second high-potential dummy pattern 88 may be changed to a floating dummy pattern 121.

[0287] Such a floating dummy pattern 121 is formed by disconnecting the first high-potential dummy pattern 87 and the second high-potential dummy pattern 88 from the high-potential connection wiring 81 (high-potential terminals 12A to 12F). Because the floating dummy pattern 121 is formed in an electrically floating state, it does not form a voltage drop with the high-potential coil 23. Therefore, the floating dummy pattern 121 can suppress the concentration of the electric field on the high-potential coil 23 while suppressing the increase in electric field strength with the high-potential coil 23. However, it should be noted that in the case of the floating dummy pattern 121, there is an electric field that leaks out to the upper side of the high-potential coil 23.

[0288] Furthermore, the floating dummy pattern 121 may be replaced with a second high-potential dummy pattern 88. However, in this case, the distance between the low-potential terminal 11 (seal conductor 61) and the second high-potential dummy pattern 88 will be reduced, resulting in a higher electric field strength between the low-potential terminal 11 (seal conductor 61) and the second high-potential dummy pattern 88. It should be noted that a higher electric field strength may cause undesirable electric field concentration in the high-potential coil 23 and the second high-potential dummy pattern 88.

[0289] Figure 19 is a plan view corresponding to Figure 7, and shows a semiconductor device 161 according to a second embodiment of the present invention. Figure 20 is a cross-sectional view along the line XX-XX shown in Figure 19. Hereinafter, structures corresponding to the structures described for semiconductor device 5 are given the same reference numerals and their descriptions are omitted. Figure 20 shows an example in which the separation structure 130 (field insulating film 131) according to the first embodiment is formed (see also Figure 13). However, in the semiconductor device 161 according to the second embodiment, one of the separation structures 130 according to the second to fifth embodiments may be formed instead of the separation structure 130 according to the first embodiment (see also Figures 14A to 14D).

[0290] Referring to Figures 19 and 20, the dummy pattern 85 relating to the semiconductor device 161 further includes a low-potential dummy pattern 162. In Figure 19, the low-potential dummy pattern 162 is shown by a thick line. It is preferable that the low-potential dummy pattern 162 is formed of the same conductive material as the low-potential coil 22, etc. That is, it is preferable that the low-potential dummy pattern 162 includes a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0291] The low-potential dummy pattern 162 is formed with a different pattern (discontinuous pattern) from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the low-potential dummy pattern 162 does not function as a transformer 21A to 21D. A voltage less than the voltage applied to the high-potential terminal 12 is applied to the low-potential dummy pattern 162. Preferably, the voltage applied to the low-potential terminal 11 (i.e., the reference voltage) is applied to the low-potential dummy pattern 162. In other words, it is preferable that the low-potential dummy pattern 162 is fixed at the same potential as the low-potential terminal 11. The low-potential dummy pattern 162 includes a connection portion 163 connected to any second electrode layer 79.

[0292] The low-potential dummy pattern 162 is formed around the low-potential terminal 11 in a plan view. Specifically, the low-potential dummy pattern 162 is formed in a region that is close to the low-potential terminal 11 relative to the high-potential coil 23 (high-potential terminal 12) in a plan view. When the low-potential dummy pattern 162 is said to be close to the low-potential terminal 11 in a plan view, it means that the distance between the low-potential dummy pattern 162 and the low-potential terminal 11 in a plan view is less than the distance between the low-potential dummy pattern 162 and the high-potential coil 23 (high-potential terminal 12).

[0293] The depth position of the low-potential dummy pattern 162 within the insulating layer 51 is arbitrary and is adjusted according to the electric field strength to be mitigated. Preferably, the low-potential dummy pattern 162 is formed in a region within the insulating layer 51 that is close to the low-potential terminal 11 relative to the low-potential coil 22 with respect to the normal direction Z. Closeness of the low-potential dummy pattern 162 to the low-potential terminal 11 with respect to the normal direction Z means that the distance between the low-potential dummy pattern 162 and the low-potential terminal 11 is less than the distance between the low-potential dummy pattern 162 and the low-potential coil 22 with respect to the normal direction Z. Preferably, the low-potential dummy pattern 162 is formed within the same interlayer insulating layer 57 as the high-potential coil 23.

[0294] The low-potential dummy pattern 162 is preferably interposed in the region between the low-potential terminal 11 and the high-potential coil 23 in a plan view. The low-potential dummy pattern 162 is preferably interposed in the region between the low-potential terminal 11 and the high-potential terminal 12 in a plan view.

[0295] In this configuration, the low-potential dummy pattern 162 is routed at a line density equal to that of the high-potential coil 23 per unit area. The line density of the low-potential dummy pattern 162 being equal to that of the high-potential coil 23 means that the line density of the low-potential dummy pattern 162 falls within ±20% of the line density of the high-potential coil 23.

[0296] The low-potential dummy pattern 162 is preferably formed with ends. This structure effectively suppresses the formation of current loop circuits within the low-potential dummy pattern 162. As a result, noise caused by the current flowing through the low-potential dummy pattern 162 can be suppressed, thereby suppressing unwanted electric field concentration caused by noise, and at the same time effectively suppressing fluctuations in the electrical characteristics of transformers 21A to 21D.

[0297] In this embodiment, the low-potential dummy pattern 162 is formed in a strip shape extending in the first direction X. In a plan view, the low-potential dummy pattern 162 crosses multiple low-potential terminals 11A to 11F. As a result, in a plan view, the low-potential dummy pattern 162 is interposed in the region between the low-potential terminals 11A to 11F and the high-potential coil 23. In addition, in a plan view, the low-potential dummy pattern 162 is interposed in the region between the low-potential terminals 11A to 11F and the high-potential terminals 12A to 12F.

[0298] In this configuration, the low-potential dummy pattern 162 includes several (three in this configuration) low-potential lines 164A, 164B, and 164C. The multiple low-potential lines 164A to 164C are formed with spacing between them, in the order from the low-potential terminals 11A to 11F to the high-potential terminals 12A to 12F. The multiple low-potential lines 164A to 164C are electrically connected to any low-potential connection wiring 72.

[0299] The multiple low-potential lines 164A to 164C are each formed as stripes extending in the first direction X when viewed from above. In other words, the multiple low-potential lines 164A to 164C are formed as a stripe extending in the first direction X when viewed from above.

[0300] The width of the low-potential lines 164A to 164C may be 0.1 μm or more and 5 μm or less. Preferably, the width of the low-potential lines 164A to 164C is 1 μm or more and 3 μm or less. The width of the low-potential lines 164A to 164C is defined by the width in the direction perpendicular to the direction in which the low-potential lines 164A to 164C extend. Preferably, the width of the low-potential lines 164A to 164C is equal to the width of the high-potential coil 23. When the width of the low-potential lines 164A to 164C is equal to the width of the high-potential coil 23, it means that the width of the low-potential lines 164A to 164C falls within ±20% of the width of the high-potential coil 23.

[0301] The 13th pitch between two adjacent low-potential lines 164A to 164C may be 0.1 μm or more and 5 μm or less. The 13th pitch is preferably 1 μm or more and 3 μm or less. The 13th pitches are preferably equal to each other. The 13th pitches being equal to each other means that the 13th pitch falls within a range of ±20% of the 13th pitch. According to these structures, since the bias of the electric field can be suppressed in the insulating layer 51, undesired electric field concentration can be suppressed. The number, width, and pitch of the low-potential lines 164A to 164C are adjusted according to the electric field to be relaxed and are not limited to specific values.

[0302] The semiconductor device 161 further includes a main surface insulating layer 165 that covers the main insulating surface 52 of the insulating layer 51. The main surface insulating layer 165 covers the low-potential terminals 11A to 11F, the high-potential terminals 12A to 12F, the organic insulating layer 145, the inorganic insulating layer 140 (second inorganic insulating layer 142), etc. together on the main insulating surface 52.

[0303] The main surface insulating layer 165 has a second dielectric breakdown strength BS2 (BS2 ≤ BS1) that is less than or equal to the first dielectric breakdown strength BS1 of the insulating layer 51. Specifically, the second dielectric breakdown strength BS2 is less than the first dielectric breakdown strength BS1 (BS2 < BS1).

[0304] Specifically, the insulating layer 51 contains silicon oxide and / or silicon nitride and has a first dielectric breakdown strength BS1 of 1 MV / cm or more and 15 MV / cm or less. The first dielectric breakdown strength BS1 is preferably 5 MV / cm or more and 15 MV / cm or less. The insulating layer 51 may contain an insulating material other than silicon oxide and silicon nitride as long as it has a first dielectric breakdown strength BS1 of 1 MV / cm or more. On the other hand, the second dielectric breakdown strength BS2 may be 0.1 MV / cm or more and 1 MV / cm or less. The second dielectric breakdown strength BS2 may be 0.1 MV / cm or more and 0.5 MV / cm or less.

[0305] In this embodiment, the main surface insulating layer 165 consists of a resin layer. The main surface insulating layer 165 may include at least one of an epoxy resin layer, a polyimide resin layer, and a polybenzoxazole resin layer. The main surface insulating layer 165 may be formed from a part of the mold resin. If the main surface insulating layer 165 is formed from a part of the mold resin, the main surface insulating layer 165 may also be formed from a part of the package body 2. In other words, the main surface insulating layer 165 may include a portion that covers the insulating main surface 52 of the insulating layer 51 in the package body 2 when sealed by the package body 2.

[0306] The electric field strength between the low-potential terminals 11A-11F and the high-potential dummy pattern 86 is governed by the distance between the low-potential dummy pattern 162 and the high-potential dummy pattern 86. Therefore, in the insulating layer 51, the electric field strength between the low-potential terminals 11A-11F and the high-potential dummy pattern 86 is increased by the low-potential dummy pattern 162.

[0307] On the other hand, the electric field strength in the main surface insulating layer 165 decreases due to the increase in electric field strength in the insulating layer 51. In other words, the low-potential dummy pattern 162 deliberately increases the electric field strength of the insulating layer 51, which has a relatively high first dielectric breakdown strength BS1, while simultaneously decreasing the electric field strength of the main surface insulating layer 165, which has a relatively low second dielectric breakdown strength BS2. This makes it possible to relatively improve the dielectric breakdown voltage of the main surface insulating layer 165.

[0308] As described above, semiconductor device 161 can achieve the same effects as those described for semiconductor device 5. Furthermore, semiconductor device 161 includes a low-potential dummy pattern 162. This improves the dielectric breakdown voltage of the main surface insulating layer 165. In addition, with semiconductor device 161, the sealing conductor 61 demarcates the region including the low-potential dummy pattern 162 from other regions in a plan view and is electrically isolated from the low-potential dummy pattern 162. With this structure, when a voltage is applied to the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the low-potential dummy pattern 162 and the sealing conductor 61 can be suppressed. Therefore, the dielectric breakdown voltage can be increased.

[0309] Figure 21 is a cross-sectional view of the region corresponding to Figure 8, and shows a semiconductor device 191 according to the third embodiment of the present invention. Hereinafter, structures corresponding to the structures described for semiconductor device 5 are given the same reference numerals and their descriptions are omitted. Figure 21 shows an example in which the separation structure 130 (field insulating film 131) according to the first embodiment is formed (see also Figure 13). However, in the semiconductor device 191 according to the third embodiment, one of the separation structures 130 according to the second to fifth embodiments may be formed instead of the separation structure 130 according to the first embodiment (see also Figures 14A to 14D).

[0310] The semiconductor device 5 according to the first embodiment has a plurality of transformers 21A to 21D, each having a low-potential coil 22 and a high-potential coil 23. In contrast, the semiconductor device 191 according to the third embodiment includes a plurality of capacitors 192 instead of the plurality of transformers 21A to 21D. The arrangement of the plurality of capacitors 192 is the same as the arrangement of the plurality of transformers 21A to 21D. In Figure 21, only one capacitor 192 is shown.

[0311] The capacitor 192 includes a flat low-potential electrode 193 (low-potential pattern) and a flat high-potential electrode 194 (high-potential pattern), respectively, in place of the low-potential coil 22 and high-potential coil 23. The low-potential electrode 193 is electrically connected to the low-potential terminal 11 via the first low-potential wiring 31. The low-potential electrode 193 is electrically connected to the lead wiring 73 via the second connecting plug electrode 75.

[0312] The planar shape of the low-potential electrode 193 is arbitrary. The low-potential electrode 193 may be formed in a polygonal shape such as a triangle or square, a circular shape, or an elliptical shape in plan view. The low-potential electrode 193 is electrically connected to the corresponding low-potential terminal 11 via the corresponding first low-potential wiring 31.

[0313] The high-potential electrode 194 faces the low-potential electrode 193 in the normal direction Z and accumulates charge between itself and the low-potential electrode 193. The high-potential electrode 194 is electrically connected to the high-potential terminal 12 via the first high-potential wiring 33. The high-potential electrode 194 is electrically connected to the high-potential terminal 12 via the pad plug electrode 82.

[0314] The planar shape of the high-potential electrode 194 is arbitrary. The high-potential electrode 194 may be formed in a polygonal shape such as a triangle or square, a circular shape, or an elliptical shape in plan view. The high-potential electrode 194 is electrically connected to the corresponding high-potential terminal 12 via the corresponding first high-potential wiring 33.

[0315] As described above, the semiconductor device 191 can achieve the same effects as those described for the semiconductor device 5. The semiconductor device 191 may include the low-potential dummy pattern 162 according to the second embodiment.

[0316] Embodiments of the present invention can be carried out in yet other forms.

[0317] In each of the embodiments described above, the semiconductor devices 5, 161, and 191 may include a separation structure 130 having a structure in which at least two of the separation structures 130 according to the first to fifth embodiments are combined in any manner.

[0318] In the embodiments described above, examples in which the first functional device 45 and the second functional device 60 are formed have been explained. However, a configuration in which the first functional device 45 is absent and only the second functional device 60 is present may also be adopted. In this case, the dummy pattern 85 may be removed. With this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0319] In other words, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, unwanted conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed.

[0320] Furthermore, in the embodiments described above, examples in which the second functional device 60 is formed were explained. However, the second functional device 60 is not necessarily required and may be removed.

[0321] Furthermore, in the embodiments described above, examples in which a dummy pattern 85 is formed were explained. However, the dummy pattern 85 is not necessarily required and may be removed.

[0322] Furthermore, in the embodiments described above, an example was given in which the first functional device 45 consists of a multi-channel type including multiple transformers 21. However, a first functional device 45 consisting of a single-channel type including a single transformer 21 may also be employed.

[0323] The following are examples of features extracted from this specification and drawings. Sections [A1] to [A19] and [B1] to [B17] below provide a semiconductor device that can improve voltage resistance in a structure equipped with a sealing conductor.

[0324] [A1] A semiconductor device comprising: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a functional device formed on at least one of the semiconductor chip and the insulating layer; a low-potential terminal formed on the insulating layer and electrically connected to the functional device; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the functional device; and a sealing conductor embedded in the insulating layer in a wall-like manner so as to demarcate the region including the functional device, the low-potential terminal and the high-potential terminal from other regions in a plan view, and electrically isolated from the semiconductor chip, the functional device, the low-potential terminal and the high-potential terminal.

[0325] This semiconductor device can suppress unwanted conduction between the high-potential terminal and the sealing conductor when voltage is applied to the low-potential and high-potential terminals. It can also suppress unwanted conduction between the low-potential terminal and the sealing conductor. Furthermore, it can suppress unwanted conduction between the functional device and the sealing conductor. Therefore, the withstand voltage can be improved.

[0326] [A2] The semiconductor device according to A1, wherein the sealing conductor is fixed in an electrically floating state.

[0327] [A3] The semiconductor device according to A1 or A2, wherein the sealing conductor is embedded in the insulating layer at a distance from the semiconductor chip in the direction normal to the main surface.

[0328] [A4] The semiconductor device according to any one of A1 to A3, further comprising a separation structure interposed between the semiconductor chip and the seal conductor to electrically separate the seal conductor from the semiconductor chip.

[0329] [A5] The semiconductor device according to A4, wherein the separation structure includes an insulating film formed on the main surface of the semiconductor chip.

[0330] [A6] The semiconductor device according to A4, wherein the separation structure includes a trench formed on the main surface and an embedded body embedded in the trench so as to be electrically isolated from the semiconductor chip.

[0331] [A7] The semiconductor device according to A4, wherein the separation structure is a part of the insulating layer.

[0332] [A8] The separation structure is exposed from the side wall of the semiconductor chip, as described in any one of A4 to A7.

[0333] [A9] The semiconductor device according to any one of A1 to A8, wherein the insulating layer has an insulating sidewall that is connected to the sidewall of the semiconductor chip.

[0334] [A10] The semiconductor device according to any one of A1 to A9, wherein the sealing conductor is formed in an annular shape surrounding the functional device, the low-potential terminal and the high-potential terminal in a plan view.

[0335] [A11] The semiconductor device according to any one of A1 to A10, further comprising an inorganic insulating layer having a plurality of pad openings that cover the sealing conductor on the insulating layer and expose the low-potential terminal and the high-potential terminal, respectively.

[0336] [A12] The semiconductor device according to A11, further comprising an organic insulating layer formed on the inorganic insulating layer so as to cover the sealing conductor with the inorganic insulating layer in between.

[0337] [A13] The semiconductor device according to any one of A1 to A12, wherein the functional device includes a low-potential pattern formed in the insulating layer and a high-potential pattern formed in the insulating layer so as to be opposite to the low-potential pattern in the direction normal to the main surface, the low-potential terminal is connected to the low-potential pattern and the high-potential terminal is electrically connected to the high-potential pattern.

[0338] [A14] The semiconductor device according to A13, wherein the high-potential pattern faces the semiconductor chip with the low-potential pattern in between.

[0339] [A15] The semiconductor device according to A13 or A14, wherein the functional device is a transformer including a low-potential coil as the low-potential pattern and a high-potential coil as the high-potential pattern.

[0340] [A16] The semiconductor device according to A13 or A14, wherein the functional device is a capacitor including a low-potential electrode as the low-potential pattern and a high-potential electrode as the high-potential pattern.

[0341] [A17] The semiconductor device according to any one of A1 to A12, wherein the functional device includes at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device, and is formed on the main surface of the semiconductor chip.

[0342] [A18] The semiconductor device according to any one of A1 to A12, wherein the functional device includes a first functional device formed on the insulating layer and a second functional device formed on the semiconductor chip.

[0343] [A19] A semiconductor device comprising: a semiconductor chip having a main surface; an insulating layer formed on the main surface; a low-potential pattern formed within the insulating layer; a high-potential pattern formed within the insulating layer so as to face the low-potential pattern in the direction normal to the main surface; a dummy pattern formed within the insulating layer around the high-potential pattern, containing a conductor, and shielding the electric field between the low-potential pattern and the high-potential pattern; a low-potential terminal formed on the insulating layer and electrically connected to the low-potential pattern; a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the high-potential pattern; and a sealing conductor embedded in the insulating layer in a wall-like manner so as to demarcate the region including the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal and the high-potential terminal from other regions in a plan view, and electrically disconnected from the semiconductor chip, the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal and the high-potential terminal.

[0344] This semiconductor device allows for the suppression of electric field concentration on high-potential patterns by a dummy pattern when voltage is applied to low-potential and high-potential terminals. Furthermore, this semiconductor device can suppress unwanted conduction between high-potential patterns (high-potential terminals) and sealing conductors when voltage is applied to low-potential and high-potential terminals. It can also suppress unwanted conduction between low-potential patterns (low-potential terminals) and sealing conductors. Additionally, it can suppress unwanted conduction between dummy patterns and sealing conductors. Therefore, the withstand voltage can be improved.

[0345] [B1] A semiconductor chip having a main surface, An insulating layer formed on the main surface, A functional device formed on at least one of the semiconductor chip and the insulating layer, A low-potential terminal formed on the insulating layer and electrically connected to the functional device, A high-potential terminal is formed on the insulating layer at a distance from the low-potential terminal and is electrically connected to the functional device. A sealing conductor is embedded in the insulating layer in a wall-like manner so as to demarcate the region including the functional device, the low-potential terminal, and the high-potential terminal from other regions in a plan view, A separation structure is interposed between the semiconductor chip and the seal conductor along the seal conductor, electrically separating the seal conductor from the semiconductor chip, and including an insulating film formed on the main surface of the semiconductor chip, Semiconductor equipment, including

[0346] [B2] The semiconductor device according to B1, wherein the sealing conductor is fixed in an electrically floating state.

[0347] [B3] The semiconductor device according to B1 or B2, wherein the sealing conductor is embedded in the insulating layer at a distance from the semiconductor chip in the direction normal to the main surface.

[0348] [B4] The semiconductor device according to B1, wherein the separation structure is a part of the insulating layer.

[0349] [B5] The separation structure is exposed from the side wall of the semiconductor chip, and is a semiconductor device according to any one of B1 to B4.

[0350] [B6] The semiconductor device according to any one of B1 to B5, wherein the insulating layer has an insulating sidewall that is connected to the sidewall of the semiconductor chip.

[0351] [B7] The semiconductor device according to any one of B1 to B6, wherein the sealing conductor is formed in an annular shape surrounding the functional device, the low-potential terminal, and the high-potential terminal in a plan view.

[0352] [B8] The semiconductor device according to any one of B1 to B7, further comprising an inorganic insulating layer having a plurality of pad openings that cover the sealing conductor on the insulating layer and expose the low-potential terminal and the high-potential terminal, respectively.

[0353] [B9] The semiconductor device according to B8, further comprising an organic insulating layer formed on the inorganic insulating layer so as to cover the sealing conductor with the inorganic insulating layer in between.

[0354] [B10] The functional device includes a low-potential pattern formed within the insulating layer and a high-potential pattern formed within the insulating layer so as to be opposite to the low-potential pattern in the direction normal to the main surface. The low-potential terminal is connected to the low-potential pattern, The semiconductor device according to any one of B1 to B9, wherein the high-potential terminal is electrically connected to the high-potential pattern.

[0355] [B11] The semiconductor device according to B10, wherein the high-potential pattern faces the semiconductor chip with the low-potential pattern in between.

[0356] [B12] The semiconductor device according to B10 or B11, wherein the functional device is a transformer including a low-potential coil as the low-potential pattern and a high-potential coil as the high-potential pattern.

[0357] [B13] The semiconductor device according to B10 or B11, wherein the functional device is a capacitor including a low-potential electrode as the low-potential pattern and a high-potential electrode as the high-potential pattern.

[0358] [B14] The functional device includes at least one of a passive device, a semiconductor rectifier device, and a semiconductor switching device, and is formed on the main surface of the semiconductor chip, according to any one of B1 to B9.

[0359] [B15] The semiconductor device according to any one of B1 to B9, wherein the functional device includes a first functional device formed on the insulating layer and a second functional device formed on the semiconductor chip.

[0360] [B16] A semiconductor chip having a main surface, An insulating layer formed on the main surface, A low-potential pattern formed within the insulating layer, A high-potential pattern formed within the insulating layer so as to face the low-potential pattern in the direction normal to the main surface, A dummy pattern is formed within the insulating layer around the high-potential pattern, containing a conductor, and shielding the electric field between the low-potential pattern and the high-potential pattern. A low-potential terminal formed on the insulating layer and electrically connected to the low-potential pattern, A high-potential terminal is formed on the insulating layer at a distance from the low-potential terminal and is electrically connected to the high-potential pattern, A sealing conductor is embedded in the insulating layer in a wall-like manner so as to demarcate the region including the low-potential pattern, the high-potential pattern, the dummy pattern, the low-potential terminal, and the high-potential terminal from other regions in a plan view, A separation structure is interposed between the semiconductor chip and the seal conductor along the seal conductor, electrically separating the seal conductor from the semiconductor chip, and including an insulating film formed on the main surface of the semiconductor chip, Semiconductor equipment, including

[0361] [B17] A semiconductor chip having a main surface, An insulating layer formed on the main surface, A functional device formed on at least one of the semiconductor chip and the insulating layer, A low-potential terminal formed on the insulating layer and electrically connected to the functional device, A high-potential terminal is formed on the insulating layer at a distance from the low-potential terminal and is electrically connected to the functional device. A sealing conductor is embedded in the insulating layer in a wall-like manner so as to demarcate the region including the functional device, the low-potential terminal, and the high-potential terminal from other regions in a plan view, A separation structure comprising a trench formed on the main surface, and an embedded body embedded in the trench so as to be electrically isolated from the semiconductor chip, interposed between the semiconductor chip and the sealing conductor, electrically separating the sealing conductor from the semiconductor chip, Semiconductor equipment, including

[0362] This application corresponds to Japanese Patent Application No. 2019-217565, filed with the Japan Patent Office on November 29, 2019, and the full disclosure of this application is incorporated herein by reference. Although embodiments of the present invention have been described in detail, these are merely examples used to illustrate the technical content of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited by the appended claims. [Explanation of Symbols]

[0363] 5: Semiconductor device, 11: Low potential terminal, 12: High potential terminal, 21: Transformer, 22: Low potential coil, 23: High potential coil, 41: Semiconductor chip, 42: First main surface, 44A: First chip sidewall, 44B: Second chip sidewall, 44C: Third chip sidewall, 44D: Fourth chip sidewall, 45: First functional device, 51: Insulating layer, 53A: First insulating sidewall, 53B: Second insulating sidewall, 5 3C: Third insulating sidewall, 53D: Fourth insulating sidewall, 60: Second functional device, 61: Seal conductor, 85: Dummy pattern, 130: Isolation structure, 131: Field insulating film, 135: Trench, 136: Embedded structure, 140: Inorganic insulating layer, 145: Organic insulating layer, 161: Semiconductor device, 191: Semiconductor device, 192: Capacitor, 193: Low potential electrode, 194: High potential electrode

Claims

1. A semiconductor chip having a main surface, An insulating layer formed on the main surface, A functional device formed on at least one of the semiconductor chip and the insulating layer, A terminal formed on the insulating layer and electrically connected to the functional device, A sealing conductor comprising a first portion and a plurality of second portions located between the semiconductor chip and the first portion, which are adjacent to each other in a plan view and each having a width smaller than that of the first portion in a plan view, demarcating a region including the functional device and at least one of the terminals from other regions in a plan view, Includes, The first and second portions of the seal conductor are respectively arranged in the direction normal to the main surface from the semiconductor chip, The second portion of the seal conductor is composed of a plurality of via-shaped conductors, A semiconductor device in which the second portion of the sealing conductor is in contact with the first portion.

2. The semiconductor device according to claim 1, further comprising a conductive film located between the semiconductor chip and the second portion of the sealing conductor and in contact with the second portion.

3. The semiconductor device according to claim 1 or 2, wherein the sealing conductor is embedded in the insulating layer in a wall-like manner.

4. The semiconductor device according to any one of claims 1 to 3, wherein at least one of the terminals includes a low-potential terminal formed on the insulating layer and electrically connected to the functional device, and a high-potential terminal formed on the insulating layer at a distance from the low-potential terminal and electrically connected to the functional device.

5. The functional device includes a low-potential pattern formed within the insulating layer and a high-potential pattern formed within the insulating layer so as to be opposite to the low-potential pattern in the direction normal to the main surface. The low-potential terminal is connected to the low-potential pattern, The semiconductor device according to claim 4, wherein the high-potential terminal is electrically connected to the high-potential pattern.

6. The semiconductor device according to claim 5, wherein the high-potential pattern faces the semiconductor chip with the low-potential pattern in between.

7. The semiconductor device according to any one of claims 1 to 6, wherein the sealing conductor is electrically isolated from the semiconductor chip, the functional device and at least one of the terminals.

8. The semiconductor device according to any one of claims 1 to 7, wherein the sealing conductor is formed in an annular shape surrounding the functional device and at least one of the terminals in a plan view.

9. The semiconductor device according to any one of claims 1 to 8, further comprising an inorganic insulating layer having a pad opening that covers the sealing conductor on the insulating layer and exposes at least one of the terminals.

10. The semiconductor device according to claim 9, further comprising an organic insulating layer formed on the inorganic insulating layer so as to cover the sealing conductor with the inorganic insulating layer in between.

11. The interlayer insulating layer on which the first and second portions of the seal conductor are formed further comprises The semiconductor device according to any one of claims 1 to 10, wherein the interlayer insulating layer comprises a first interlayer insulating layer and a second interlayer insulating layer having a width and material in the direction normal to the main surface that differs from that of the first interlayer insulating layer.

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