Semiconductor structure

Abstract

The present invention provides a depletion-mode high electron mobility transistor structure comprising a substrate, a semiconductor barrier layer, and a gate electrode. [Solution] In a normally-off high electron-mobility transistor, the semiconductor barrier layer 140 is placed on the substrate 100. The gate electrode 180 is placed on the semiconductor barrier layer and has a first gate barrier layer 182 and a second gate barrier layer 184. The first gate barrier layer is placed between the semiconductor barrier layer and the second gate barrier layer. The work function of the first gate barrier layer is greater than the work function of the semiconductor barrier layer. The work function of the second gate barrier layer is greater than the work function of the first gate barrier layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a high electron mobility transistor.

Background Art

[0002] In recent years, the demand for high-frequency and high-power products has been increasing. Semiconductor power devices made of gallium nitride such as aluminum gallium nitride / gallium nitride (AlGaN / GaN) can achieve very high switching speeds due to their wide energy bandgap and fast-moving electrons. In addition, because they operate at high frequencies, high powers, and high temperatures, they are widely used particularly in high-power semiconductors for radio frequency and power applications. Conventionally, high electron mobility transistors have been made by stacking III-V semiconductors and forming a heterojunction at their interface. Since the energy band of the heterojunction is bent, a potential well is formed at the deepest part of the bend in the conduction band, and a two-dimensional electron gas (2DEG) is formed in the potential well.

[0003] Generally, high electron mobility transistors are normally-on (D-mode) or so-called depletion-mode (D-mode) elements, requiring a negative bias voltage to turn them off. In addition to being relatively inconvenient to use, their range of application is also limited. On the other hand, another type of high electron mobility, enhancement-mode transistors, has also been proposed. These types of transistors do not require an additional bias voltage to turn off normally-off (E-mode) elements of a two-dimensional electron gas, because they are formed by destroying the lattice structure of the aluminum gallium nitride layer by fluoride ion bombardment before forming the metal gate, or by etching to create recesses in the aluminum gallium nitride layer, or by a gate stacked structure of gallium nitride layers with P-type impurities.

[0004] However, in currently common E-mode gallium nitride high electron mobility transistors, when the gate-source drive voltage (Vgs) reaches 7V to 10V, the gate leakage current becomes too high, causing a gate hard breakdown. Therefore, the operating range is limited to 0V to 6V. On the other hand, in common D-mode gallium nitride high electron mobility transistors, the gate leakage current is relatively high, sometimes reaching milliamperes. During operation of the above devices, the gate leakage current increases as the gate voltage rises. Since an increase in gate leakage current leads to device failure, it is necessary to effectively control the gate leakage current of the device. To overcome the above problems, developing innovative semiconductor structures that can improve the gate leakage current that causes device failure has become an urgent task for the industry. [Overview of the project]

[0005] The main objective of this invention is to provide an innovative semiconductor structure. By increasing the gate breakdown voltage, the voltage operating range of the device is broadened, improving the problem of device failure due to high gate leakage current in conventional high-electron-mobility transistors.

[0006] To achieve the above objective, the present invention provides a semiconductor structure comprising a substrate, a semiconductor barrier layer, and a gate electrode. The semiconductor barrier layer is disposed on the substrate. The gate electrode is disposed on the semiconductor barrier layer and comprises a first gate barrier layer and a second gate barrier layer. The first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer. The work function of the first gate barrier layer is greater than that of the semiconductor barrier layer. The work function of the second gate barrier layer is greater than that of the first gate barrier layer.

[0007] In embodiments of the present invention, the first gate barrier layer is a conductive metal compound having a work function of 4 eV or higher.

[0008] In embodiments of the present invention, the conductive metal compound material is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

[0009] In embodiments of the present invention, the second gate barrier layer is a conductive material with a work function of 5 eV or higher.

[0010] In embodiments of the present invention, the conductive material is one selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

[0011] In embodiments of the present invention, the semiconductor structure further includes a source electrode and a drain electrode disposed on a semiconductor barrier layer.

[0012] In embodiments of the present invention, the materials of the source electrode and the drain electrode are one selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof.

[0013] In an embodiment of the present invention, the semiconductor barrier layer is an aluminum gallium nitride layer.

[0014] In embodiments of the present invention, the semiconductor structure further comprises a gallium nitride layer, and the aluminum gallium nitride layer is disposed on the gallium nitride layer.

[0015] In embodiments of the present invention, the semiconductor structure further includes a p-type doped gallium nitride layer disposed between the aluminum gallium nitride layer and the first gate barrier layer, wherein the work function of the first gate barrier layer is greater than the work function of the p-type doped gallium nitride layer.

[0016] In an embodiment of the present invention, the semiconductor barrier layer beneath the gate electrode has a recess, and the first gate barrier layer fills the recess.

[0017] In an embodiment of the present invention, a portion of the aluminum gallium nitride layer beneath the gate electrode is doped with fluoride ions.

[0018] In embodiments of the present invention, the gate electrode further comprises a low-resistance metal layer disposed on the second gate barrier layer.

[0019] In embodiments of the present invention, the material of the low-resistance metal layer is one selected from aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold, or a combination thereof.

[0020] To achieve the above objective, the present invention provides a semiconductor structure comprising a substrate, a semiconductor barrier layer, an anode electrode, and a cathode electrode. The semiconductor barrier layer is disposed on the substrate. The anode electrode and cathode electrode are disposed at two opposing ends on the semiconductor barrier layer. The anode electrode has a first anode barrier layer and a second anode barrier layer. The first anode barrier layer is disposed between the semiconductor barrier layer and the second anode barrier layer. The work function of the first anode barrier layer is greater than the work function of the semiconductor barrier layer. The work function of the second anode barrier layer is greater than the work function of the first anode barrier layer.

[0021] In an embodiment of the present invention, the first anode barrier layer is a conductive metal compound having a work function of 4 eV or more.

[0022] In an embodiment of the present invention, the material of the conductive metal compound is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride.

[0023] In an embodiment of the present invention, the second anode barrier layer is a conductive material having a work function of 5 eV or more.

[0024] In an embodiment of the present invention, the conductive material is one selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

[0025] In an embodiment of the present invention, the semiconductor barrier layer is a gallium aluminum nitride layer, and the semiconductor structure further includes a P-type doped gallium nitride layer disposed between the gallium aluminum nitride layer and the first anode barrier layer, and the work function of the first anode barrier layer is greater than the work function of the P-type doped gallium nitride layer.

[0026] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below.

Brief Description of the Drawings

[0027] [Figure 1] Schematic diagram showing the manufacturing process of a normally-on high electron mobility transistor according to an embodiment of the present invention [Figure 2] Schematic diagram showing the manufacturing process of a normally-on high electron mobility transistor according to an embodiment of the present invention [Figure 3] Schematic diagram showing the manufacturing process of a normally-on high electron mobility transistor according to an embodiment of the present invention [Figure 4] Schematic diagram showing the manufacturing process of a normally-on high electron mobility transistor according to an embodiment of the present invention [Figure 5]A schematic diagram showing the manufacturing process of a normally-on high electron mobility transistor according to an embodiment of the present invention. [Figure 6] A graph comparing the gate current and voltage of the normally-on high electron mobility transistor of the present invention and a conventional normally-on high electron mobility transistor. [Figure 7] A schematic diagram showing the manufacturing process of a normally-off high electron mobility transistor according to an embodiment of the present invention. [Figure 8] A schematic diagram showing the manufacturing process of a normally-off high electron mobility transistor according to an embodiment of the present invention. [Figure 9] A schematic diagram showing the manufacturing process of a normally-off high electron mobility transistor according to an embodiment of the present invention. [Figure 10] A schematic diagram showing the manufacturing process of a normally-off high electron mobility transistor according to an embodiment of the present invention. [Figure 11] A schematic diagram showing the manufacturing process of a normally-off high electron mobility transistor according to an embodiment of the present invention. [Figure 12] A schematic diagram showing the manufacturing process of a normally-off high electron mobility transistor according to an embodiment of the present invention. [Figure 13] A graph comparing the gate current and voltage of the normally-off high electron mobility transistor of the present invention with that of a conventional normally-off high electron mobility transistor. [Figure 14] A schematic diagram showing a normally-off high electron mobility transistor having a concave gate structure according to an embodiment of the present invention. [Figure 15] A schematic diagram showing a normally-off high electron-mobility transistor doped with fluoride ions according to an embodiment of the present invention. [Figure 16] A schematic diagram showing a normally-on Schottky barrier diode according to an embodiment of the present invention. [Figure 17] A schematic diagram showing a normally-off Schottky barrier diode according to an embodiment of the present invention. [Modes for carrying out the invention]

[0028] The present invention will be described below through examples. These examples illustrate the embodiments of the present invention and are not intended to limit the invention to any particular environment, application, or specific configuration described therein. Therefore, while the examples illustrate the present invention, they do not limit it. Components not directly related to the present invention are omitted and not shown in the embodiments and drawings. The dimensional relationships of the components in the drawings are for ease of understanding and do not limit the actual dimensions.

[0029] Figure 1 shows a semiconductor structure and a method for manufacturing the same according to an embodiment of the present invention, and in particular shows a normally-on or so-called depletion-mode (D-mode) high electron-mobility transistor and a method for manufacturing the same. A nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140 are sequentially formed on a substrate 100. The material of the substrate 100 is silicon, sapphire, diamond, gallium nitride, silicon carbide, gallium arsenide, etc. The nucleation layer 110 is placed on the substrate 100. The thickness of the nucleation layer 110 is about several tens to several hundred nanometers, which can reduce the lattice difference between the substrate 100 and the semiconductor barrier layer 140. The nucleation layer 110 is a III-V group material including, for example, aluminum nitride, gallium nitride, and aluminum gallium nitride. The buffer layer 120 is placed on the nucleation layer 110, and its thickness is about several micrometers to several tens of micrometers. The buffer layer 120 is made of a III-V material and can similarly reduce the lattice difference between the substrate 100 and the semiconductor barrier layer 140. In this embodiment, the buffer layer 120 is a single-layer or multilayer structure, for example, a multilayer superlattice multilayer, or a III-V semiconductor single-layer film of aluminum nitride, gallium nitride, or aluminum gallium nitride.

[0030] The channel layer 130 is formed on the buffer layer 120 and has a first energy gap. The semiconductor barrier layer 140 is formed on the channel layer 130 and has a second energy gap. The second energy gap is higher than the first energy gap. The lattice constant of the semiconductor barrier layer 140 is smaller than the lattice constant of the channel layer 130. In this embodiment, the material of the channel layer 130 and the semiconductor barrier layer 140 is aluminum indium gallium nitride (Al x In y Ga (1-x-y) The vector N) contains 0≦x<1 and 0≦x+y≦1. In this embodiment, the channel layer 130 is a gallium nitride layer. The semiconductor barrier layer 140 is an aluminum gallium nitride layer or an indium gallium nitride layer. Due to spontaneous polarization in the channel layer 130 and the semiconductor barrier layer 140, and piezoelectric polarization between the channel layer 130 and the semiconductor barrier layer 140, a two-dimensional electron gas 2DEG is formed in the heterojunction between the channel layer 130 and the semiconductor barrier layer 140.

[0031] As shown in Figure 2, a separation and isolation process is performed between the active and inactive regions of the element. For example, a MESA etching process or an ion implantation process is performed. In this embodiment, ion implantation of nitrogen, argon, boron, oxygen, arsenic, etc. is performed to separate the element. As shown in Figure 3, an insulating protective layer 150 is then formed to cover the substrate and define the source region and drain region. The material of the insulating protective layer 150 is silicon nitride, aluminum nitride, aluminum oxide, silicon dioxide, silicon oxynitride, or silicon carbide. As shown in Figure 4, source electrodes 160 and drain electrodes 170 are formed in the source and drain regions on the semiconductor barrier layer 140, making ohmic contact with the semiconductor barrier layer 140. Specifically, the source electrodes and drain electrodes are made of an alloy material formed by metal deposition on an aluminum gallium nitride layer, and ohmic contact is formed at high temperatures. The alloy material is one selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof. Specifically, the source and drain electrodes are made of metal alloys such as titanium / aluminum / nickel / gold, titanium / aluminum / titanium / gold, titanium / aluminum / molybdenum / gold, and titanium / aluminum / titanium / titanium nitride.

[0032] Next, as shown in Figure 5, a gate electrode region is defined in the insulating protective layer 150 such that a portion of the semiconductor barrier layer 140 is exposed. A metal deposition process is performed in this gate electrode region, and a gate electrode 180 is formed on the exposed portion of the semiconductor barrier layer 140. The present invention suppresses gate leakage current by an innovative gate structure having a double barrier layer to solve the problem of hard breakdown due to high gate leakage current in conventional high electron mobility transistors. Specifically, the gate electrode 180 according to the present invention has a first gate barrier layer 182 and a second gate barrier layer 184. The first gate barrier layer 182 is placed on the exposed portion of the semiconductor barrier layer 140. The second gate barrier layer 184 is placed on the first gate barrier layer 182. In particular, the work function of the first gate barrier layer 182 is greater than that of the semiconductor barrier layer 140. The work function of the second gate barrier layer 184 is greater than that of the first gate barrier layer 182. In specific embodiments, the first gate barrier layer 182 is a conductive metal compound or a conductive ceramic. The work function of the conductive metal compound is 4 eV or greater, but is not limited thereto. The material of the conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The second gate barrier layer 184 is a conductive material having a work function of 5 eV or greater, for example, a metal material having a relatively high work function, but is not limited thereto. The conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. The gate electrode 180 further has a low-resistance metal layer 186 disposed on the second gate barrier layer 184. The material of the low-resistance metal layer is selected from aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold, or a combination thereof.

[0033] Figure 6 is a graph comparing the gate current and voltage of the normally-on high electron mobility transistor (D-mode HEMT) of the present invention and a conventional D-mode HEMT element. In Figure 6, curve I represents the current and voltage of a conventional D-mode HEMT element. On the other hand, curve II represents the current and voltage of the D-mode HEMT element of the present invention. Comparing the current and voltage curves I and II in Figure 6, it can be seen that the gate leakage current of the conventional D-mode HEMT element is relatively high, at about 1.00E-02 to 1.00E-03 amperes. In contrast, the present invention significantly suppresses the gate leakage current by the difference in the work function of the gate's double barrier layer, thereby reducing the gate leakage current of the D-mode HEMT element to about 1 / 1000th, and reducing it to about 1.00E-05 to 1.00E-07 amperes.

[0034] It should be noted that the above description describes a normally-on or so-called depletion-mode high electron-mobility transistor as one embodiment among several embodiments of the present invention. In fact, those skilled in the art can apply the technical features of the gate structure having a double barrier layer of the present invention to a normally-off high electron-mobility transistor. This will be explained with reference to Figures 1 and 7 and the above description. Similar to the manufacturing of D-mode HEMT elements, the E-mode HEMT element is manufactured by sequentially forming a nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140 on a substrate 100. In this embodiment, the material composition and formation method of the substrate 100, nucleation layer 110, buffer layer 120, channel layer 130, and semiconductor barrier layer 140 can be found in the above disclosures and will not be described further. Next, a P-type doped semiconductor layer is formed on the semiconductor barrier layer 140. In this embodiment, this P-type doped semiconductor layer is a P-type doped gallium nitride layer 190. Specifically, the gallium nitride layer is doped with a P-type dopant. P-type dopants include, for example, magnesium, calcium, zinc, beryllium, carbon, or combinations thereof. In specific embodiments, the P-type doped gallium nitride layer 190 has a thickness of about 1 nm to about 100 nm.

[0035] As shown in Figure 8, a separation and insulation process is performed between the active and inactive regions of the device. In this embodiment, as in the previous embodiment, ions such as nitrogen, argon, boron, oxygen, and arsenic are implanted by an ion implantation process to separate the device. Next, as shown in Figure 9, etching is performed on the P-type doped gallium nitride layer 190 to define the gate structure. As shown in Figure 10, as in the previous embodiment, an insulating protective layer 150 is formed on the semiconductor barrier layer 140, defining the source region and drain region. In this embodiment, the material composition and formation method of the insulating protective layer 150 can be found in the disclosures above, and their explanation is omitted. Next, as shown in Figure 11, a source electrode 160 and a drain electrode 170 are formed in the source region and drain region on the semiconductor barrier layer 140, making ohmic contact with the semiconductor barrier layer 140. The material composition and formation method of the source electrode and drain electrode can be found in the disclosures above, and their explanation is omitted.

[0036] Next, as shown in Figure 12, a gate electrode region is defined in the insulating protective layer 150 such that a portion of the P-type doped gallium nitride layer 190 is exposed. A metal deposition process is performed on this gate electrode region, and the gate electrode 180 is formed on the exposed portion of the P-type doped gallium nitride layer 190. This embodiment suppresses gate leakage current by an innovative gate structure with a double barrier layer to solve the problem of hard breakdown due to high gate leakage current in conventional high electron mobility transistors. Specifically, similar to the previous embodiment, the gate electrode 180 according to the present invention has a first gate barrier layer 182 and a second gate barrier layer 184. The first gate barrier layer 182 is placed on the exposed portion of the P-type doped gallium nitride layer 190. The second gate barrier layer 184 is placed on the first gate barrier layer 182. In particular, the work function of the first gate barrier layer 182 is greater than that of the P-type doped gallium nitride layer 190. The work function of the second gate barrier layer 184 is greater than that of the first gate barrier layer 182. In a specific embodiment, the first gate barrier layer 182 is a conductive metal compound or a conductive ceramic. The work function of the conductive metal compound is 4 eV or more, but is not limited thereto. The material of the conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The second gate barrier layer 184 is a conductive material having a work function of 5 eV or more, for example, a metal material having a relatively high work function, but is not limited thereto. The conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. The gate electrode 180 further has a low-resistance metal layer 186 disposed on the second gate barrier layer 184. The material of the low-resistance metal layer is selected from aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold, or a combination thereof.

[0037] Figure 13 is a graph comparing the gate current and voltage of the p-type doped gallium nitride enhancement high electron mobility transistor (pGaN E-mode HEMT) of the present invention and a conventional pGaN E-mode HEMT element. In Figure 13, the curve formed by connecting the square-shaped marking points is current-voltage curve I, which represents the current and voltage of the conventional pGaN E-mode HEMT element. On the other hand, in Figure 13, the curve formed by connecting the diamond-shaped marking points is current-voltage curve II, which represents the current and voltage of the pGaN E-mode HEMT element according to the present invention. Comparing current-voltage curves I and II in Figure 13, it can be seen that when the gate voltage of the conventional pGaN E-mode HEMT element is 7V to 10V, the gate leakage current is too high, causing a hard breakdown of the gate. Therefore, the operating range is limited to 0V to 6V. In contrast, the gate structure according to the present invention suppresses gate leakage current due to the difference in work functions of the different materials in the double barrier layer. As a result, the gate voltage of the pGaN E-mode HEMT element according to the present invention can be increased from 7V to approximately 19V, significantly improving the operable voltage range of the high electron mobility transistor.

[0038] It should be noted that the above is merely one embodiment of the normally-off high electron mobility transistor of the present invention, and the technical features of the gate structure having a double barrier layer disclosed in the present invention are applicable to other normally-off HEMT elements. Figure 14 shows a normally-off HEMT element having a recessed gate structure. Specifically, this gate electrode 180 also has a gate structure having a double barrier layer including a first gate barrier layer 182 and a second gate barrier layer 184. However, unlike the previous embodiment, there is no P-type doped gallium nitride layer 190 under the gate electrode 180, and a recess 142 exists in the semiconductor barrier layer 140 under the gate electrode 180. The first gate barrier layer 182 fills the recess 142 to enhance the gate's ability to control the electron channel. In this embodiment, even in a gate with a double barrier layer having a recess, the effect of suppressing gate leakage current can be obtained by utilizing the difference in work functions of the different materials in the double barrier layer in the gate structure.

[0039] On the other hand, Figure 15 shows another normally-off HEMT element to which the present invention is applied. Specifically, similar to the previous embodiment, in the HEMT element of the embodiment shown in Figure 15, the gate electrode 180 also has a gate structure having a double barrier layer including a first gate barrier layer 182 and a second gate barrier layer 184. A portion of the semiconductor barrier layer (i.e., aluminum gallium nitride layer) 140 below the gate electrode 180 is doped with fluoride ions. In this way, the bending of the energy band between the semiconductor barrier layer and the channel layer can be changed, and the gate voltage required to open the electron channel can be adjusted. Furthermore, by utilizing the difference in work functions of the different materials in the gate's double barrier layer, the gate leakage current suppression effect intended by the present invention can be obtained.

[0040] The technical feature of the present invention, which suppresses leakage current by a multilayer barrier layer, can also be applied to Schottky barrier diodes (SBDs). Details are described below. Figure 16 shows one embodiment of a D-mode SBD element to which the double barrier layer structure of the present invention is applied. This structure has, from bottom to top, a substrate 100, a nucleation layer 110, a buffer layer 120, a channel layer 130, and a semiconductor barrier layer 140. In this embodiment, the material composition and formation method of the substrate 100, nucleation layer 110, buffer layer 120, channel layer 130, and semiconductor barrier layer 140 can be described by referring to the information disclosed above, and their explanation is omitted here. An example of the semiconductor barrier layer 140 is an aluminum gallium nitride layer. The anode electrode 200 and cathode electrode 210 are arranged at two opposing ends on the semiconductor barrier layer 140. The anode electrode 200 has a first anode barrier layer 202 and a second anode barrier layer 204. The first anode barrier layer 202 is positioned between the semiconductor barrier layer 140 and the second anode barrier layer 204. The work function of the first anode barrier layer 202 is greater than that of the semiconductor barrier layer 140. The work function of the second anode barrier layer 204 is greater than that of the first anode barrier layer 202. In a specific embodiment, the first anode barrier layer 202 is a conductive metal compound with a work function of 4 eV or more. The material of the conductive metal compound is selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The second anode barrier layer 204 is a conductive material with a work function of 5 eV or more. The conductive material is selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride. The material of the cathode electrode 210 is selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof.

[0041] Figure 17 shows one embodiment of an E-mode SBD element to which the double barrier layer structure of the present invention is applied. This embodiment is substantially the same as that of Figure 16. This E-mode SBD element further includes a P-type doped gallium nitride layer 220 disposed between the semiconductor barrier layer 140 (i.e., the aluminum gallium nitride layer) and the first anode barrier layer 202. The work function of the first anode barrier layer 202 is greater than the work function of the P-type doped gallium nitride layer 220.

[0042] The above-described embodiments illustrate embodiments of the present invention and describe the characteristic configuration of the present invention. The present invention is not limited to the above embodiments. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention shall be based on the claims. [Explanation of Symbols]

[0043] 100 circuit boards 110 Nucleation layer 120 buffer layers 130 channel layers 140 Semiconductor barrier layer 142 recess 150 Insulating protective layer 160 source electrodes 170 Drain electrode 180 gate 182 First Gate Barrier Layer 184 Second Gate Barrier Layer 186 Low resistance metal layer 190 P-type doped gallium nitride layer 200 anode electrodes 202 First Anode Barrier Layer 204 Second Anode Barrier Layer 210 Cathode electrodes 220 P-type doped gallium nitride layer

Claims

1. Depletion mode high electron mobility transistor structure, circuit board and Disposed on the aforementioned substrate is a semiconductor barrier layer which is an aluminum gallium nitride layer, Disposed on the semiconductor barrier layer, the gate electrode includes a first gate barrier layer, a second gate barrier layer, and a low-resistance metal layer, The first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer. The low-resistance metal layer is disposed on the second gate barrier layer, The first gate barrier layer is a conductive metal compound with a work function of 4 eV or higher. The conductive metal compound material is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The work function of the first gate barrier layer is greater than the work function of the semiconductor barrier layer. A depletion-mode high electron-mobility transistor structure in which the work function of the second gate barrier layer is greater than that of the first gate barrier layer.

2. The depletion-mode high electron mobility transistor structure according to claim 1, characterized in that the second gate barrier layer is a conductive material with a work function of 5 eV or more.

3. The depletion-mode high electron mobility transistor structure according to claim 2, characterized in that the conductive material is one selected from the group consisting of nickel, platinum, tungsten, and tungsten nitride.

4. The depletion-mode high electron mobility transistor structure according to claim 1, further comprising a source electrode and a drain electrode disposed on the semiconductor barrier layer.

5. The depletion-mode high electron mobility transistor structure according to claim 4, characterized in that the materials of the source electrode and the drain electrode are one selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold, or a combination thereof.

6. The depletion-mode high electron-mobility transistor structure according to claim 1, further comprising a gallium nitride layer, wherein the aluminum gallium nitride layer is disposed on the gallium nitride layer.

7. The depletion-mode high electron mobility transistor structure according to claim 1, characterized in that the material of the low-resistance metal layer is one selected from the group consisting of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold, or a combination thereof.

8. Enhancement-type high electron mobility transistor structure, circuit board and Disposed on the aforementioned substrate is a semiconductor barrier layer which is an aluminum gallium nitride layer, Disposed on the semiconductor barrier layer, the gate electrode includes a first gate barrier layer, a second gate barrier layer, and a low-resistance metal layer, The semiconductor barrier layer beneath the gate electrode has a recess, and the first gate barrier layer fills the recess. The first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer. The low-resistance metal layer is disposed on the second gate barrier layer, The first gate barrier layer is a conductive metal compound with a work function of 4 eV or higher. The conductive metal compound material is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The work function of the first gate barrier layer is greater than the work function of the semiconductor barrier layer. An enhancement-type high-electron-mobility transistor structure in which the work function of the second gate barrier layer is greater than that of the first gate barrier layer.

9. Enhancement-type high electron mobility transistor structure, circuit board and Disposed on the aforementioned substrate is a semiconductor barrier layer which is an aluminum gallium nitride layer, Disposed on the semiconductor barrier layer, the gate electrode includes a first gate barrier layer, a second gate barrier layer, and a low-resistance metal layer, A portion of the aluminum gallium nitride layer beneath the gate electrode is doped with fluoride ions. The first gate barrier layer is disposed between the semiconductor barrier layer and the second gate barrier layer. The low-resistance metal layer is disposed on the second gate barrier layer, The first gate barrier layer is a conductive metal compound with a work function of 4 eV or higher. The conductive metal compound material is one selected from the group consisting of titanium nitride, tantalum nitride, and tungsten nitride. The work function of the first gate barrier layer is greater than the work function of the semiconductor barrier layer. An enhancement-type high-electron-mobility transistor structure in which the work function of the second gate barrier layer is greater than that of the first gate barrier layer.

10. The enhancement-type high electron mobility transistor structure according to claim 8 or 9, characterized in that the material of the low-resistance metal layer is one selected from the group consisting of aluminum, platinum, titanium, nickel, tungsten, copper, palladium, and gold, or a combination thereof.

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