memory devices

Abstract

We provide memory devices. [Solution] This disclosure provides a three-dimensional memory and a method for manufacturing the same, a memory system, and an electronic device, relating to the technical field of semiconductor chips. The three-dimensional memory includes a stacked structure, an etching stop layer, a protective layer, and a plurality of connecting pillars. The stacked structure includes alternating gate layers and dielectric layers and a plurality of steps. The etching stop layer is placed on the steps. The protective layer covers the stacked structure and the etching stop layer. The connecting pillar penetrates the protective layer and etching stop layer on the corresponding step and is electrically connected to the gate layer of the corresponding step.

Description

Technical Field

[0001] This disclosure relates to the technical field of semiconductor chips, and in particular, to memory devices.

Background Art

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become difficult and expensive, and the memory density of 2D or planar NAND flash approaches its upper limit. To overcome the limitations caused by 2D or planar NAND flash, the industry has developed memories having a three-dimensional structure (3D NAND) in which memory cells are arranged three-dimensionally on a substrate to increase the memory density.

[0003] In 3D NAND, a memory array device includes an array region and a step region. During the manufacture of the memory array device, contact holes are formed in each step of the step region by etching and filled with a conductive material to form connection pillars, thereby enabling the electrical signals of the gate layer to be input and output.

[0004] However, during the etching to form the contact holes, the gate layer is etched, so that the contact holes pass through the dielectric layer between two adjacent gate layers, resulting in a short circuit between different gate layers, that is, a short circuit between word lines of different layers, thereby causing a control error for the memory cells and possibly causing memory defects.

Summary of the Invention

[0005] Examples of this disclosure provide a three-dimensional memory and a method for manufacturing the same, a memory system, and an electronic device.

[0006] Examples of this disclosure adopt the following technical solutions.

[0007] In one embodiment, a three-dimensional memory is provided. The three-dimensional memory comprises a stacked structure, an etching stop layer, a protective layer, and a plurality of connecting pillars. The stacked structure includes alternately arranged gate layers and dielectric layers. The stacked structure includes a plurality of stages. The etching stop layer is disposed on the stages. The protective layer covers the stacked structure and the etching stop layer. Each stage corresponds to at least one connecting pillar, the connecting pillar penetrating the protective layer and etching stop layer on the corresponding stage and electrically connected to the gate layer of the corresponding stage.

[0008] In some examples, the etching stop layer includes multiple etching stop sections, one of which is provided on each step, and the multiple etching stop sections are spaced apart from each other.

[0009] In some cases, the etching stop layer is a continuous film layer covering multiple stages.

[0010] In some cases, the etching stop layer material includes an insulating material.

[0011] In some examples, the three-dimensional memory further comprises a first dielectric layer and a second dielectric layer, the first dielectric layer being positioned around a gate layer and the second dielectric layer being positioned around an etching stop layer.

[0012] In some examples, the three-dimensional memory further includes an isolation structure. The isolation structure penetrates the stacked structure and protective layer and comprises a first insulating layer, the material of which is different from the material of the etching stop layer.

[0013] In some examples, the isolation structure further includes a packing layer, and the first insulating layer is located between the packing layer and the laminated structure.

[0014] In some cases, the etching stop layer material includes silicon nitride or polysilicon.

[0015] In some examples, the three-dimensional memory further comprises a separation structure that penetrates the stacked structure and protective layer and has a second insulating layer, the material of which is the same as the material of the etching stop layer.

[0016] In some examples, the isolation structure further includes a packing layer, and the second insulating layer is located between the packing layer and the laminated structure.

[0017] In some examples, the isolation structure further comprises a third insulating layer located between the packing layer and the second insulating layer.

[0018] In some examples, the materials for the first insulating layer and the etching stop layer include silicon nitride.

[0019] In some cases, the thickness of the etching stop layer is greater than the thickness of the gate layer.

[0020] In another embodiment, a method for manufacturing a three-dimensional memory is provided. The manufacturing method includes forming an initial stacked structure comprising a plurality of initial stages, each comprising an alternately arranged first sacrificial layer and dielectric layers; forming a second sacrificial layer on the initial stacked structure; forming a gate line slit penetrating the second sacrificial layer and the initial stacked structure; removing the first sacrificial layer to form a first cavity; removing the second sacrificial layer to form a second cavity penetrating the gate line slit; forming a gate layer within the first cavity; forming an etching stop layer within the second cavity; and forming a separation structure within the gate line slit.

[0021] In some examples, after forming a second sacrificial layer on an initial laminated structure, the manufacturing method further includes patterning the second sacrificial layer to form a plurality of sacrificial parts, one of which is provided on each of the initial stages, and the plurality of sacrificial parts being spaced apart from each other.

[0022] In some examples, forming a gate layer in a first cavity and forming an etching stop layer in a second cavity includes filling the first cavity with gate material, partially filling the second cavity with gate material through gate line slits, removing the gate material from the second cavity, and forming an etching stop layer in the second cavity.

[0023] In some examples, forming an etch stop layer within the second cavity includes filling the second cavity with a dielectric material through the gate line slit. The dielectric material within the second cavity forms the etch stop layer.

[0024] In some examples, forming an etch stop layer within the second cavity includes filling the second cavity with a semiconductor material through the gate line slit and removing the semiconductor material covering the sidewalls of the gate line slit to form the etch stop layer.

[0025] In some examples, before forming a gate layer within the first cavity and an etch stop layer within the second cavity, the manufacturing method further includes forming a first dielectric layer within the first cavity and a second dielectric layer within the second cavity, where the first dielectric layer covers the sidewalls of the first cavity and the second dielectric layer covers the sidewalls of the second cavity.

[0026] In some examples, the manufacturing method further includes forming a protective layer covering the initial stacked structure and the second sacrificial layer, and the gate line slit also penetrates the protective layer.

[0027] In some examples, the manufacturing method further includes forming a plurality of initial contact holes penetrating the protective layer, etching the etch stop layer exposed by the initial contact holes to form the contact holes, and filling the contact holes with a conductive material to form connection pillars, where the connection pillars are electrically connected to the gate layer of the corresponding stage.

[0028] In yet another aspect, a memory system is provided. The memory system includes a controller and a three-dimensional memory, where the three-dimensional memory is the three-dimensional memory described in any one of the above examples or is manufactured by the manufacturing method of the three-dimensional memory described in any one of the above examples, and the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0029] In yet another aspect, an electronic device is provided. The electronic device includes the memory system described in any of the above examples.

Brief Description of the Drawings

[0030] To more clearly explain the technical solutions in the present disclosure, the drawings used in some examples of the present disclosure are briefly introduced below. Obviously, the drawings in the following description are only drawings of some examples of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings. Also, the drawings in the following description do not limit the actual size of the products included in the examples of the present disclosure, the actual flow of the methods, the actual timing of the signals, etc., and can be regarded as schematic diagrams. [Figure 1] It is a perspective view of a 3D memory structure provided by some examples. [Figure 2] It is a top view of a 3D memory provided by some examples. [Figure 3] It is a cross-sectional view taken along AA' of the 3D memory shown in FIG. 2. [Figure 4] It is an equivalent circuit diagram of the memory cell string of the 3D memory in FIG. 1. [Figure 5] It is a cross-sectional view taken along the first direction of the stage region of a 3D memory provided by some examples. [Figure 6] It is a cross-sectional view taken along the first direction of the stage region of another 3D memory provided by some examples. [Figure 7] It is a cross-sectional view taken along the second direction of the stage region of a 3D memory provided by some examples. [Figure 8] It is a cross-sectional view taken along the second direction of the stage region of another 3D memory provided by some examples. [Figure 9] It is a flowchart of a method for manufacturing a 3D memory according to some examples. [Figure 10] It is a diagram of the manufacturing operation of a method for manufacturing a 3D memory according to some examples. [Figure 11] It is a flowchart of a method for manufacturing a 3D memory according to some examples. [Figure 12]This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 13] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 14] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 15] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 16] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 17] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 18] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 19] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 20] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 21] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 22] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 23] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 24] This is a flowchart illustrating a method for manufacturing 3D memory, based on some examples. [Figure 25] This is a flowchart illustrating a method for manufacturing 3D memory, based on some examples. [Figure 26] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 27] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 28] This is a flowchart illustrating a method for manufacturing 3D memory, based on some examples. [Figure 29] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 30]This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 31] This is a flowchart illustrating a method for manufacturing 3D memory, based on some examples. [Figure 32] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 33] This is a diagram illustrating the manufacturing process for a 3D memory manufacturing method, based on some examples. [Figure 34] This is a diagram of a 3D memory structure, based on some examples. [Figure 35] This is a block diagram of a memory system, based on some examples. [Figure 36] This is a block diagram of a memory system, using some other examples. [Modes for carrying out the invention]

[0031] Technical solutions in some examples of this disclosure are described below clearly and completely, together with the drawings. Obviously, the examples described are only a part of, not all, of the examples of this disclosure. All other examples that can be obtained by those skilled in the art based on the examples provided in this disclosure should fall within the scope of protection of this disclosure.

[0032] In the description of this disclosure, terms such as “center,” “top,” “bottom,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside” indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and do not indicate or imply that the shown devices or elements have a particular orientation or must be constructed and operated in a particular orientation. They are merely intended to facilitate and simplify the description of this disclosure and should therefore not be understood as limiting the disclosure.

[0033] Unless otherwise specified in the context, the term “includes” throughout this specification and the claims shall be interpreted in an open and comprehensive sense, for example, “not limited to, but including.” In this description, terms such as “one implementation,” “some implementations,” “one example,” or “some examples” are intended to indicate that certain features, structures, materials, or properties relating to that implementation or example are included in at least one implementation or example of this disclosure. The schematic diagrams of the above terms do not necessarily refer to the same implementation or example. Furthermore, certain features, structures, materials, or properties may be included in any one or more implementations or examples in any appropriate manner.

[0034] In the following, the terms “First” and “Second” are for illustrative purposes only and should not be interpreted as indicating or implying relative importance or implicitly indicating the number of technical features shown. Therefore, features defined by “First” and “Second” may explicitly or implicitly include one or more such features. In the descriptions of the examples in this disclosure, “multiple” means two or more unless otherwise specified.

[0035] The term “connected” and its derivatives may be used to describe some examples. For example, the term “connected” may be used in the description of some examples to indicate that two or more components have direct physical or electrical contact with each other. The examples disclosed herein are not necessarily limited to those contained herein.

[0036] "At least one of A, B, and C" and "at least one of A, B, or C" have the same meaning and both include the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0037] "A and / or B" includes the following three combinations: A only, B only, and the combination of A and B.

[0038] The meanings of “on,” “above,” and “over” in this disclosure should be interpreted most broadly, with “on” meaning not only “directly on something” but also “on something” with an intermediate feature or layer in between, and “above” or “over” meaning not only “above” or “over” something but also “above” or “over” something without an intermediate feature or layer in between (for example, directly on something).

[0039] Exemplary configurations are described herein with reference to at least one cross-sectional or plan view used as idealized exemplary drawings. In the drawings, layer and area thicknesses are exaggerated for clarity. Thus, variations in shape from the drawings are possible, for example, due to manufacturing techniques and tolerances. Accordingly, exemplary configurations should not be construed as being limited to the shapes of the areas shown herein, and include shape deviations caused by manufacturing, for example. For example, an etching area shown as a rectangle typically has curved characteristics. Thus, the areas shown in the drawings are essentially schematic, and their shapes are not intended to represent the actual shapes of areas in the apparatus, nor are they intended to limit the scope of exemplary configurations.

[0040] Figure 1 is a perspective view of the structure of the 3D memory 100 provided by some examples. Figure 2 is a top view of the 3D memory 100 provided by some examples. Figure 3 is a cross-sectional view of the 3D memory 100 along AA' shown in Figure 2. Figure 2 shows a top view of only a portion of the 3D memory 100.

[0041] Referring to Figures 1 and 2, the three-dimensional memory 100 includes array region A and tier region B. Tier region B may be located between array region A or around array region A. In one example, along a first direction X, the three-dimensional memory 100 comprises array region A and tier region B arranged juxtaposed and contiguously, where array region A is configured to form memory cells and tier region B is configured to provide contacts for connecting to word line connection lines (WL1 to WL4 are used as examples for illustrative purposes in Figure 1).

[0042] Referring to Figures 1 and 3, the three-dimensional memory 100 comprises a stacked structure 2 and a protective layer 3 covering the stacked structure 2, the stacked structure 2 comprising alternately arranged gate layers 21 and dielectric layers 22 (not shown in Figure 1).

[0043] The number of gate layers 21 and dielectric layers 22 in the laminated structure 2 may be set according to actual needs, and it should be noted that this disclosure does not impose any specific limitations here.

[0044] In some examples, as shown in Figures 1 and 3, the three-dimensional memory 100 further comprises a substrate 1, and the stacked structure 2 is arranged on the substrate 1.

[0045] In some examples, the substrate 1 is configured to support a laminated structure 2 and may include doped regions 11, and the material of the substrate 1 includes at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0046] In some other examples, the substrate 1 does not function to support the laminated structure 2 and may be a source layer, and the material of the source layer includes a semiconductor material. The semiconductor material may be, for example, single-crystal silicon, polysilicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer may be partially or completely doped. In one example, the source layer may include doped regions doped with a p-type dopant.

[0047] In some examples, the material of the dielectric layer 22 includes an insulating material. In one example, the material of the dielectric layer 22 includes silicon oxide or silicon nitride. For example, the material of the dielectric layer 22 includes silicon dioxide, but is not limited to this disclosure.

[0048] In some examples, the gate layer 21 material includes a conductive material. In one example, the gate layer 21 material includes a metal or doped polysilicon. For example, the gate layer 21 material includes, but is not limited to, at least one of tungsten, cobalt, copper, aluminum, and doped crystalline silicon.

[0049] In some examples, the material of protective layer 3 includes an insulating material. The material of protective layer 3 may be the same as the material of dielectric layer 22. In one example, the material of protective layer 3 includes silicon oxide or silicon nitride. For example, the material of protective layer 3 includes silicon dioxide, but this disclosure is not limited thereto.

[0050] As shown in Figures 1, 2, and 3, the array region A contains multiple memory cell strings 4, which penetrate the stacked structure 2 along the third direction Z, and the multiple memory cell strings 4 may be arranged in a matrix in the first direction X and the second direction Y.

[0051] Note that the substrate 1 extends in the XY plane, and the first direction X and the second direction Y may be two orthogonal directions on the plane of the substrate 1. For example, the first direction X is the direction of extension of the word line WL, the second direction Y is the direction of extension of the bit line BL, and the third direction Z is perpendicular to the substrate 1, i.e., perpendicular to the XY plane.

[0052] Figure 4 is an equivalent circuit diagram of the memory cell string 4 of the three-dimensional memory 100 shown in Figure 1. As shown in Figures 1 and 4, one memory cell string 4 corresponds to the storage capacity of multiple planar memory cells. Therefore, the three-dimensional memory 100 can provide a large storage capacity.

[0053] Referring to Figures 1 and 4, the first end of the memory cell string 4 is connected to the bit line BL, and the second end is connected to the source line SL. That is, the memory cell string 4 comprises a plurality of transistors connected in series between the first end and the second end, and the plurality of transistors comprises at least one top-selection transistor Q1, at least one storage transistor M, and at least one bottom-selection transistor Q2. Figure 4 illustrates a plurality of transistors including one top-selection transistor Q1, four storage transistors M, and one bottom-selection transistor Q2.

[0054] During the write operation, data is written to the memory cell string 4 using the FN (Fowler-Nordheim) tunneling effect to a selected memory transistor (one of M1 to M4 in Figure 4) among the memory transistors M.

[0055] In the read operation, for memory cell string 4, the amount of stored charge is determined according to the ON state of the selected storage transistor (one of M1 to M4 in Figure 4) within the storage transistor M, and the data represented by that amount of charge is obtained.

[0056] Figure 5 is a cross-sectional view of a stepped region B of a three-dimensional memory 100 provided by some examples, along the first direction X. As shown in Figures 2 and 5, a portion of the stacked structure 2 within the stepped region B includes multiple steps 23, and each gate layer 21 of the stacked structure 2 is electrically connected to the corresponding signal line connection via a connecting pillar 5.

[0057] In one example, referring to Figure 1, along the third direction Z, at least one of the bottom gate layers 21 is configured as a ground selection line layer SGS, and at least one of the top gate layers 21 is configured as a string selection line layer SGD. The intermediate gate layers 21 are configured as word line layers WL. In Figure 1, as an example, one gate layer 21 configured as a ground selection line layer SGS (gate of bottom selection transistor Q2), one gate layer 21 configured as a string selection line layer SGD (gate of top selection transistor Q1), and four gate layers configured as word line layers WL (gate of memory transistor M) are shown.

[0058] The string selection line layer SGD is electrically connected to the corresponding selection line connection line (one of SSL1 to SSL4) via the connection pillar 5, the ground selection line layer SGS is electrically connected to the ground selection line GSL via the connection pillar 5, and the word line layer WL is electrically connected to the corresponding word line connection line (one of WL1 to WL4) via the connection pillar 5.

[0059] In the process of forming the connecting pillar 5, first, the protective layer 3 covering the stacked structure 2 is etched to form contact holes 6 (see Figure 33). However, during the etching of the protective layer 3 to form the contact holes 6, due to the different thicknesses of the protective layer 3 across different stages 23, the gate layer 21 of the stage 23 corresponding to the thinner protective layer 3 tends to be etched, thereby causing the contact holes 6 (see Figure 33) to pass through the dielectric layer 22 between two adjacent gate layers 21, resulting in a short circuit between different gate layers 21, which in turn causes a control error to the memory cell and leads to a memory failure.

[0060] Based on this, with reference to Figures 3 and 5, some examples of the present disclosure provide a three-dimensional memory 100 comprising a stacked structure 2, an etching stop layer 7, a protective layer 3, and a plurality of connecting pillars 5.

[0061] The etching stop layer 7 is arranged on multiple stages 23, and the protective layer 3 covers the laminated structure 2 and the etching stop layer 7. Each stage 23 corresponds to at least one connecting pillar 5 that penetrates the protective layer 3 and the etching stop layer 7 on the corresponding stage 23 and is electrically connected to the gate layer 21 of the corresponding stage 23.

[0062] It should be noted that the protective layer 3 has a high etching selectivity ratio with respect to the etching stop layer 7, and that the initial contact hole 61 (see Figure 33) can be reliably stopped on the etching stop layer 7 during the subsequent removal of the protective layer 3 to form the contact hole 6 (see Figure 32). It should also be understood that the initial contact hole 61 (see Figure 32) may extend through the protective layer 3 and stop within the etching stop layer 7. In one example, the material of the protective layer 3 contains silicon oxide and the material of the etching stop layer 7 contains silicon nitride. The step of removing the protective layer 3 to form the contact hole 6 (see Figure 33) can be described later in the method for fabricating the 3D memory 100 and will not be repeated here.

[0063] In the three-dimensional memory 100 provided in the above example of the present disclosure, the etching stop layer 7 is located on a step 23. In this case, in the step of forming the contact hole 6 (see Figure 33), the initial contact hole 61 may be formed by stopping the via formed by etching the protective layer 3 at the etching stop layer 7 (see Figure 32). Then, the etching stop layer 7 exposed by the initial contact hole 61 (see Figure 32) is etched, and the etching stops at the gate layer 21 of the corresponding step 23 to form the contact hole 6 (see Figure 33).

[0064] Based on this, in the three-dimensional memory 100 provided in the above example of the present disclosure, during etching to form the contact holes 6, the contact holes 6 for forming the connecting pillars 5 (see Figure 33) can be stopped by two-step etching at the corresponding gate layer 21, thereby solving the problem of short circuits between different gate layers 21 caused by etching of the contact holes 6 that penetrate the gate layer 21, and thereby improving product yield.

[0065] In some examples, as shown in Figure 5, the thickness of the etching stop layer 7 is greater than the thickness of the gate layer 21. The thickness of the etching stop layer 7 may be designed according to the thickness of the laminated structure 2, and this disclosure does not impose any further limitations.

[0066] In some examples, the 3D memory 100 further comprises a first dielectric layer and a second dielectric layer, the first dielectric layer being located between the gate layer 21 and the dielectric layer 22, and the second dielectric layer being located between the etching stop layer 7 and the dielectric layer 22, thereby reducing the risk of leakage current in the memory cell. The materials of the first and second dielectric layers are high dielectric constant materials. For example, the materials of the first and second dielectric layers include at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0067] In some examples, the three-dimensional memory 100 further comprises an adhesive layer placed between the second dielectric layer and the gate layer 21 to enhance adhesion between the gate layer 21 and the second dielectric layer. The material of the adhesive layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride.

[0068] In some examples, as shown in Figure 5, the etching stop layer 7 comprises multiple etching stop sections 71, one of which is provided on each step 23, and the multiple etching stop sections 71 are spaced apart from each other. That is, of two adjacent steps 23, the step 23 further away from the substrate 1 is the first step, and the step 23 closer to the substrate 1 is the second step, with the etching stop section 71 on the first step spaced apart from the etching stop section 71 on the second step. In other words, by separating the etching stop sections 71 on different steps 23, structural stress is reduced and reliability is improved.

[0069] As shown in Figure 5, the etching stop section 71 of the second stage is also spaced apart from the first stage. That is, a gap exists between the etching stop section 71 on the second stage and the gate layer 21 included in the first stage, and for example, the etching stop section 71 is electrically insulated from the gate layer 21 included in the first stage. In this case, the material of the etching stop section 71 may further contain a conductive material, and the connecting pillar 5 is electrically connected only to the gate layer 21 of the stage 23 below it, there is no short circuit between different gate layers 21, and no memory failure occurs.

[0070] It should be noted that the material of the etching stop section 71 may include an insulating material or a conductive material. For example, the material of the etching stop section 71 may include, but is not limited to, silicon nitride, polysilicon, and metal.

[0071] Figure 6 is a cross-sectional view of a step region B of another three-dimensional memory 100 provided by some examples, along the first direction X. In some other examples, as shown in Figure 6, the etching stop layer 7 is a continuous film layer covering multiple steps 23.

[0072] To avoid short circuits between gate layers by electrically connecting different gate layers 21 via the etching stop layer 7, the material of the etching stop layer 7 is an insulating material. In this way, the connecting pillar 5 is electrically connected only to the gate layer 21 of the layer 23 below it by direct contact, there is no short circuit between different gate layers 21, and no memory failure occurs.

[0073] If the second dielectric layer is placed between the etching stop layer 7 and the dielectric layer 22, it should be noted that the second dielectric layer is also an insulating material such as aluminum oxide to avoid short circuits between different gate layers that would occur by electrically connecting different gate layers 21 via the etching stop layer 7. In this case, the continuous etching stop layer 7 may also be a conductive material.

[0074] Figure 7 is a cross-sectional view of a stepped region B of a three-dimensional memory 100 provided in some examples, along the second direction Y. As shown in Figures 1, 2, and 7, the three-dimensional memory 100 further comprises a separation structure 8 penetrating the stacked structure 2 and the protective layer 3 in order to divide the three-dimensional memory 100 into a plurality of memory blocks.

[0075] In some examples, referring to Figures 7 and 23, the laminated structure 2 has a gate line slit GLS, and the isolation structure 8 is located within the gate line slit GLS. The isolation structure 8 includes a first insulating layer 81 that fills the gate line slit GLS to prevent short circuits between different gate layers 21 within the gate line slit GLS, or to prevent oxidation of the gate layers 21. The material of the first insulating layer 81 is different from the material of the etching stop layer 7, for example, the first insulating layer 81 and the etching stop layer 7 are formed by different process operations.

[0076] In some other examples, as shown in Figures 7 and 23, the isolation structure 8 comprises a first insulating layer 81 and a packing layer 82, wherein the first insulating layer 81 covers the sidewalls of the gate wire slit GLS to prevent short circuits between different gate layers 21 within the gate wire slit GLS or to prevent oxidation of the gate layers 21. The packing layer 82 fills the gate wire slit GLS to provide a mechanical support function and prevent the collapse of the laminated structure 2. The material of the first insulating layer 81 is different from the material of the etching stop layer 7, for example, the first insulating layer 81 and the etching stop layer 7 are formed by different process operations, that is, there is a clear interface distinction between the first insulating layer 81 and the etching stop layer 7.

[0077] It should be noted that if the etching stop layer 7 includes a plurality of spaced-apart etching stop portions 71, the etching stop layer 7 may be made of an insulating material or a conductive material. If the etching stop layer 7 is a continuous film layer, the etching stop layer 7 may be made of an insulating material. In one example, the etching stop layer 7 contains silicon nitride.

[0078] Furthermore, the material of the first insulating layer 81 includes an insulating material. In one example, the material of the first insulating layer 81 includes silicon oxide, but the disclosure is not limited thereto. The material of the packing layer 82 may be a conductive material or an insulating material. In one example, the material of the packing layer 82 includes polysilicon, but the disclosure is not limited thereto. When forming an array common source doped region on the substrate 1 exposed by the gate line slit GLS, the material of the packing layer 82 may be a conductive material, and the source signal may be derived through the packing layer 82 placed within the gate line slit GLS.

[0079] Figure 8 is a cross-sectional view of a layer region B along a second direction Y of another three-dimensional memory 100 provided by some examples. As shown in Figures 1, 2, and 8, the three-dimensional memory 100 further comprises a separation structure 8 that penetrates the stacked structure 2 and the protective layer 3 so as to divide the semiconductor structure 100 into a plurality of memory blocks.

[0080] In some examples, as shown in Figures 8 and 29, the isolation structure 8 includes a second insulating layer 83 that fills the gate wire slit GLS to prevent short circuits between different gate layers 21 within the gate wire slit GLS, or to prevent oxidation of the gate layers 21. The material of the second insulating layer 83 is the same as the material of the etching stop layer 7, and for example, the second insulating layer 83 and the etching stop layer 7 may be formed together in the same process operation. That is, there is no clear interface distinction between the second insulating layer 83 and the etching stop layer 7.

[0081] In some other examples, as shown in Figures 8 and 29, the isolation structure 8 comprises a second insulating layer 83, a third insulating layer 84, and a filling layer 82, wherein the second insulating layer 83 covers the sidewalls of the gate wire slit GLS to prevent short circuits between different gate layers 21 within the gate wire slit GLS or to prevent oxidation of the gate layers 21. The third insulating layer 84 is located on the side of the second insulating layer 83 furthest from the laminated structure 2 and is situated between the filling layer 82 and the second insulating layer 83. The filling layer 82 is located on the side of the third insulating layer 84 furthest from the second insulating layer 83 and fills the gate wire slit GLS, providing a mechanical support function and preventing the collapse of the laminated structure 2.

[0082] The material of the second insulating layer 83 is the same as the material of the etching stop layer 7, and for example, the second insulating layer 83 and the etching stop layer 7 may be formed together in the same process operation. That is, there is no clear interface distinction between the second insulating layer 83 and the etching stop layer 7. In one example, the material of the second insulating layer 83 includes silicon nitride, but the disclosure is not limited thereto. The material of the third insulating layer 84 includes an insulating material. In one example, the material of the third insulating layer 84 includes silicon oxide, but the disclosure is not limited thereto. The material of the packing layer 82 may be as referred to above and is not repeated here.

[0083] When the second insulating layer 83 and the etching stop layer 7 are formed together in the same process, it should be noted that the etching stop layer 7 is an insulating material, regardless of whether the etching stop layer 7 includes multiple spaced etching stop portions 71 or whether the etching stop layer 7 is a continuous film layer. In one example, the etching stop layer 7 contains silicon nitride.

[0084] As shown in Figure 9, some examples of this disclosure further provide a method for manufacturing a three-dimensional memory 100 (see Figure 3) including S1 to S6.

[0085] S1: Referring to Figures 9 and 10, the initial laminated structure 200 is formed.

[0086] In the above operation, the initial stacked structure 200 comprises alternatingly arranged first sacrificial layers 211 and dielectric layers 22. The initial stacked structure 200 includes a plurality of initial stages 23, the uppermost layer of each initial stage 23 being a dielectric layer 22.

[0087] The initial stacked structure 200 can be formed by any of the following thin-film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In one example, a plurality of initial film layer pairs 210 are sequentially formed on the substrate 1 using the CVD thin-film deposition process, each initial film layer pair 210 including sequentially arranged first sacrificial layers 211 and dielectric layers 22.

[0088] It should be noted that multiple initial stages 23 of the initial stacked structure 200 may be formed by performing multiple "trim etching" cycles. The region where the multiple initial stages 23 are located can be called stage region B (see Figure 2).

[0089] The material of the dielectric layer 22 is different from the material of the first sacrificial layer 211. The material of the dielectric layer 22 includes an insulating material. For example, the material of the dielectric layer 22 includes silicon oxide or silicon nitride. For example, the material of the dielectric layer 22 includes silicon dioxide, but is not limited to this disclosure. The material of the first sacrificial layer 211 includes at least one of polysilicon, silicon nitride, or polycrystalline germanium, but is not limited to this disclosure.

[0090] S2: Referring to Figures 9, 12, and 13, the second sacrificial layer 710 is formed on the initial laminated structure 200.

[0091] In the above operation, the second sacrificial layer 710 is placed on the initial stage 23. The second sacrificial layer 710 may be formed by any of the thin film deposition processes such as CVD, PVD, or ALD. In one example, the second sacrificial layer 710 is formed on multiple initial stages 23 using a PVD thin film deposition process.

[0092] The material of the second sacrificial layer 710 is the same as the material of the first sacrificial layer 211 and includes, but is not limited to, at least one of polysilicon, silicon nitride, and polycrystalline germanium. It should also be understood that the material of the dielectric layer 22 is different from the material of the second sacrificial layer 710. For example, the material of the dielectric layer 22 includes silicon dioxide, and the material of the second sacrificial layer 710 includes silicon nitride.

[0093] S3: Referring to Figures 9, 17, and 18, gate line slits GLS are formed that penetrate the second sacrificial layer 710 and the initial laminated structure 200.

[0094] In the above operation, the gate line slit GLS may be formed by dry etching or by a combination of dry etching and wet etching processes. In one example, the gate line slit GLS is formed using an anisotropic etching process (any dry etching such as ion milling etching, plasma etching, reactive ion etching, or laser ablation), and the etching duration is controlled so that the etching penetrates the initial laminated structure 200.

[0095] S4: Referring to Figures 9, 17, and 18, the first sacrificial layer 211 is removed via the gate line slit GLS to form the first cavity C1, and the second sacrificial layer 710 is removed to form the second cavity C2.

[0096] In the above operation, referring to Figure 15, when forming the first cavity C1 and the second cavity C2, the gate line slit GLS is used as an etchant channel to remove the first sacrificial layer 211 by isotropic etching to form the first cavity C1. The gate line slit GLS is used as an etchant channel to remove the second sacrificial layer 710 by isotropic etching to form the second cavity C2. Isotropic etching can be performed using selective wet etching or vapor etching. In wet etching, an etching solution is used as the etchant. In vapor etching, an etching gas is used as the etchant.

[0097] When the protective layer 3 and dielectric layer 22 are made of silicon oxide, and the first sacrificial layer 211 and second sacrificial layer 710 are made of silicon nitride, a phosphoric acid solution may be used as the etchant during wet etching. Note that at least one of C4F8, C4F6, and CH2F2 may be used as the etching gas during vapor etching.

[0098] S5: Referring to Figures 9, 17, and 19, the gate layer 21 is formed in the first cavity C1. The etching stop layer 7 is formed in the second cavity C2.

[0099] In the above operation, if the inner wall of the second cavity C2 is covered with gate material and the gap is held within the second cavity C2, as shown in Figures 21 and 22, other steps are required to form the etching stop layer 7, and exemplary steps can be found below and are not repeated here.

[0100] S6: Referring to Figures 7, 9, and 23, the separation structure 8 is formed within the gate line slit GLS.

[0101] Through the above operation, the separation structure 8 is formed within the gate line slit GSL, preventing short circuits between different gate layers 21 within the gate line slit GLS, preventing oxidation of the gate layer 21, and providing a mechanical support function. The separation structure 8 may be formed within the gate line slit GLS by any of the thin film deposition processes such as CVD, PVD, and ALD.

[0102] In some examples, as shown in Figures 7 and 23, the isolation structure 8 comprises a first insulating layer 81 and a filling layer 82. The first insulating layer 81 covers the sidewalls of the gate wire slit GLS and is located between the filling layer 82 and the isolation structure 8 to prevent short circuits between different gate layers 21 within the gate wire slit GLS and to prevent oxidation of the gate layers 21. The filling layer 82 fills the gate wire slit GLS to provide mechanical support and prevent the collapse of the laminated structure 2.

[0103] It should be noted that the material of the first insulating layer 81 includes an insulating material. In one example, the material of the first insulating layer 81 includes silicon oxide, but is not limited thereto. The material of the packing layer 82 may be a conductive material or an insulating material. In one example, the material of the packing layer 82 is a conductive material and includes polysilicon, but is not limited thereto. When an array common source doped region is formed on the substrate 1 exposed by the gate line slit GLS, the material of the packing layer 82 may be a conductive material in order to draw the source signal through the packing layer 82.

[0104] In some other examples, as shown in Figures 8 and 29, the isolation structure 8 comprises a second insulating layer 83, a third insulating layer 84, and a filler layer 82. The second insulating layer 83 covers the sidewalls of the gate wire slit GLS. The third insulating layer 84 is located on the side of the second insulating layer 83 furthest from the laminated structure 2, between the filler layer 82 and the second insulating layer 83. The filler layer 82 is located on the side of the third insulating layer 84 furthest from the second insulating layer 83 and fills the gate wire slit GLS. Note that the material of the second insulating layer 83 includes, but is not limited to, silicon nitride. The material of the third insulating layer 84 includes, but is not limited to, silicon oxide.

[0105] In some examples, prior to S5, the method for manufacturing the three-dimensional memory 100 further includes S10.

[0106] S10: The first dielectric layer is formed in the first cavity C1, and the second dielectric layer is formed in the second cavity C2.

[0107] In the above operation, to reduce the leakage current of the gate layer 21, the first dielectric layer covers the sidewall of the first cavity C1, and the second dielectric layer covers the sidewall of the second cavity C2. The materials of the first and second dielectric layers are high dielectric constant materials. For example, the materials of the first and second dielectric layers include at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0108] In some examples, between S10 and S5, the method for manufacturing the three-dimensional memory 100 further includes S11.

[0109] S11: The adhesive layer is formed in the first cavity C1.

[0110] In the above operation, the adhesive layer is placed between the second dielectric layer and the gate layer 21 to enhance the adhesion between the gate layer 21 and the second dielectric layer. The material of the adhesive layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride.

[0111] It should be noted that the etching rate of the adhesive layer may be close to that of the gate material, and the adhesive layer may be etched off during the subsequent etching process to remove the gate material in the second cavity C2.

[0112] In some examples, referring to Figure 25, the method for manufacturing the three-dimensional memory 100 after S2 further includes S21.

[0113] S21: Referring to Figures 12, 14, and 25, the second sacrificial layer 710 is etched to form a plurality of sacrificial parts 711.

[0114] In the above operation, a sacrificial section 711 is provided on each initial stage 23, and multiple sacrificial sections 711 are arranged spaced apart from one another. That is, the sacrificial sections 711 on different initial stages 23 are separated from each other, reducing structural stress and thus improving reliability.

[0115] During the patterning of the second sacrificial layer 710, a photoresist layer can be applied onto the second sacrificial layer 710. Subsequently, a patterned photoresist layer is formed by process operations such as exposure and development. The second sacrificial layer 710 is etched using the patterned photoresist layer as a mask, and finally the photoresist layer is removed to form a plurality of sacrificial portions 711.

[0116] In some examples, referring to Figures 17, 21, and 24, S5 includes S51 to S53.

[0117] S51: The gate wire slit GLS fills the first cavity C1 with gate material, and the second cavity C2 is partially filled with gate material.

[0118] In the above operation, the first cavity C1 is filled with gate material, and a portion of the gate material in the first cavity C1 forms a gate layer 21. A gap is maintained in the second cavity C2. The thickness of the second cavity C2 is greater than the thickness of the first cavity C1. At this time, once the first cavity C1 is completely filled with gate material so that the gate layer 21 is formed, the filling of the gate material may be stopped, and the filling time of the gate material may be controlled so that the inner wall of the second cavity C2 is covered with gate material and a gap is maintained in the second cavity C2.

[0119] S52: The gate material inside the second cavity C2 is removed.

[0120] In the above operation, the gate material covering the sidewall of the gate line slit GLS is removed during the process of removing the gate material covering the sidewall of the gate line slit GLS. That is, the removal of the gate material covering the sidewall of the gate line slit GLS and the removal of the gate material in the second cavity C2 may be performed in the same process. For example, the gate material on the sidewall of the gate line slit GLS and the gate material in the second cavity C2 are removed by a single etching process.

[0121] Because the gate material in the second cavity C2 maintains the gap, in the process of removing the gate material from the sidewall of the gate line slit GLS, the etchant enters the gap in the second cavity C2 and comes into contact with the gate material in the second cavity C2 over a wide area for etching, and after the gate material from the sidewall of the gate line slit GLS is removed, the gate material in the second cavity C2 is also removed. Here, the etching time may be controlled so that both the gate material covering the sidewall of the gate line slit GLS and the gate material in the second cavity C2 are completely removed.

[0122] S53: The etching stop layer 7 is formed in the second cavity C2.

[0123] In some cases, S53 includes S531.

[0124] S531: Referring to Figures 19 and 29, the second cavity C2 is filled with dielectric material via the gate wire slit GLS.

[0125] In the above operation, referring to Figures 19 and 20, the dielectric material fills the second cavity C2 to form the etching stop layer 7. The dielectric material covers the sidewalls of the gate line slit GLS to form the second insulating layer 83 of the isolation structure 8 (see Figure 8). The dielectric material is an insulating material.

[0126] During the filling of the second cavity C2 with dielectric material, the gate line slit GLS can be used as a deposition channel to fill the second cavity C2 with dielectric material by any one of the thin film deposition processes such as CVD, PVD, and ALD. In the process of filling the second cavity C2 with dielectric material using the gate line slit GLS as a deposition channel, dielectric material is also formed on the sidewalls of the gate line slit GLS.

[0127] It should be noted that the material of protective layer 3 has a high etching selectivity ratio with respect to the dielectric material, which ensures that the initial contact holes 61 (see Figure 33) are stopped on the etching stop layer 7 formed by the dielectric material during the subsequent removal of protective layer 3 to form contact holes 6 (see Figure 32), thereby ensuring that the etching stop layer 7 is hardly removed. It should also be understood that the aforementioned initial contact holes 61 (see Figure 32) may also extend through protective layer 3 and stop within the etching stop layer 7 formed by the dielectric material.

[0128] In some other examples, referring to Figure 28, S53 includes S532 and S533.

[0129] S532: Referring to Figures 19, 28, and 29, the semiconductor material is filled into the second cavity C2 via the gate line slit GLS.

[0130] Referring to Figures 19 and 20, when filling the second cavity C2 with semiconductor material, the gate line slit GLS may be used as a deposition channel for filling the second cavity C2 with semiconductor material by any of the thin film deposition processes such as CVD, PVD, and ALD. In the process of filling the second cavity C2 with semiconductor material using the gate line slit GLS as a deposition channel, semiconductor material is also formed on the sidewalls of the gate line slit GLS.

[0131] S533: Referring to Figures 28 and 30, the semiconductor material covering the sidewall of the gate line slit GSL is removed.

[0132] In the above operation, the semiconductor material on the sidewall of the gate line slit GLS is etched off using an etchant, and the etching time may be controlled so that etching is stopped after the semiconductor material on the sidewall of the gate line slit GLS has been etched off. In this case, the semiconductor material may be a different material from the material of the protective layer 3, as the material of the protective layer 3 has a high etching selectivity ratio with respect to the semiconductor material. In one example, the semiconductor material includes, but is not limited to, polysilicon or a metal.

[0133] In some cases, the manufacturing method further includes S22.

[0134] S22: Referring to Figures 11, 15, and 16, the protective layer 3 is formed on the second sacrificial layer 710 and the initial laminated structure 200.

[0135] In the above operation, the protective layer 3 covers the initial laminated structure 200 and the second sacrificial layer 710. The protective layer 3 may also be formed by filling the stepped region B by any thin-film deposition process such as CVD, PVD, or ALD (see Figure 3) and by a planarization process. The planarization process includes, but is not limited to, a chemical mechanical planarization (CMP) process or a recess etching (REP) process.

[0136] It should be noted that the material of protective layer 3 is different from the materials of both the first sacrificial layer 211 and the second sacrificial layer 710. The material of protective layer 3 includes an insulating material and may be the same as the material of dielectric layer 22. In one example, the material of protective layer 3 includes silicon dioxide. For example, the material of protective layer 3 includes silicon dioxide, but this disclosure is not limited thereto.

[0137] In some examples, after the etching stop layer 7 is formed, referring to Figure 31, the manufacturing method of the 3D memory 100 further includes steps S7 to S9.

[0138] S7: Referring to Figures 31 and 32, a plurality of initial contact holes 61 are formed that penetrate the protective layer 3.

[0139] In the above operation, each initial contact hole 61 corresponds to one stage 23, and the initial contact hole 61 is located on the corresponding stage 23. Here, the stage 23 includes the gate layer 21 and the dielectric layer 22.

[0140] The initial contact holes 61 may be formed by dry etching or a combination of dry etching and wet etching processes. In one example, the initial contact holes 61 are formed using an anisotropic etching process (any dry etching such as ion milling etching, plasma etching, reactive ion etching, or laser ablation), and the etching time is controlled so that etching stops at the etching stop layer 7 after penetrating the protective layer 3. Note that the initial contact holes 61 may extend until they stop within the etching stop layer 7.

[0141] S8: Referring to Figures 31, 32, and 33, the etching stop layer 7 exposed at the initial contact hole 61 is etched to form the contact hole 6.

[0142] In the above operation, each contact hole 6 corresponds to one step 23, and the orthogonal projection of the contact hole 6 on the substrate 1 lies within the orthogonal projection of the corresponding step 23 on the substrate 1.

[0143] It should be noted that the shape of the contact hole 6 may be cylindrical. For example, the shape of the contact hole 6 may be cylindrical or prismatic, but this disclosure is not limited thereto.

[0144] S9: Referring to Figures 5, 31, and 33, a conductive material is filled into the contact hole 6 to form a connecting pillar 5.

[0145] In the above operation, the connecting pillar 5 is electrically connected to the gate layer 21 of the corresponding step 23. Here, the contact hole 6 is filled with a conductive material by one of the thin film deposition processes such as CVD, PVD, or ALD. The gate layer 21 is electrically connected to the corresponding signal line via the connecting pillar 5. The signal line includes at least one of the string selection line (one of SSL1 to SSL4), the ground selection line GSL, and the word line (one of WL1 to WL4).

[0146] It should be noted that the shape of the connecting pillar 5 may be cylindrical. For example, the shape of the connecting pillar 5 may be cylindrical or prismatic, and this disclosure is not limited thereto.

[0147] Referring to Figure 34, the 3D memory 100 further comprises an array interconnection layer 110, a peripheral interconnection layer 120, and peripheral circuits 130.

[0148] The array interconnection layer 110 may be coupled to the memory cell string 4. The array interconnection layer 110 may include one or more first interlayer insulating layers 111, and may further include a plurality of contacts insulated from one another via these first interlayer insulating layers 111, the contacts including, for example, bit line contacts coupled to bit lines and drain selection gate contacts coupled to drain selection gates. The array interconnection layer 110 may further include one or more first interconnection conductor layers 112. The first interconnection conductor layers 112 may include a plurality of connection lines, for example, bit lines and word line connection lines coupled to word lines. The material of the first interconnection conductor layers 112 and the contacts may be a conductive material, for example, a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable material. The material of the first interlayer insulating layer 111 is an insulating material, for example, a combination of one or more of silicon oxide, silicon nitride, high dielectric constant insulating materials, or other suitable material.

[0149] The peripheral circuit 130 is configured to control and sense the array device. The peripheral circuit 130 may be any suitable digital, analog, and / or hybrid signal control and sensing circuit configured to support the operation (or operation) of the array device, including, but not limited to, a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit may further comprise any other circuitry suitable for advanced logic processes, including logic circuits (e.g., processors and programmable logic units (PLDs)) or memory circuits (e.g., static random access memory (SRAM)).

[0150] The peripheral interconnection layer 120 is coupled to the peripheral circuit 130 to achieve the transmission of electrical signals between the peripheral circuit 130 and the peripheral interconnection layer 120. The peripheral interconnection layer 120 may comprise one or more second interlayer insulating layers 121 and may further comprise one or more second interconnection conductor layers 122. Different second interconnection conductor layers 122 may be coupled via contacts. The materials of the second interconnection conductor layers 122 and the contacts may be conductive materials, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The material of the second interlayer insulating layer 121 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, high dielectric constant insulating materials, or other suitable materials.

[0151] The peripheral interconnect layer 120 may be coupled to the array interconnect layer 110 so that the memory cell string 4 can be coupled to the peripheral circuit. In one example, the peripheral interconnect layer 120 is coupled to the array interconnect layer 110 so that the peripheral circuit 130 is coupled to the memory cell string 4, enabling the transmission of electrical signals between the peripheral circuit 130 and the memory cell string 4. An adhesive interface may be provided between the peripheral interconnect layer 120 and the array interconnect layer 110, and the peripheral interconnect layer 120 and the array interconnect layer 110 may be bonded and coupled to each other via the adhesive interface.

[0152] Figure 35 is a block diagram of a memory system 10 in one example. Figure 36 is a block diagram of a memory system 10 in another example. As shown in Figures 35 and 36, some examples of the present disclosure further provide a memory system 10. The memory system 10 comprises a controller 300 and a three-dimensional memory 100 in the above example, the controller 300 being coupled to the three-dimensional memory 100 to control the three-dimensional memory 100 to store data.

[0153] The memory system 10 may be integrated into various types of storage devices, for example, and may be contained in the same package (such as a universal flash memory (UFS) package or an embedded multimedia card (eMMC) package). That is, the memory system 10 may be applied to and packaged in different types of electronic products such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices that have internal storage devices.

[0154] In some examples, referring to Figure 35, the memory system 10 may include a controller 300 and a three-dimensional memory 100, which may be integrated into a memory card.

[0155] The memory card includes one of the following: PC (PCMCIA, Personal Computer Memory Card International Association) card, CompactFlash® (CF) card, SmartMedia (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD), and UFS.

[0156] In some other examples, referring to Figure 36, the memory system 10 comprises a controller 300 and multiple three-dimensional memories 100, and is integrated into a solid-state drive (SSD).

[0157] Some examples of this disclosure further provide electronic devices. An electronic device may be any one of the following: a mobile communication terminal, a tablet, a game console, a digital multimedia player, or a smart wearable device (such as a smartwatch, smart bracelet, or smart glasses).

[0158] The electronic device may include the memory system 10 described above, and may further include at least one of a central processing unit (CPU) and a cache.

[0159] The beneficial effects that can be achieved by the three-dimensional memory 100, memory system 10, and method of manufacturing the electronic device provided by the above examples of this disclosure can be referenced to the beneficial effects of the three-dimensional memory 100 described above, and it will be understood that this will not be repeated here.

[0160] The above description is merely an exemplary implementation of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modifications or substitutions that are readily understood by those skilled in the art within the technical scope disclosed herein shall be included within the scope of protection of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be defined by the scope of protection of the claims.

Claims

1. A memory device, Two array regions and a stepped region arranged along a first direction, wherein the stepped region is located between the two array regions and connected to the two array regions, A laminated structure comprising gate layers and first dielectric layers arranged alternately along a second direction intersecting the first direction, wherein the laminated structure includes a stepped structure in the stepped region, and the stepped structure includes a plurality of steps, An isolated structure extending through the laminated structure along the second direction, including a first insulating layer, A second dielectric layer is disposed on the first of the aforementioned plurality of stages, The stepped structure and the third dielectric layer covering the second dielectric layer, A connecting pillar extending along the second direction through the third dielectric layer and the second dielectric layer, and in contact with the first gate layer of the gate layers in the first stage, Includes, The material of the first insulating layer is different from the material of the second dielectric layer. Memory device.

2. The aforementioned plurality of stages include a second stage adjacent to the first stage, The second dielectric layer covering the first and second stages is continuous. The memory device according to claim 1.

3. The second dielectric layer comprises an insulating material. The etching selectivity ratio of the second dielectric layer is different from that of the third dielectric layer. The memory device according to claim 1.

4. The material of the third dielectric layer contains silicon oxide, and the material of the second dielectric layer contains silicon nitride. The memory device according to claim 1.

5. The size of the second dielectric layer in the second direction is larger than the size of the first gate layer in the second direction. The memory device according to claim 1.

6. The separation structure further includes a packed layer, and the first insulating layer is located between the packed layer and the laminated structure in a first direction. The memory device according to claim 1.

7. The material of the aforementioned filling layer includes polysilicon. The memory device according to claim 6.

8. The separation structure further includes a second insulating layer between the first insulating layer and the filling layer in the first direction. The memory device according to claim 6.

9. The material of the first insulating layer is different from the material of the second insulating layer. The memory device according to claim 8.

10. Further including peripheral devices including peripheral circuits, The peripheral device is joined to the laminated structure in the second direction. The memory device according to claim 1.

11. A memory device, A laminated structure comprising gate layers and first dielectric layers arranged alternately along a first direction, wherein the laminated structure includes a stepped structure, and the stepped structure includes a plurality of steps, An isolation structure extending through the laminated structure along the first direction and including a first insulating layer, A second dielectric layer is disposed on the first of the aforementioned plurality of stages, The stepped structure and the third dielectric layer covering the second dielectric layer, A connecting pillar extending along the first direction through the third dielectric layer and the second dielectric layer, and in contact with the first gate layer of the gate layers in the first stage, A first semiconductor structure comprising a first insulating layer, wherein the material of the first insulating layer is different from the material of the second dielectric layer, A second semiconductor structure including peripheral circuits, Includes, The second semiconductor structure is joined to the first semiconductor structure in the first direction. Memory device.

12. The first semiconductor structure includes two array regions and a layer region arranged along a second direction intersecting the first direction, The aforementioned stepped region is located between the two array regions and is connected to the two array regions, and the stepped structure is located within the stepped region. The memory device according to claim 11.

13. The aforementioned plurality of stages include a second stage adjacent to the first stage, The second dielectric layer covering the first and second stages is continuous. The memory device according to claim 12.

14. The second dielectric layer comprises an insulating material, and the etching selectivity of the second dielectric layer is different from that of the third dielectric layer. The memory device according to claim 12.

15. The material of the third dielectric layer contains silicon oxide, and the material of the second dielectric layer contains silicon nitride. The memory device according to claim 12.

16. The size of the second dielectric layer in the first direction is larger than the size of the first gate layer in the first direction. The memory device according to claim 12.

17. The separation structure further includes a packed layer, and the first insulating layer is located between the packed layer and the laminated structure in the second direction. The memory device according to claim 12.

18. The material of the aforementioned filling layer includes polysilicon. The memory device according to claim 17.

19. The separation structure further includes a second insulating layer between the first insulating layer and the filling layer in the second direction. The memory device according to claim 17.

20. The material of the first insulating layer is different from the material of the second insulating layer. The memory device according to claim 19.

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