Method of forming wiring
A two-step exposure process with multilayer resist layers addresses the challenge of forming accurate resist patterns with high aspect ratios, enhancing pattern accuracy and aspect ratio in wiring formation.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SHANGHAI AVIC OPTO ELECTRONICS CO LTD
- Filing Date
- 2024-12-26
- Publication Date
- 2026-07-08
AI Technical Summary
Existing methods for forming resist patterns with high aspect ratios face challenges in achieving accurate line and space dimensions due to difficulties in exposing the resist layer thickness, leading to unevenness and increased steps, which affect pattern accuracy.
A method involving two exposure steps with multilayer resist layers, where each layer is exposed and developed to form a resist pattern, followed by plating to create wiring, allowing for high pattern accuracy and aspect ratio.
The method enables easy formation of wiring with high pattern accuracy and aspect ratio by ensuring exposure light reaches deeper layers, reducing the number of steps and improving resist pattern formation.
Smart Images
Figure 2026113858000001_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for forming wiring.
Background Art
[0002] A method of forming wiring is known in which a resist pattern is formed on a substrate and the substrate on which the resist pattern is formed is subjected to a plating process. In this forming method, after forming a resist layer on the substrate, the resist layer is exposed using a mask, and a resist pattern is formed by developing the exposed resist layer.
[0003] With the increase in the fineness of wiring patterns, when forming a resist pattern with a high aspect ratio by the above forming method, it is necessary to increase the thickness of the resist layer. On the other hand, when the thickness of the resist layer is increased, it becomes difficult for the exposure light to reach the deep part of the resist layer, so there is a risk that the line and space (L / S) of the resist pattern will not be formed in the desired dimensions. That is, there is a risk that the pattern accuracy (L / S accuracy) of the resist pattern will decrease.
[0004] In Patent Document 1, a printed wiring board having a circuit with a high aspect ratio is manufactured by repeating the formation, exposure, and development of a resist layer. Specifically, a resist patterning step of exposing and developing a circuit pattern on a resist laminated on a base substrate and covering a non-circuit forming portion with a crosslinked resist, and a resist lamination step of exposing and developing the same circuit pattern as the resist patterning step on the resist laminated again and laminating a crosslinked resist on the non-circuit forming portion are performed to form a high-layer resist on the base substrate. Then, a conductor is deposited and laminated on the uncovered portion of the high-layer resist by electrolytic or electroless plating to form a circuit.
Prior Art Documents
Patent Documents
[0005]
Patent Document 1
[0006] The manufacturing method described in Patent Document 1 involves developing the resist layer after each exposure, resulting in a large number of steps. Furthermore, since another resist layer is formed on top of the developed resist layer, unevenness (thickness variations, exposure variations) is likely to occur in the upper resist layer. Moreover, although Patent Document 1 forms a resist pattern with a high aspect ratio and a circuit with a large circuit height, Patent Document 1 does not disclose or suggest anything about the pattern accuracy of the resist pattern or the accuracy of the circuit pattern.
[0007] This disclosure is made in view of the above circumstances and aims to provide a wiring formation method that can easily form wiring with high pattern accuracy and a high aspect ratio. [Means for solving the problem]
[0008] The method for forming wiring in this disclosure is: A first exposure step involves forming a first resist layer on the main surface of a substrate and exposing the first resist layer to a predetermined wiring pattern, A second exposure step involves forming a second resist layer on the exposed first resist layer and exposing the second resist layer to the predetermined wiring pattern, A developing step to form a resist pattern according to the predetermined wiring pattern by developing the exposed first resist layer and the exposed second resist layer, The process includes a wiring formation step of forming wiring by plating based on the resist pattern. [Effects of the Invention]
[0009] According to this disclosure, a resist pattern is formed by developing the exposed first resist layer and the exposed multilayer resist layer, making it possible to easily form wiring with high pattern accuracy and a high aspect ratio. [Brief explanation of the drawing]
[0010] [Figure 1] It is a cross-sectional view showing a wiring board according to Embodiment 1. [Figure 2] It is a flowchart showing a method for forming wiring according to Embodiment 1. [Figure 3] It is a cross-sectional view showing a seed layer according to Embodiment 1. [Figure 4] It is a cross-sectional view showing a first resist layer according to Embodiment 1. [Figure 5] It is a schematic diagram for explaining a first exposure process according to Embodiment 1. [Figure 6] It is a cross-sectional view showing a second resist layer according to Embodiment 1. [Figure 7] It is a schematic diagram for explaining a second exposure process according to Embodiment 1. [Figure 8] It is a cross-sectional view showing a resist pattern according to Embodiment 1. [Figure 9] It is a schematic diagram for explaining a wiring formation process according to Embodiment 1. [Figure 10] It is a schematic diagram for explaining a peeling process according to Embodiment 1. [Figure 11] It is a flowchart showing a method for forming wiring according to Embodiment 2. [Figure 12] It is a cross-sectional view showing a resist pattern according to Embodiment 2. [Figure 13] It is a plan view showing a wiring board and a semiconductor according to a modification example. [Figure 14] It is a cross-sectional view of the wiring board and the semiconductor chip shown in FIG. 13, viewed along line A-A. [Figure 15] It is a photograph showing a laminated resist layer according to an example. [Figure 16] It is a photograph showing a resist layer according to a comparative example. [Figure 17] It is a photograph showing wiring according to an example.
Modes for Carrying Out the Invention
[0011] Hereinafter, a method for forming a wiring according to an embodiment will be described with reference to the drawings.
[0012] <Embodiment 1> Referring to FIGS. 1 to 10, a method for forming a wiring 10 according to this embodiment will be described. The method for forming the wiring 10 according to this embodiment is used, for example, for forming wirings such as data lines and gate lines in an active matrix type display device that connect to a driver IC (Integrated Circuit).
[0013] In this embodiment, the method for forming the wiring 10 will be described by taking a wiring substrate 100 as an example. As shown in FIG. 1, the wiring substrate 100 has a wiring 10, a base material 20, and a seed layer 30. In the wiring substrate 100, the seed layer 30 is formed on the main surface 20a of the base material 20, and the wiring 10 is formed on the main surface 20a of the base material 20 via the seed layer 30.
[0014] FIG. 2 is a flowchart showing a method for forming the wiring 10 (a method for manufacturing the wiring substrate 100). The method for forming the wiring 10 includes a preparation step (step S110) of preparing the base material 20 on which the seed layer 30 is formed on the main surface 20a, a first exposure step (step S120) of forming a first resist layer 40 on the main surface 20a of the base material 20 and exposing the first resist layer 40, a second exposure step (step S130) of forming a second resist layer 50 on the exposed first resist layer 40a and exposing the second resist layer 50, and a development step (step S140) of developing the exposed first resist layer 40a and the exposed second resist layer 50a. The method for forming the wiring 10 further includes a wiring formation step (step S150) of forming the wiring 10 by plating based on the resist pattern RP formed in the development step (step S140), a peeling step (step S160) of peeling the laminated resist layer 60, and a removal step (step S170) of removing the excess seed layer 30.
[0015] In the preparation step (step S110), a substrate 20 is prepared, on which a seed layer 30 is formed on the main surface 20a, as shown in Figure 3. The substrate 20 is, for example, a glass substrate. The seed layer 30 is formed from a conductive metal such as copper (Cu), nickel (Ni), or titanium (Ti). The seed layer 30 is provided on the main surface 20a of the substrate 20, for example, by sputtering. The thickness of the seed layer 30 is, for example, 0.05 μm to 0.5 μm.
[0016] Returning to Figure 2, in the first exposure step (step S120), first, as shown in Figure 4, a first resist layer 40 is formed on the main surface 20a of the substrate 20. The first resist layer 40 is formed from, for example, a positive-type resist. Specifically, the first resist layer 40 is formed on the seed layer 30 (i.e., on the main surface 20a of the substrate 20) by a spin coating method, slit coating method, or the like. The thickness of the first resist layer 40 is, for example, 5 μm.
[0017] Next, after pre-baking the first resist layer 40, as shown in Figure 5, the first resist layer 40 is exposed to a predetermined wiring pattern LP using a mask M. This forms the exposed first resist layer 40a. The wavelength of the exposure light ExL used to expose the first resist layer 40 (i.e., the photosensitive wavelength of the first resist layer 40) is preferably 300 nm or more. The exposure light ExL is g-line (436 nm), h-line (405 nm), i-line (365 nm), etc. The line and space (L / S) of the wiring pattern LP is, for example, 5 μm / 5 μm.
[0018] Returning to Figure 2, in the second exposure step (step S130), first, as shown in Figure 6, a second resist layer 50 is formed on the exposed first resist layer 40a. The second resist layer 50 is formed from a positive-type resist. In this embodiment, the first resist layer 40 and the second resist layer 50 are formed from the same resist material.
[0019] The second resist layer 50 is formed on the exposed first resist layer 40a by a method such as spin coating or slit coating. The thickness of the second resist layer 50 is, for example, 5 μm.
[0020] Next, after pre-baking the second resist layer 50, the second resist layer 50 is exposed to the wiring pattern LP using a mask M, as shown in Figure 7. This forms the exposed, stacked second resist layer 50a. In this embodiment, the mask M is the same mask used in the first exposure step (step S120). The mask M is aligned such that, when the substrate 20 is viewed from above, the wiring pattern LP in this step is formed in the same position as the wiring pattern LP in the first exposure step (step S120).
[0021] Furthermore, the wavelength of the exposure light ExL used to expose the second resist layer 50 is the same as the wavelength of the exposure light ExL used in the first exposure step (step S120). Exposure amount (mJ / cm²) used to expose the second resist layer 50 2 ) is the exposure amount (mJ / cm²) used to expose the first resist layer 40. 2 It is preferable that it is larger than ). The focal position is adjusted individually in the first exposure step (step S120) and the second exposure step (step S130) by, for example, the autofocus mechanism of the exposure machine.
[0022] Returning to Figure 2, in the development step (step S140), the exposed first resist layer 40a and the exposed second resist layer 50a are developed with a developer to form a resist pattern RP corresponding to the wiring pattern LP. As shown in Figure 8, the laminated resist layer 60 consisting of the exposed first resist layer 40a and the exposed second resist layer 50a forms a resist pattern RP corresponding to the wiring pattern LP on the main surface 20a of the substrate 20.
[0023] In this embodiment, the resist pattern RP is formed by two layers (multilayer resist layer 60) consisting of a first resist layer 40 and a second resist layer 50. This allows for a higher height of the resist pattern RP and a higher aspect ratio (the ratio of the spacing between the multilayer resist layers 60 to the height of the multilayer resist layers 60) for forming the wiring 10 of the resist pattern RP (multilayer resist layer 60) (in this embodiment, the height is 10 μm and the aspect ratio is 1:2). Furthermore, since the first resist layer 40 and the second resist layer 50 are exposed individually, the exposure light ExL reaches the deeper parts of the first resist layer 40 and the second resist layer 50, improving pattern accuracy (i.e., L / S accuracy). In other words, a resist pattern RP with high pattern accuracy can be formed. Moreover, since the exposed first resist layer 40a and the exposed second resist layer 50a are developed at the same time, the number of steps required to form the resist pattern RP can be reduced, and the resist pattern RP can be easily formed.
[0024] In this embodiment, the first resist layer 40 and the second resist layer 50 are exposed using g-lines, h-lines, i-lines, etc. Therefore, a resist pattern RP with a high aspect ratio for forming the wiring 10 can be formed using a conventional exposure machine and resist material.
[0025] Returning to Figure 2, in the wiring formation process (step S150), wiring 10 is formed on the main surface 20a of the substrate 20 by known electroplating based on the resist pattern RP. Specifically, by passing an electric current through the seed layer 30 in the plating bath, a conductor (for example, copper) is deposited on the seed layer 30. As a result, as shown in Figure 9, wiring 10 is formed in the portion of the seed layer 30 that is not covered by the multilayer resist layer 60.
[0026] In this embodiment, the aspect ratio for forming the wiring 10 of the resist pattern RP can be increased, thus increasing the aspect ratio of the wiring 10 formed by plating based on the resist pattern RP. Furthermore, since a resist pattern RP with high pattern accuracy can be formed, wiring 10 with high pattern accuracy (L / S accuracy) can be formed.
[0027] Returning to Figure 2, in the peeling step (step S160), the laminated resist layer 60 is peeled off from the seed layer 30 using a peeling solution. As a result, as shown in Figure 10, the laminated resist layer 60 is removed from the seed layer 30, and the seed layer 30 that was located beneath the laminated resist layer 60 is exposed.
[0028] Returning to Figure 2, in the removal process (step S170), the exposed excess seed layer 30 is removed from the main surface 20a of the substrate 20 by etching. As a result, the wiring 10 is formed on the main surface 20a of the substrate 20, and the wiring board 100 (Figure 1) is manufactured.
[0029] As described above, the method for forming the wiring 10 allows for the easy formation of wiring 10 with high pattern accuracy and a high aspect ratio.
[0030] <Embodiment 2> In Embodiment 1, one second resist layer 50 (an exposed second resist layer 50a) is laminated on top of an exposed first resist layer 40a. Multiple second resist layers 50 may be laminated on top of the exposed first resist layer 40a.
[0031] Figure 11 is a flowchart of the method for forming the wiring 10 (manufacturing method for the wiring substrate 100) according to this embodiment. The method for forming the wiring 10 according to this embodiment includes a preparation step (step S110), a first exposure step (step S120), a second exposure step (step S130), a thickness determination step (step S135), and a development step (step S140). Furthermore, the method for forming the wiring 10 according to this embodiment includes a wiring formation step (step S150), a peeling step (step S160), and an etching step (step S170).
[0032] The preparation step (step S110), first exposure step (step S120), wiring formation step (step S150), peeling step (step S160), and etching step (step S170) of this embodiment are the same as in Embodiment 1. Here, the second exposure step (step S130), discrimination step (step S135), and development step (step S140) of this embodiment will be described.
[0033] In this embodiment, the second exposure step (step S130) is repeated until the sum of the thickness of the exposed first resist layer 40a and the thickness of the exposed second resist layer 50a reaches a predetermined value (desired thickness).
[0034] In the first second exposure step (step S130), similar to the second exposure step (step S130) of Embodiment 1, the first second resist layer 50 is formed on the exposed first resist layer 40a, the first second resist layer 50 is pre-baked, and then the first second resist layer 50 is exposed. This forms the first exposed second resist layer 50a.
[0035] In the determination step (step S135), the sum of the thickness of the exposed first resist layer 40a and the thickness of the exposed second resist layer 50a is determined. If the sum of the thicknesses of the exposed first resist layer 40a and the exposed second resist layer 50a is less than a predetermined value, it is determined that the sum of the thicknesses of the exposed first resist layer 40a and the exposed second resist layer 50a has not reached the predetermined value (step S135; NO). If it is determined that the predetermined value has not been reached, the method for forming the wiring 10 of this embodiment returns to the second exposure step (step S130).
[0036] In the second exposure step (step S130) from the second exposure onwards, the second resist layer 50 is formed and exposed on top of the exposed first resist layer 40a on which the exposed second resist layer 50a is formed. Specifically, the second resist layer 50 is formed on top of the exposed second resist layer 50a, and the formed second resist layer 50 is exposed. As a result, multiple exposed second resist layers 50a are formed on top of the exposed first resist layer 40a.
[0037] The second resist layer 50 formed in the second exposure step (step S130) from the second time onward is formed from the same resist material as the first second resist layer 50. Furthermore, the mask M used in the second exposure step (step S130) from the second time onward is the same as the mask M used in the first exposure step (step S120). In this embodiment as well, it is preferable that the exposure amount for the second resist layer 50 is greater than the exposure amount for the first resist layer 40.
[0038] In the determination step (step S135), if the sum of the thickness of the exposed first resist layer 40a and the thickness of the exposed second resist layer 50a is a predetermined value, it is determined that the sum of the thickness of the exposed first resist layer 40a and the thickness of the exposed second resist layer 50a has reached the predetermined value (step S135; YES). Once it is determined that the predetermined value has been reached, the method for forming the wiring 10 of this embodiment proceeds to the development step (step S140).
[0039] In the development step (step S140), the exposed first resist layer 40a and the exposed second resist layer 50a are developed with a developer solution. As a result, as shown in Figure 12, a resist pattern RP corresponding to the wiring pattern LP is formed on the main surface 20a of the substrate 20 by the multilayer resist layer 60. Figure 12 shows an example of a resist pattern RP (multilayer resist layer 60) after the second exposure step (step S130) has been performed twice.
[0040] In this embodiment, a resist pattern RP is formed by a laminated resist layer 60 consisting of a first resist layer 40 and a plurality of second resist layers 50, so that the height of the resist pattern RP and the aspect ratio for forming the wiring 10 can be increased. For example, the aspect ratio for forming the wiring 10 of the resist pattern RP can be made 1:2 or greater.
[0041] Since the aspect ratio for forming the wiring 10 of the resist pattern RP can be increased, the aspect ratio of the wiring 10 can also be increased. In addition, since the exposed first resist layer 40a and the multiple exposed second resist layers 50 are developed at the same time, the number of steps required to form the wiring 10 can be reduced. Furthermore, since the first resist layer 40 and the multiple second resist layers 50 are exposed individually, the exposure light ExL reaches the deeper parts of the first resist layer 40 and the second resist layers 50, respectively. This makes it easy to form wiring 10 with high pattern accuracy and a high aspect ratio.
[0042] As described above, the method for forming the wiring 10 of this embodiment also allows for the easy formation of wiring 10 with high pattern accuracy and a high aspect ratio.
[0043] <Variation> While embodiments have been described above, this disclosure can be modified in various ways without departing from its essence.
[0044] In this embodiment, the first resist layer 40 and the second resist layer 50 are formed from the same resist material. The first resist layer 40 and the second resist layer 50 may be formed from different resist materials. Furthermore, if the second exposure process (step S130) is performed multiple times, a different resist material may be used for each second exposure process (step S130).
[0045] In this embodiment, a positive-type resist is used in the first exposure step (step S120) and the second exposure step (step S130). The resist material used in the first exposure step (step S120) and the second exposure step (step S130) is not limited to a positive-type resist. For example, a negative-type resist may be used in the first exposure step (step S120) and the second exposure step (step S130). Alternatively, a dry film resist may be used in the first exposure step (step S120) and the second exposure step (step S130).
[0046] In this embodiment, the first resist layer 40 and the second resist layer 50 are formed by a spin coating method, a slit coating method, or the like. The first resist layer 40 and the second resist layer 50 may be formed by a known method (for example, a dipping method) depending on the resist material used to form the first resist layer 40 and the second resist layer 50.
[0047] The mask M used in the first exposure step (step S120) and the mask M used in the second exposure step (step S130) may be different from each other.
[0048] In the wiring formation step (step S150) of the embodiment, the wiring 10 is formed by electroplating. In the wiring formation step (step S150), the wiring 10 can be formed by plating.
[0049] For example, the wiring 10 may be formed by electroless plating. In this case, the wiring substrate 100 does not need to have a seed layer 30. Also, the substrate 20 prepared in the preparation step (step S110) does not need to have a seed layer 30.
[0050] The substrate 20 is not limited to a glass substrate. The substrate 20 may also be an insulating resin film.
[0051] The method for forming the wiring 10 can also be used in the manufacture of a wiring board 300 for connecting the signal wiring of a semiconductor chip 200 to the outside. In this case, connection wiring 302 for connecting the signal wiring of the semiconductor chip 200 to the wiring 10 of the wiring board 300, connection wiring 304 for connecting the wiring 10 of the wiring board 300 to the outside, etc., are provided on the wiring 10 via an insulating layer 310. The wiring 10 of the wiring board 300 functions as lead-out wiring.
[0052] For example, as shown in Figures 13 and 14, a semiconductor chip 200 having a light-receiving element 210 is mounted on the wiring board 300. The semiconductor chip 200 is mounted on the wiring board 300 with the light-receiving element 210 facing the wiring board 300. Nothing is provided between the light-receiving element 210 of the semiconductor chip 200 and the substrate 20 of the wiring board 300, and an opening 312 is formed. As a result, the substrate 20 of the wiring board 300 can seal the light-receiving element 210 and protect the light-receiving element 210.
[0053] The wiring board 300 has a fan-out structure in which the signal wiring of the semiconductor chip 200 is connected to an external terminal 308 of the wiring board 300 via a terminal (not shown) that connects to the signal wiring of the semiconductor chip 200 and a chip mounting terminal 306 of the wiring board 300.
[0054] The wiring 10 of the wiring board 300 is formed on the substrate 20 by a formation method similar to that of the embodiment. An insulating layer (e.g., a polyimide layer) 310 is formed on the wiring 10 of the wiring board 300, and connecting wires 302 and 304 are formed on the insulating layer 310. The connecting wires 302 and 304 are connected to the wiring 10 through through holes provided in the insulating layer 310.
[0055] The connection wiring 302 connects to the chip mounting terminal 306 formed on the insulating layer 314, and the chip mounting terminal 306 connects to the terminals of the semiconductor chip 200. In addition, the connection wiring 304 connects to the external terminal 308 formed on the insulating layer 314. The external terminal 308 connects to an external device, an external control unit, etc.
[0056] Due to the miniaturization of semiconductors and semiconductor chips 200, the spacing between chip mounting terminals 306 for mounting the semiconductor chip 200 must be narrowed, and the wiring (lead wires) 10 must also be made thinner. When the wiring 10 is made thinner, the resistance of the wiring 10 increases, which may degrade the signal quality. In this disclosure, since wiring 10 with high pattern accuracy and a high aspect ratio can be formed, high-density wiring 10 can be formed while suppressing the increase in the resistance of the wiring 10.
[0057] While preferred embodiments have been described above, this disclosure is not limited to these specific embodiments, and includes the invention described in the claims and its equivalents. [Examples]
[0058] The present invention will be described in more detail by the following examples, but the present invention is not limited to these examples.
[0059] In this embodiment, the wiring 10 was formed using the method for forming the wiring 10 of Embodiment 1 (Figure 2).
[0060] Specifically, in the preparation step (step S110), a substrate (glass substrate) having a seed layer 30 made of copper with a thickness of 0.05 μm to 0.5 μm was prepared.
[0061] In the first exposure step (step S120), a 6.5 μm thick first resist layer 40 (manufactured by Tokyo Ohka Kogyo: PMER P-WG series) was formed on the main surface 20a of the substrate 20 by spin coating and pre-baked at 110°C for 120 seconds. Next, the first resist layer 40 was exposed using a mask M with a wiring pattern LP with an L / S ratio of 5 μm / 5 μm. The exposure light ExL is light containing both g-line and h-line light. Note that the exposure light ExL may be g-line only or h-line only.
[0062] In the second exposure step (step S130), the second resist layer 50 was formed and pre-baked under the same conditions as in the first exposure step (step S120), and then the second resist layer 50 was exposed.
[0063] In the development step (step S140), the exposed first resist layer 40a and the exposed second resist layer 50a were developed with a 2.38% tetramethylammonium hydroxide (TMAH) solution (paddle method, 300 seconds).
[0064] In the wiring formation process (step S150), wiring 10 was formed by electrolytic copper plating using a copper sulfate-based solution. In the stripping process (step S160), the laminated resist layer 60 was stripped from the seed layer 30 using a stripping solution. Furthermore, in the removal process (step S170), the seed layer 30 was removed from the main surface 20a of the substrate 20 by etching.
[0065] Figure 15 shows the laminated resist layer 60 of the resist pattern RP formed in the development process (step S140). Figure 16 shows the resist layer 90 of the resist pattern formed by the formation method of the comparative example. Figure 17 shows the wiring 10 formed in this embodiment. In the formation method of the comparative example, a resist layer with a thickness of 13 μm was formed, and then the formed resist layer was exposed (L / S: 5 μm / 5 μm) and developed to form the resist pattern.
[0066] In this embodiment, the width L1 of the laminated resist layer 60 and the spacing S1 of the laminated resist layer 60 were L1 = 5.2 μm and S1 = 4.9 μm, respectively, and the L / S ratio for this embodiment was 5.2 / 4.9. Also, the height H1 of the laminated resist layer 60 in this embodiment was H1 = 11.5 μm, and the aspect ratio (4.9 / 11.5) for forming the wiring 10 of the laminated resist layer 60 was 1:2.3. On the other hand, in the comparative example, the width L2 of the resist layer and the spacing S2 of the laminated resist layer 60 in the resist pattern were L2 = 4.5 μm and S2 = 5.6 μm, respectively, and the L / S ratio for the comparative example was 4.5 / 5.6. In the comparative example, the height H2 of the resist layer 90 was H2 = 13.7, and the aspect ratio (5.6 / 13.7) for forming the wiring 10 of the resist layer 90 was 1:2.4.
[0067] In this embodiment, a resist pattern RP with high pattern accuracy and a high aspect ratio for forming the wiring 10 could be easily formed. Furthermore, in the laminated resist layer 60 of this embodiment, the boundary between the first resist layer 40 and the second resist layer 50 was not visible (Figure 15), and a good resist pattern RP was formed in this embodiment.
[0068] Furthermore, in this embodiment, as shown in Figure 17, wiring 10 with high pattern accuracy and a high aspect ratio could be easily formed. [Explanation of symbols]
[0069] 10 Wiring, 20 Substrate, 20a Main surface, 30 Seed layer, 40 First resist layer, 40a Exposed first resist layer, 50 Second resist layer, 50a Exposed second resist layer, 60 Multilayer resist layer, 90 Resist layer, 100 Wiring substrate, 200 Semiconductor chip, 210 Photodetector, 300 Wiring substrate, 302,304 Connection wiring, 306 Chip mounting terminals, 308 External terminals, 310,314 Insulation layer, 312 Aperture, M Mask, ExL Exposure light, L1,L2 Width, LP Wiring pattern, H1,H2 Height, RP Resist pattern, S1,S2 Spacing
Claims
1. A first exposure step involves forming a first resist layer on the main surface of a substrate and exposing the first resist layer to a predetermined wiring pattern, A second exposure step involves forming a second resist layer on the exposed first resist layer and exposing the second resist layer to the predetermined wiring pattern, A developing step to form a resist pattern corresponding to the predetermined wiring pattern by developing the exposed first resist layer and the exposed second resist layer, The process includes a wiring formation step of forming wiring by plating based on the resist pattern, Method for forming wiring.
2. The second exposure step is repeated multiple times. A method for forming wiring according to claim 1.
3. In the exposure of the first and second exposure steps, the wavelength of the exposure light is 300 nm or greater. A method for forming wiring according to claim 1 or 2.
4. The aspect ratio of the resist pattern is 1:2 or greater. A method for forming wiring according to claim 1 or 2.