Manufacturing method for epitaxial silicon wafers

By controlling defect sizes and thermal history during epitaxial growth, the method addresses Epi-SF suppression in boron-doped silicon wafers, improving yield and quality by eliminating oxygen precipitates and preventing Epi-SF formation.

JP2026114012APending Publication Date: 2026-07-08GLOBALWAFERS JAPAN

Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
GLOBALWAFERS JAPAN
Filing Date
2024-12-26
Publication Date
2026-07-08

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Abstract

To suppress the generation of epitaxial silicon sintered (Epi-SF) in a method for manufacturing epitaxial silicon wafers using a silicon wafer doped with boron as a dopant. [Solution] The method for manufacturing an epitaxial silicon wafer involves slicing a silicon single crystal grown by doping with boron into a silicon wafer, extracting a sample from the silicon wafer, and measuring the size and density of defects using light scattering, determining that the defect size is 30-35 nm and the density is 1 × 10⁻⁶ 7 pieces / cm 3 A silicon wafer is selected as described below, and the selected silicon wafer is epitaxially grown.
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Description

[Technical Field]

[0001] This invention relates to a method for manufacturing epitaxial silicon wafers. [Background technology]

[0002] Epitaxial silicon wafers for power MOS transistors require extremely low electrical resistivity. To sufficiently lower the electrical resistivity of the silicon crystal substrate, a technique is known in which boron is doped into the molten silicon as a resistivity-reducing dopant during the pulling process of the silicon crystal ingot, which is the material for the wafer.

[0003] A silicon wafer doped with a high concentration of boron has a problem in that when an epitaxial layer of silicon is formed on an excess of vacancies and oxygen, stacking faults (Epi-SF; EPItaxial Stacking Fault) occur from microdefects inherent in a region of the silicon wafer called the R-OSF region toward the silicon epitaxial layer.

[0004] As a method for resolving Epi-SF in boron-doped silicon wafers, for example, Patent Document 1 describes a method that includes cooling the ingot segment below 950°C from the solidification temperature during growth, and reducing the number of groin nuclei that become epitaxial defects in a boron-doped substrate by limiting the dwell time in which a segment of a certain diameter portion of the ingot is in the temperature range of 1150°C to 950°C to less than 160 minutes. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Special Publication No. 2023-548240 [Overview of the project] [Problems that the invention aims to solve]

[0006] Furthermore, the disclosures in the above-mentioned prior art documents are incorporated into this book by reference. The following analysis was conducted by the inventors.

[0007] However, conventional methods have not been able to completely suppress Epi-SF, and there is a need for a method to suppress Epi-SF with higher accuracy. In particular, the method described in Patent Document 1 mentioned above includes cases in which the number of epitaxial defects cannot be completely reduced, and the fact that silicon wafers that are prone to Epi-SF flow and the resulting decrease in yield are recognized as problems.

[0008] It has been revealed that in silicon single crystals with high oxygen and boron concentrations, abnormal precipitates are generated in a region called the R-OSF (Ring Oxidation induced Stacking Fault) region due to the thermal history around 1050°C during crystal growth. Furthermore, experiments by the inventors of this application have revealed that these abnormal precipitates act as nuclei for the generation of Epi-SF.

[0009] In view of the above-mentioned problems, the object of the present invention is to provide a method for manufacturing epitaxial silicon wafers using a silicon wafer doped with boron as a dopant, which contributes to suppressing the generation of epi-SF. [Means for solving the problem]

[0010] To solve the above problems, the present invention provides a method for manufacturing an epitaxial silicon wafer, in which a silicon single crystal grown by doping with boron is sliced ​​into a silicon wafer, and the defect size is 30-35 nm and the density is 1 × 10⁻⁶ 7 pieces / cm 3 The following silicon wafers are epitaxially grown: 30-35 nm in size, with 1 × 10⁶ defects. 7 pieces / cm 3When the following conditions are met, the oxygen precipitates can be eliminated by heat treatment during epitaxial growth, and the generation of Epi-SF can be suppressed.

[0011] Moreover, the measurement in the method for manufacturing an epitaxial silicon wafer of the present invention is performed by extracting a sample from a silicon wafer sliced from the silicon single crystal, and the size of the defects in the extracted sample is 30 to 35 nm, and the density is 1×10 7 pieces / cm 3 or less, and epitaxial growth is performed on a silicon wafer sliced from the same silicon single crystal as the sample. This is because it is not efficient to measure and perform epitaxial growth on all silicon wafers.

[0012] In addition, the method for manufacturing an epitaxial silicon wafer of the present invention makes the thermal history at 1000°C - 900°C 80 minutes or less in the cooling process of crystal growth. By making the thermal history at 1000°C - 900°C 80 minutes or less in the cooling process during crystal growth, a silicon single crystal in which the number of defects with a size of 30 to 35 nm is 1×10 7 pieces / cm 3 or less can be manufactured.

[0013] In addition, the method for manufacturing an epitaxial silicon wafer of the present invention has a boron concentration in the silicon wafer of 1×10 18 atoms / cm 3 ~1×10 20 atoms / cm 3 . The position and width of the R-OSF region vary according to the dopant boron concentration, and the density of oxygen precipitates also varies, generally increasing as the boron concentration increases. Since the method for manufacturing an epitaxial silicon wafer of the present invention assumes the problems caused by abnormal precipitates generated in the R-OSF region, the doping concentration of boron is preferably within the above range.

[0014] In addition, the method for manufacturing an epitaxial silicon wafer of the present invention has an oxygen concentration in the silicon wafer of 1.3×10 18atoms / cm 3 ~2×10 18 atoms / cm 3 The position and width of the R-OSF region vary depending on the oxygen concentration of the silicon wafer, and the density of oxygen deposition also varies, generally increasing as the oxygen concentration increases. Since the method for manufacturing epitaxial silicon wafers of the present invention is based on the premise of problems caused by abnormal precipitates occurring in the R-OSF region, it is preferable to set the oxygen concentration within the aforementioned range.

[0015] Furthermore, the present invention relates to a method for manufacturing an epitaxial silicon wafer in which the silicon wafer is nitrogen-undoped and the silicon wafer includes an OSF region. This is because the present invention relates to a method for manufacturing an epitaxial silicon wafer in which problems caused by abnormal precipitates occurring in the R-OSF region are addressed. [Effects of the Invention]

[0016] According to each aspect of the present invention, a method for manufacturing epitaxial silicon wafers using a silicon wafer doped with boron as a dopant can be provided that contributes to suppressing the generation of epitaxial silicon wafers. [Brief explanation of the drawing]

[0017] [Figure 1] Figure 1 shows the characteristics of the samples in the examples and comparative examples. [Figure 2] Figure 2 shows the surface examination results for each sample after epitaxial growth. [Modes for carrying out the invention]

[0018] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the embodiments described below. In each drawing, the same or corresponding elements are appropriately denoted by the same reference numerals. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from those of reality. Even between drawings, there may be parts where the dimensional relationships and ratios differ from each other.

[0019] The silicon wafer used in the present invention's method for manufacturing epitaxial silicon wafers is a silicon wafer sliced ​​from a silicon single crystal grown by the CZ method. The CZ method involves filling a quartz crucible with polycrystalline silicon, heating and melting it with a heater, immersing a small single crystal as a seed crystal in the surface of the molten silicon, and pulling up a large-diameter crystal rod while rotating the quartz crucible and seed crystal. When a silicon single crystal is produced by the CZ method, oxygen atoms dissolved from the quartz crucible gather together at high temperatures. Therefore, by controlling the temperature of the crucible and the rotation speed of the quartz crucible and seed crystal, the CZ method can produce a raw silicon wafer containing oxygen at a desired concentration.

[0020] Furthermore, the present invention's method for manufacturing epitaxial silicon wafers uses boron-doped silicon wafers. Therefore, boron is added to the molten silicon in the quartz crucible in the CZ method. It should be noted that the present invention's method for manufacturing epitaxial silicon wafers assumes that nitrogen doping is not performed.

[0021] The grown silicon single crystals are sliced ​​into silicon wafers using a wire. For example, silicon wafers sliced ​​from the same silicon single crystal are managed as one lot, or 10 to 400 wafers, preferably 50 to 200 wafers, are managed as one lot. Then, one silicon wafer is taken from each lot, and the size and density of defects are measured radially from the center to the edge at a pitch of 2 to 10 mm using the light scattering method. Defects with a size of 30 to 35 nm are found to be 1 × 10⁻¹⁶.7 pieces / cm 3 If the following results are obtained, proceed to the next process, and if there are 1 x 10 defects in the 30-35 nm range, 7 pieces / cm 3 If the result exceeds the specified limit, the lot will be discarded. The measurement target may be a silicon wafer actually used for epitaxial growth, or a silicon wafer that has been mirror-polished. Considering the yield, it is preferable to take one evaluation wafer as a sample from a lot sliced ​​from a crystal ingot, perform various processing steps, and then subject it to measurement.

[0022] Defects with a size of 30-35nm: 1 x 10 7 pieces / cm 3 The following silicon wafers will be subjected to epitaxial growth. Epitaxial growth involves forming single-crystal silicon on a silicon wafer using chemical vapor deposition (CVD), for example, by using a carrier gas such as hydrogen (H2) and a source gas such as trichlorosilane (SiHCl3). Conventional known epitaxial growth process conditions can be employed.

[0023] Defects in the 30-35 nm size are mainly oxygen precipitates, but defects that appear to be anomalous precipitates in the R-OSF region are of a similar size. These 30-35 nm size defects are 1 × 10⁻¹⁶ 7 pieces / cm 3 In the following cases, it is thought that the oxygen precipitate can be eliminated by heat treatment during epitaxial growth, thereby suppressing the generation of Epi-SF: 1 × 10 7 pieces / cm 3 If the value exceeds this, it is thought that the oxygen precipitate will not disappear but will aggregate and grow during the heat treatment performed during epitaxial growth, leading to the generation of Epi-SF.

[0024] During the cooling process in crystal growth, it is necessary to shorten the thermal history around 1050°C, and in particular, by reducing the thermal history from 1000°C to 900°C to 80 minutes or less, defects of 30-35 nm size can be reduced to 1 × 10⁻¹⁶ 7 pieces / cm 3The following silicon single crystals can be manufactured. When the correlation coefficient between the LPD number after epitaxial growth and four temperature ranges—1050°C-950°C, 1000°C-900°C, 1000°C-950°C, and 950°C-850°C—was examined, the correlation coefficient was largest in the 1000°C-900°C temperature range, indicating that controlling this temperature range is important. Methods for adjusting the thermal history include, for example, increasing the volume of the shield's insulating material to block radiant heat from the molten metal and make it less likely to reach the crystal, and increasing the pulling speed.

[0025] The position and width of the R-OSF region vary depending on the boron and oxygen concentrations of the dopant. The density of oxygen deposition also varies, generally increasing as the boron concentration increases and as the oxygen concentration increases. Furthermore, since the present invention's method for manufacturing epitaxial silicon wafers is based on the premise of problems caused by abnormal deposition in the R-OSF region, it is assumed that the base silicon single crystal includes the OSF region.

[0026] For example, a silicon single crystal containing an OSF region used in the manufacturing method of the epitaxial silicon wafer of the present invention may have a boron concentration of 1 × 10⁻⁶ 18 atoms / cm 3 ~2×10 19 atoms / cm 3 And, 1 × 10 18 atoms / cm 3 ~1.5×10 19 atoms / cm 3 This is preferable because if the ring diameter in the R-OSF region decreases with increasing boron concentration and exceeds the aforementioned range, there is a risk that the ring may close completely.

[0027] (Examples) As examples and comparative examples, seven lots of 200 mm p-type samples were prepared with varying oxygen concentrations, boron concentrations, and thermal histories around 1050°C (see Figure 1). Each sample was sliced, ground, and etched using the method described above, and microdefect measurements were performed. Microdefect measurements were performed at 2 mm pitches, and the density at each measurement location was determined. In the two lots with high oxygen and boron concentrations (Sample 3 and Sample 6), the defect density at 30-35 nm was 1 × 10⁻⁶. 7 pieces / cm 3 The temperature exceeded [a certain value]. During the cooling process of crystal growth for each sample, the thermal history from 1000°C to 900°C exceeded 80 minutes for samples 3 and 6, while it was 80 minutes or less for the other samples. When slice wafers that had not undergone microdefect measurement were processed into mirror wafers using a normal processing procedure and epitaxial growth was performed, the defect density was 1 × 10⁻⁶. 7 pieces / cm 3 Epi-SF occurred in samples 3 and 6, which exceeded the specified limit, while it did not occur in the other samples. Furthermore, the areas where Epi-SF occurred were near the locations where the defect density in the 30-35 nm range was highest. Figure 2 shows the surface inspection results after epitaxial growth for each sample. In Figure 2, what appears as defects are Epi-SF, and it can be seen that the areas where Epi-SF occurred are near the locations where the defect density in the 30-35 nm range was highest.

[0028] Furthermore, the disclosures of the above-mentioned patent documents and other materials cited are incorporated into this document by reference. Within the framework of the full disclosure of the present invention (including the claims), further modifications and adjustments to the embodiments or examples are possible based on the fundamental technical concept. Also, within the framework of the full disclosure of the present invention, various combinations or selections (including partial deletions) of various disclosure elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. In other words, the present invention naturally includes the full disclosure, including the claims, and various modifications and alterations that a person skilled in the art could make in accordance with the technical concept. In particular, with respect to the numerical ranges described in this document, any numerical value or sub-range included within that range should be interpreted as being specifically described, even if not otherwise stated. Furthermore, the disclosures of the above-mentioned cited documents may, if necessary, be used in part or in whole as part of the disclosure of the present invention, in accordance with the spirit of the present invention, and these may also be considered to be included in the disclosures of this application.

Claims

1. A silicon single crystal grown by doping with boron is sliced ​​onto a silicon wafer. The defect size is 30-35 nm, and the density is 1 × 10⁻⁶ 7 pieces / cm 3 A method for manufacturing an epitaxial silicon wafer, comprising epitaxially growing the silicon wafer described below.

2. Samples were extracted from silicon wafers sliced ​​from the aforementioned silicon single crystal, and the size and density of defects were measured using light scattering. The extracted samples showed a defect size of 30-35 nm and a density of 1 × 10⁻¹⁶ nm. 7 pieces / cm 3 The method for manufacturing an epitaxial silicon wafer according to claim 1, wherein a silicon wafer sliced ​​from the same silicon single crystal as the sample is epitaxially grown.

3. The method for manufacturing an epitaxial silicon wafer according to claim 1, wherein the thermal history of 1000°C-900°C during the crystal growth cooling process is 80 minutes or less.

4. The boron concentration in the silicon wafer is 1 × 10 18 atoms / cm 3 ~1 x 10 20 atoms / cm 3 The method for manufacturing an epitaxial silicon wafer according to any one of claims 1 to 3.

5. The oxygen concentration in the silicon wafer is 1.3 × 10 18 atoms / cm 3 ~ 2 × 10 18 atoms / cm 3 The method for manufacturing an epitaxial silicon wafer according to any one of claims 1 to 3, wherein the oxygen concentration in the silicon wafer is 1.3 × 10

6. The method for manufacturing an epitaxial silicon wafer according to any one of claims 1 to 3, wherein the silicon wafer is nitrogen-undoped.

7. A method for manufacturing an epitaxial silicon wafer according to any one of claims 1 to 3, wherein the silicon wafer includes an OSF region.