Multilayer ceramic electronic components and circuit boards

Abstract

This invention provides a thin, multilayer ceramic electronic component in which capacitance reduction is suppressed. [Solution] A multilayer ceramic capacitor 100 comprising a laminate 20 having internal electrodes 22 and a ceramic layer 21, a protective part 30 covering its surface, via conductors 23a, 23b arranged to penetrate the ceramic layer in the lamination direction, one end of which is drawn out to the surface of the protective part and electrically connected to the internal electrodes, and terminal electrodes 40a, 40b on the surface from which the ends of the via conductors are drawn out and electrically connected to each via conductor, wherein the via conductor has a reduced-diameter stretched portion 231 whose dimension in the direction perpendicular to the lamination direction is smaller than the minimum dimension in the internal region 24 of the laminate, which is the region inside the fifth layer of internal electrodes from the protective part side, and an enlarged-diameter portion 232 formed in the protective part where the reduced-diameter stretched portion is located or in the external region 25 of the laminate located between the protective part where the reduced-diameter stretched portion is located and the internal region of the laminate, and whose dimension in the direction perpendicular to the lamination direction is larger than the maximum dimension in the internal region of the laminate.

Description

[Technical Field]

[0001] This invention relates to multilayer ceramic electronic components and circuit boards. [Background technology]

[0002] High-frequency communication systems, such as mobile phones, utilize a wide variety of ceramic electronic components. These ceramic electronic components require miniaturization and thinning, and miniaturization and thinning are being considered for multilayer ceramic capacitors as well.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor that can improve ESL characteristics and packing efficiency while reducing delamination. Patent Document 1 states that by making the through-electrode that penetrates the body of the multilayer ceramic capacitor include a tapered section with a trapezoidal cross-section, the phenomenon of the cover being pressed by external forces can be improved, thereby improving the ESL characteristics. Furthermore, Patent Document 1 states that by adjusting the diameter of the through-electrode, the paste-fillability of the via can be improved, thereby improving the packing efficiency.

[0004] Patent Document 2 discloses a multilayer ceramic capacitor with reduced equivalent series inductance (ESL). Patent Document 2 states that by making the columnar electrode a wave-shaped form including a small diameter section and a large diameter section, and connecting the large diameter section to the internal electrode, the electrical and mechanical connection between the columnar electrode and the internal electrode can be made more reliable. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-13008 [Patent Document 2] Japanese Patent Publication No. 2005-117004 [Overview of the project] [Problems that the invention aims to solve]

[0006] Patent Document 1 describes a through electrode (via conductor) whose diameter monotonically increases from the bottom end to the top end. In a multilayer ceramic capacitor with a via conductor having such a shape, delamination at the interface between the via conductor and the ceramic layer, and at the interface between the via conductor and the internal electrode, and the decrease in capacitance due to the interruption of the connection between the via conductor and the internal electrode caused by the delamination, are suppressed. However, further suppression of delamination and suppression of capacitance decrease are required.

[0007] Furthermore, unlike Patent Document 1, in multilayer ceramic capacitors where the external electrodes (terminal electrodes) are formed on only one of the first or second main surfaces, a problem arises during firing in the manufacturing process: stress caused by the different shrinkage behavior of the via conductor and the terminal electrode can lead to delamination at the interface between the via conductor and the internal electrode, resulting in a disruption of the connection between the two and a decrease in capacitance.

[0008] In the multilayer ceramic capacitor disclosed in Patent Document 2, due to the shape of the columnar electrodes (via conductors), stress concentration is likely to occur at the tip of the large-diameter portion and at the boundary between the large-diameter portion and the small-diameter portion, and the large-diameter portion is prone to deformation or displacement due to the aforementioned stress. Therefore, there is a concern that delamination may occur at the interface between the internal electrode in contact with the large-diameter portion and the ceramic layer, leading to a decrease in capacitance.

[0009] The present invention was made to solve the above problems and aims to provide a thin multilayer ceramic electronic component with suppressed capacitance reduction, and a circuit board on which the multilayer ceramic capacitor is mounted. [Means for solving the problem]

[0010] The inventors conducted various studies to solve the aforementioned problems and found that the above objective can be achieved in a multilayer ceramic electronic component in which internal electrodes are electrically connected via via conductors, by providing the via conductor with a reduced-diameter extended portion that extends to the surface of the protective portion and has a smaller dimension in the direction perpendicular to the stacking direction than the internal region of the stack, and an enlarged-diameter portion that is positioned closer to the stack than the reduced-diameter extended portion and has a larger dimension in the direction perpendicular to the stacking direction than the internal region of the stack, thereby completing the present invention.

[0011] In other words, the first aspect of the present invention for solving the above problem is a laminate having a plurality of internal electrodes facing each other in the stacking direction and a ceramic layer disposed between the plurality of internal electrodes, a protective portion covering the surface of the laminate, and a rectangular parallelepiped body having a plurality of via conductors disposed through the ceramic layer in the stacking direction of the laminate, with at least one end drawn out to the surface of the protective portion and electrically connected to the internal electrodes, and at least one of the surfaces forming the surface of the body, disposed on the surface from which the ends of the via conductors are drawn out and electrically connected to at least one of the plurality of via conductors. The multilayer ceramic electronic component comprises multiple terminal electrodes, wherein the via conductor extends through the protective portion to the surface of the protective portion, and has a reduced-diameter stretched portion whose dimension in the direction perpendicular to the stacking direction of the laminate is smaller than the minimum dimension obtained in the internal region of the laminate, which is the region inside the fifth internal electrode counted from the protective portion side of the laminate, and an enlarged-diameter portion formed in the protective portion where the reduced-diameter stretched portion is located, or in the external region of the laminate located between the protective portion where the reduced-diameter stretched portion is located and the internal region of the laminate, and whose dimension in the direction perpendicular to the stacking direction of the laminate is larger than the maximum dimension obtained in the internal region of the laminate.

[0012] Furthermore, a second aspect of the present invention for solving the aforementioned problems is a circuit board on which the multilayer ceramic electronic component relating to the first aspect is mounted. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor in which the decrease in capacitance is suppressed, and a circuit board on which the multilayer ceramic capacitor is mounted. [Brief explanation of the drawing]

[0014] [Figure 1] This is a schematic diagram (perspective view) showing the structure of a multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 2] This is the AA section view (LT section view) in Figure 1. [Figure 3] This figure illustrates the procedure for determining whether a via conductor has a reduced-diameter stretched portion and a widened-diameter portion, as well as the procedure for determining the minimum dimension of the reduced-diameter stretched portion in the direction perpendicular to the lamination direction of the laminate, and the maximum dimension of the widened-diameter portion in the direction perpendicular to the lamination direction of the laminate. [Figure 4] This diagram illustrates the procedure for determining whether the enlarged diameter portion and the end located within the cover portion of a via conductor form a flange, the procedure for determining the dimensions of each part of the via conductor, and the procedure for determining whether the dimensions of the via conductor in the direction perpendicular to the stacking direction monotonically decrease within the internal region of the stack. [Figure 5] This diagram illustrates the procedure for determining the presence of free metal elements near the diameter-reduced and stretched portion within the cover. [Figure 6] This is a schematic diagram (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor equipped with via conductors that have cavities formed at their ends, located within the protective section (cover section). [Figure 7] This diagram illustrates the procedure for determining the dimensions of the cavity formed at the end located within the cover portion of a via conductor. [Figure 8] This is a schematic diagram (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor equipped with via conductors that have a bulging shape in the center of the end located within the cover. [Figure 9a]This is a schematic diagram (LT cross-sectional view) of a multilayer ceramic capacitor in which a via conductor is formed, in which the dimension perpendicular to the stacking direction of the laminate in the reduced-diameter stretched portion decreases as it approaches the surface of the cover portion, and the dimension perpendicular to the stacking direction of the laminate in the via conductor gradually increases from the internal region of the laminate towards the reduced-diameter stretched portion. [Figure 9b] This is a schematic diagram (LT cross-sectional view) of a multilayer ceramic capacitor that includes a via conductor in which the dimension perpendicular to the stacking direction of the laminate gradually increases from the internal region of the laminate towards the reduced-diameter extended region, thereby forming an enlarged-diameter portion. [Figure 10] This is a schematic diagram (LT cross-sectional view) showing the structure of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 11] This is a schematic diagram (perspective view) showing the structure of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Modes for carrying out the invention]

[0015] The structure and effects of the present invention will be explained below, along with the technical concepts, with reference to the drawings. However, the mechanism of action is based on assumptions, and its accuracy does not limit the present invention.

[0016] [Multilayer ceramic electronic components] <First Embodiment> Figures 1 and 2 show a multilayer ceramic capacitor, which is an embodiment of a multilayer ceramic electronic component according to the first aspect of the present invention, as a first embodiment. The multilayer ceramic capacitor 100 according to the first embodiment has a rectangular parallelepiped shape and has one pair of faces that are orthogonal to each of three mutually orthogonal axes, namely the L-axis (length direction), the W-axis (width direction), and the T-axis (height direction). The rectangular parallelepiped is not limited to a mathematically defined rectangular parallelepiped, but any shape that is recognized as a rectangular parallelepiped when the overall shape is observed is acceptable. For this reason, shapes with slightly rounded edges or corners, slightly curved edges, and surfaces with small curvature also fall under the category of rectangular parallelepipeds in this disclosure. The dimensions of the ceramic capacitor 100 in the length (L) direction, width (W) direction, and height (T) direction can each take on any independent value.

[0017] Examples of dimensions for a multilayer ceramic capacitor 100 include a length of 200 μm or more and 2000 μm or less in the L direction, a length of 100 μm or more and 2000 μm or less in the W direction, and a length of 30 μm or more and 220 μm or less in the T direction, with a W / L ratio of 0.3 or more and 1.0 or less. Preferably, the dimensions are such that the length of the L direction is 400 μm or more and 1200 μm or less, the length of the W direction is 400 μm or more and 1200 μm or less, and the length of the T direction is 40 μm or more and 150 μm or less, with a W / L ratio of 0.4 or more and 1.0 or less. A T direction length of 100 μm or less is more preferable because it is less subject to design constraints on the circuit board on which it is mounted.

[0018] The multilayer ceramic capacitor 100 according to the first embodiment comprises a laminate 20 having a plurality of internal electrodes 22 mainly composed of metal, which face each other in the stacking direction (T direction), and a ceramic layer 21 disposed between the plurality of internal electrodes 22, and a base body 10 having a protective part 30 that covers the surface of the laminate 20. The internal electrodes 22 include an internal electrode 22a of one polarity that is electrically connected to each other, and an internal electrode 22b of a different polarity that is electrically connected to each other.

[0019] A protective portion 30 is positioned on the surface of the base body 10, covering the surface of the laminated body 20. The protective portion 30 includes a cover portion 31 positioned on a plane perpendicular to the T direction, and margin portions 32 positioned on a plane perpendicular to the W direction and a plane perpendicular to the L direction, respectively.

[0020] The base body 10 is arranged to penetrate the ceramic layer 21 in the stacking direction of the laminate 20, with at least one end extended to the surface of the protective part 30 (cover part 31), and has a plurality of via conductors 23 electrically connected to the internal electrode 22. The via conductors 23 include via conductors 23a electrically connected to the internal electrode 22a and via conductors 23b electrically connected to the internal electrode 22b. Although the multilayer ceramic capacitor 100 shown in Figures 1 and 2 has two via conductors 23, the number of via conductors in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0021] The via conductors 23 (23a, 23b) extend through the protective portion 30 (cover portion 31) to the surface of the protective portion 30, and have a reduced-diameter stretched portion 231 whose dimension in the direction perpendicular to the lamination direction of the laminate 20 is smaller than the minimum dimension obtained in the laminate internal region 24, which is the region inside the fifth layer of internal electrodes 22 (22a, 22b) counted from the cover portion 31 side of the laminate 20. In addition, the via conductors 23 (23a, 23b) are formed in the cover portion 31 where the reduced-diameter stretched portion 231 is located, or in the laminate external region 25 located between the cover portion 31 where the reduced-diameter stretched portion 231 is located and the laminate internal region 24, and have an enlarged-diameter portion 232 whose dimension in the direction perpendicular to the lamination direction of the laminate 20 is larger than the maximum dimension obtained in the laminate internal region 24. This suppresses delamination at the interface between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b), thereby suppressing a decrease in the capacitance of the multilayer ceramic capacitor 100. This is presumed to be due to the following two points. (1) The presence of the diameter-reduced and stretched portion 231 reduces the contact area with the terminal electrodes 40 (40a, 40b) described later, thereby reducing the force applied from the terminal electrodes 40 (40a, 40b) to the via conductors 23 (23a, 23b) in the stacking direction. Examples of such forces include those caused by differences in expansion and contraction behavior due to temperature changes during firing during manufacturing and soldering during circuit board mounting, as well as those caused by the bending deformation of the circuit board after circuit board mounting. (2) The enlarged diameter portion 232 obstructs the relative movement of the via conductors 23 (23a, 23b) in the stacking direction relative to the ceramic layer 21, the internal electrodes 22 (22a, 22b), and the protective portion 30, thereby suppressing delamination at the interface between the internal electrodes 22 (22a, 22b) and the via conductors 23 (23a, 23b). Details regarding the shape and structure of the via conductors 23 (23a, 23b) will be described later.

[0022] The multilayer ceramic capacitor 100 according to the first embodiment includes a plurality of terminal electrodes 40, which are arranged on at least one of the surfaces forming the surface of the base body 10, on the surface from which the ends of the via conductors 23 (23a, 23b) are drawn out, and which are electrically connected to at least one of the via conductors 23 (23a, 23b). The terminal electrodes 40 include a terminal electrode 40a electrically connected to the via conductor 23a and a terminal electrode 40b electrically connected to the via conductor 23b. Although the multilayer ceramic capacitor 100 shown in Figures 1 and 2 has two terminal electrodes 40, the number of terminal electrodes in the multilayer ceramic capacitor according to the first aspect of the present invention is not limited to this.

[0023] The thickness of the base body 10, obtained by subtracting the thickness of the terminal electrodes 40 (40a, 40b) from the T-direction dimension of the multilayer ceramic capacitor 100 described above, is, for example, 20 μm or more and 200 μm or less, and preferably 30 μm or more and 180 μm or less.

[0024] The following describes in detail the various components that make up the multilayer ceramic capacitor 100 according to the first embodiment.

[0025] (Ceramic layer) The ceramic layer 21 is formed of ceramic. The composition of the ceramic is not particularly limited as long as it forms a dense ceramic layer 21 by co-firing with the internal electrodes 22, which will be described later, and can be appropriately selected according to the characteristics required for the multilayer ceramic capacitor. Examples of ceramic compositions include those mainly composed of barium titanate (BaTiO3), those mainly composed of strontium titanate (SrTiO3), and those having a perovskite-type structure. 1-x-y Ca x Sr y Ti 1-z Zr z Examples include ceramics with O3 as the main component. The ceramic may also contain additive elements along with the main component. Examples of additive elements include Mo, Nb, Ta, W, Mg, Mn, V, Cr, and rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, and Yb), as well as at least one selected from Co, Ni, Li, B, Na, K, and Si. The additive elements may be included as individual elements or in the form of compounds such as oxides, nitrides, and carbides. Furthermore, the additive elements may exist in a solid solution state in the main component, and may form a different phase with the elements constituting the main component or other additive elements.

[0026] (Internal electrode) The internal electrodes 22 (22a, 22b) are mainly composed of metal. The type of metal is not particularly limited, and nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), as well as alloys thereof, can be used. Of these, nickel (Ni) is preferred as the main component element because its high heat resistance allows for a higher firing temperature when firing it together with the ceramic layer 21, enabling the formation of a dense ceramic layer 21, and it is also relatively inexpensive. Here, "main component element" in this specification means the element that has the highest content expressed as atomic percentage (atomic %).

[0027] The internal electrodes 22 (22a, 22b) may contain, in addition to metal, ceramic particles having a similar composition to the ceramics that make up the ceramic layer 21, or glass components.

[0028] (Laminated structure) The laminate 20 has a plurality of internal electrodes 22 (22a, 22b) facing each other in the stacking direction, and a ceramic layer 21 disposed between the plurality of internal electrodes 22 (22a, 22b). The laminate 20 has an internal region 24 which is the area inside the fifth internal electrode 22 (22a, 22b) counting from the outermost layer in the stacking direction, and an external region 25 which is located outside the internal region 24 in the stacking direction.

[0029] (Protection Department) The protective part 30 has the function of protecting the ceramic layer 21 and the internal electrodes 22. The material of the protective part 30 is not limited as long as it has high electrical insulation properties and low permeability to degradation factors such as moisture. From the viewpoint of ensuring uniform shrinkage during firing when manufacturing the multilayer ceramic capacitor 100 and easing internal stress within the multilayer ceramic capacitor 100, it is preferable that the main component of the protective part 30 be the same as the ceramic forming the ceramic layer 21.

[0030] In the protective portion 30, it is preferable that the cover portion 31 through which the diameter-reduced and stretched portions 231 of the via conductors 23 (23a, 23b), described later, pass has a metal element free portion 311 near the diameter-reduced and stretched portion 231, where the concentration of the same type of metal element as the main component element of the via conductors 23 (23a, 23b) is higher than that of the surrounding area. This makes the mechanical and thermal properties of the cover portion 31 located around the diameter-reduced and stretched portion 231 approach those of the diameter-reduced and stretched portion 231, and suppresses delamination at the interface between the diameter-reduced and stretched portion 231 and the cover portion 31. A method for determining whether or not there is a metal element free portion 311 near the diameter-reduced and stretched portion 231 will be described later.

[0031] (via conductor) The via conductors 23 (23a, 23b), like the internal electrodes 22 (22a, 22b), are mainly composed of metal. Suitable metals include those used for the internal electrodes 22 (22a, 22b) as described above. The metal composition of the via conductors may differ from that of the internal electrodes 22 (22a, 22b), but it is preferable to use the same metal composition. By using the same metal composition for the via conductors (23a, 23b) and the internal electrodes 22 (22a, 22b), the magnitude of shrinkage caused by firing during the manufacturing of the multilayer ceramic capacitor 100 is uniform, suppressing deformation. Furthermore, the resistivity of the conductive paths of the multilayer ceramic capacitor 100 becomes uniform, suppressing localized heat generation during use.

[0032] As described above, the via conductors 23 (23a, 23b) have a reduced-diameter stretched portion 231 and a widened-diameter portion 223. The reduced-diameter stretched portion 231 extends through the cover portion 31 to the surface of the cover portion 31, and is the portion whose dimension in the direction perpendicular to the stacking direction of the laminate 20 is smaller than the minimum dimension obtainable in the internal region 24 of the laminate. The widened-diameter portion 232 is formed in the cover portion 31 where the reduced-diameter stretched portion 231 is located, or in the external region 25 of the laminate adjacent to the cover portion 31 where the reduced-diameter stretched portion 23 is located, and is the portion whose dimension in the direction perpendicular to the stacking direction of the laminate 20 is larger than the maximum dimension obtainable in the internal region 24 of the laminate.

[0033] Preferably, the maximum dimension of the enlarged diameter portion 232 of the via conductor 23 (23a, 23b) in the direction perpendicular to the lamination direction of the laminate 20 is 1.2 times or more the minimum dimension of the reduced diameter stretched portion 231 in the direction perpendicular to the lamination direction of the laminate 20. This significantly suppresses the relative movement of the via conductor 23 (23a, 23b) in the lamination direction relative to the ceramic layer 21, internal electrodes 22 (22a, 22b), and protective portion 30. The maximum dimension is more preferably 1.5 times or more the minimum dimension, and even more preferably 2.0 times or more.

[0034] Here, the determination of whether the via conductor 23 (23a, 23b) has a reduced-diameter extension portion 231 and an enlarged-diameter portion 232, and the determination of the minimum dimension in the direction perpendicular to the lamination direction of the laminate 20 for the reduced-diameter extension portion 231 and the maximum dimension in the direction perpendicular to the lamination direction of the laminate 20 for the enlarged-diameter portion 232 are each performed according to the following procedure. First, the multilayer ceramic capacitor 100 is cut or polished along a plane parallel to the lamination direction of the laminate 20 using a focused ion beam (FIB) apparatus or a cross-section polisher (registered trademark) (CP) to expose the vicinity of the center of gravity of the via conductor 23 (23a, 23b) to be determined. The cutting or polishing may be performed on the multilayer ceramic capacitor 100 embedded in the resin. Hereinafter, the case where the via conductor 23a is the determination target will be described. Next, the surface on which the via conductor 23a is exposed is observed with a scanning electron microscope (SEM) equipped with an energy-dispersive X-ray spectroscopic analyzer (EDS), and among the via conductor 23a to be determined, one end drawn out to the surface of the cover portion 31, and the cover portion 31 and the laminate 20 through which the via conductor 23a to be determined penetrates, the region where the portion located near the via conductor 23a to be determined enters is determined as the measurement target region. Next, the measurement target region is analyzed using EDS to obtain a mapping image of the main component elements of the via conductor 23a and the internal electrodes 22 (22a, 22b) or the main component elements common to the ceramic layer 21 and the cover portion 31 as shown in FIG. 3. Note that FIG. ⑶ shows the analysis result of Ni, which is the main component element of the via conductor 23a. Next, in the obtained mapping image, the shapes of the internal electrodes 22 (22a, 22b) located in the outermost layer in the lamination direction of the laminate 20 are linearly approximated by line segments having the same thickness as their thicknesses, respectively, and line segments h o1 and line segment h o2 are each drawn. Next, in the mapping image, the shapes of the internal electrodes 22 (22a, 22b) in the fifth layer counted from the outermost layer in the lamination direction of the laminate 20 are linearly approximated by line segments having the same thickness as their thicknesses, respectively, and line segments h i1 and line segment h i2 are each drawn. Then, the region sandwiched between the line segment h i1 and the line segment h i2 is defined as the internal region 24 of the laminate, and the line segment h o1 and the line segment hi1 The region between and the line segment h o2 and line segment h i2 The regions sandwiched between and are designated as the external regions 25 of the laminate. Next, in the mapping image, line segment h i2 line segment h parallel to x Draw the line segment h x However, the two points where the boundary line between the via conductor 23a and the laminate 20 intersects are point e x1 and point e x2 Let's assume this line segment h x Draw at various positions, point e x1 and point e x2 distance d x Measure the distances and select the longest distance among them as d max And the shortest one is d min Next, in the mapping image, the end of the via conductor 23a to be determined is extended to the surface of the cover portion 31, and the line segment h i1 line segment h parallel to y Draw the line segment h y However, two points that intersect either the boundary line between the via conductor 23a to be judged and the laminate 20, or the boundary line between the via conductor 23a to be judged and the cover portion 31, are respectively called point e. y1 and point e y2 Let's assume this line segment h y Draw at various positions, point e y1 and point e y2 distance d y Measure the obtained d. y However, on the surface side of a certain position, d is always y <d min If the following conditions are met, it is determined that the via conductor 23a subject to evaluation has a diameter-reduced extension portion 231. Also, at this time, d max <d y The presence of such a position indicates that the via conductor 23a being judged has an enlarged diameter portion 232. Then, the obtained d y The minimum value of is divided by the observation magnification of the SEM and is taken as the minimum dimension in the direction perpendicular to the lamination direction of the laminate 20 for the diameter-reduced stretched portion 231, and the obtained d yThe maximum value of this value divided by the SEM observation magnification is taken as the maximum dimension of the enlarged diameter portion 232 in the direction perpendicular to the stacking direction of the laminate 20.

[0035] Preferably, the enlarged diameter portion 232 of the via conductor 23 (23a, 23b) forms a flange that protrudes outward with respect to the axis of the via conductor 23 (23a, 23b). This makes it possible to reduce the diameter of most of the via conductor 23 (23a, 23b) passing through the inside of the laminate 20, thereby increasing the area of ​​the internal electrodes 22 (22b, 22a) which are formed not to be electrically connected to the via conductor 23 (23a, 23b), and thus increasing the capacitance of the multilayer ceramic capacitor 100.

[0036] When the enlarged diameter portion 232 forms a flange, the thickness of the flange, i.e., the dimension A1 in the stacking direction, is preferably 0.1 μm or more and 10 μm or less. A flange thickness of 0.1 μm or more formed by the enlarged diameter portion 232 ensures sufficient resistance to suppress the relative displacement of the via conductors 23 (23a, 23b) in the stacking direction, as described above. On the other hand, a flange thickness of 10 μm or less allows for a reduction in the number of internal electrodes 22 (22b, 22a) whose area is reduced to avoid contact with the flange, thereby increasing the capacitance of the multilayer ceramic capacitor 100.

[0037] Preferably, the via conductors 23 (23a, 23b) have their ends opposite to the diameter-reduced and extended portion 231 positioned within the protective portion 30 (cover portion 31), and these opposite ends form a flange that protrudes outward relative to the axis of the via conductor. This further increases the resistance of the via conductors 23 (23a, 23b) to relative displacement in the stacking direction, and significantly suppresses the decrease in capacitance of the multilayer ceramic capacitor 100.

[0038] It is preferable that the via conductors 23 (23a, 23b) satisfy the condition D1 > D2 when D1 is the dimension perpendicular to the stacking direction of the laminate 20 at the end of the internal region 24 of the laminate on the side of the reduced diameter extension portion 231, and D2 is the dimension perpendicular to the stacking direction of the laminate 20 at the end of the internal region 24 of the laminate opposite to the reduced diameter extension portion 231, and that the dimension perpendicular to the stacking direction decreases monotonically from D1 to D2. This increases the suppression of delamination at the interface between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b), and further suppresses the decrease in capacitance of the multilayer ceramic capacitor 100. This is presumed to be due to the tapered shape of the via conductors 23 (23a, 23b), which increases the contact area with the laminate 20 and increases the frictional resistance.

[0039] In this case, if the via conductors 23 (23a, 23b) satisfy D3 ≥ D1, where D3 is the dimension of the flange formed at the end located in the cover portion 31 in the direction perpendicular to the stacking direction, then the effect of suppressing delamination at the interface between the via conductors 23 (23a, 23b) and the internal electrodes 22 (22a, 22b) is greater, and the decrease in capacitance of the multilayer ceramic capacitor 100 is further suppressed. This is presumed to be because the larger dimension of the flange 231 in the direction perpendicular to the stacking direction significantly increases the resistance force when the via conductors 23 (23a, 23b) are displaced relative to the stacking direction.

[0040] The values ​​of D1, D2, and D3 are not particularly limited, but in order to reduce electrical resistance and suppress heat generation during circuit operation while ensuring the capacitance of the multilayer ceramic capacitor 100, the value of D2 is preferably 5 μm or more and 100 μm or more, and more preferably 10 μm or more and 50 μm or less. Furthermore, the value of D3 is preferably 110% or more and 225% or less of the value of D2, and more preferably 150% or more and 180% or less. Moreover, the value of D3 is preferably 100% or more and 150% or less of the value of D1, and more preferably 100% or more and 120% or less.

[0041] Preferably, the dimension of the flange 231 formed at the end of the via conductor 23 (23a, 23b) located in the cover portion 31, i.e., the thickness A2 of the flange 231, is 0.1 μm or more and 10 μm or less. A flange thickness of 0.1 μm or more ensures sufficient resistance to suppress displacement of the via conductor 23 (23a, 23b) in the stacking direction. On the other hand, a flange thickness of 10 μm or less ensures sufficient distance from the surface and internal electrodes 22 of the base body 10 to the via conductor 23 (23a, 23b), thereby ensuring the reliability of the multilayer ceramic capacitor 100.

[0042] Here, the determination that the enlarged diameter portion 232 of the via conductor 23 (23a, 23b) and the end located within the cover portion 31 form a flange, the determination of the dimensions D1, D2, D3, A1, and A2 of each part of the via conductor 23 (23a, 23b), and the determination that the dimensions of the via conductor 23 (23a, 23b) monotonically decrease from D1 to D2 are performed by the following procedure. First, a mapping image is obtained in the same manner as the procedure for determining that the via conductor 23 (23a, 23b) has a reduced diameter extension portion 231 and an enlarged diameter portion 232 described above, and a line segment h is added to the mapping image. o1 , line segment h o2 , line segment h i1 , line segment h i2 and line segment h x , and point e x1 and point e x2 Construct each of them. At this time, line segment h o1 and line segment h i1 The line segment h is drawn on the side of the via conductor 23 (23a, 23b) that is close to the enlarged diameter portion 232. o2 and line segment h i2The lines are drawn on the side of the via conductor 23 (23a, 23b) that is located within the cover portion 31, near the end. Next, in the mapping image, as shown in Figure 4, line segments v1 and v2 are drawn that define both sides of the portion of the via conductor 23a that is located within the laminated internal region 24. Then, it is determined that the enlarged diameter portion 232 forms a flange if the enlarged diameter portion 232 extends outward from the axis of the via conductor 23a beyond line segments v1 and v2. Similarly, it is determined that the end of the via conductor 23a located within the cover portion 31 forms a flange if it extends outward from the axis of the via conductor 23a beyond line segments v1 and v2. Next, in the mapping image, line segment h i1 The intersection point e1 of and line segment v1, and line segment h i1 The intersection point e2 between the line segment and v2 is drawn, and the value D1 is obtained by dividing the distance d1 between point e1 and point e2 by the observation magnification of the SEM. Next, in the mapping image, the line segment h i2 The intersection point e3 of and line segment v1, and line segment h i2 Construct the intersection point e4 between point h and line segment v2, and let D2 be the value obtained by dividing the distance d2 between point e3 and point e4 by the SEM observation magnification. At this time, line segment h x is line segment h i1 from h i2 As we approach point e x1 and point e x2 distance d x However, since it decreases monotonically from d1 to d2, it is determined that the dimensions of the via conductor 23a decrease monotonically from D1 to D2. Next, in the mapping image, points e5 and e6 are drawn in the cover portion 31 containing the end of the via conductor 23a, furthest from the axis of the via conductor 23a toward line segment v1 and furthest from the axis of the via conductor 23a toward line segment v2, and the value obtained by dividing the distance d3 between points e5 and e6 by the observation magnification of the SEM is taken as D3. Next, in the mapping image, points e7 and e8 are drawn at the two points where the enlarged diameter portion 232 and line segment v1 intersect, and points e9 and e 10 Draw each of them. At this time, place point e7 closer to the laminate 20 than point e8, and place point e9 closer to point e 10Draw the points closer to the laminate 20. Then, the distance between point e7 and point e8, and the distance between point e9 and point e 10 Let A1 be the average of the distances divided by the SEM's observation magnification. Next, in the mapping image, point e is placed at two points where the end of the via conductor 23a located in the cover portion 31 intersects with the line segment v1. 11 and point e 12 Each of these is drawn, and at the two points where the end of the via conductor 23a located in the cover portion 31 intersects with the line segment v2, point e 13 and point e 14 Construct each of them. At this time, point e 11 point e 12 Point e is located closer to the laminate 20. 13 point e 14 The drawings are then made on the side closer to the laminate 20. Then, point e 11 and point e 12 The distance, and point e 13 and point e 14 A2 is the average distance divided by the SEM's observation magnification. When plotting line segments v1 and v2, if the side surface of the via conductor 23a observed in the mapping image forms a curve or a broken line, the curve or broken line is linearly approximated to form the line segment. Furthermore, although the procedure described above applies to the vicinity of via conductor 23a, it goes without saying that it may also be performed in the vicinity of via conductor 23b, which has a different polarity.

[0043] Furthermore, the determination of whether a metal element free portion 311 exists near the diameter-reduced stretched portion 231 in the cover portion 31, as described above as a preferred embodiment of the cover portion 31, is performed by the following procedure. First, a mapping image is obtained in the same manner as the procedure described above for determining whether the via conductor 23 (23a, 23b) has a diameter-reduced stretched portion 231 and a diameter-expanded portion 232, and line segments v1 and v2 are drawn in the mapping image as shown in Figure 5. Next, in the mapping image, if regions with high concentrations of the same type of metal element as the main component element of the via conductor 23 (23a, 23b) are observed in an island-like manner in the region located between line segment v1 and the diameter-reduced stretched portion 231, and in the region located between line segment v2 and the diameter-reduced stretched portion 231, it is determined that a metal element free portion 311 exists near the diameter-reduced stretched portion 231 in the cover portion 31.

[0044] Preferably, as shown in Figure 6, via conductors 23 (23a, 23b) have opening cavities formed at the ends that form flanges located within the cover portion 31. This suppresses delamination at the interface between the via conductors 23 (23a, 23b) and the cover portion 31 in the cover portion 31 that includes the ends of the via conductors 23 (23a, 23b). This is presumed to be because the presence of cavities reduces the contact area between the via conductors 23 (23a, 23b) and the cover portion 31, thereby reducing the stress generated at the interface between them due to the difference in shrinkage between the via conductors 23 (23a, 23b) and the cover portion 31 during firing in manufacturing.

[0045] It is more preferable that the maximum dimension D4 of the cavity formed at the end of the via conductor 23 (23a, 23b) located within the cover portion 31 is 10% to 90% of D2, i.e., the dimension of the internal region 24 of the laminate 24 at the end opposite to the reduced diameter stretched portion 231, in the direction perpendicular to the lamination direction of the laminate 20. When D4 is 10% or more of D2, delamination at the interface between the via conductor 23 (23a, 23b) and the cover portion 31 is significantly suppressed. On the other hand, when D4 is 90% or less of D2, the resistance to displacement of the via conductor 23 (23a, 23b) in the lamination direction and in the direction perpendicular to the lamination direction is sufficient, thereby suppressing delamination at the interface between the via conductor 23 (23a, 23b) and the internal electrode 22 (22a, 22b).

[0046] The maximum dimension A3 in the stacking direction of the cavity formed at the end of the via conductor 23 (23a, 23b) located within the cover portion 31 is preferably 1 μm or more and 20 μm or less, more preferably 1 μm or more and 10 μm or less, and even more preferably 1 μm or more and 5 μm or less. When A3 is 1 μm or more, delamination at the interface between the via conductor 23 (23a, 23b) and the cover portion 31 is significantly suppressed. On the other hand, when A3 is 10 μm or less, the resistance to displacement of the via conductor 23 (23a, 23b) in the stacking direction and in the direction perpendicular to the stacking direction is made sufficient, and delamination at the interface between the via conductor 23 (23a, 23b) and the internal electrode 22 (22a, 22b) can be suppressed.

[0047] Here, the dimensions D4 and A3 of each part in the cavity formed at the end of the via conductor 23 (23a, 23b) located in the cover portion 31 are determined by the following procedure. First, a mapping image is obtained using the same procedure as when determining D1, D2, D3, A1, and A2 above, and in the mapping image, line segment h is added as shown in Figure 7. o2 , line segment v1 and line segment v2, and point e 12 and point e 14 Each of these is plotted. Next, in the mapping image, point e 12 and point e 14 line segment e connecting to 12 e14 Draw a diagram, and for line segment e 12 e 14 Among the points where line segment e intersects the contour line of via conductor 23a that defines a cavity at the end located within the cover portion 31 of via conductor 23a, select the point e 12 close to point e 15 as e 14 and select the point close to point e 16 as e 15 If point e does not exist, in subsequent operations, treat point e 12 as point e 15 and if point e 16 does not exist, in subsequent operations, treat point e 14 as point e 16 Next, in the said image, draw a line segment v3 passing through point e 15 and perpendicular to line segment h o2 , and draw a line segment v4 passing through point e 16 and perpendicular to line segment h[[ID=Q32]] o2 . Let the value obtained by dividing the distance d4 between line segment v3 and line segment v4 by the magnification of the microscopic image be D4. Next, in the said mapping image, draw a line segment h o2 parallel to line segment h 12 e 14 and contacting the contour line of via conductor 23a that defines the cavity, and having the maximum distance from line segment e v . Let the value obtained by dividing the shortest distance a3 between line segment h v and line segment e 12 e 14 by the observation magnification of the SEM be A3.

[0048] The ends of the via conductors 23 (23a, 23b) located within the protective portion 30 (cover portion 31) may have a shape in which the central part bulges out, as shown in Figure 8, contrary to the aforementioned cavity, that is, a shape having a convex portion that protrudes in the stacking direction of the laminate 20. Such a shape is formed during the manufacturing process of the multilayer ceramic capacitor 100, described later, when the raw sheet for forming the cover portion is pressed down, and the conductor paste for forming the via conductor remains without moving towards the diameter-reduced stretched portion 231, pushing back the raw sheet for forming the cover portion. Therefore, the bulge in the central part of the ends of the via conductors 23 (23a, 23b) located within the cover portion 31 indicates high adhesion between the via conductors 23 (23a, 23b) and the adjacent cover portion 31, ceramic layer 21, and internal electrodes 22 (22a, 22b), thereby obtaining a multilayer ceramic capacitor 100 with high mechanical strength.

[0049] Figures 2 to 8 show via conductors 23 (23a, 23b) in which the diameter-reduced extension portion 231 has substantially constant dimensions in the vertical direction of the laminate 20, and the diameter-enlarged portion 232 forms a flange. However, the shape of the via conductors 23 (23a, 23b) is not limited to this. For example, as shown in Figure 9a, the dimension of the diameter-reduced extension portion 231 in the direction perpendicular to the lamination direction of the laminate 20 may decrease as it approaches the surface of the cover portion 31. Also, as shown in Figures 9a and 9b, the dimension of the via conductors 23 (23a, 23b) in the direction perpendicular to the lamination direction of the laminate 20 may gradually increase from the internal region 24 side of the laminate towards the diameter-reduced extension portion 231 side, thereby forming the diameter-enlarged portion 232.

[0050] (terminal electrode) The material of the terminal electrodes 40 (40a, 40b) is not limited as long as it is conductive. Examples of materials include metals such as nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), and gold (Au), alloys in which any of these are the main component elements, and conductive resins.

[0051] The terminal electrodes 40 (40a, 40b) may have a base conductor 41 that contacts the base body 10 and a plated conductor 42 formed on the surface of the base conductor 41. Terminal electrodes 40 (40a, 40b) with such a structure can improve adhesion to the base body 10 with the base conductor 41, while improving solder wettability when mounted on a circuit board with the plated conductor 42.

[0052] Ni is an example of a material for the base conductor 41. The thickness of the base conductor 41 can be 0.1 μm or more and 10 μm or less, and preferably 0.5 μm or more and 5 μm or less.

[0053] The plated conductor 42 may be formed as a single layer or as multiple layers. When the plated conductor 42 is made up of multiple layers, the number of layers is preferably two to four. Examples of the material and structure of the plated conductor 42 include those made of Cu, Ni, and Sn in that order. The thickness of the plated conductor 42 can be 1 μm or more and 20 μm or less, and preferably 3 μm or more and 10 μm or less.

[0054] <Second Embodiment> Another embodiment (second embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention is characterized in which internal electrodes are drawn out on a surface perpendicular to the surface from which the ends of the via conductors 23 (23a, 23b) of the element 10 are drawn out, and external electrodes are placed on the surface from which the internal electrodes are drawn out (internal electrode lead-out surface), and electrical connection between the internal electrodes is also made via the external electrodes. An example of a multilayer ceramic capacitor 200 according to the second embodiment is shown in Figure 10. Although Figure 10 shows an example in which two opposing surfaces are used as internal electrode lead-out surfaces, the number of internal electrode lead-out surfaces is not limited thereto. Also, although Figure 10 shows an example in which terminal electrodes 40 (40a, 40b) extending to the internal electrode lead-out surface form external electrodes 50 (50a, 50b), the external electrodes 50 (50a, 50b) may be formed separately from the terminal electrodes 40 (40a, 40b). In the multilayer ceramic capacitor 200, the current flowing through the internal electrodes 22 (22a, 22b) is split between the via conductors 23 (23a, 23b) and the external electrodes 50 (50a, 50b), resulting in smaller currents flowing through each individual via conductor 23 (23a, 23b) and external electrode 50 (50a, 50b). This reduces heat generation during operation.

[0055] <Third Embodiment> Another embodiment (third embodiment) of the multilayer ceramic capacitor according to the first aspect of the present invention is one in which the number of terminal electrodes arranged on one face of the element is four or more, and each terminal electrode has a different polarity from the nearest terminal electrode on the face. An example of a multilayer ceramic capacitor 300 according to the third embodiment is shown in Figure 11. Although Figure 11 shows an example in which the number of terminal electrodes 40 arranged on one face of the element 10 is four, the number of terminal electrodes arranged on one face of the element 10 is not limited to this. The multilayer ceramic capacitor 300 has the advantage that the direction of the current flowing through the via conductors (not shown) electrically connected to each terminal electrode 40 (40a, 40b) is opposite for nearest conductors, so the magnetic fields generated by the current cancel each other out and the equivalent series inductance (ESL) can be reduced. The aforementioned effects become particularly noticeable when the multilayer ceramic capacitor 300 has two sets of opposing surfaces parallel to the stacking direction of the laminate, where the distance between one set of surfaces, i.e., the dimension in the L direction, is Lμm, and the distance between the other set of surfaces, i.e., the dimension in the W direction, is Wμm (where L≧W), and the ratio of W to L, W / L, is between 0.8 and 1, i.e., when the surface on which the terminal electrodes are arranged has a shape close to a square.

[0056] [Manufacturing method for multilayer ceramic electronic components] A multilayer ceramic capacitor according to the first aspect of the present invention can be manufactured by the procedure described below.

[0057] ((A) Preparation of ceramic powder) First, prepare the ceramic powder. Commercially available ceramic powder can be used as appropriate. If you are making your own ceramic powder, mix the various raw material powders containing the constituent elements in a predetermined ratio and pre-fire them (calcination). When mixing the various raw material powders in a predetermined ratio, you may further add the aforementioned additive elements and sintering aids, or you may further add these additives to the powder after calcination.

[0058] ((B) Preparation of raw sheets) Next, the aforementioned ceramic powder is mixed with a binder and a dispersion medium to prepare a slurry, and the slurry is formed into a sheet to obtain a raw sheet.

[0059] The binder used should be one that can maintain the shape of the raw sheet and volatilize without leaving any carbon residue after the binder removal process prior to firing. Examples of usable binders include polyvinyl alcohol-based, polyvinyl butyral-based, cellulose-based, urethane-based, and vinyl acetate-based binders. The amount of binder used is not particularly limited, but since it will be removed in a later process, it is preferable to use as little as possible within the range where the desired moldability and shape retention can be achieved, in order to reduce raw material costs.

[0060] As the dispersion medium, one should be used that does not cause aggregation of the calcined powder and binder, and can be easily removed by volatilization or other means after the formation of the raw sheet, as described later. Examples of usable dispersion media include water and alcohol-based solvents.

[0061] Components that adjust the properties of the slurry, such as dispersants, plasticizers, and thickeners, may be added to the slurry.

[0062] The method for mixing the above-mentioned mixed powder with a binder and dispersion medium is not particularly limited, as long as it ensures that each component is uniformly mixed while preventing the introduction of impurities. One example is ball mill mixing.

[0063] Conventional methods such as the doctor blade method and the die-coating method can be used to form the prepared slurry into a sheet and obtain a raw sheet.

[0064] ((C) Formation of internal electrode pattern) Next, an internal electrode pattern containing metal is formed on the raw sheet. The internal electrode pattern can be formed by printing or coating an internal electrode paste in a predetermined pattern, or by forming a metallic film in a predetermined pattern by vapor deposition or sputtering. The internal electrode pattern is formed with a sufficient margin to ensure electrical insulation from via conductor patterns that are formed later but do not come into contact with it.

[0065] When forming an internal electrode pattern using an internal electrode paste, the internal electrode paste is obtained by mixing metal particles and a vehicle in a three-roll mill. In addition to the components mentioned above, the internal electrode paste may also contain glass frit or ceramic powder.

[0066] The type and amount of binder and solvent contained in the vehicle used are not limited and should be selected appropriately considering the viscosity of the internal electrode paste, ease of handling, and compatibility with the raw sheet.

[0067] The printing of the paste for the internal electrodes onto the raw sheet can be performed, for example, using a screen mask on which a predetermined internal electrode pattern has been formed. During printing, it is also possible to print with a space left to form a margin when the multilayer ceramic capacitor is assembled.

[0068] ((D) Preparation of biolaminates) Next, a predetermined number of raw sheets with internal electrode patterns are stacked, and the raw sheets are pressed together to obtain a raw laminate. The stacking and pressing can be carried out using conventional methods, such as pressing the stacked raw sheets in the stacking direction while heating them, and then heat-pressing them together using the action of a binder.

[0069] ((E) Formation of through-holes for via conductors) Next, through-holes for via conductors are formed in the raw laminate. Conventional methods such as drilling or lasers can be used to form the holes. Among these, the use of a laser is preferred because it can form a smooth processed surface. If the end located in the enlarged diameter portion or the cover portion of the via conductor in the final multilayer ceramic capacitor is to be flange-shaped, after forming the through-holes, a portion of the material forming the raw laminate may be removed from the periphery of one of the openings to form a gap in the shape corresponding to the flange. Examples of methods for removing the raw sheet include pressing a mold with a convex portion against the periphery of the opening or polishing.

[0070] ((F) Lamination of raw sheets for the cover part (1)) Next, a raw sheet for the cover portion, which will form the cover portion when the laminated body is assembled into a multilayer ceramic capacitor, is added to at least one of the surfaces perpendicular to the lamination direction of the raw laminated body in which through holes for via conductors are formed. The raw sheet for the cover portion may have the same composition as the raw sheet on which the internal electrode pattern is printed, or a different composition. From the viewpoint of matching the shrinkage rate during firing, it is preferable that the composition of the raw sheet for the cover portion is the same as or similar to the composition of the raw sheet on which the internal electrode precursor is arranged.

[0071] The raw sheet for the cover added in this operation forms a cover portion in the final multilayer ceramic capacitor in which the via conductors are extended to the surface. Therefore, when obtaining a multilayer ceramic capacitor in which both ends of the via conductors are extended to the surface of the cover portion, the raw sheet for the cover portion is added to both surfaces perpendicular to the stacking direction of the raw laminate. On the other hand, when obtaining a multilayer ceramic capacitor in which one end of the via conductor is located within the cover portion, the raw sheet for the cover portion is stacked on the surface of the raw laminate on the side of that one end after the filling of the via conductor paste (G) described later has been completed.

[0072] The raw sheet for the cover added in this operation has through holes smaller in diameter than the via conductor through holes in the raw laminate at positions corresponding to those through holes in the raw laminate. These small-diameter through holes form the reduced-diameter extended portion of the via conductor in the final multilayer ceramic capacitor. These small-diameter through holes can be formed using a punching machine or a laser processing machine. Alternatively, instead of using a raw sheet for the cover with small-diameter through holes, a raw sheet for the cover without through holes may be laminated, and then through holes smaller in diameter than those through holes may be formed at positions corresponding to those through holes in the raw laminate. The method for forming the small-diameter through holes can be the same as the method used when forming via conductor through holes in the raw laminate.

[0073] ((G) Filling with paste for via conductors) Next, via conductor paste is filled into the through-holes to form a via conductor pattern. Conventional methods such as injection using a syringe or printing using a metal mask can be used to fill the holes with via conductor paste. Among these, printing using a metal mask is preferable because it is excellent in filling small-diameter holes. The components of the via conductor paste can be the same as those of the internal electrode paste described above, and the amount of each component should be determined considering the ability to fill the holes. When forming a cavity at the end of a via conductor located in the cover, a convex member smaller in dimensions than the through-hole is inserted from the side where the cavity is to be formed, and then the via conductor paste is filled in. After that, the convex member is removed, or after filling the through-hole with via conductor paste, vibration is applied to the raw laminate with the side where the cavity is to be formed facing upwards. On the other hand, when the end of a via conductor located in the cover is to be shaped with a bulge in the center, the via conductor paste should be filled so that it protrudes (rises) above the surface height of the raw laminate on the end side.

[0074] ((H) Lamination of raw sheets for the cover part (2)) When obtaining a multilayer ceramic capacitor in which one end of a via conductor is located within the cover portion, a raw sheet that will form the cover portion of the multilayer ceramic capacitor is laminated onto the surface of the raw laminate where the via conductor through-holes are opened. The laminated raw sheet may have the same composition as the raw sheet forming the raw laminate, or a different composition. Examples of lamination methods include pressing the raw sheet using a mold after placement, or applying pressure to the raw sheet using rollers.

[0075] (Formation of terminal electrode pattern (I)) Next, a terminal electrode pattern is formed on at least one surface of the raw laminate perpendicular to the lamination direction where the via conductor pattern is exposed. The terminal electrode pattern can be formed by printing or coating a terminal electrode paste, or by forming a metallic film by vapor deposition or sputtering. In this case, the terminal electrode pattern may be formed using a mask on which a predetermined pattern has been formed, or a paste film or metal film may be formed on the entire surface of the raw laminate where the via conductor pattern is exposed, and then the parts other than the terminal electrode pattern may be removed. Face milling and barrel polishing can be used to remove the parts other than the terminal electrode pattern. When a terminal electrode paste is used to form the terminal electrode pattern, the same components as the internal electrode paste described above can be used, and the amount of each component should be determined so that a uniform pattern of a predetermined thickness is obtained.

[0076] ((J) Preparation of chips before firing) Next, the raw laminate is divided into individual pieces to obtain chips before firing. Conventional methods such as dicing saws or laser cutting machines can be used for piece formation. After piece formation of the raw laminate to form surfaces where the internal electrode precursors are exposed, the surfaces with exposed internal electrode precursors may be covered with a material for forming margins to obtain chips before firing.

[0077] ((K) Binder removal) Next, the obtained unfired chips are heated to remove the binder by volatilization. The heating conditions should be set appropriately considering the volatilization temperature and content of the binder. As an example, the chips may be held in a nitrogen (N2) atmosphere at a temperature of 200°C to 500°C for 5 to 20 hours.

[0078] ((L) Firing of chips before firing) Next, the unfired chips, from which the binder has been removed, are heated to a predetermined temperature for firing. When setting the firing conditions, it is preferable to consider the sinterability of the ceramic powder, as well as the heat resistance and oxidation resistance of the metals contained in the internal electrode pattern, via conductor pattern, and terminal electrode pattern, respectively. An example of firing conditions is to hold the chips at a temperature of 1100°C to 1400°C for 10 minutes to 2 hours in a reducing atmosphere of nitrogen (N2), hydrogen (H2), and water vapor (H2O). After firing, a re-oxidation treatment may be performed by holding the chips at 600°C to 1000°C in a nitrogen (N2) gas atmosphere or a low-oxygen atmosphere.

[0079] The sintered body obtained in this way may be used as is as a multilayer ceramic capacitor, or a conductive layer may be formed on the surface of the terminal electrode pattern by plating before it is used as a multilayer ceramic capacitor.

[0080] In order to obtain a preferred configuration of the multilayer ceramic capacitor relating to the first side, in which a metal element free portion exists near the diameter-reduced and stretched portion in the cover portion, first, the order of (F) and (G) described above is reversed. Then, after (F), a paste for the metal element free portion, made by mixing the material that forms the cover portion with the material that forms the via conductor, is applied to the inner circumferential wall of the recess on the raw sheet side of the raw laminate surface. After that, the via conductor paste is filled into the center of the recess, and the process from (H) onwards is performed. In this case, the through-hole formed in the raw sheet for the cover portion used in (F) is reduced in diameter by the application of the paste for the metal element free portion, so it may be the same diameter as the via conductor through-hole formed in the raw laminate, or it may be larger in diameter.

[0081] [Circuit board] A circuit board relating to a second aspect of the present invention is equipped with a multilayer ceramic capacitor according to the first embodiment. Because this circuit board uses a thin multilayer ceramic capacitor with suppressed capacitance reduction, it is highly reliable and can be installed in a narrow space. To become something.

[0082] This specification also discloses the following technologies:

[0083] (Note 1) A laminate having a plurality of internal electrodes facing each other in the stacking direction, and a ceramic layer disposed between the plurality of internal electrodes, A protective part that covers the surface of the laminate, and A plurality of via conductors are arranged in the stacking direction of the laminate, penetrating the ceramic layer, with at least one end extended to the surface of the protective portion, and electrically connected to the internal electrode. A rectangular parallelepiped body having, and A plurality of terminal electrodes are arranged on at least one of the surfaces forming the surface of the substrate, on the surface from which the end of the via conductor is drawn, and are electrically connected to at least one of the plurality of via conductors. Equipped with, The aforementioned euro conductor is A reduced-diameter stretched portion that extends through the protective portion to the surface of the protective portion, and whose dimension in the direction perpendicular to the stacking direction of the laminate is smaller than the minimum dimension obtained in the internal region of the laminate which is the region inside the fifth layer of internal electrodes counted from the protective portion side of the laminate, and A diameter-enlarged portion is formed in the protective portion where the diameter-reduced extension portion is located, or in the external region of the laminate located between the protective portion where the diameter-reduced extension portion is located and the internal region of the laminate, and the dimension in the direction perpendicular to the lamination direction of the laminate is larger than the maximum dimension obtained in the internal region of the laminate. has Multilayer ceramic electronic components.

[0084] (Note 2) The multilayer ceramic electronic component as described in (Note 1), wherein the maximum dimension in the enlarged diameter portion in the direction perpendicular to the lamination direction of the laminate is 1.2 times or more the minimum dimension in the enlarged diameter portion in the direction perpendicular to the lamination direction of the laminate.

[0085] (Note 3) The multilayer ceramic electronic component according to (Note 1) or (Note 2), wherein the enlarged diameter portion forms a flange that protrudes outward with respect to the axis of the via conductor.

[0086] (Note 4) The multilayer ceramic electronic component as described in (Note 3), wherein the dimension A1 in the stacking direction of the flange formed by the enlarged diameter portion is 0.1 μm or more and 10 μm or less.

[0087] (Note 5) The multilayer ceramic electronic component according to any one of (Appendix 1) to (Appendix 4), wherein the protective portion through which the diameter-reduced stretched portion passes has a metal element free zone near the diameter-reduced stretched portion in which the concentration of the same type of metal element as the main component element of the via conductor is higher than that of the surrounding area.

[0088] (Note 6) The multilayer ceramic electronic component according to any one of (Appendix 1) to (Appendix 5), wherein the via conductor has an end opposite to the diameter-reduced stretched portion disposed within the protective portion, and the opposite end forms a flange that protrudes outward with respect to the axis of the via conductor.

[0089] (Note 7) The aforementioned euro conductor is Let D1 be the dimension in the direction perpendicular to the lamination direction of the laminate at the end of the internal region of the laminate on the side of the reduced diameter extension portion. When D2 is the dimension perpendicular to the lamination direction of the laminate at the end of the internal region of the laminate opposite to the diameter-reduced stretched portion, A multilayer ceramic electronic component as described in (Appendix 6), satisfying D1 > D2, wherein the dimension in the direction perpendicular to the stacking direction decreases monotonically from D1 to D2.

[0090] (Note 8) The via conductor satisfies D3 ≥ D1 when the dimension of the flange formed at the end opposite to the diameter-reduced extension portion in the direction perpendicular to the lamination direction is D3, as described in (Appendix 7).

[0091] (Note 9) The via conductor is a multilayer ceramic electronic component according to any one of (Appendix 6) to (Appendix 8), wherein the dimension A2 in the stacking direction of the flange formed at the end opposite to the diameter-reduced stretched portion is 0.1 μm or more and 10 μm or less.

[0092] (Note 10) The multilayer ceramic electronic component according to any one of (Appendix 6) to (Appendix 9), wherein the via conductor has a cavity formed that opens at the end opposite to the diameter-reduced stretched portion.

[0093] (Note 11) A multilayer ceramic electronic component as described in any of (Appendix 1) to (Appendix 10), wherein the dimension in the stacking direction is 100 μm or less.

[0094] (Note 12) A circuit board on which a multilayer ceramic electronic component described in any of (Appendix 1) to (Appendix 11) is mounted. [Industrial applicability]

[0095] According to the present invention, it is possible to provide a thin multilayer ceramic capacitor in which capacitance reduction is suppressed. Such a multilayer ceramic capacitor is useful not only because of its high reliability, but also because it can be placed in a narrow space, thus reducing the design constraints on the circuit board. [Explanation of symbols]

[0096] 100, 200, 300 Multilayer Ceramic Capacitors 10 Base Body 20 Laminate 21 Ceramic layer 22(22a, 22b) Internal electrode 23 (23a, 23b) via conductor 231 Diameter reduction extension part 232 Expanded diameter part 24. Internal region of the laminate 25. External region of the laminate 30 Protection Department 31 Cover section 311 Metal element free part 32 Margin section 40(40a, 40b) terminal electrode 41 Underlayment conductor 42 Plated conductors 50(50a, 50b) External electrode

Claims

1. A laminate having a plurality of internal electrodes facing each other in the stacking direction, and a ceramic layer disposed between the plurality of internal electrodes, A protective part that covers the surface of the laminate, and A plurality of via conductors are arranged in the stacking direction of the laminate, penetrating the ceramic layer, with at least one end extended to the surface of the protective portion, and electrically connected to the internal electrode. A rectangular parallelepiped body having, and A plurality of terminal electrodes are arranged on at least one of the surfaces forming the surface of the substrate, on the surface from which the end of the via conductor is drawn, and are electrically connected to at least one of the plurality of via conductors. Equipped with, The aforementioned euro conductor is A reduced-diameter stretched portion that extends through the protective portion to the surface of the protective portion, and whose dimension in the direction perpendicular to the stacking direction of the laminate is smaller than the minimum dimension obtained in the internal region of the laminate which is the region inside the fifth internal electrode from the protective portion side of the laminate, and A diameter-enlarged portion is formed in the protective portion where the diameter-reduced extension portion is located, or in the external region of the laminate located between the protective portion where the diameter-reduced extension portion is located and the internal region of the laminate, and the dimension in the direction perpendicular to the lamination direction of the laminate is larger than the maximum dimension obtained in the internal region of the laminate. has Multilayer ceramic electronic components.

2. The multilayer ceramic electronic component according to claim 1, wherein the maximum dimension in the enlarged diameter portion in the direction perpendicular to the lamination direction of the laminate is 1.2 times or more the minimum dimension in the enlarged diameter portion in the direction perpendicular to the lamination direction of the laminate.

3. The multilayer ceramic electronic component according to claim 1, wherein the enlarged diameter portion forms a flange that protrudes outward with respect to the axis of the via conductor.

4. The multilayer ceramic electronic component according to claim 3, wherein the dimension A1 in the stacking direction of the flange formed by the enlarged diameter portion is 0.1 μm or more and 10 μm or less.

5. The multilayer ceramic electronic component according to claim 1, wherein the protective portion through which the diameter-reduced stretched portion passes has a metal element free portion near the diameter-reduced stretched portion in which the concentration of the same type of metal element as the main component element of the via conductor is higher than that of the surrounding area.

6. The multilayer ceramic electronic component according to claim 1, wherein the via conductor has an end opposite to the diameter-reduced stretched portion that is positioned within the protective portion, and the opposite end forms a flange that protrudes outward with respect to the axis of the via conductor.

7. The aforementioned euro conductor is Let D1 be the dimension in the direction perpendicular to the lamination direction of the laminate at the end of the internal region of the laminate on the side of the reduced diameter extension portion. When D2 is the dimension in the direction perpendicular to the lamination direction of the laminate at the end of the internal region of the laminate opposite to the diameter-reduced stretched portion, The multilayer ceramic electronic component according to claim 6, wherein D1 > D2 is satisfied, and the dimension in the direction perpendicular to the stacking direction decreases monotonically from D1 to D2.

8. The multilayer ceramic electronic component according to claim 7, wherein the via conductor satisfies D3 ≥ D1 when D3 is the dimension of the flange formed at the end opposite to the diameter-reduced extension portion in the direction perpendicular to the lamination direction.

9. The multilayer ceramic electronic component according to claim 6, wherein the via conductor has a flange dimension A2 in the stacking direction of the end opposite to the diameter-reduced stretched portion, which is 0.1 μm or more and 10 μm or less.

10. The multilayer ceramic electronic component according to claim 6, wherein the via conductor has a cavity formed in the end opposite to the diameter-reduced stretched portion.

11. The multilayer ceramic electronic component according to claim 1, wherein the dimension in the stacking direction is 100 μm or less.

12. A circuit board on which a multilayer ceramic electronic component according to any one of claims 1 to 11 is mounted.

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