Semiconductor devices and power modules

Abstract

This disclosure aims to provide a semiconductor device capable of improving voltage resistance. [Solution] The semiconductor device according to this disclosure comprises a semiconductor substrate, a base layer provided on the upper side of the semiconductor substrate, at least one carrier storage layer provided below the base layer, and at least one two-stage trench provided on the upper side of the semiconductor substrate, penetrating the base layer and the carrier storage layer, having an upper electrode in the upper stage and a lower electrode in the lower stage, wherein the lower end of the upper electrode is located above the lower end of the carrier storage layer and below the vertical center position of the carrier storage layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal and a power module including the semiconductor device.

Background Art

[0002] Conventionally, an IGBT (Insulated Gate Bipolar Transistor) including a two-stage trench having an upper electrode and a lower electrode inside the trench and a carrier accumulation layer has been disclosed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an IGBT including a two-stage trench and a carrier accumulation layer, there are three high electric field regions. The first high electric field region is a region between the interface of the carrier accumulation layer and the base layer and the central position of the carrier accumulation layer. In this region, the electric field becomes high in the depletion layer region composed of a p-type semiconductor layer and an n-type semiconductor layer.

[0005] The second high electric field region is a region below the carrier accumulation layer where holes are accumulated from the viewpoint of dynamic withstand voltage. When the gate is suddenly turned off at turn-off, the injection of electrons from the channel is reduced, and in the region below the carrier accumulation layer, the holes of the positive charges accumulated in the carrier accumulation layer are more than the electrons of the negative charges, and the space charge increases, so the electric field may become strong.

[0006] The third high-field region is the corner at the lower end of the upper electrode. The electric field is concentrated and high at this corner. This third high-field region is unique to IGBTs equipped with a two-stage trench.

[0007] The inventors identified a problem specific to IGBTs with a two-stage trench and carrier storage layer: when the third high-electric-field region overlaps with the first or second high-electric-field region, the electric field is amplified and the breakdown voltage decreases.

[0008] This disclosure was made to solve such problems and aims to provide a semiconductor device capable of improving voltage resistance. [Means for solving the problem]

[0009] To solve the above problems, the semiconductor device according to this disclosure comprises a semiconductor substrate, a base layer provided on the upper side of the semiconductor substrate, at least one carrier storage layer provided below the base layer, and at least one two-stage trench provided on the upper side of the semiconductor substrate, penetrating the base layer and the carrier storage layer, having an upper electrode in the upper stage and a lower electrode in the lower stage, wherein the lower end of the upper electrode is located above the lower end of the carrier storage layer and below the vertical center position of the carrier storage layer. [Effects of the Invention]

[0010] According to this disclosure, it is possible to improve pressure resistance. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a cross-sectional view of a semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a diagram illustrating the high-electric-field region in the semiconductor device according to Embodiment 1. [Figure 3] Figure 3 is a diagram showing the relationship between the vertical direction of the upper electrode, the breakdown voltage, and the impurity concentration in the semiconductor device according to Embodiment 1. [Figure 4]FIG. 4 is a diagram for explaining a high electric field region in a semiconductor device. [Figure 5] FIG. 5 is a diagram for explaining a high electric field region in a semiconductor device. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 1. [Figure 7] FIG. 7 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 1. [Figure 8] FIG. 8 is a cross-sectional view of a semiconductor device according to Modification 3 of Embodiment 1. [Figure 9] FIG. 9 is a cross-sectional view of a semiconductor device according to Modification 4 of Embodiment 1. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device according to Modification 5 of Embodiment 1. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor device according to Modification 5 of Embodiment 1. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device according to Modification 6 of Embodiment 1. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to Modification 7 of Embodiment 1. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 1. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device according to Modification 9 of Embodiment 1. [Figure 16] FIG. 16 is a cross-sectional view of a semiconductor device according to Modification 10 of Embodiment 1. [Figure 17] FIG. 17 is a cross-sectional view of a semiconductor device according to Modification 11 of Embodiment 1. [Figure 18] FIG. 18 is a cross-sectional view of a semiconductor device according to Modification 12 of Embodiment 1. [Figure 19] FIG. 19 is a diagram showing the impurity density of each layer in a semiconductor device according to Modification 13 of Embodiment 1. [Figure 20] FIG. 20 is a diagram showing the impurity density of each layer in a semiconductor device according to Modification 13 of Embodiment 1. [Figure 21] FIG. 21 is a cross-sectional view of a semiconductor device according to Modification 15 of Embodiment 1. [Figure 22] FIG. 22 is a cross-sectional view of a semiconductor device according to Modification 16 of Embodiment 1. [Figure 23] FIG. 23 is a cross-sectional view of a semiconductor device according to Modification 17 of Embodiment 1. [Figure 24] FIG. 24 is a cross-sectional view of a semiconductor device according to Modification 18 of Embodiment 1. [Figure 25] FIG. 25 is a cross-sectional view of a semiconductor device according to Modification 19 of Embodiment 1. [Figure 26] FIG. 26 is a cross-sectional view of a semiconductor device according to Modification 20 of Embodiment 1. [Figure 27] FIG. 27 is a cross-sectional view of a semiconductor device according to Modification 21 of Embodiment 1. [Figure 28] FIG. 28 is a plan view of a power module according to Embodiment 2.

MODE FOR CARRYING OUT THE INVENTION

[0012] <Embodiment 1> Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. The semiconductor device is an IGBT. Note that the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted. In the following description, n and p indicate the conductivity type of the semiconductor. These conductivity types may be reversed.

[0013] FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1. In FIG. 1, the semiconductor substrate ranges from the source layer 3 to the collector layer 8. In FIG. 1, the upper end of the source layer 3 is referred to as the upper surface of the semiconductor substrate, and the lower end of the collector layer 8 is referred to as the lower surface of the semiconductor substrate. The upper surface and the lower surface are opposed to each other.

[0014] As shown in FIG. 1, an n-type carrier accumulation layer 5 having an n-type impurity concentration higher than that of the drift layer 6 is provided on the upper surface side of the n-type drift layer 6. Hereinafter, the carrier accumulation layer 5 is also referred to as a "CS layer".

[0015] A p-type base layer 4 is provided on the upper side of the carrier storage layer 5. An n-type source layer 3 is provided on the upper side of the base layer 4.

[0016] The semiconductor substrate is provided with a two-stage trench 10 that penetrates the source layer 3, the base layer 4, and the carrier storage layer 5 to reach the drift layer 6. The two-stage trench 10 has an upper electrode 11 in the upper stage and a lower electrode 12 in the lower stage inside the trench provided on the upper side of the semiconductor substrate. The upper electrode 11 is covered with an upper insulating film 13, and the lower electrode 12 is covered with a lower insulating film 14. The two-stage trench 10 also has a boundary insulating film 15 between the upper electrode 11 and the lower electrode 12. The upper electrode 11 and the lower electrode 12 are electrically isolated via the boundary insulating film 15.

[0017] The lower end of the upper electrode 11 is located above the lower end of the carrier storage layer 5, and below the vertical center of the carrier storage layer 5 (the "CS layer center" shown in Figure 1).

[0018] An interlayer insulating film 2 is provided on top of the two-stage trench 10. An emitter electrode 1 is provided on top of the source layer 3 and the interlayer insulating film 2.

[0019] An n-type buffer layer 7 with a higher n-type impurity concentration than the drift layer 6 is provided on the underside of the drift layer 6. A p-type collector layer 8 is provided on the underside of the buffer layer 7. A collector electrode 9 is provided on the underside of the collector layer 8.

[0020] Figure 2 is a diagram illustrating the high-electric-field region in the semiconductor device according to Embodiment 1. As shown in Figure 2, the lower end of the upper electrode 11 is located above the lower end of the carrier storage layer 5 and below the vertical center of the carrier storage layer 5 (center of the CS layer). Therefore, the third high-electric-field region does not overlap with either the first or second high-electric-field region. Consequently, the breakdown voltage of the semiconductor device can be improved as shown in Figure 3. Figure 3 is a diagram showing the relationship between the vertical direction of the upper electrode 11, the breakdown voltage (collector-emitter breakdown voltage), and the impurity concentration in the semiconductor device according to Embodiment 1. The hatched area in Figure 3 indicates the range in which the lower end of the upper electrode 11 is located. If the lower end of the upper electrode 11 is located within this range, the third high-electric-field region does not overlap with either the first or second high-electric-field region.

[0021] On the other hand, when the third high-electric-field region and the first high-electric-field region overlap (see Figure 4), or when the third high-electric-field region and the second high-electric-field region overlap (see Figure 5), the electric field becomes concentrated, causing the breakdown voltage of the semiconductor device to decrease.

[0022] In Figures 2, 4, and 5, the lower end of the second high-electric-field region is positioned to coincide with the lower end of the two-stage trench 10, but this is not the only position. The lower end of the second high-electric-field region may be located either above or below the lower end of the two-stage trench 10.

[0023] According to Embodiment 1, the lower end of the upper electrode 11 is located above the lower end of the carrier storage layer 5 and below the vertical center of the carrier storage layer 5. Therefore, the breakdown voltage (collector-emitter breakdown voltage) of the semiconductor device can be improved.

[0024] Furthermore, the influence of the second high-electric-field region caused by holes is particularly significant in IGBTs that use holes as carriers, and the breakdown voltage of the semiconductor device according to Embodiment 1, which is an IGBT, can be further improved.

[0025] <Example 1> Figure 6 is a cross-sectional view of a semiconductor device according to a modification 1 of Embodiment 1. As shown in Figure 6, the impurity concentration peak of the carrier storage layer 5 is located below the upper end of the carrier storage layer 5. Also, the lower end of the upper electrode 11 is located below the impurity concentration peak of the carrier storage layer 5.

[0026] According to Modification 1, the breakdown voltage of the semiconductor device can be improved by positioning the lower end of the upper electrode 11 (third high-electric field region) below the impurity concentration peak of the carrier storage layer 5, where a large amount of carriers accumulate and the electric field becomes high.

[0027] <Modification 2> Figure 7 is a cross-sectional view of a semiconductor device according to a modified example 2 of Embodiment 1. As shown in Figure 7, the length L2 between the lower end of the carrier storage layer 5 and the lower end of the two-stage trench 10 is shorter than the vertical length L1 of the carrier storage layer 5. It is desirable that L1 be at least twice the length of L2.

[0028] According to Modification 2, during turn-off, the hole density below the two-stage trench 10 increases due to the dynamic avalanche. Therefore, the electric field strength can be mitigated by bringing the lower end of the two-stage trench 10 closer to the carrier storage layer 5, where the electron density is high.

[0029] <Variation 3> Figure 8 is a cross-sectional view of a semiconductor device according to a modification 3 of Embodiment 1. As shown in Figure 8, the vertical length β of the lower electrode 12 is shorter than the vertical length α of the upper electrode 11.

[0030] According to Modification 3, the gate wiring resistance can be reduced by increasing the cross-sectional area of ​​the upper electrode 11 that contributes to the channel, and the breakdown voltage of the semiconductor device does not decrease by not increasing the depth of the two-stage trench 10 (the vertical length of the two-stage trench 10).

[0031] Furthermore, since the N-layer region formed on the sidewall of the two-stage trench 10 increases, the ON voltage of the semiconductor device can be reduced. This effect is particularly pronounced when combined with the semiconductor device configuration described in Modification 9, which will be discussed later. The N-layer region is the combined region of the inversion layer channel formed at the boundary between the base layer 4 and the two-stage trench 10 by minority carriers, and the region where the carrier storage layer 5 faces the upper electrode 11 via the upper insulating film 13 (n-type storage layer).

[0032] <Modification 4> Figure 9 is a cross-sectional view of a semiconductor device according to a modification 4 of Embodiment 1. As shown in Figure 9, the width D1 of the upper electrode 11 in the left-right direction is longer than the width D2 of the lower electrode 12 in the left-right direction. Here, the left-right direction refers to the direction perpendicular to the vertical direction of the semiconductor substrate.

[0033] Because the upper electrode 11 protrudes more in the left-right direction than the lower electrode 12 in a cross-sectional view, the electric field concentrates at the lower corner of the upper electrode 11, reducing the breakdown voltage of the semiconductor device.

[0034] According to Modification 4, the lower end of the upper electrode 11 is located above the lower end of the carrier storage layer 5 and below the vertical center of the carrier storage layer 5, thereby achieving a higher electric field relaxation effect and improving the breakdown voltage of the semiconductor device.

[0035] <Modification 5> Figures 10 and 11 are cross-sectional views of a semiconductor device according to a modification 5 of Embodiment 1. As shown in Figures 10 and 11, the upper electrode 11 has a pointed portion at its lower end. In the example of Figure 10, the upper electrode 11 has a pointed portion at the corner of its lower end. In the example of Figure 11, the upper electrode 11 has a pointed portion in the center of its lower end.

[0036] If the thickness of the lower insulating film 14 is greater than the thickness of the upper insulating film 13, a sharp point may form at the lower end corner of the upper electrode 11. At this sharp point, the electric field becomes more concentrated, reducing the breakdown voltage of the semiconductor device.

[0037] According to modification 5, the lower end of the upper electrode 11 is located above the lower end of the carrier storage layer 5 and below the vertical center of the carrier storage layer 5, thereby achieving a higher electric field relaxation effect and improving the breakdown voltage of the semiconductor device.

[0038] In the examples in Figures 10 and 11, the thickness of the lower insulating film 14 is shown to be thicker than the thickness of the upper insulating film 13. However, the thickness of the lower insulating film 14 and the upper insulating film 13 may be the same.

[0039] <Variation 6> Figure 12 is a cross-sectional view of a semiconductor device according to a modification 6 of Embodiment 1. As shown in Figure 12, the vertical length x of the base layer 4 at the interface with the two-stage trench 10 is shorter than the vertical length y of the base layer 4 at the center of the mesa portion. The mesa portion corresponds to the region between adjacent two-stage trenches 10.

[0040] According to modification 6, the distance between the interface between the base layer 4, which tends to become a high electric field, and the carrier storage layer 5, and the lower corner of the upper electrode 11 can be increased. As a result, the high electric field regions do not overlap, and the breakdown voltage of the semiconductor device can be improved.

[0041] Note that while Figure 12 shows an example where the upper electrode 11 has a pointed portion, this is not the only example. The configuration of the two-stage trench 10 may also be the configuration of the two-stage trench 10 shown in Modifications 1 to 4.

[0042] <Example 7> Figure 13 is a cross-sectional view of a semiconductor device according to Modification 7 of Embodiment 1. As shown in Figure 13, the semiconductor device according to Modification 7 includes a two-stage active trench 16 in which the upper electrode 11 and the lower electrode 12 are electrically connected to a gate electrode (not shown). That is, the two-stage trench 10 shown in Figure 1 includes the two-stage active trench 16.

[0043] According to Modification 7, by electrically connecting the lower electrode 12 to the gate electrode, an n-type storage layer can be formed at the trench interface around the lower electrode 12, thereby increasing the amount of electron injection. Furthermore, the electron density during turn-off can be increased, reducing the space charge and lowering the electric field in the second high-electric-field region, thus improving the breakdown voltage of the semiconductor device.

[0044] The configuration of the two-stage active trench 16 shown in Figure 13 may also be applied to the configuration of the two-stage trench 10 shown in Modifications 1 to 6.

[0045] <Differentiation Example 8> Figure 14 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 1. As shown in Figure 14, the semiconductor device according to Modification 8 includes a two-stage dummy active trench 17 in which the upper electrode 11 is electrically connected to the emitter electrode 1 and the lower electrode 12 is electrically connected to the gate electrode (not shown). That is, the two-stage trench 10 shown in Figure 1 includes the two-stage dummy active trench 17.

[0046] According to Modification 8, by electrically connecting the lower electrode 12 to the gate electrode, an n-type storage layer can be formed at the trench interface around the lower electrode 12, thereby increasing the amount of electron injection. Furthermore, the electron density during turn-off can be increased, reducing the space charge and lowering the electric field in the second high-electric-field region, thus improving the breakdown voltage of the semiconductor device.

[0047] Furthermore, by electrically connecting the upper electrode 11 to the emitter electrode 1, the potential of the mesa region around the upper electrode 11 can be lowered compared to the case where the upper electrode 11 is electrically connected to the gate electrode. In this way, by lowering the potential of the mesa region around the upper electrode 11, the electric field at the interface between the base layer 4 and the carrier storage layer 5 included in the first high electric field region can be further reduced, thereby improving the breakdown voltage of the semiconductor device.

[0048] The configuration of the two-stage dummy active trench 17 shown in Figure 14 may also be applied to the configuration of the two-stage trench 10 shown in Modifications 1 to 6. Furthermore, as shown in Figure 14, the semiconductor device may have a mixture of the two-stage dummy active trench 17 and the two-stage active trench 16 according to Modification 7.

[0049] <Modification 9> Figure 15 is a cross-sectional view of a semiconductor device according to modification 9 of Embodiment 1. As shown in Figure 15, the semiconductor device according to modification 9 includes a two-stage active dummy trench 18 in which the upper electrode 11 is electrically connected to the gate electrode (not shown) and the lower electrode 12 is electrically connected to the emitter electrode 1. That is, the two-stage trench 10 shown in Figure 1 includes the two-stage active dummy trench 18.

[0050] According to Modification 9, by electrically connecting the lower electrode 12 to the emitter electrode 1, the potential around the trench can be reduced, thereby mitigating the electric field and improving the breakdown voltage of the semiconductor device.

[0051] Furthermore, by reducing the feedback capacitance, the negative capacitance effect can be reduced, which is expected to improve the voltage withstand capability of the semiconductor device while avoiding oscillation during short-circuit current flow.

[0052] The configuration of the two-stage active dummy trench 18 shown in Figure 15 may also be applied to the configuration of the two-stage trench 10 shown in Modifications 1 to 6. Furthermore, the semiconductor device shown in Figure 15 mixes the two-stage active dummy trench 18 and the two-stage active trench 16 according to Modification 7, but is not limited to this. The semiconductor device may appropriately mix the two-stage active dummy trench 18, the two-stage dummy active trench 17 according to Modification 8, and the two-stage active trench 16 according to Modification 7.

[0053] <Variation 10> Figure 16 is a cross-sectional view of a semiconductor device according to a modified example 10 of Embodiment 1. As shown in Figure 16, the thickness L3 of the boundary insulating film 15 in the vertical direction is thicker than the thickness L4 of the upper insulating film 13 in the horizontal direction.

[0054] According to the modified example 10, in a configuration where the thinness of the film thickness L4 of the upper insulating film 13 is a concern and thus the breakdown voltage of the semiconductor device is likely to deteriorate, an improvement in the breakdown voltage of the semiconductor device can be expected.

[0055] <Variation 11> Figure 17 is a cross-sectional view of a semiconductor device according to a modified example 11 of Embodiment 1. As shown in Figure 17, the length h1 between adjacent two-stage trenches 10 is longer than the width h2 of the two-stage trenches 10 in the left-right direction.

[0056] According to modification 11, in a configuration where increasing the length h1 between adjacent two-stage trenches 10 increases the electric field concentration per trench and raises concerns about a decrease in breakdown voltage, an improvement in the breakdown voltage of the semiconductor device can be expected.

[0057] <Variation 12> Figure 18 is a cross-sectional view of a semiconductor device according to modified example 12 of Embodiment 1. As shown in Figure 18, the semiconductor device according to modified example 12 includes a first buffer layer 71 and a second buffer layer 72.

[0058] According to Modification 12, since the semiconductor substrate has multiple buffer layers (first buffer layer 71 and second buffer layer 72) on the lower side, the electric field on the lower side (collector electrode 9 side) decreases and the electric field on the upper side (upper side of source layer 3) increases, thereby improving the breakdown voltage of the semiconductor device.

[0059] <Example 13> Figures 19 and 20 show the impurity densities of each layer in a semiconductor device according to modification 13 of Embodiment 1. As shown in Figures 19 and 20, the semiconductor device according to modification 13 comprises multiple carrier storage layers. That is, the carrier storage layer 5 shown in Figure 1 includes multiple carrier storage layers. In the example in Figure 19, the impurity concentration peak of each carrier storage layer gradually decreases from the top side to the bottom side. In the example in Figure 20, the impurity concentration peak of each carrier storage layer gradually increases from the top side to the bottom side.

[0060] According to Modification 13, by providing multiple carrier storage layers to store more carriers, an improvement in the voltage withstand capability of the semiconductor device can be expected.

[0061] Furthermore, as shown in Figure 19, by making the impurity concentration of the carrier storage layer on the upper side higher than that of the carrier storage layer on the lower side, the carrier storage effect is increased, and the on-voltage of the semiconductor device can be reduced.

[0062] As shown in Figure 20, by making the impurity concentration of the carrier storage layer on the lower side higher than that of the carrier storage layer on the upper side, it is possible to avoid the lower end of the upper electrode 11, where the electric field tends to concentrate, overlapping with the carrier storage layer with a high impurity concentration, thereby improving the breakdown voltage of the semiconductor device.

[0063] <Example 14> In the semiconductor device according to Modification 14, the semiconductor substrate includes a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include SiC (silicon carbide), GaN (gallium nitride), and Ga2O3 (gallium oxide).

[0064] Wide-bandgap semiconductors tend to have higher electric field strengths compared to silicon (Si). According to Modification 14, a greater electric field relaxation effect can be obtained, thus improving the breakdown voltage of semiconductor devices.

[0065] <Variation 15> Figure 21 is a cross-sectional view of a semiconductor device according to a modified example 15 of Embodiment 1. As shown in Figure 21, the semiconductor device according to modified example 15 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) comprising a drain layer 20 provided on the lower side of a semiconductor substrate, a drain electrode 21 provided on the lower side of the drain layer 20, and a source electrode 19 provided so as to cover the interlayer insulating film 2 and the source layer 3.

[0066] According to Modification 15, even when the semiconductor device is a MOSFET, the same electric field relaxation effect as the semiconductor device (IGBT) according to Embodiment 1 can be obtained.

[0067] Furthermore, because a Hall current flows when the parasitic body diode operates, the electric field in the second high-field region can be reduced, although not to the same extent as with IGBTs.

[0068] <Variation 16> Figure 22 is a cross-sectional view of a semiconductor device according to a modified example 16 of Embodiment 1. As shown in Figure 22, the position X of the impurity concentration peak of the carrier storage layer 5 from the upper surface of the source layer 3 is above the center position Z of the vertical length Y of the carrier storage layer 5. That is, the impurity concentration peak of the carrier storage layer 5 is located above the center position of the carrier storage layer 5 in the vertical direction.

[0069] According to modification 16, since the hole accumulation region is above the third high-electric-field region, the electric field concentration in the third high-electric-field region is mitigated, and the breakdown voltage of the semiconductor device can be improved.

[0070] <Example 17> Figure 23 is a cross-sectional view of a semiconductor device according to a modified example 17 of Embodiment 1. As shown in Figure 23, the position X of the impurity concentration peak of the carrier storage layer 5 from the upper surface of the source layer 3 is below the center position Z of the vertical length Y of the carrier storage layer 5. That is, the impurity concentration peak of the carrier storage layer 5 is located below the center position of the carrier storage layer 5 in the vertical direction.

[0071] According to modification 17, the impurity concentration peak of the carrier storage layer 5 can be moved away from the interface between the base layer 4 and the carrier storage layer 5. Therefore, the electric field concentration in the first high electric field region is mitigated, and the breakdown voltage of the semiconductor device can be improved.

[0072] <Variation 18> Figure 24 is a cross-sectional view of a semiconductor device according to modified example 18 of Embodiment 1. As shown in Figure 24, the semiconductor device according to modified example 18 is an RC-IGBT (Reverse Conducting IGBT) comprising an IGBT region including a collector layer 8 provided on the lower side of a semiconductor substrate, and a diode region including a cathode layer 23 provided on the lower side of a semiconductor substrate and an anode layer 22 provided on the upper side of a semiconductor substrate.

[0073] The influence of the second high-electric-field region caused by holes is particularly large in IGBTs that use holes as carriers. According to Modification 18, the breakdown voltage in the IGBT region can be further improved.

[0074] Furthermore, electric field concentration tends to occur at the boundary between the diode region and the IGBT region, but in the RC-IGBT according to Modification 18, such electric field concentration can be mitigated.

[0075] <Modification Example 19> Figure 25 is a cross-sectional view of a semiconductor device according to a modified example 19 of Embodiment 1. As shown in Figure 25, the semiconductor device according to modified example 19 includes a single-stage trench 24. The single-stage trench 24 has a single gate electrode 25 inside the trench, which is provided penetrating the source layer 3, base layer 4, and carrier storage layer 5 on the upper surface side of the semiconductor substrate.

[0076] The semiconductor device according to Modification 19 includes a two-stage trench 10 in addition to the one-stage trench 24. The configuration of this two-stage trench 10 may be the same as that shown in Modifications 1 to 11, 16, and 17. Furthermore, the configuration of the semiconductor device according to Modification 19 may be the same as that shown in Modifications 12 to 15 and 18.

[0077] According to modification 19, by providing a single-stage trench 24 in which the third high-electric-field region does not exist, the breakdown voltage reduction that is characteristic of semiconductor devices equipped with a two-stage trench 10 can be suppressed.

[0078] <Modification 20> Figure 26 is a cross-sectional view of a semiconductor device according to a modified example 20 of Embodiment 1. As shown in Figure 26, the semiconductor device according to the modified example 20 includes a dummy trench 26. The dummy trench 26 has a dummy electrode 27 inside a trench that penetrates the source layer 3, base layer 4, and carrier storage layer 5 on the upper surface side of the semiconductor substrate. The dummy electrode 27 is electrically connected to the emitter electrode.

[0079] The semiconductor device according to Modification 20 includes a two-stage trench 10 in addition to the dummy trench 26. The configuration of this two-stage trench 10 may be the same as that shown in Modifications 1 to 11, 16, and 17. Furthermore, the configuration of the semiconductor device according to Modification 20 may be the same as that shown in Modifications 12 to 15 and 18.

[0080] According to Modification 20, by providing a dummy trench 26, the potential around the trench can be reduced, thereby mitigating the electric field and improving the breakdown voltage of the semiconductor device. Furthermore, since the number of trenches is not reduced, electric field concentration caused by a reduction in the number of trenches is less likely to occur.

[0081] <Variation 21> Figure 27 is a cross-sectional view of a semiconductor device according to a modified example 21 of Embodiment 1. As shown in Figure 27, the upper electrode 11 in the two-stage trench 28 is a control gate electrode electrically connected to the control gate potential. The control gate potential is a different potential from the gate potential used to turn the semiconductor device ON or OFF. By removing or injecting carriers at any timing via the control electrode, the switching loss of the semiconductor device can be reduced.

[0082] In the example shown in Figure 27, the upper electrode 11 is used as the control gate electrode, but the lower electrode 12 may also be used as the control gate electrode. In other words, it is sufficient for at least one of the upper electrode 11 and the lower electrode 12 to be the control gate electrode.

[0083] The semiconductor device according to Modification 21 includes a two-stage trench 10 that does not have a control gate electrode. The configuration of this two-stage trench 10 may be the same as the two-stage trench 10 shown in Modifications 1 to 11, 16, and 17. Furthermore, the configuration of the semiconductor device according to Modification 21 may be the same as the semiconductor device shown in Modifications 12 to 15 and 18.

[0084] According to Modification 21, by providing a control electrode, carriers can be properly discharged, so the carrier concentration in the carrier accumulation layer 5 can be increased, and such a design is more effective in maintaining pressure resistance.

[0085] <Embodiment 2> Figure 28 is a plan view of the power module 30 according to Embodiment 2. As shown in Figure 28, the power module 30 according to Embodiment 2 includes a control unit 31 and a power unit 32.

[0086] The control unit 31 corresponds to an IC (Integrated Circuit) chip and controls the power unit 32. Therefore, the power module 30 equipped with the control unit 31 is also called an intelligent power module.

[0087] The power unit 32 corresponds to a semiconductor device according to Embodiment 1 and any of the modifications 1 to 21.

[0088] The control unit 31 and the power unit 32 are sealed with molded resin or gel.

[0089] According to Embodiment 2, the voltage withstand capability of the power module can be improved by providing a semiconductor device according to Embodiment 1 or any of the modifications 1 to 21 as the power unit 32.

[0090] Within the scope of this disclosure, it is possible to freely combine the embodiments, or to modify or omit the embodiments as appropriate.

[0091] <Note> The various aspects of this disclosure are summarized below as an appendix.

[0092] (Note 1) Semiconductor substrate and A base layer provided on the upper surface side of the semiconductor substrate, A carrier storage layer is provided below the base layer, Inside a trench provided on the upper surface side of the semiconductor substrate, penetrating the base layer and the carrier storage layer, there is at least one two-stage trench having an upper electrode in the upper stage and a lower electrode in the lower stage, Equipped with, A semiconductor device in which the lower end of the upper electrode is located above the lower end of the carrier storage layer and below the vertical center of the carrier storage layer.

[0093] (Note 2) The impurity concentration peak in the carrier accumulation layer is located below the upper end of the carrier accumulation layer. The semiconductor device according to Appendix 1, wherein the lower end of the upper electrode is located below the impurity concentration peak of the carrier accumulation layer.

[0094] (Note 3) The semiconductor device according to Appendix 1 or 2, wherein the length between the lower end of the carrier storage layer and the lower end of the two-stage trench is shorter than the vertical length of the carrier storage layer.

[0095] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein the vertical length of the lower electrode is shorter than the vertical length of the upper electrode.

[0096] (Note 5) The semiconductor device according to any one of the appendices 1 to 4, wherein the width of the upper electrode in the left-right direction is longer than the width of the lower electrode in the left-right direction.

[0097] (Note 6) The semiconductor device according to any one of the appendices 1 to 5, wherein the upper electrode has a pointed portion at its lower end.

[0098] (Note 7) The semiconductor device according to any one of the appendices 1 to 6, wherein the vertical length of the base layer at the interface with the two-stage trench is shorter than the vertical length of the base layer at the center of the mesa portion.

[0099] (Note 8) The semiconductor device according to any one of appendices 1 to 7, wherein the two-stage trench includes a two-stage active trench in which the upper electrode and the lower electrode are electrically connected to the gate electrode.

[0100] (Note 9) The semiconductor device according to any one of appendices 1 to 8, wherein the two-stage trench includes a two-stage dummy active trench in which the upper electrode is electrically connected to the emitter electrode and the lower electrode is electrically connected to the gate electrode.

[0101] (Note 10) The semiconductor device according to any one of appendices 1 to 9, wherein the two-stage trench includes a two-stage active dummy trench in which the upper electrode is electrically connected to the gate electrode and the lower electrode is electrically connected to the emitter electrode.

[0102] (Note 11) The two-stage trench has an upper insulating film covering the upper electrode and a boundary insulating film located between the upper electrode and the lower electrode. The semiconductor device according to any one of appendices 1 to 10, wherein the thickness of the boundary insulating film in the vertical direction is greater than the thickness of the upper insulating film in the horizontal direction.

[0103] (Note 12) A semiconductor device according to any one of the appendices 1 to 11, wherein the length between adjacent two-stage trenches is longer than the width of the two-stage trenches in the left-right direction.

[0104] (Note 13) The semiconductor device according to any one of the appendices 1 to 12, further comprising a plurality of buffer layers on the lower surface side of the semiconductor substrate.

[0105] (Note 14) A semiconductor device according to any one of the appendices 1 to 13, which is an IGBT (Insulated Gate Bipolar Transistor) having a collector layer provided on the lower surface side of the semiconductor substrate.

[0106] (Note 15) A semiconductor device according to any one of appendices 1 to 14, comprising a plurality of carrier storage layers.

[0107] (Note 16) The semiconductor substrate is a semiconductor device according to any one of the appendices 1 to 15, including a wide-bandgap semiconductor.

[0108] (Note 17) A semiconductor device according to any one of the appendices 1 to 16, which is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain layer provided on the lower side of the semiconductor substrate.

[0109] (Note 18) The semiconductor device according to any one of appendices 1 to 17, wherein the impurity concentration peak of the carrier storage layer is located above the vertical center position of the carrier storage layer.

[0110] (Note 19) The semiconductor device according to any one of appendices 1 to 17, wherein the impurity concentration peak of the carrier storage layer is located below the vertical center position of the carrier storage layer.

[0111] (Note 20) A semiconductor device according to any one of the appendices 1 to 19, which is an RC-IGBT (Reverse Conducting IGBT) comprising an IGBT region including a collector layer provided on the lower side of the semiconductor substrate and a diode region including a cathode layer provided on the lower side of the semiconductor substrate.

[0112] (Note 21) The semiconductor device according to any one of appendices 1 to 20, further comprising at least one single-stage trench having one electrode inside a trench provided on the upper surface side of the semiconductor substrate, penetrating the base layer and the carrier storage layer.

[0113] (Note 22) The semiconductor device according to Appendix 21, wherein the aforementioned one-stage trench includes a dummy trench in which the electrode is electrically connected to the emitter electrode.

[0114] (Note 23) The semiconductor device according to any one of Appendix 1 to 22, wherein at least one of the upper electrode and the lower electrode is a control gate electrode electrically connected to the control gate potential.

[0115] (Note 24) A power module comprising a semiconductor device described in any one of the appendices 1 to 23.

[0116] (Note 25) The power module described in Appendix 24 further comprises a molded resin or gel.

[0117] (Note 26) A power module as described in Appendix 24 or 25, further comprising an IC (Integrated Circuit) chip. [Explanation of Symbols]

[0118] 1 Emitter electrode, 2 Interlayer insulating film, 3 Source layer, 4 Base layer, 5 Carrier storage layer, 6 Drift layer, 7 Buffer layer, 8 Collector layer, 9 Collector electrode, 10 Two-stage trench, 11 Upper electrode, 12 Lower electrode, 13 Upper insulating film, 14 Lower insulating film, 15 Boundary insulating film, 16 Two-stage active trench, 17 Two-stage dummy active trench, 18 Two-stage active dummy trench, 19 Source electrode, 20 Drain layer, 21 Drain electrode, 22 Anode layer, 23 Cathode layer, 24 One-stage trench, 25 Gate electrode, 26 Dummy trench, 27 Dummy electrode, 28 Two-stage trench, 29 Control gate electrode, 30 Power module, 31 Control unit, 32 Power unit, 71 First buffer layer, 72 Second buffer layer.

Claims

1. Semiconductor substrate and A base layer provided on the upper surface side of the semiconductor substrate, A carrier storage layer is provided below the base layer, Inside a trench provided on the upper surface side of the semiconductor substrate, penetrating the base layer and the carrier storage layer, there is at least one two-stage trench having an upper electrode in the upper stage and a lower electrode in the lower stage, Equipped with, A semiconductor device in which the lower end of the upper electrode is located above the lower end of the carrier storage layer and below the vertical center of the carrier storage layer.

2. The impurity concentration peak in the carrier accumulation layer is located below the upper end of the carrier accumulation layer. The semiconductor device according to claim 1, wherein the lower end of the upper electrode is located below the impurity concentration peak of the carrier accumulation layer.

3. The semiconductor device according to claim 1, wherein the length between the lower end of the carrier storage layer and the lower end of the two-stage trench is shorter than the vertical length of the carrier storage layer.

4. The semiconductor device according to claim 1, wherein the vertical length of the lower electrode is shorter than the vertical length of the upper electrode.

5. The semiconductor device according to claim 1, wherein the width of the upper electrode in the left-right direction is longer than the width of the lower electrode in the left-right direction.

6. The semiconductor device according to claim 1, wherein the upper electrode has a pointed portion at its lower end.

7. The semiconductor device according to claim 1, wherein the vertical length of the base layer at the interface with the two-stage trench is shorter than the vertical length of the base layer at the center of the mesa portion.

8. The semiconductor device according to claim 1, wherein the two-stage trench includes a two-stage active trench in which the upper electrode and the lower electrode are electrically connected to the gate electrode.

9. The semiconductor device according to claim 1, wherein the two-stage trench includes a two-stage dummy active trench in which the upper electrode is electrically connected to the emitter electrode and the lower electrode is electrically connected to the gate electrode.

10. The semiconductor device according to claim 1, wherein the two-stage trench includes a two-stage active dummy trench in which the upper electrode is electrically connected to the gate electrode and the lower electrode is electrically connected to the emitter electrode.

11. The two-stage trench has an upper insulating film covering the upper electrode and a boundary insulating film located between the upper electrode and the lower electrode. The semiconductor device according to claim 1, wherein the thickness of the boundary insulating film in the vertical direction is thicker than the thickness of the upper insulating film in the horizontal direction.

12. The semiconductor device according to claim 1, wherein the length between adjacent two-stage trenches is longer than the width of the two-stage trenches in the left-right direction.

13. The semiconductor device according to claim 1, further comprising a plurality of buffer layers on the lower surface side of the semiconductor substrate.

14. The semiconductor device according to claim 1, wherein the IGBT (Insulated Gate Bipolar Transistor) comprises a collector layer provided on the lower surface side of the semiconductor substrate.

15. The semiconductor device according to claim 1, comprising a plurality of carrier storage layers.

16. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a wide-bandgap semiconductor.

17. The semiconductor device according to claim 1, which is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a drain layer provided on the lower side of the semiconductor substrate.

18. The semiconductor device according to claim 1, wherein the impurity concentration peak of the carrier storage layer is located above the vertical center position of the carrier storage layer.

19. The semiconductor device according to claim 1, wherein the impurity concentration peak of the carrier storage layer is located below the vertical center position of the carrier storage layer.

20. The semiconductor device according to claim 1, which is an RC-IGBT (Reverse Conducting IGBT) comprising an IGBT region including a collector layer provided on the lower side of the semiconductor substrate and a diode region including a cathode layer provided on the lower side of the semiconductor substrate.

21. The semiconductor device according to claim 1, further comprising at least one single-stage trench having one electrode inside a trench provided on the upper surface side of the semiconductor substrate, penetrating the base layer and the carrier storage layer.

22. The semiconductor device according to claim 21, wherein the one-stage trench includes a dummy trench in which the electrode is electrically connected to the emitter electrode.

23. The semiconductor device according to claim 1, wherein at least one of the upper electrode and the lower electrode is a control gate electrode electrically connected to the control gate potential.

24. A power module comprising a semiconductor device according to any one of claims 1 to 23.

25. The power module according to claim 24, further comprising a molded resin or gel.

26. The power module according to claim 25, further comprising an IC (Integrated Circuit) chip.

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