Power supply device

Abstract

This disclosure provides a power supply device that can suppress malfunctions in the switching section. [Solution] The switching unit 11 is connected between an input terminal Tin and an output terminal Tout, and the switching unit 12 is connected between a reference potential terminal Tst1, whose absolute potential is lower than the potential of the first input terminal Tin, and the output terminal Tout, wherein in a series of switching operations, the on period of the first switching operation of the switching unit 11 is longer than the on period of the second and subsequent switching operations.

Description

Technical Field

[0001] The present disclosure relates to a power supply device.

Background Art

[0002] In a power supply device composed of a half-bridge, for example, when the low-side switching part is turned on, a high current flows through the switching part to the output terminal, and when the low-side switching part is turned off, the voltage of the output terminal may change steeply (see, for example, Patent Document 1). This switching operation is called hard switching.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a power supply device composed of a half-bridge, pulse density modulation control may be performed in which a plurality of consecutive switching operations and their pauses are alternately repeated. In continuous switching operations, the low-side switching part and the high-side switching part alternately turn on and off complementarily.

[0005] In a power supply device, the first switching operation in pulse density modulation control becomes hard switching due to the turn-on of the low-side switching part, and ringing is likely to occur at both ends of the high-side switching part. If the low-side switching part turns off and the high-side switching part turns on before this ringing decays, ringing with high-frequency noise superimposed on the voltage at both ends of the low-side switching part is likely to occur. At this time, if the degree of ringing is large, the low-side switching part may malfunction, and in some cases, the output performance of the power supply device may deteriorate.

[0006] This disclosure provides a power supply device that can suppress malfunctions in the switching section. [Means for solving the problem]

[0007] The power supply device according to this disclosure includes a first switching unit connected between an input terminal and an output terminal, and a second switching unit connected between a reference potential terminal, the absolute value of which is lower than the potential of the first input terminal, and the output terminal, wherein in a series of switching operations, the on-period of the first switching operation is longer than the on-period of the second and subsequent switching operations. [Effects of the Invention]

[0008] The power supply device described herein can suppress malfunctions in the switching section. [Brief explanation of the drawing]

[0009] [Figure 1] A circuit diagram showing the schematic configuration of the power supply device according to the embodiment. [Figure 2] A circuit diagram showing the configuration of the switching section in the embodiment. [Figure 3] Waveform diagram showing the operation of the switching section in the embodiment. [Figure 4] Waveform diagram showing the output voltage of the power supply in the embodiment. [Figure 5] A waveform diagram showing the operation of the switching section in a first modified example of the embodiment. [Figure 6] A circuit diagram showing the schematic configuration of a power supply device according to a second modified embodiment. [Modes for carrying out the invention]

[0010] Hereinafter, embodiments of the power supply device according to this disclosure will be described with reference to the drawings.

[0011] (Embodiment) In the power supply according to this embodiment, when the low-side switching unit is turned off, the voltage at the output terminal changes abruptly in a switching operation, but measures are taken to suppress malfunctions of the switching unit.

[0012] The power supply unit 1 may be configured as shown in Figure 1. Figure 1 is a circuit diagram showing the schematic configuration of the power supply unit 1.

[0013] Power supply unit 1 is connected between the voltage source E and the load LD. Power supply unit 1 generates power corresponding to the voltage of the voltage source E and supplies it to the load LD. Power supply unit 1 may also perform a switching operation using the voltage of the voltage source E to convert the power corresponding to the voltage of the voltage source E to power corresponding to the output voltage Vout, and supply the converted power to the load LD.

[0014] Power supply unit 1 is configured as a 2-input, 2-output half-bridge, and has an input terminal Tin, an input-side reference potential terminal Tst1, an output terminal Tout, and an output-side reference potential terminal Tst2. Note that the input-side reference potential terminal Tst1 and the output-side reference potential terminal Tst2 are at the same potential. Therefore, both are collectively referred to as the reference potential terminal Tst.

[0015] Furthermore, the input terminal Tin, the input-side reference potential terminal Tst1, the output terminal Tout, and the output-side reference potential terminal Tst2 may be part of the electrical wiring or electrodes, etc.

[0016] Voltage source E generates a voltage E. The high-potential side of voltage source E is connected to a reference potential GND (e.g., ground potential) and an input-side reference potential terminal Tst1 via a reference node Nst, and the low-potential side is connected to an input terminal Tin. As a result, power supply unit 1 receives a negative voltage -E at input terminal Tin, with reference to the reference potential GND received at input-side reference potential terminal Tst1. The negative voltage -E may be, for example, -12kV.

[0017] The load LD has one end LDa connected to the output side reference potential terminal Tst2, and the other end LDb connected to the output terminal Tout. As a result, the load LD receives the reference potential GND from the output side reference potential terminal Tst2 and the output voltage Vout from the output terminal Tout. Consequently, the load LD receives power corresponding to the output voltage Vout, which is referenced to the reference potential GND.

[0018] The power supply unit 1 includes a switching unit 11, a switching unit 12, a timing signal output unit 13, a driver unit 14, and a driver unit 15.

[0019] In this embodiment, the switching unit 11 is an example of the first switching unit of the present invention, and the switching unit 12 is an example of the second switching unit of the present invention.

[0020] The switching unit 11 is connected between the input terminal Tin and the output terminal Tout. The low-potential side of the switching unit 11 is connected to the low-potential side of the voltage source E via the input terminal Tin. The switching unit 11 is also called the low-side switching unit. Each control terminal of the switching unit 11 is connected to the timing signal output unit 13 via the drive circuit of the driver unit 14, which will be described later. The high-potential side of the switching unit 11 is connected to the load LD via the intermediate node Nmid and the output terminal Tout.

[0021] The switching unit 12 is connected between the input-side reference potential terminal Tst1 and the output terminal Tout. The high-potential side of the switching unit 12 is connected to the high-potential side of the voltage source E via the input-side reference potential terminal Tst1. The switching unit 12 is also called the high-side switching unit. Each control terminal of the switching unit 12 is connected to the timing signal output unit 13 via the drive circuit of the driver unit 15, which will be described later. The low-potential side of the switching unit 12 is connected to the load LD via the intermediate node Nmid and the output terminal Tout.

[0022] The intermediate node Nmid is the connection point between switching unit 11 and switching unit 12. Therefore, switching unit 12 and switching unit 11 are connected between the high-potential side and the low-potential side of the voltage source E via the intermediate node Nmid.

[0023] The timing signal output unit 13 is connected to the driver unit 14 and the driver unit 15, respectively. The timing signal output unit 13 is connected to the driver unit 14 via signal line L1. The driver unit 14 is connected to the switching unit 11. The timing signal output unit 13 is connected to the driver unit 15 via signal line L2. The driver unit 15 is connected to the switching unit 12.

[0024] As a result, the power supply unit 1 can control the switching operation of the switching unit 11 and the switching unit 12 using timing signals output from the timing signal output unit 13 in response to control signals from a higher-level controller (not shown).

[0025] The timing signal output unit 13 outputs the timing signal DP to the driver unit 14. L It supplies a timing signal DP to the driver unit 15. H To supply.

[0026] The switching unit 11 has one or more switching elements SW. The switching unit 11 may have n switching elements SW_1 to SW_n, as shown in Figure 2. Figure 2 is a circuit diagram showing the configuration of the switching units 11 and 12. n is any integer of 2 or more. n can be determined experimentally in advance depending on the driving capability required of the switching unit 11. For example, n may be 8.

[0027] n switching elements SW_1 to SW_n may be connected in series between the intermediate node Nmid and the input terminal Tin. Each switching element SW has its high-potential side connected to the intermediate node Nmid or an adjacent switching element SW on the intermediate node Nmid side, and its low-potential side connected to the input terminal Tin or an adjacent switching element SW on the input terminal Tin side.

[0028] The driver unit 14 has a drive circuit corresponding to the switching element SW of the switching unit 11. Each drive circuit of the driver unit 14 receives a timing signal DP from the timing signal output unit 13. L Accordingly, a drive signal is applied to each switching element in the switching unit 11 to perform a switching operation that turns the switching elements on or off.

[0029] Each control terminal of the n switching elements SW_1 to SW_n is connected to the corresponding drive circuit of the driver unit 14 via a dedicated signal line.

[0030] Each drive circuit of the driver unit 14 receives the timing signal DP output from the timing signal output unit 13. L This is input. In this case, n signal lines (8 in the case of Figure 2) are required to connect the timing signal output unit 13 and the driver unit 14, but in Figure 2, in order to simplify the drawing, these are shown together as signal line L1.

[0031] With the configuration described above, n switching elements SW_1 to SW_n can be switched on and off simultaneously, or at different timings. Note that when switching n switching elements SW_1 to SW_n simultaneously, a common timing signal DP is used, as shown in Figure 2. L The timing signal DP should be supplied from the timing signal output unit 13 to the n drive circuits. The n drive circuits will receive the timing signal DP. LA drive signal may be supplied to the control terminals of the corresponding n switching elements SW_1 to SW_n according to the situation. When turning on and off at different timings, a dedicated timing signal may be supplied from the timing signal output unit 13 to the n drive circuits. The n drive circuits are the timing signal DP L A drive signal may be supplied to the control terminals of the corresponding n switching elements SW_1 to SW_n according to the situation. In the following, the common timing signal DP L is used as an example for explanation.

[0032] The switching unit 12 has one or more switching elements SW. The switching unit 12 may have m switching elements SW_n+1 to SW_n+m. m is an arbitrary integer of 2 or more. m may be equal to n or different. m can be determined experimentally in advance according to the driving ability required for the switching unit 12. For example, m = 8 may be used.

[0033] The m switching elements SW_n+1 to SW_n+m may be connected in series between the input-side reference potential terminal Tst1 and the intermediate node Nmid. Each switching element SW has its high potential side connected to the input-side reference potential terminal Tst1 or the adjacent switching element SW on the input-side reference potential terminal Tst1 side, and its low potential side connected to the intermediate node Nmid or the adjacent switching element SW on the intermediate node Nmid side.

[0034] The driver unit 15 has drive circuits corresponding to the switching elements SW of the switching unit 12. Each drive circuit of the driver unit 15 performs a switching operation of applying a drive signal to each switching element in the switching unit 11 according to the timing signal DP H given from the timing signal output unit 13 to turn on or off the switching element.

[0035] The control terminals of the m switching elements SW_n+1 to SW_n+m are respectively connected to the corresponding drive circuits of the driver unit 15 via dedicated signal lines.

[0036] Each drive circuit of the driver unit 15 receives the timing signal DP output from the timing signal output unit 13. H This is input. In this case, n signal lines (8 in the case of Figure 2) are required to connect the timing signal output unit 13 and the driver unit 15, but in Figure 2, in order to simplify the drawing, these are shown together as signal line L2.

[0037] With the configuration described above, m switching elements SW_n+1 to SW_n+m can be switched on and off simultaneously, or at different timings. Note that when switching m switching elements SW_n+1 to SW_n+m simultaneously, a common timing signal DP is used, as shown in Figure 2. H The timing signal DP should be supplied from the timing signal output unit 13 to m drive circuits. The m drive circuits will receive the timing signal DP. H Depending on the situation, drive signals should be supplied to the corresponding m control terminals of the switching elements SW_n+1 to SW_n+m. If the elements are to be switched on and off at different timings, a dedicated timing signal should be supplied from the timing signal output unit 13 to the m drive circuits. The m drive circuits are controlled by the timing signal DP. H The corresponding m switching elements SW_n+1 to SW_n+m should be supplied to their respective control terminals. Below, a common timing signal DP is used. H Let's explain using the example of [this method].

[0038] Each switching element SW can be any element capable of switching operation. Each switching element SW may be, for example, a field-effect transistor (FET), an insulated-gate bipolar transistor (IGBT), or other semiconductor switches.

[0039] Figure 2 illustrates the case where each switching element SW is an N-type field-effect transistor. In this case, the source of each switching element SW constitutes the low-potential terminal, the drain constitutes the high-potential terminal, and the gate constitutes the control terminal. Each switching element SW is equivalently connected between the source and drain with a parasitic diode whose forward direction is from source to drain.

[0040] The switching element SW of the switching unit 11 receives the drive signals output from each drive circuit of the driver unit 14 at its control terminal, thereby receiving the timing signal DP. L It is switched on and off accordingly. As a result, the switching unit 11 performs a switching operation.

[0041] The switching element SW of the switching unit 12 receives the drive signals output from each drive circuit of the driver unit 14 at its control terminal, thereby receiving the timing signal DP. H It is switched on and off accordingly. As a result, the switching unit 12 performs a switching operation.

[0042] Here, the switching unit 11 and the switching unit 12 repeatedly switch on and off complementaryly at a predetermined first frequency (for example, 400 kHz). That is, the switching unit 11 and the switching unit 12 each alternately switch between an on state and an off state, and an off state and an on state, at the first frequency which is the switching operating frequency.

[0043] The timing signal output unit 13 outputs the timing signal DP L DP H By supplying this, pulse density modulation control may be performed on each of the switching units 11 and 12.

[0044] For example, the switching element SW of switching unit 11 and the switching element SW of switching unit 12 perform the operation shown in Figure 3 in response to pulse density modulation control by the timing signal output unit 13. In pulse density modulation control, multiple continuous switching operations and their pauses are repeated alternately. The operation in pulse density modulation control can also be considered as an operation that performs intermittent power conversion. Figure 3 shows waveforms that illustrate the operation of switching units 11 and 12. Switching units 11 and 12 may alternately repeat multiple continuous switching operations and their pauses for each period SP_0 to SP_3. Figure 3 shows four examples of periods SP_0 to SP_3. The period SP may be approximately constant. The period SP corresponds to a predetermined second frequency. The second frequency may be, for example, 2 kHz.

[0045] The period during which multiple consecutive switching operations occur within a period SP will be called the continuous operation period OT. The period during which switching operations are paused within a period SP will be called the pause period RT.

[0046] Specifically, the switching unit 11 and the switching unit 12 perform a switching operation in which they complementarily turn on and turn off at a first frequency (e.g., 400kHz) that is higher than the second frequency, during a continuous operation period OT defined by a predetermined on-duty ratio (e.g., 50%) during a repeating period of a predetermined second frequency (e.g., 2kHz). At the same time, both the switching unit 11 and the switching unit 12 suspend their switching operations during a pause period RT defined by a predetermined off-duty ratio (e.g., 50%). The on-duty ratio is the ratio expressed as continuous operation period OT / (continuous operation period OT + pause period RT), and the off-duty ratio is the ratio expressed as pause period RT / (continuous operation period OT + pause period RT).

[0047] In the manufacturing process of semiconductor manufacturing equipment, the output control described above is sometimes called pulse density modulation control (PDM).

[0048] The repetition period SP during pulse density modulation control includes a continuous operation period OT and a pause period RT. The continuous operation period OT begins at the beginning of the period SP and ends in the middle of the period SP. The pause period RT follows the continuous operation period OT. The pause period RT begins in the middle of the period SP and ends at the end of the period SP.

[0049] As described above, the switching unit 11 and the switching unit 12 repeatedly switch on and off in a complementary manner during the continuous operation period OT. This allows the switching unit 11 and the switching unit 12 to perform multiple continuous switching operations. The switching unit 11 and the switching unit 12 operate under a period T. SW_1 ~T SW_4 The switching operation may be repeated each time. In Figure 3, there are four periods T SW_1 ~T SW_4 Examples are given.

[0050] Note that in Figure 3, the timing signal DP is used for ease of explanation. H and timing signal DP L Because the diagram illustrates the time axis, it differs from the actual time axis. For example, if the first frequency is 400 kHz, the second frequency is 2 kHz, and the on-duty ratio defining the continuous operation period OT is 50%, then the switching unit 11 and the switching unit 12 will perform 100 switching operations during the continuous operation period OT. However, Figure 3 illustrates it as if only 4 switching operations are performed.

[0051] Each period T SW This refers to the ON period T of the switching section 11 on the low side. L and the ON period T of the high-side switching section 12 H This includes the on-period T. L and ON period T HA dead time may be provided between these two states. During the dead time, both switching unit 11 and switching unit 12 are turned off. This prevents both switching unit 11 and switching unit 12 from being turned on at the same time, thus avoiding the flow of overcurrent. In Figure 3, the illustration of the dead time is omitted for simplicity.

[0052] Here, the first period T in each continuous operation period OT SW_1 Then, from a state where both switching units 11 and 12 were off, the low-side switching unit 11 is selectively turned on. The initial switching operation by the low-side switching unit 11 is hard switching, which easily causes high-frequency ringing across the voltage across the high-side switching unit 12, and as shown in Figure 4, ringing is likely to occur in the voltage Vout at the output terminal Tout. If the low-side switching unit 11 turns off and the high-side switching unit 12 turns on before this ringing attenuates, high-frequency noise of even higher frequencies is likely to be superimposed on the voltage across the low-side switching unit 11, causing further ringing. In this case, if the degree of ringing is large, the low-side switching unit may malfunction, and in some cases, the output performance of the power supply unit may decrease.

[0053] Therefore, in this embodiment, the power supply unit 1 ensures sufficient ringing decay time and suppresses malfunctions of the switching unit 11 by making the on-period of the first switching operation by the switching unit 11 longer than the on-period of the second and subsequent switching operations.

[0054] For example, the period T of multiple consecutive switching operations in each continuous operation period OT SW_1 ~T SW_4These may be equal to each other. In this case, as shown in Figure 3, the timing signal output unit 13 may perform pulse density modulation control such that, in a series of switching operations of the low-side switching unit 11, the duty cycle of the first switching operation is greater than the duty cycle of the second and subsequent switching operations. The duty cycles of the second and subsequent switching operations may be equal to each other. That is, the timing signal output unit 13 may perform pulse density modulation control that satisfies the following equations 1 and 2. T SW_1 ≒T SW_2 ≒T SW_3 ≒T SW_4 ...Formula 1 T L_1 / T SW_1 >T L_2 / T SW_2 ≒T L_3 / T SW_3 ≒T L_4 / T SW_4 ...Formula 2

[0055] This makes it possible to make the on-period of the first switching operation by the switching unit 11 longer than the on-period of the second and subsequent switching operations. In other words, by performing pulse density modulation control that satisfies equations 1 and 2, the following equation 3 can be obtained. T L_1 >T L_2 ≒T L_3 ≒T L_4 ...Equation 3

[0056] As long as equation 3 holds true, a ringing decay time TP_1 can be secured, as shown in Figure 4, and the high-side switching unit 12 can be turned on after the decay time TP_1 has ended. The decay time TP_1 is the time from when ringing occurs until the magnitude of the ringing (for example, the average amplitude of ringing per unit time) falls within an acceptable range. This suppresses ringing caused by the superposition of even higher frequency high-frequency noise on the voltage across the low-side switching unit 11. Therefore, malfunctions of the switching unit 11 can be suppressed.

[0057] Note that the decay time of subsequent ringings (e.g., TP_2) is shorter than the decay time of the first ringing. Therefore, the initial on time T L_1 Compared to other on-time T H_1 ,T L_2 ,T H_3 ,T L_3 ,T H_4 ,T L_4 It's okay if it's short.

[0058] As described above, in this embodiment, the power supply unit 1 is controlled so that the on-period of the first switching operation in a series of multiple switching operations by the switching unit 11 is longer than the on-period of the second and subsequent switching operations. This ensures sufficient decay time for ringing during the first switching operation and helps to suppress malfunctions of the switching unit 11.

[0059] <First Modified Example of the Embodiment> As a first modification of the embodiment, the duty cycles of the multiple consecutive switching operations by the switching unit 11 in each continuous operation period OTa shown in Figure 5 may be equal to each other. In this case, as shown in Figure 5, the timing signal output unit 13 may perform pulse density modulation control such that the period of the first switching operation is larger than the period of the second and subsequent switching operations in the multiple consecutive switching operations of the low-side switching unit 11 (an example of the first switching unit of the present invention). Figure 5 is a waveform diagram showing the operation of the switching units 11 and 12 in the first modification of the embodiment. The periods of the second and subsequent switching operations may be equal to each other. That is, the timing signal output unit 13 may perform pulse density modulation control that satisfies the following equations 4 and 5. T L_1a / T SW_1a ≒T L_2 / T SW_2 ≒T L_3 / T SW_3 ≒T L_4 / T SW_4 ...Formula 4 TSW_1a >T SW_2 ≒T SW_3 ≒T SW_4 ...Formula 5

[0060] This makes it possible to make the on-period of the first switching operation by the switching unit 11 longer than the on-period of the second and subsequent switching operations. In other words, by performing pulse density modulation control that satisfies equations 4 and 5, the following equation 6 can be obtained. T L_1a >T L_2 ≒T L_3 ≒T L_4 ...Formula 6

[0061] As long as equation 6 holds true, a ringing decay time TP_1 can be secured, as shown in Figure 4, and the high-side switching unit 12 can be turned on after the decay time TP_1 has ended. This suppresses ringing caused by the superposition of even higher frequency high-frequency noise on the voltage across the low-side switching unit 11. Therefore, malfunctions of the switching unit 11 can be suppressed.

[0062] <Second modified example of the embodiment> As a second modification of the embodiment, the power supply unit 101 may be configured to receive a positive voltage +E from a voltage source E, as shown in Figure 6. Figure 6 is a circuit diagram showing the schematic configuration of the power supply unit 101.

[0063] The power supply unit 101 has an output terminal Tout2 and an output-side reference potential terminal Tst2 instead of the output terminal Tout and output-side reference potential terminal Tst (see Figure 1).

[0064] In Figure 6, the input-side reference potential terminal Tst1 and the output-side reference potential terminal Tst2 are at the same potential. Therefore, both are collectively referred to as the reference potential terminal Tst.

[0065] The voltage source E has its high-potential side connected to the input terminal Tin, and its low-potential side connected to the reference potential GND (e.g., ground potential) and the input-side reference potential terminal Tst1 via the reference node Nst. As a result, the power supply unit 101 receives a positive voltage +E at the input terminal Tin, with the reference potential GND received at the input-side reference potential terminal Tst1 as the reference. The positive voltage +E may be, for example, +12kV.

[0066] The load LD has one end, LDa, connected to the output terminal Tout2, and the other end, LDb, connected to the output-side reference potential terminal Tst2. As a result, the load LD receives the reference potential GND from the output-side reference potential terminal Tst2 and the output voltage Vout from the output terminal Tout2. Consequently, the load LD receives power corresponding to the output voltage Vout, which is referenced to the reference potential GND.

[0067] The power supply unit 101 includes a switching unit 111, a switching unit 112, a timing signal output unit 13, a driver unit 14, and a driver unit 15.

[0068] In other words, the power supply unit 101 has switching units 111 and 112 instead of switching units 11 and 12 (see Figure 1).

[0069] In the second modified example, the switching unit 111 is an example of the second switching unit of the present invention, and the switching unit 112 is an example of the first switching unit of the present invention.

[0070] The switching unit 111 is connected between the output terminal Tout2 and the output-side reference potential terminal Tst2. The low-potential side of the switching unit 111 is connected to the low-potential side of the voltage source E via the input-side reference potential terminal Tst1 and the reference node Nst. The low-potential side of the switching unit 111 is also connected to the load LD via the output-side reference potential terminal Tst2. The switching unit 111 is also called the low-side switching unit. Each control terminal of the switching unit 111 is connected to the timing signal output unit 13 via the drive circuit of the driver unit 14. The high-potential side of the switching unit 111 is connected to the load LD via the intermediate node Nmid and the output terminal Tout2.

[0071] The switching unit 112 is connected between the input terminal Tin and the output terminal Tout2. The high-potential side of the switching unit 112 is connected to the high-potential side of the voltage source E via the input terminal Tin. The switching unit 112 is also called the high-side switching unit. Each control terminal of the switching unit 112 is connected to the timing signal output unit 13 via the drive circuit of the driver unit 15. The low-potential side of the switching unit 112 is connected to the load LD via the intermediate node Nmid and the output terminal Tout2.

[0072] The intermediate node Nmid is the connection point between switching unit 111 and switching unit 112. Therefore, switching unit 112 and switching unit 111 are connected between the high-potential side and the low-potential side of the voltage source E via the intermediate node Nmid.

[0073] The fact that each of the switching unit 111 and the switching unit 112 has one or more switching elements SW is the same as in the embodiment.

[0074] Furthermore, the driver unit 14 and the driver unit 15 are the same as in the embodiment.

[0075] Furthermore, the relationship between the driver unit 14 and the switching unit 111 is the same as in the embodiment.

[0076] Furthermore, the relationship between the driver unit 15 and the switching unit 112 is the same as in the embodiment.

[0077] In the power supply unit 1 described in Figure 1, the first period T in each continuous operation period OT SW_1 In this configuration, the low-side switching unit 11 is selectively turned on from a state where both switching unit 11 and switching unit 12 were previously off. As a result, the initial switching operation by the low-side switching unit 11 becomes hard switching, and high-frequency ringing is likely to occur across the voltage of the low-side switching unit 11.

[0078] In contrast, the power supply unit 101 shown in Figure 6 has a period T at the beginning of each continuous operation period OT. SW_1 In this state, the high-side switching unit 112 is selectively turned on from a state where both the switching unit 111 and the switching unit 112 were previously off. The initial switching operation by the high-side switching unit 112 is hard switching, and high-frequency ringing is likely to occur in the voltage across the high-side switching unit 112.

[0079] Even in this configuration, the switching unit 112 controls the on-period of the first switching operation to be longer than the on-period of subsequent switching operations. This ensures sufficient decay time for ringing during the first switching operation, thereby suppressing ringing caused by high-frequency noise of even higher frequencies being superimposed on the voltage across the high-side switching unit 112. As a result, malfunctions of the switching unit 112 can be suppressed.

[0080] Furthermore, similar to the first modification of the embodiment, pulse density modulation control may be performed such that, in a series of multiple switching operations of the high-side switching unit 112, which is an example of the first switching unit of the present invention, the period of the first switching operation is larger than the period of the second and subsequent switching operations.

[0081] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0082] 1,101 Power supplies 11,12,111,112 Switching section 13 Timing signal output section 14, 15 Driver section

Claims

1. A first switching unit connected between the input terminal and the output terminal, A second switching unit is connected between a reference potential terminal, whose absolute potential is lower than the potential of the input terminal, and the output terminal, Equipped with, In the first switching unit, during multiple consecutive switching operations, the on-period of the first switching operation is longer than the on-period of the second and subsequent switching operations. power supply.

2. The first switching unit and the second switching unit are configured to perform a switching operation in which they complementarily turn on and turn off at the first frequency during a continuous operation period defined by a predetermined on-duty ratio during the repetition period of the second frequency, which is lower than the first frequency, which is the switching operating frequency, and both the first switching unit and the second switching unit are configured to pause their switching operation during a pause period defined by a predetermined off-duty ratio. In the first switching unit, during the continuous operation period, the on-period of the first switching operation is longer than the on-period of the second and subsequent switching operations. The power supply device according to claim 1.

3. The periods of the aforementioned continuous multiple switching operations are equal to each other. In the first switching unit, during the continuous multiple switching operations, the duty cycle of the first switching operation is greater than the duty cycle of the second and subsequent switching operations. The power supply device according to claim 1 or claim 2.

4. The duty cycles of the aforementioned consecutive switching operations are equal to each other. In the first switching unit, in the continuous multiple switching operations, the period of the first switching operation is longer than the period of the second and subsequent switching operations. The power supply device according to claim 1 or claim 2.

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