Semiconductor testing equipment and inspection systems

Abstract

In semiconductor testing equipment where multiple types of circuit board units are housed inside the enclosure, this prevents incorrect insertion of circuit board units during assembly. [Solution] The system comprises a main body housing, a plurality of circuit board units 11 inserted and installed inside the main body housing, and a misinsertion prevention mechanism 20 formed in a shape corresponding to the type of circuit board unit 11, which restricts the insertion of the circuit board unit 11 into the wrong position inside the main body housing. The misinsertion prevention mechanism 20 comprises a pin unit 21 having pins arranged in positions corresponding to the type of circuit board unit 11, and a pin insertion plate 22 having pin insertion holes in positions into which the pins of the pin unit 21 can be inserted. The pin unit 21 is installed on one of the main body housing and the circuit board unit 11, and the pin insertion plate is installed on the other of the main body housing and the circuit board unit 11.

Description

Technical Field

[0001] The present invention relates to a semiconductor test apparatus and an inspection system.

Background Art

[0002] For example, Patent Document 1 discloses a wafer test system including a test head and a probe. The wafer test system disclosed in Patent Document 1 includes a test head and a test head support / damping device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An inspection system such as the wafer system disclosed in Patent Document 1 includes a semiconductor test apparatus that inspects a semiconductor integrated circuit like the test head of Patent Document 1. The semiconductor test apparatus includes a housing and a plurality of substrate units housed inside the housing. Among the plurality of substrate units, many have different functions. That is, a plurality of types of substrate units are housed inside the housing. Therefore, when assembling the semiconductor test apparatus, it is necessary to prevent the substrate units from being inserted into incorrect positions.

[0005] The present invention has been made in view of the above problems, and an object thereof is to prevent incorrect insertion of substrate units during assembly in a semiconductor test apparatus in which a plurality of types of substrate units are housed inside a housing.

Means for Solving the Problems

[0006] As means for solving the above problems, the present invention adopts the following configuration.

[0007] A semiconductor testing apparatus according to one aspect of the present invention comprises a housing, a plurality of substrate units inserted and installed inside the housing, and a misinsertion prevention mechanism formed in a shape corresponding to the type of substrate unit, which restricts the insertion of the substrate unit into the wrong position inside the housing, wherein the misinsertion prevention mechanism comprises a pin unit having pins arranged at positions corresponding to the type of substrate unit, and a pin insertion portion having pin insertion holes at positions into which the pins of the pin unit can be inserted, wherein the pin unit is installed on one of the housing and the substrate units, and the pin insertion portion is installed on the other of the housing and the substrate units.

[0008] An inspection system according to one aspect of the present invention comprises the above-described semiconductor testing apparatus and a test object transport device that moves a test object on which a semiconductor integrated circuit is provided and connects it to the semiconductor testing apparatus. [Effects of the Invention]

[0009] According to the present invention, in a semiconductor testing apparatus in which multiple types of substrate units are housed inside a casing, it is possible to prevent incorrect insertion of substrate units during assembly. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic diagram showing the general configuration of an inspection system in one embodiment of the present invention. [Figure 2] This is a perspective view of the tester in one embodiment of the present invention. [Figure 3] This is an exploded perspective view of a tester in one embodiment of the present invention. [Figure 4] This is a front view of a substrate unit in one embodiment of the present invention, viewed from the horizontal direction. [Figure 5] This is a schematic enlarged view of the pin unit of the first misinsertion prevention mechanism in one embodiment of the present invention. [Figure 6]This is a schematic enlarged view of the pin unit of the second misinsertion prevention mechanism in one embodiment of the present invention. [Figure 7] This is a schematic enlarged view of the pin insertion plate of the first misinsertion prevention mechanism in one embodiment of the present invention. [Figure 8] This is a schematic enlarged view of the pin insertion plate of the second misinsertion prevention mechanism in one embodiment of the present invention. [Figure 9] This is a schematic plan view of the main enclosure of one embodiment of the present invention, seen from above. [Modes for carrying out the invention]

[0011] Hereinafter, an embodiment of the semiconductor testing apparatus and inspection system according to the present invention will be described with reference to the drawings.

[0012] Figure 1 is a schematic diagram showing the general configuration of the inspection system 1 of this embodiment. The inspection system 1 of this embodiment uses a wafer W on which semiconductor circuits are provided as the test object and performs inspection of the electrical characteristics of the semiconductor integrated circuit. As shown in Figure 1, the inspection system 1 comprises a tester 2 (semiconductor test equipment) and a prober 3 (test object transport equipment). This inspection system 1 inspects the electrical characteristics of each semiconductor circuit before separating the multiple semiconductor circuits formed on the wafer W into individual chips.

[0013] A probe card 4 is attached to the tester 2. The probe card 4 has multiple probes. The prober 3 brings the multiple probes on the probe card 4 into contact with the pads of multiple semiconductor circuits formed on the wafer W. The prober 3 includes a tester moving device 3a, a stage device 3b, and a wafer transport device 3c.

[0014] The tester moving device 3a includes a moving mechanism (not shown) and moves the tester 2 between the standby position 1A and the inspection position 1B. The stage device 3b supports the wafer W and aligns the tester 2 located at the inspection position 1B with the wafer W. The stage device 3b is movable in a planar direction along the horizontal plane and in a vertical direction perpendicular to the horizontal plane, and is further rotatable in the θ direction around the vertical axis. The wafer transfer device 3c transfers the wafer W onto the stage device 3b.

[0015] When performing an inspection, the stage device 3b moves the wafer W and causes the pads of a plurality of semiconductor circuits formed on the wafer W to contact the tip portions of a plurality of probes of a probe card 4 provided on the tester 2 located at the inspection position 1B. In this state, the tester 2 inspects each semiconductor circuit by simultaneously inputting test signals to each semiconductor circuit via the plurality of probes and receiving output signals from each semiconductor circuit.

[0016] FIG. 2 is a perspective view of the tester 2. Further, FIG. 3 is an exploded perspective view of the tester 2. As shown in these figures, the tester 2 includes a main body portion 2a and a performance board unit 2b. In FIGS. 2 and 3, the tester 2 arranged at the standby position 1A is illustrated. At the standby position 1A, the tester 2 is in a posture with the side where the probe card 4 is mounted facing upward. In the following description, the description will be made based on the direction in the state where the tester 2 is arranged at the standby position 1A.

[0017] The main body portion 2a is a unit that performs signal processing and the like for testing the wafer W, and detachably supports the performance board unit 2b. The main body portion 2a includes a main body housing 10 (housing) and a plurality of board units 11. The main body portion 2a also includes a control processing unit (not shown) and the like. The control processing unit inputs a control signal to each board unit 11, for example. The control processing unit may also process signals input from each board unit 11. Further, a battery may be housed inside the main body housing 10, and the control processing unit may include a power supply unit for supplying the power of the battery to each board unit 11 and the like.

[0018] The main body housing 10 is a housing that houses the substrate unit 11. In the present embodiment, the main body housing 10 is formed in a box shape that opens upward. Inside the main body housing 10, a plurality of slots into which the substrate unit 11 can be inserted are provided. The substrate unit 11 is housed inside the main body housing 10 by being inserted into these slots one by one. Further, a plurality of positioning pins 10a for the performance board unit are provided on the upper surface of the main body housing 10. These positioning pins 10a for the performance board unit perform horizontal positioning of the performance board unit 2b when the performance board unit 2b is mounted on the main body portion 2a from above.

[0019] The substrate unit 11 is a substrate on which electronic components for performing various signal processes are mounted, and is replaceable according to the type of test to be performed on the wafer W and the like. FIG. 4 is a front view of the substrate unit 11 as viewed from the horizontal direction. Note that FIG. 4 also shows an insertion prevention mechanism 20 described later. As shown in this figure, the substrate unit 11 includes a substrate body 11a, an upper plate 11b, an upper connector portion 11c, and a lower connector portion 11d.

[0020] The substrate body 11a is an electronic substrate and is housed in the main body housing 10 such that the front and back surfaces face in the horizontal direction. As shown in FIG. 3, the plurality of substrate units 11 are arranged such that the front and back surfaces of the respective substrate bodies 11a face each other. In the following description, the direction in which the substrate units 11 are arranged is referred to as the substrate arrangement direction (first direction). This substrate arrangement direction is horizontal when the tester 2 is located at the standby position 1A. That is, the substrate unit 11 has a substrate body 11a that is inserted into the main body housing 10 in a posture in which the front and back surfaces face in the substrate arrangement direction along the horizontal direction. In the following description, the horizontal direction orthogonal to the substrate arrangement direction is referred to as the substrate extension direction.

[0021] The upper plate 11b is a strip-shaped plate member connected to the upper end of each substrate body 11a. The upper plate 11b extends along the substrate extension direction in a plan view. An upper connector portion 11c is fixed to each upper plate 11b. The upper plate 11b may be formed from a single strip-shaped plate member, or it may be formed by stacking multiple plate members.

[0022] The upper connector section 11c is provided for each board body 11a. For example, one to three upper connector sections 11c are provided for each board body 11a. Each upper connector section 11c is fixed to the upper plate 11b and is electrically connected to the board body 11a. Such upper connector sections 11c can be connected to the lower connector section for the performance board unit, which will be described later, provided on the performance board unit 2b. The board unit 11 is electrically connected to the performance board unit 2b by the connection of the upper connector section 11c to the lower connector section for the performance board unit.

[0023] The lower connector section 11d is provided on the lower edge of each board body 11a (the lower edge 11e of the board unit 11). Multiple bottom connector sections 12 (see Figure 9) are provided at the bottom of the main body housing 10. Each lower connector section 11d is connected to a bottom connector section 12. For example, the board unit 11 is electrically connected to the control processing unit by being connected to the bottom connector section 12. The number of lower connector sections 11d can be changed according to the number of board units 11.

[0024] Each circuit board unit 11 is housed inside the main housing 10 by inserting the circuit board body 11a into a slot provided in the main housing 10. Each circuit board unit 11 is inserted into the main housing 10 from top to bottom, as shown by the arrows in Figure 4. Multiple types of circuit board units 11 exist, for example, depending on differences in function. In other words, different types of circuit board units 11 are housed in the main housing 10. These circuit board units 11 are installed in predetermined positions inside the main housing 10 according to their type. The tester 2 of this embodiment is equipped with a misinsertion prevention mechanism 20 to prevent the circuit board unit 11 from being inserted into the wrong position in the main housing 10 during assembly.

[0025] The misinsertion prevention mechanism 20 is formed in a shape corresponding to the type of substrate unit 11 and restricts insertion of the substrate unit 11 into the wrong position inside the main housing 10. As shown in Figure 4, two such misinsertion prevention mechanisms 20 are provided for one substrate unit 11. Of these two misinsertion prevention mechanisms 20, the one positioned closer to the center in the substrate extension direction of the substrate unit 11 is referred to as the first misinsertion prevention mechanism 30. The misinsertion prevention mechanism 20 positioned closer to the end in the substrate extension direction of the substrate unit 11 than the first misinsertion prevention mechanism 30 is referred to as the second misinsertion prevention mechanism 40.

[0026] As shown in Figure 4, the first misinsertion prevention mechanism 30 and the second misinsertion prevention mechanism 40, provided on a single substrate unit 11, are positioned off-center (to the right in Figure 4) relative to the center of the lower edge 11e in the extending direction of the lower edge 11e of the substrate unit 11. In other words, the first misinsertion prevention mechanism 30 and the second misinsertion prevention mechanism 40 are positioned on only one side of the center of the lower edge 11e and are not provided on the opposite side.

[0027] Each misinsertion prevention mechanism 20 comprises a pin unit 21 and a pin insertion plate 22 (pin insertion portion). In this embodiment, the pin unit 21 is installed on the circuit board unit 11. The pin insertion plate 22 is provided on the main body housing 10. However, the pin unit 21 may be provided on the main body housing 10 and the pin insertion plate 22 may be provided on the circuit board unit 11.

[0028] Figure 5 is a schematic enlarged view of the pin unit 21 of the first misinsertion prevention mechanism 30. As shown in this figure, the pin unit 21 of the first misinsertion prevention mechanism 30 has a base 21a fixed to the substrate body 11a and pins 21b protruding downward from the base 21a. There are four possible positions on the base 21a where the pins 21b can be placed. Specifically, on the base 21a, the positions where the pins 21b can be placed are the position shown by the solid line in Figure 5 and the three positions shown by the dashed line. The pins 21b are placed in predetermined positions depending on the type of substrate unit 11 on which the first misinsertion prevention mechanism 30 is installed.

[0029] Figure 6 is a schematic enlarged view of the pin unit 21 of the second misinsertion prevention mechanism 40. As shown in this figure, the pin unit 21 of the second misinsertion prevention mechanism 40 also has a base 21a fixed to the substrate body 11a and pins 21b protruding downward from the base 21a. The base 21a of the second misinsertion prevention mechanism 40 has a smaller length dimension in the substrate extension direction than the base 21a of the first misinsertion prevention mechanism 30. However, like the base 21a of the first misinsertion prevention mechanism 30, the base 21a of the second misinsertion prevention mechanism 40 also has four possible positions for the pins 21b. In other words, the length dimension of the base 21a can be changed according to the space in which it is installed. The pins 21b of the second misinsertion prevention mechanism 40 are also positioned in predetermined positions according to the type of substrate unit 11 on which the second misinsertion prevention mechanism 40 is installed.

[0030] Thus, in this embodiment, there are four possible positions for the pin 21b in the first misinsertion prevention mechanism 30, and four possible positions for the pin 21b in the second misinsertion prevention mechanism 40. Therefore, there are a total of 16 possible shape patterns for the misinsertion prevention mechanism 20. In other words, in this embodiment, the two misinsertion prevention mechanisms 20 can accommodate 16 different types of substrate units 11.

[0031] Figure 7 is a schematic enlarged view of the pin insertion plate 22 of the first misinsertion prevention mechanism 30. As shown in this figure, the pin insertion plate 22 of the first misinsertion prevention mechanism 30 is provided with pin insertion holes 22a into which the pins 21b of the first misinsertion prevention mechanism 30 are inserted. There are four possible positions on the pin insertion plate 22 where the pin insertion holes 22a can be located. Specifically, the positions on the pin insertion plate 22 where the pin insertion holes 22a are located are shown by solid lines in Figure 7, and the three positions shown by dashed lines. The pin insertion holes 22a are located in positions into which the corresponding pins 21b can be inserted.

[0032] Figure 8 is a schematic enlarged view of the pin insertion plate 22 of the second misinsertion prevention mechanism 40. As shown in this figure, the pin insertion plate 22 of the second misinsertion prevention mechanism 40 is provided with pin insertion holes 22a into which the pins 21b of the second misinsertion prevention mechanism 40 are inserted. There are four possible positions for the pin insertion holes 22a of the second misinsertion prevention mechanism 40, similar to the positions for the pin insertion holes 22a of the first misinsertion prevention mechanism 30. The pin insertion holes 22a of the second misinsertion prevention mechanism 40 are also positioned so that the corresponding pins 21b can be inserted.

[0033] Figure 9 is a schematic plan view of the main housing 10 as seen from above. As shown in Figure 9, the main housing 10 is provided with slots 13 into which circuit board units 11 can be inserted. A slot 13 is provided for each circuit board unit 11 and is arranged in the direction of the circuit board arrangement.

[0034] Each slot 13 contains the aforementioned bottom connector portion 12 and two pin insertion plates 22. Of these two pin insertion plates 22, one is provided for the first misinsertion prevention mechanism 30, and the other is provided for the second misinsertion prevention mechanism 40. As shown in Figure 9, pin insertion plates 22 located in adjacent slots 13 may be integrated together.

[0035] In Tester 2, each slot 13 is equipped with a misinsertion prevention mechanism 20 shaped to match the correct type of circuit board unit 11. Therefore, if the wrong type of circuit board unit 11 is inserted into a slot 13 during assembly, the pins 21b cannot be inserted into the pin insertion holes 22a, and the circuit board unit 11 cannot be pushed in. Thus, the operator can realize that the wrong type of circuit board unit 11 has been inserted into the slot 13.

[0036] Returning to Figures 2 and 3, the performance board unit 2b is detachable from the main body 2a and is fixed to the main body 2a by a locking mechanism (not shown). The performance board unit 2b is connected to the probe card 4 from above and can be electrically connected to the wafer W via the probe card 4.

[0037] Such a performance board unit 2b includes multiple lower connectors for the performance board unit (not shown) that are connected to the upper connector 11c of the board unit 11. Furthermore, as shown in Figures 2 and 3, the performance board unit 2b includes multiple upper connectors 2b1 for the performance board unit that are connected to the probe card 4.

[0038] When assembling Tester 2, the circuit board units 11 are inserted into each slot 13 of the main body casing 10. If an attempt is made to insert the wrong type of circuit board unit 11 into a slot 13, the incorrect insertion prevention mechanism 20 prevents the insertion of the circuit board unit 11. Once all the circuit board units 11 have been inserted into the slots 13, the performance board unit 2b is fixed to the main body 2a, completing the assembly of Tester 2.

[0039] The tester 2 of this embodiment, as described above, comprises a main body housing 10, a circuit board unit 11, and a misinsertion prevention mechanism 20. Multiple circuit board units 11 are provided, inserted and installed inside the main body housing 10. The misinsertion prevention mechanism 20 is formed in a shape corresponding to the type of circuit board unit 11 and restricts the insertion of the circuit board unit 11 into the wrong position inside the main body housing 10. The misinsertion prevention mechanism 20 also comprises a pin unit 21 and a pin insertion plate 22. The pin unit 21 is positioned in a location corresponding to the type of circuit board unit 11. The pin insertion plate 22 is provided with pin insertion holes 22a at a position into which the pins 21b of the pin unit 21 can be inserted. In addition, in the tester 2 of this embodiment, the pin unit 21 is installed in the circuit board unit 11, and the pin insertion plate 22 is installed in the main body housing 10.

[0040] According to the tester 2 of this embodiment, the incorrect insertion prevention mechanism 20 prevents the insertion of the wrong type of circuit board unit 11. Therefore, according to the tester 2 of this embodiment, in a tester 2 in which multiple types of circuit board units 11 are housed inside the main body housing 10, it is possible to prevent the incorrect insertion of the circuit board units 11 during assembly.

[0041] Furthermore, the tester 2 of this embodiment is equipped with multiple misinsertion prevention mechanisms 20 for a single circuit board unit 11. Therefore, according to the tester 2 of this embodiment, it is possible to support a wider variety of circuit board units 11 by combining multiple misinsertion prevention mechanisms 20.

[0042] Furthermore, in the tester 2 of this embodiment, the circuit board unit 11 has a circuit board body 11a that is inserted into the main body housing 10 in a position where its front and back surfaces are oriented in a first direction along the horizontal direction. In addition, the misinsertion prevention mechanism 20 is provided on the lower edge 11e of the circuit board unit 11.

[0043] According to the tester 2 of this embodiment, since the misinsertion prevention mechanism 20 is provided on the lower edge 11e of the circuit board unit 11, the pins 21b can be reliably inserted into the pin insertion holes 22a by their own weight during insertion. Therefore, the circuit board unit 11 can be easily and reliably inserted into the main body housing 10.

[0044] Furthermore, in the tester 2 of this embodiment, the misinsertion prevention mechanism 20 is positioned offset to one side relative to the center of the lower edge 11e in the extending direction of the lower edge 11e. With this tester 2 of this embodiment, the misinsertion prevention mechanism 20 makes it possible to distinguish between the front and back sides of the substrate unit 11. For example, if an attempt is made to insert the substrate unit 11 with the front and back sides of the substrate unit 11 (i.e., the front and back sides of the substrate body 11a) facing the wrong way, the position of the misinsertion prevention mechanism 20 will be on the opposite side from its original position. With this tester 2 of this embodiment, it is also possible to prevent errors in the front and back sides of the substrate unit 11.

[0045] Furthermore, the inspection system 1 of this embodiment includes a tester 2 and a prober 3. The prober 3 moves the wafer W on which the semiconductor integrated circuit is provided to connect with the tester 2. With this inspection system 1 of this embodiment, because it includes a tester 2, it is possible to prevent the substrate unit 11 from being incorrectly inserted into the main body housing 10.

[0046] While preferred embodiments of the present invention have been described and explained above, it should be understood that these are illustrative and should not be considered limiting. Additions, omissions, substitutions, and other modifications can be made without departing from the scope of the invention. Therefore, the present invention should not be considered limited by the foregoing description, but rather limited by the claims.

[0047] For example, the above embodiment described an example in which the present invention is applied to an inspection system equipped with a prober 3 as a test object transport device. However, the present invention is not limited thereto. For example, the present invention can also be applied to an inspection system equipped with a handler as a test object transport device. When the present invention is applied to an inspection system equipped with a handler, the tester 2 is moved relative to the handler, and the tester 2 and the wafer are connected via a probe card.

[0048] Note that the test object is not limited to wafers. For example, the test object may be a packaged device. In such cases, tester 2 is connected to the device via a test socket.

[0049] Furthermore, the above embodiment described a configuration in which two misinsertion prevention mechanisms 20 are provided for one substrate unit 11. However, the present invention is not limited thereto. For example, it is also possible to adopt a configuration in which one misinsertion prevention mechanism 20 is provided for one substrate unit 11, or a configuration in which three or more misinsertion prevention mechanisms 20 are provided for one substrate unit 11. [Explanation of Symbols]

[0050] 1. Inspection System 2. Tester (semiconductor testing equipment) 2a Main body 3. Probe (Test object transport device) 10. Main unit (casing) 10a pin 11 Circuit board unit 11a Main board 11b Upper plate 11c Upper connector section 11d Lower connector section 11e Lower edge 20. Mechanism to prevent incorrect insertion 21-pin unit 21a base 21b pin 22 Pin insertion plate (pin insertion section) 22a Pin insertion hole 30. First misinsertion prevention mechanism 40. Second misinsertion prevention mechanism W wafer (test subject)

Claims

1. The casing and Multiple circuit board units are inserted and installed inside the aforementioned housing, A misinsertion prevention mechanism is formed in a shape corresponding to the type of substrate unit and prevents the substrate unit from being inserted into the wrong position inside the housing. Equipped with, The aforementioned misinsertion prevention mechanism is, A pin unit having pins arranged in positions corresponding to the type of substrate unit, The pin insertion portion of the pin unit is provided with a pin insertion hole at a position into which the pin can be inserted, Equipped with, The pin unit is installed on one of the housing and the circuit board unit, and the pin insertion portion is installed on the other of the housing and the circuit board unit. Semiconductor testing equipment.

2. Multiple misinsertion prevention mechanisms are provided for one of the substrate units. The semiconductor testing apparatus according to claim 1.

3. The aforementioned substrate unit has a substrate body that is inserted into the housing in a position in which the front and back surfaces are oriented in a first direction along the horizontal direction, The aforementioned misinsertion prevention mechanism is provided at the lower edge of the substrate unit. The semiconductor testing apparatus according to claim 1 or 2.

4. In the extending direction of the lower edge, the misinsertion prevention mechanism is positioned off-center to one side relative to the center of the lower edge. The semiconductor testing apparatus according to claim 3.

5. A semiconductor testing apparatus according to claim 1 or 2, A test object transport device that moves a test object equipped with a semiconductor integrated circuit and connects it to the semiconductor test apparatus, Equipped with, Inspection system.

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