Method for manufacturing a Josephson junction and Josephson junction

Abstract

The present invention provides a method for manufacturing a Josephson junction element that can suppress the degradation of its characteristics. [Solution] A method for manufacturing a Josephson junction element comprises the steps of: forming a lower electrode on a substrate using a superconducting material; depositing a first insulating film on the substrate to cover the lower electrode; depositing a superconducting film on the first insulating film; and etching the superconducting film to form an upper electrode that covers the entire lower electrode in a plan view and whose outer edge is located outside the outer edge of the lower electrode.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a Josephson junction element and a Josephson junction element.

Background Art

[0002] A quantum bit device including a quantum bit in which a Josephson junction element and a capacitor are connected in parallel is known. It is also known that a Josephson junction element is used for an amplifier connected to a readout terminal of a quantum bit. A Josephson junction element has a structure in which an insulating film is sandwiched between a lower electrode and an upper electrode each formed of a superconducting material. Various methods are known as a method for manufacturing a Josephson junction element (for example, Patent Documents 1 to 4).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is conceivable to form a Josephson junction element by depositing a first superconducting film serving as a lower electrode, an insulating film, and a second superconducting film serving as an upper electrode on a substrate and then patterning each film by etching. However, in this case, an etching damage layer may be formed in the insulating film, and the characteristics of the Josephson junction element may deteriorate.

[0005] One aspect of this is the aim to suppress the degradation of characteristics. [Means for solving the problem]

[0006] In one embodiment, the method for manufacturing a Josephson junction element comprises the steps of: forming a lower electrode on a substrate using a superconducting material; depositing a first insulating film on the substrate to cover the lower electrode; depositing a superconducting film on the first insulating film; and etching the superconducting film to form an upper electrode that, in a plan view, covers the entire lower electrode and whose outer edge is located outside the outer edge of the lower electrode.

[0007] In one embodiment, the Josephson junction element comprises a substrate, a lower electrode provided on the substrate and formed of a superconducting material, an insulating film provided on the lower electrode in contact with the lower electrode, and an upper electrode provided on the insulating film in contact with the insulating film and formed of a superconducting material in a region that overlaps with the lower electrode in a plan view, wherein the upper electrode covers the entire lower electrode in a plan view, the outer edge of the upper electrode is located outside the outer edge of the lower electrode, and the insulating film is provided below the upper electrode and over the entire upper electrode. [Effects of the Invention]

[0008] One aspect of this is that it can suppress the degradation of characteristics. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1(a) is a cross-sectional view of the Josephson junction element according to Example 1, and Figure 1(b) is a plan view of the lower wiring, lower electrode, insulating film, and upper electrode in Example 1. [Figure 2] Figures 2(a) to 2(c) are cross-sectional views (part 1) showing the method for manufacturing a Josephson junction element according to Example 1. [Figure 3] Figures 3(a) to 3(c) are cross-sectional views (part 2) showing the method for manufacturing a Josephson junction element according to Example 1. [Figure 4] Figs. 4(a) to 4(c) are cross-sectional views (Part 3) showing a method for manufacturing a Josephson junction device according to Example 1. [Figure 5] Fig. 5 is a cross-sectional view of a Josephson junction device according to a comparative example. [Figure 6] Figs. 6(a) to 6(c) are cross-sectional views (Part 1) showing a method for manufacturing a Josephson junction device according to a comparative example. [Figure 7] Figs. 7(a) to 7(c) are cross-sectional views (Part 2) showing a method for manufacturing a Josephson junction device according to a comparative example. [Figure 8] Fig. 8 is a cross-sectional view for explaining problems occurring in a Josephson junction device according to a comparative example. [Figure 9] Fig. 9 is a cross-sectional view of a Josephson junction device according to Example 2. [Figure 10] Figs. 10(a) to 10(c) are cross-sectional views showing a method for manufacturing a Josephson junction device according to Example 2. [Figure 11] Figs. 11(a) to 11(c) are cross-sectional views showing another example of a method for manufacturing a Josephson junction device according to Example 2.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Examples

[0011] Fig. 1(a) is a cross-sectional view of a Josephson junction device 100 according to Example 1, and Fig. 1(b) is a plan view of a lower wiring 25, a lower electrode 20, an insulating film 30, and an upper electrode 40 in Example 1. As shown in Fig. 1(a), an insulating film 11 is provided on a substrate 10. The substrate 10 is, for example, a silicon (Si) substrate. The insulating film 11 is, for example, a silicon oxide (SiO2) film.

[0012] The lower wiring 25 is provided on the insulating film 11. The lower wiring 25 is formed of a superconducting material. For example, the lower wiring 25 is formed of aluminum (Al). An insulating film 12 is provided on the insulating film 11 so as to cover the lower wiring 25. The insulating film 12 is, for example, a silicon oxide (SiO2) film.

[0013] The insulating film 12 has an opening 13 reaching the lower wiring 25. A lower electrode 20 contacting the lower wiring 25 is embedded in the opening 13. The lower electrode 20 is formed of a superconducting material. For example, the lower electrode 20 is formed of aluminum (Al). The upper surface of the lower electrode 20 and the upper surface of the insulating film 12 are flush.

[0014] An insulating film 30 is provided on the insulating film 12 and the lower electrode 20. The insulating film 30 is provided in contact with the lower electrode 20. The insulating film 30 is, for example, an aluminum oxide (Al2O3) film.

[0015] An upper electrode 40 is provided on the insulating film 30. The upper electrode 40 is provided in contact with the insulating film 30. The upper electrode 40 is formed of a superconducting material. For example, the upper electrode 40 is formed of aluminum (Al). The region where the lower electrode 20 and the upper electrode 40 face each other with the insulating film 30 interposed therebetween becomes the Josephson junction 60.

[0016] An insulating film 15 is provided on the insulating film 30 so as to cover the upper electrode 40. The insulating film 15 is, for example, a silicon oxide (SiO2) film. An opening 17 reaching the lower wiring 25 is provided in the insulating film 15, the insulating film 30, and the insulating film 12. An opening 18 reaching the upper electrode 40 is provided in the insulating film 15. A lead wiring 50 connecting to the lower wiring 25 is provided in the opening 17. A lead wiring 51 connecting to the upper electrode 40 is provided in the opening 18. The lead wirings 50 and 51 are formed of a superconducting material. For example, the lead wirings 50 and 51 are formed of aluminum (Al).

[0017] As shown in Figures 1(a) and 1(b), in a plan view (viewed from the +Z direction), the outer edge 41 of the upper electrode 40 is located outside the outer edge 21 of the lower electrode 20, and the upper electrode 40 covers the entire lower electrode 20. The shortest distance L between the outer edges 41 and 21 is greater than or equal to the thickness T of the insulating film 30 (distance L ≥ thickness T). Since the upper electrode 40 is larger than the lower electrode 20, the area of ​​the Josephson junction 60 is defined by the lower electrode 20. The area of ​​the Josephson junction 60 is, for example, 0.04 μm². 2 ~0.8μm 2 Furthermore, in a plan view, the insulating film 30 is provided below the upper electrode 40 and extends over the entire upper electrode 40.

[0018] [Manufacturing method] Figures 2(a) to 4(c) are cross-sectional views showing a method for manufacturing a Josephson junction element 100 according to Example 1. As shown in Figure 2(a), an insulating film 11 is formed on a substrate 10. For example, the insulating film 11, which is an SiO2 film, is formed on the substrate 10 by thermal oxidation of the upper surface of the substrate 10, which is a Si substrate. The thickness of the insulating film 11 is, for example, 100 nm. Next, a superconducting film is deposited on the insulating film 11 using, for example, sputtering, chemical vapor deposition (CVD), or vacuum deposition, and then the superconducting film is patterned using photolithography and etching to form the lower wiring 25. For example, an Al film is used as the superconducting film. When an Al film is used, the Al film is patterned using, for example, reactive ion etching with a chlorine-based gas to form the lower wiring 25. The thickness of the lower wiring 25 is, for example, 200 nm.

[0019] As shown in Figure 2(b), an insulating film 12 is deposited on the insulating film 11 so as to cover the lower wiring 25. For example, a 400 nm thick insulating film 12, which is an SiO2 film, is deposited using the CVD method. Then, the surface of the insulating film 12 is planarized using, for example, a chemical vapor deposition (CMP) method. The thickness of the insulating film 12 on the lower wiring 25 is, for example, 200 nm. Next, an opening 13 is formed in the insulating film 12 in which the lower wiring 25 is exposed. For example, if the insulating film 12 is an SiO2 film, the opening 13 is formed by reactive ion etching using a fluorine-based gas. Alternatively, the insulating film 12 may be formed by polishing using the CMP method until the lower wiring 25 is exposed, and then depositing another SiO2 film using the CVD method.

[0020] As shown in Figure 2(c), a superconducting film 24 is deposited on the insulating film 12 so as to fill the opening 13. For example, a 300 nm superconducting film 24 is deposited using sputtering, CVD, or vacuum deposition. For example, an Al film is used as the superconducting film 24. When depositing the superconducting film 24 by sputtering, reverse sputtering may be performed before deposition to remove the native oxide film on the surface of the lower wiring 25 exposed in the opening 13.

[0021] As shown in Figure 3(a), the superconducting film 24 on the insulating film 12 is removed using, for example, the CMP method until the surface of the insulating film 12 is exposed. As a result, the superconducting film 24 remains only in the opening 13 of the insulating film 12, and a lower electrode 20 made of the superconducting film 24 is formed in the opening 13. The upper surface of the lower electrode 20 and the upper surface of the insulating film 12 become the same plane.

[0022] As shown in Figure 3(b), the surface of the lower electrode 20 is treated with an organic solution (for example, an organic alkaline solution such as TMAH (Tetramethyl ammounium hydroxide)) to remove the contaminated and damaged layers from the surface of the lower electrode 20. Next, an insulating film 30 is deposited on the insulating film 12 and the lower electrode 20. For example, the insulating film 30 is deposited to a thickness of 20 nm using atomic layer deposition (ALD), sputtering, or CVD. An Al2O3 film is used as the insulating film 30.

[0023] As shown in Figure 3(c), a superconducting film 44 is deposited on the insulating film 30. For example, a 200 nm thick superconducting film 44 is deposited using sputtering, CVD, or vacuum deposition. An Al film is used as the superconducting film 44.

[0024] As shown in Figure 4(a), the upper electrode 40 is formed by patterning the superconducting film 44 using photolithography and etching methods so that a Josephson junction 60 is formed, which is the region that overlaps with the lower electrode 20 with the insulating film 30 in between. At this time, in a plan view, the upper electrode 40 is formed such that the upper electrode 40 covers the entire lower electrode 20 and the outer edge 41 of the upper electrode 40 is located outside the outer edge 21 of the lower electrode 20. For example, the upper electrode 40 is formed such that the shortest distance L between the outer edge 41 of the upper electrode 40 and the outer edge 21 of the lower electrode 20 is greater than or equal to the thickness T of the insulating film 30. If the superconducting film 44 is an Al film, the upper electrode 40 is formed by patterning the superconducting film 44 by reactive ion etching using a chlorine-based gas.

[0025] As shown in Figure 4(b), an insulating film 15 is deposited on the insulating film 30 so as to cover the upper electrode 40. For example, a 400 nm thick insulating film 15, which is an SiO2 film, is deposited using the CVD method. Then, the surface of the insulating film 15 is planarized using the CMP method.

[0026] As shown in Figure 4(c), the insulating film 15, insulating film 30, and insulating film 12 are etched to form an opening 17 in which the lower wiring 25 is exposed. The insulating film 15 is also etched to form an opening 18 in which the upper electrode 40 is exposed. If insulating films 15 and 12 are SiO2 films, they are etched by reactive ion etching using a fluorine-based gas. If insulating film 30 is an Al2O3 film, it is etched using ion milling. Next, lead wires 50 embedded in the opening 17 and connected to the lower wiring 25, and lead wires 51 embedded in the opening 18 and connected to the upper electrode 40 are formed from a superconducting material (e.g., Al). Lead wires 50 and 51 are formed, for example, using the lift-off method. Thus, the Josephson junction element 100 according to Example 1 is formed.

[0027] [Comparative Example] Figure 5 is a cross-sectional view of a Josephson junction element 500 according to a comparative example. As shown in Figure 5, an insulating film 11 is provided on the substrate 10. A lower electrode 20 is provided on the insulating film 11. An insulating film 30 is provided on the lower electrode 20. An upper electrode 40 is provided on the insulating film 30. As a result, a Josephson junction 60 is formed, which is the region where the lower electrode 20 and the upper electrode 40 face each other with the insulating film 30 in between. In the comparative example, the upper electrode 40 is smaller than the lower electrode 20 in a plan view. Therefore, the area of ​​the Josephson junction 60 is defined by the upper electrode 40.

[0028] An insulating film 16 is provided on the substrate 10 so as to cover the lower electrode 20, the insulating film 30, and the upper electrode 40. An opening is provided in the insulating film 16, and a lead wire 50 connected to the lower electrode 20 and a lead wire 51 connected to the upper electrode 40 are provided in the opening.

[0029] [Comparative method] Figures 6(a) to 7(c) are cross-sectional views showing a method for manufacturing a Josephson junction element 500 according to a comparative example. As shown in Figure 6(a), an insulating film 11 is formed on a substrate 10, for example by thermal oxidation. A superconducting film 24 is deposited on the insulating film 11 using, for example, sputtering, CVD, or vacuum deposition. An insulating film 30 is deposited on the superconducting film 24 using, for example, ALD, sputtering, or CVD. A superconducting film 44 is deposited on the insulating film 30 using, for example, sputtering, CVD, or vacuum deposition.

[0030] As shown in Figure 6(b), the superconducting film 44 is patterned using photolithography and etching to form the upper electrode 40. The area of ​​the Josephson junction 60 is determined by the upper electrode 40.

[0031] As shown in Figure 6(c), the insulating film 30 is patterned using photolithography and etching methods.

[0032] As shown in Figure 7(a), the superconducting film 24 is patterned using photolithography and etching to form the lower electrode 20.

[0033] As shown in Figure 7(b), an insulating film 16 is formed on the insulating film 11, for example, using a CVD method, so as to cover the lower electrode 20, the insulating film 30, and the upper electrode 40.

[0034] As shown in Figure 7(c), an opening is formed in the insulating film 16 using photolithography and etching. Lead wires 50 connected to the lower electrode 20 and lead wires 51 connected to the upper electrode 40 are formed in the opening. Lead wires 50 and 51 are formed, for example, by the lift-off method. Thus, a Josephson junction element 500 according to the comparative example is formed.

[0035] [Challenges of the comparative example] Figure 8 is a cross-sectional view illustrating the problems that arise in the Josephson junction element 500 according to the comparative example. As explained in Figures 6(a) and 6(b), in the comparative example, a superconducting film 24, an insulating film 30, and a superconducting film 44 are deposited on the substrate 10, and then the upper electrode 40 is formed by etching the superconducting film 44. In this case, as shown in Figure 8, a damage layer 75 is formed on the side surface of the upper electrode 40 and on the upper surface of the insulating film 30 due to etching. For example, when forming the upper electrode 40 by patterning the superconducting film 44 by reactive ion etching, the damage layer 75 is formed on the side surface of the upper electrode 40 and on the upper surface of the insulating film 30 due to exposure to the plasma of reactive ion etching. Since the Josephson junction 60 is defined by the upper electrode 40, a portion of the damage layer 75 is formed in the Josephson junction 60. The insulating properties of the insulating film 30 decrease in the region where the damage layer 75 is formed. As a result, the effective area of ​​the Josephson junction 60 may change from the desired size. This can cause the characteristics of the Josephson junction element (e.g., current-voltage characteristics) to degrade and not meet the desired specifications.

[0036] On the other hand, according to Example 1, as shown in Figure 4(a), when etching the superconducting film 44 to form the upper electrode 40, the upper electrode 40 is formed so that it covers the entire lower electrode 20 in a plan view, and the outer edge 41 of the upper electrode 40 is located outside the outer edge 21 of the lower electrode 20. As a result, even if a damage layer is formed in the insulating film 30 (first insulating film) when etching the superconducting film 44, the damage layer is formed away from the Josephson junction 60. Therefore, the influence of the damage layer on the Josephson junction 60 is suppressed, and thus the degradation of the characteristics of the Josephson junction element can be suppressed.

[0037] Furthermore, by forming the Josephson junction element 100 using the manufacturing method of Example 1, as shown in Figures 1(a) and 1(b), in a plan view, the upper electrode 40 covers the entire lower electrode 20, and the outer peripheral edge 41 of the upper electrode 40 is located outside the outer peripheral edge 21 of the lower electrode 20. The insulating film 30 is provided below the upper electrode 40 and extends over the entire upper electrode 40. With such a Josephson junction element 100, the influence of the damage layer on the Josephson junction 60 is suppressed, and thus the degradation of the characteristics of the Josephson junction element can be suppressed.

[0038] Furthermore, in Example 1, as shown in Figure 4(a), the upper electrode 40 is formed such that the shortest distance L between the outer peripheral edge 41 of the upper electrode 40 and the outer peripheral edge 21 of the lower electrode 20 is greater than or equal to the thickness T of the insulating film 30. This suppresses the influence of the damage layer on the Josephson junction 60 and suppresses the degradation of the characteristics of the Josephson junction element. From the viewpoint of suppressing characteristic degradation, the distance L is preferably 1.5 times or more the thickness T, more preferably 2.0 times or more, and even more preferably 2.5 times or more.

[0039] In Example 1, as shown in Figure 2(b), an insulating film 12 (second insulating film) having an opening 13 (first opening) is formed on the substrate 10. As shown in Figure 3(a), a lower electrode 20 embedded in the opening 13 is formed. As shown in Figure 3(b), an insulating film 30 (first insulating film) is deposited on the lower electrode 20 and the insulating film 12. As a result, the insulating film 30 is formed in a flat shape. As shown in Figure 3(c), the superconducting film 44 formed on the insulating film 30 is also formed in a flat shape. Therefore, as shown in Figure 4(a), by patterning the superconducting film 44 to form an upper electrode 40, a Josephson junction 60 whose area is defined by the lower electrode 20 is formed. Thus, a Josephson junction 60 with a desired area can be formed.

[0040] Furthermore, in Example 1, as shown in Figure 3(b), after treating the surface of the lower electrode 20 with an organic solution, an insulating film 30 (first insulating film) is formed to cover the lower electrode 20. This suppresses the interposition of an unnecessary layer between the lower electrode 20 and the insulating film 30, thereby suppressing the degradation of the characteristics of the Josephson junction element.

[0041] In Example 1, as shown in Figure 2(a), a lower wiring 25 (first wiring) is formed on the substrate 10. As shown in Figure 2(b), an insulating film 12 (second insulating film) is formed on the substrate 10 so as to cover the lower wiring 25. As shown in Figure 3(a), a lower electrode 20 connected to the lower wiring 25 is formed in an opening 13 (first opening) formed in the insulating film 12. This makes it easy to obtain a configuration in which a voltage can be applied to the Josephson junction 60, even when the entire lower electrode 20 is covered by the upper electrode 40.

[0042] Furthermore, in Example 1, as shown in Figure 3(b), the insulating film 30 is deposited using the ALD method, CVD method, or sputtering method. For example, when the insulating film 30 is formed by thermal oxidation of the surface of the lower electrode 20, the oxidation rate may differ between the central and edge portions of the lower electrode 20, resulting in an insulating film 30 with large variations in film thickness. Also, stress may concentrate at the edges of the insulating film 30 due to thermal expansion during oxidation. As a result, degradation of the characteristics of the Josephson junction element may occur. However, by depositing the insulating film 30 using the ALD method, CVD method, or sputtering method, it is possible to form an insulating film 30 that is dense overall and has small variations in film thickness and stress concentration. Therefore, degradation of the characteristics of the Josephson junction element can be suppressed. In particular, by depositing the insulating film 30 using the ALD method, the film quality and controllability of the film thickness of the insulating film 30 can be improved.

[0043] Furthermore, in Example 1, as shown in Figures 2(c) and 3(a), the lower electrode 20 is formed by patterning a superconducting film 24 deposited using sputtering, CVD, or vacuum deposition. As shown in Figures 3(c) and 4(a), the upper electrode 40 is formed by patterning a superconducting film 44 deposited using sputtering, CVD, or vacuum deposition. By depositing the superconducting films 24 and 44 using sputtering, CVD, or vacuum deposition, it is possible to obtain superconducting films 24 and 44 with small variations in film thickness across the entire surface of the substrate 10. In particular, by depositing the superconducting films 24 and 44 using sputtering, it is possible to form the lower electrode 20 and upper electrode 40 with few impurities and a dense, excellent film quality. [Examples]

[0044] Figure 9 is a cross-sectional view of the Josephson junction element 200 according to Example 2. As shown in Figure 9, in Example 2, the insulating film 30 is provided only below the upper electrode 40. Therefore, in a plan view, the upper electrode 40 and the insulating film 30 are the same size. The other configurations are the same as in Example 1, so their description is omitted.

[0045] [Manufacturing method] Figures 10(a) to 10(c) are cross-sectional views showing the manufacturing method of the Josephson junction element 200 according to Example 2. First, the same steps as in Figures 2(a) to 4(a) of Example 1 are performed to form the upper electrode 40 as shown in Figure 10(a). The resist mask 72 used when patterning the superconducting film 44 to form the upper electrode 40 is also shown here.

[0046] As shown in Figure 10(b), the insulating film 30 is etched using the resist mask 72 as a mask, for example, by ion milling. As a result, the insulating film 30 remains only beneath the upper electrode 40, and in a plan view, the upper electrode 40 and the insulating film 30 are the same size.

[0047] As shown in Figure 10(c), after removing the resist mask 72, an insulating film 15 is deposited on the insulating film 12 so as to cover the upper electrode 40. The insulating film 15 and insulating film 12 are etched to form an opening 17 in which the lower wiring 25 is exposed. The insulating film 15 is also etched to form an opening 18 in which the upper electrode 40 is exposed. Next, a lead wire 50 embedded in the opening 17 and connected to the lower wiring 25, and a lead wire 51 embedded in the opening 18 and connected to the upper electrode 40 are formed from a superconducting material (e.g., Al). Thus, the Josephson junction element 200 according to Example 2 is formed.

[0048] Figures 11(a) to 11(c) are cross-sectional views showing another example of the method for manufacturing the Josephson junction element 200 according to Example 2. First, the same steps as in Figures 2(a) to 3(c) of Example 1 are performed. Then, as shown in Figure 11(a), a hard mask 73 made of, for example, titanium nitride (TiN) is deposited on the superconducting film 44.

[0049] As shown in Figure 11(b), the hard mask 73 and the superconducting film 44 are etched using the resist mask 72 formed on the hard mask 73 as a mask. This forms the upper electrode 40. When a TiN film is used for the hard mask 73, it can be etched together with the Al film superconducting film 44 by reactive ion etching using a chlorine-based gas.

[0050] As shown in Figure 11(c), the insulating film 30 is etched using, for example, an ion milling method, with the resist mask 72 and the hard mask 73 as masks. As a result, the insulating film 30 remains only beneath the upper electrode 40, and in a plan view, the upper electrode 40 and the insulating film 30 are the same size.

[0051] Next, after removing the resist mask 72 and the hard mask 73, the same process as in Figure 10(c) is performed to form the insulating film 15 covering the upper electrode 40, the lead wire 50 connected to the lower wiring 25, and the lead wire 51 connected to the upper electrode 40. Thus, the Josephson junction element 200 according to Example 2 is formed.

[0052] According to Example 2, as shown in Figures 10(b) and 11(c), the insulating film 30 (first insulating film) is etched using the resist mask 72 and / or hard mask 73 (mask layer) formed on the upper electrode 40 as a mask. Then, as shown in Figure 10(c), an insulating film 15 (third insulating film) is formed covering the upper electrode 40, and then an opening 17 (second opening) is formed in the insulating film 15 and insulating film 12, exposing the lower wiring 25 (first wiring). Next, a lead wiring 50 (second wiring) connected to the lower wiring 25 is formed in the opening 17. As a result, the opening 17 can be easily formed because it is formed in insulating films 12 and 15, which are, for example, SiO2 films. Therefore, the lead wiring 50 connected to the lower wiring 25 can be easily formed.

[0053] In Example 2, as shown in Figures 11(b) and 11(c), the insulating film 30 is etched using a hard mask 73 made of TiN. When the insulating film 30 is an Al2O3 film, the insulating film 30 is etched using the ion milling method, which can result in the resist mask 72 being completely removed during etching. Therefore, it is preferable to use a hard mask 73 in addition to or instead of the resist mask 72. The hard mask 73 may be made of a film other than TiN as long as it can withstand etching by ion milling; for example, a silicon nitride (SiN) film may be used. When a TiN film is used for the hard mask 73, if the superconducting film 44 for forming the upper electrode 40 is an Al film, the hard mask 73, the superconducting film 44, and the hard mask 73 can be etched simultaneously by reactive ion etching using a chlorine-based gas.

[0054] In Examples 1 and 2, the lower electrode 20 and upper electrode 40 were shown as examples where they are made of aluminum, but they may also be made of superconducting materials other than aluminum. For example, they may be single-layer or multilayer films containing at least one of the following: aluminum (Al), silicon (Si), titanium (Ti), vanadium (V), zinc (Zn), gallium (Ga), germanium (Ge), antimony (Sb), tellurium (Te), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), and titanium nitride (TiN). The lower wiring 25 and lead wiring 50 and 51 may also be single-layer or multilayer films containing at least one of the superconducting materials mentioned above.

[0055] In Examples 1 and 2, the insulating film 30 was shown to be formed of aluminum oxide as an example, but it may also be formed of an insulating film other than aluminum oxide. For example, aluminum oxide (AlO X ), may be a single-layer or multilayer film containing at least one of aluminum nitride (AlN), silicon nitride (SiN), hafnium oxide (HfO2), and tantalum oxide (Ta2O5). From the viewpoint of adhesion, it is preferable that the insulating film 30 contains the same metal element as the lower electrode 20 and the upper electrode 40. For example, if the lower electrode 20 and the upper electrode 40 are formed of Al, the insulating film 30 may be AlO X Alternatively, it is preferable that the dielectric film is formed of AlN. If the lower electrode 20 and the upper electrode 40 are formed of Hf, it is preferable that the insulating film 30 is formed of HfO2. If the lower electrode 20 and the upper electrode 40 are formed of Ta, it is preferable that the insulating film 30 is formed of Ta2O5.

[0056] Although embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims.

[0057] Furthermore, the following additional information is disclosed regarding the above explanation. (Note 1) A method for manufacturing a Josephson junction element, comprising the steps of: forming a lower electrode on a substrate using a superconducting material; depositing a first insulating film on the substrate to cover the lower electrode; depositing a superconducting film on the first insulating film; and etching the superconducting film to form an upper electrode that, in a plan view, covers the entire lower electrode and whose outer edge is located outside the outer edge of the lower electrode. (Note 2) The method for manufacturing a Josephson junction element according to Note 1, characterized in that, in the step of forming the upper electrode, the shortest distance between the outer peripheral edge of the upper electrode and the outer peripheral edge of the lower electrode is greater than or equal to the thickness of the first insulating film when the upper electrode is formed. (Note 3) A method for manufacturing a Josephson junction element according to Note 1 or 2, further comprising the step of forming a second insulating film having a first opening on the substrate, wherein in the step of forming the lower electrode, the lower electrode is formed in the first opening, and in the step of depositing the first insulating film, the first insulating film is deposited on the lower electrode and the second insulating film. (Note 4) A method for manufacturing a Josephson junction element according to Note 1 or 2, further comprising the step of treating the surface of the lower electrode with an organic solution before the step of depositing the first insulating film. (Note 5) The method for manufacturing a Josephson junction element according to Note 3, further comprising the step of forming a first wiring on the substrate before the step of forming the second insulating film, wherein in the step of forming the second insulating film, the second insulating film is formed to cover the first wiring, and in the step of forming the lower electrode, the lower electrode is formed to be connected to the first wiring. (Note 6) A method for manufacturing a Josephson junction element according to Note 5, further comprising the steps of: etching the first insulating film using a mask layer formed on the upper electrode as a mask; forming a third insulating film that covers the upper electrode after etching the first insulating film; forming a second opening in the third insulating film and the second insulating film in which the first wiring is exposed; and forming a second wiring connected to the first wiring in the second opening. (Note 7) The method for manufacturing a Josephson junction element according to Note 6, characterized in that the mask layer includes a hard mask layer formed of titanium nitride or silicon nitride. (Note 8) A method for manufacturing a Josephson junction element according to Note 1 or 2, characterized in that the first insulating film is deposited using atomic layer volume deposition, chemical vapor deposition, or sputtering in the step of depositing the first insulating film. (Note 9) A method for manufacturing a Josephson junction element according to Note 1 or 2, characterized in that, in the step of forming the lower electrode, the lower electrode is formed by patterning a film made of the superconducting material deposited using a sputtering method, chemical vapor deposition method, or vacuum deposition method, and in the step of depositing the superconducting film, the superconducting film is deposited using a sputtering method, chemical vapor deposition method, or vacuum deposition method. (Note 10) The method for manufacturing a Josephson junction element according to Note 1 or 2, characterized in that the first insulating film contains the same metal element as the lower electrode and the upper electrode. (Note 11) A Josephson junction element comprising: a substrate; a lower electrode provided on the substrate and formed of a superconducting material; a first insulating film provided on the lower electrode in contact with the lower electrode; and an upper electrode provided on the first insulating film in contact with the first insulating film and formed of a superconducting material in a region that overlaps with the lower electrode in a plan view, wherein the upper electrode covers the entire lower electrode in a plan view, the outer edge of the upper electrode is located outside the outer edge of the lower electrode, and the first insulating film is provided below the upper electrode and over the entire upper electrode. (Note 12) The Josephson junction element according to Note 11, characterized in that the shortest distance between the outer edge of the upper electrode and the outer edge of the lower electrode is greater than or equal to the thickness of the first insulating film. (Note 13) The Josephson junction element according to Note 11 or 12, further comprising a second insulating film provided on the substrate and having an opening, wherein the lower electrode is provided within the opening, and the first insulating film is provided extending from the lower electrode to the second insulating film. (Note 14) The Josephson junction element according to Note 13, further comprising a first wiring provided on the substrate, wherein the second insulating film covers the first wiring and is provided on the substrate, and the lower electrode is connected to the first wiring. (Note 15) The Josephson junction element according to Note 14, further comprising a third insulating film covering the upper electrode, and a second wiring provided in an opening formed in the third insulating film and the second insulating film and connected to the first wiring, wherein the upper electrode and the first insulating film are the same size in a plan view. (Note 16) The Josephson junction element according to Note 11 or 12, characterized in that the first insulating film contains the same metal element as the lower electrode and the upper electrode. [Explanation of Symbols]

[0058] 10...Substrate, 11...Insulating film, 12...Insulating film, 13...Aperture, 15...Insulating film, 16...Insulating film, 17...Aperture, 18...Aperture, 20...Lower electrode, 21...Peripheral edge, 24...Superconducting film, 25...Lower wiring, 30...Insulating film, 40...Upper electrode, 41...Peripheral edge, 44...Superconducting film, 50...Leader wiring, 51...Leader wiring, 60...Josephson junction, 72...Resist mask, 73...Hard mask, 75...Damage layer, 100, 200, 500...Josephson junction element

Claims

1. A process of forming a lower electrode on a substrate using a superconducting material, A step of depositing a first insulating film covering the lower electrode on the substrate, A step of depositing a superconducting film on the first insulating film, A method for manufacturing a Josephson junction element, comprising the step of etching the superconducting film to form an upper electrode that covers the entire lower electrode in a plan view and whose outer edge is located outside the outer edge of the lower electrode.

2. The method for manufacturing a Josephson junction element according to claim 1, characterized in that, in the step of forming the upper electrode, the upper electrode is formed such that the shortest distance between the outer edge of the upper electrode and the outer edge of the lower electrode is equal to or greater than the thickness of the first insulating film.

3. The process further comprises forming a second insulating film having a first opening on the substrate, In the step of forming the lower electrode, the lower electrode is formed in the first opening. A method for manufacturing a Josephson junction element according to claim 1 or 2, characterized in that, in the step of depositing the first insulating film, the first insulating film is deposited on the lower electrode and the second insulating film.

4. The method for manufacturing a Josephson junction element according to claim 1 or 2, further comprising the step of treating the surface of the lower electrode with an organic solution before the step of depositing the first insulating film.

5. The process further includes a step of forming a first wiring on the substrate before the step of forming the second insulating film, In the step of forming the second insulating film, the second insulating film covering the first wiring is formed. The method for manufacturing a Josephson junction element according to claim 3, characterized in that the lower electrode connected to the first wiring is formed in the step of forming the lower electrode.

6. A step of etching the first insulating film using the mask layer formed on the upper electrode as a mask, The process involves etching the first insulating film and then forming a third insulating film that covers the upper electrode, A step of forming a second opening in which the first wiring is exposed in the third insulating film and the second insulating film, The method for manufacturing a Josephson junction element according to claim 5, further comprising the step of forming a second wiring connected to the first wiring in the second opening.

7. A method for manufacturing a Josephson junction element according to claim 1 or 2, characterized in that the first insulating film is deposited using atomic layer volume deposition, chemical vapor deposition, or sputtering in the step of depositing the first insulating film.

8. In the step of forming the lower electrode, the lower electrode is formed by patterning a film made of the superconducting material deposited using sputtering, chemical vapor deposition, or vacuum deposition. A method for manufacturing a Josephson junction element according to claim 1 or 2, characterized in that the superconducting film is deposited using sputtering, chemical vapor deposition, or vacuum deposition in the step of depositing the superconducting film.

9. circuit board and A lower electrode, provided on the aforementioned substrate and formed of a superconducting material, An insulating film is provided on the lower electrode in contact with the lower electrode, The system comprises an upper electrode provided on the insulating film in contact with the insulating film, and formed of a superconducting material in a region that overlaps with the lower electrode in a plan view, The upper electrode covers the entire lower electrode in a plan view, and the outer edge of the upper electrode is located outside the outer edge of the lower electrode. A Josephson junction element characterized in that the insulating film is provided below the upper electrode and extends over the entire upper electrode.

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