Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can achieve high voltage resistance by mitigating electric field concentration at the edge of the p-type region of the active area. [Solution] The semiconductor device comprises a first semiconductor layer 2 of the first conductivity type provided on the front surface of a first conductivity type semiconductor substrate 1, and a parallel pn structure 51 in which a first column region 52 of the first conductivity type and a second column region 53 of the second conductivity type are repeatedly and alternately arranged. The active region 10 comprises a first semiconductor region 4 of the second conductivity type, a second semiconductor region 5 of the first conductivity type, a gate electrode 9 provided via a gate insulating film 8, and a third semiconductor region 12 of the second conductivity type. The end S of the third semiconductor region 12 on the terminal structure 30 side is located 50% of the width of the first column region 52 from the column end X2 on the active region 10 side of the second column region 53 on the active region 10 side of the terminal structure 30, and 50% of the width of the second column region 53 from the column end X2 on the active region 10 side of the terminal structure 30 side.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices. [Background technology]

[0002] Conventionally, the thickness of the parallel pn layer in the active section is made thinner than the pn layer in the pressure-resistant structure section, and a p is placed between the parallel pn layer in the active section and the p-type base region. + Superjunction semiconductor devices with a molded outer region are known (see, for example, Patent Document 1 below). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-139377 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Conventional semiconductor devices have a problem in that the edges of the active p-type region are located on the n-column of a parallel pn layer, which tends to concentrate the electric field at the corners of the active p-type region, causing a decrease in breakdown voltage. This disclosure aims to provide a semiconductor device that can mitigate electric field concentration at the edges of the active p-type region and achieve high breakdown voltage. [Means for solving the problem]

[0005] To solve the above-mentioned problems and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features: It is a semiconductor device having an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region. It comprises a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the front surface of a semiconductor substrate of a first conductivity type, and a parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type provided within the first semiconductor layer are repeatedly and alternately arranged in a direction parallel to the front surface. The active region comprises a first semiconductor region of a second conductivity type provided on the surface layer of the parallel pn structure, a second semiconductor region of a first conductivity type selectively provided on the surface layer of the first semiconductor region, a gate electrode provided via a gate insulating film in contact with a part of the first semiconductor region and a part of the second semiconductor region, and a third semiconductor region of a second conductivity type provided on the surface layer of the parallel pn structure closer to the termination structure than the gate electrode closest to the termination structure. The end of the third semiconductor region on the terminal structure side is located 50% of the width of the first column region toward the terminal structure from the column end on the active region side of the second column region, which is closest to the active region, and 50% of the width of the second column region toward the active region from the column end toward the active region from the position toward the terminal structure side.

[0006] According to the disclosure mentioned above, p + The active region side of the p-type region (third semiconductor region of the second conductivity type) is located 50% of the width of the n-type region (first column region of the first conductivity type) from the edge termination region's edge of the p-type region (second column region of the second conductivity type) closest to the active region, and 50% of the width of the p-type region from the edge termination region's edge, closer to the active region. + The electric field at the corner of the p-type region is mitigated by the presence of the immediately surrounding p-type region, making electric field concentration less likely and increasing the edge breakdown voltage. As a result, even when the edge length is shortened, creating a situation where electric field concentration is more likely, a high edge breakdown voltage can be ensured. [Effects of the Invention]

[0007] The semiconductor device described herein has the effect of mitigating electric field concentration at the edge of the active p-type region and achieving high voltage resistance. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view taken along line X-X' in Figure 3, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is a cross-sectional view taken along line Y-Y' in Figure 3, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 3] This is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 4] This graph shows the relationship between the p+ region edge position of the active region and the edge breakdown voltage in a silicon carbide semiconductor device according to the embodiment. [Figure 5] This is a cross-sectional view showing the edge position of the p+ type region in the active region of the silicon carbide semiconductor device according to the embodiment. [Figure 6] This is a cross-sectional view taken along line X-X' in Figure 7, showing the structure of a conventional silicon carbide semiconductor device. [Figure 7] This is a top view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0009] <Summary of the embodiments of this disclosure> To solve the above-mentioned problems and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features: It is a semiconductor device having an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region. It comprises a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate, provided on the front surface of a semiconductor substrate of a first conductivity type, and a parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type provided within the first semiconductor layer are repeatedly and alternately arranged in a direction parallel to the front surface. The active region comprises a first semiconductor region of a second conductivity type provided on the surface layer of the parallel pn structure, a second semiconductor region of a first conductivity type selectively provided on the surface layer of the first semiconductor region, a gate electrode provided via a gate insulating film in contact with a part of the first semiconductor region and a part of the second semiconductor region, and a third semiconductor region of a second conductivity type provided on the surface layer of the parallel pn structure closer to the termination structure than the gate electrode closest to the termination structure. The end of the third semiconductor region on the terminal structure side is located 50% of the width of the first column region toward the terminal structure from the column end on the active region side of the second column region, which is closest to the active region, and 50% of the width of the second column region toward the active region from the column end toward the active region from the position toward the terminal structure side.

[0010] According to the disclosure mentioned above, p + The active region side of the p-type region (third semiconductor region of the second conductivity type) is located 50% of the width of the n-type region (first column region of the first conductivity type) from the edge termination region's edge of the p-type region (second column region of the second conductivity type) closest to the active region, and 50% of the width of the p-type region from the edge termination region's edge, closer to the active region. + The electric field at the corner of the p-type region is mitigated by the presence of the immediately surrounding p-type region, making electric field concentration less likely and increasing the edge breakdown voltage. As a result, even when the edge length is shortened, creating a situation where electric field concentration is more likely, a high edge breakdown voltage can be ensured.

[0011] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above-described disclosure, the end of the third semiconductor region on the termination structure side is located 30% of the width of the first column region toward the termination structure side from the column end on the active region side of the second column region, which is closest to the active region of the termination structure, and 30% of the width of the second column region toward the active region side from the column end toward the active region side from the position toward the termination structure side.

[0012] Furthermore, the semiconductor device according to the present disclosure is characterized in that, in the above-described disclosure, the active region includes a trench that penetrates the first semiconductor region and the second semiconductor region and reaches the first semiconductor layer, the gate insulating film is provided inside the trench, and the gate electrode is provided inside the trench via the gate insulating film.

[0013] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the termination structure, the first column region and the second column region are not exposed on the surface of the first semiconductor layer opposite to the semiconductor substrate.

[0014] <Knowledge forming the basis of this disclosure> Conventionally, semiconductor devices with a superjunction (SJ) structure are known, in which the drift layer is a parallel pn layer formed by repeatedly arranging n-type and p-type regions alternately adjacent to each other in a direction parallel to the main surface of the substrate. The n-type and p-type regions constituting the parallel pn layer extend in a stripe-like manner parallel to the main surface of the semiconductor substrate (semiconductor chip). The n-type and p-type regions constituting the parallel pn layer are provided almost uniformly across almost the entire semiconductor substrate, from the active region in the center of the semiconductor substrate (center of the chip) to the edge of the semiconductor substrate (edge ​​of the chip).

[0015] Regarding the structure of a conventional silicon carbide semiconductor device with an SJ structure, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, an MOS-type field effect transistor with an insulated gate composed of a three-layer structure of metal-oxide-semiconductor) will be used as an example for explanation. FIG. 6 is a cross-sectional view taken along the line X-X' of FIG. 7 showing the structure of a conventional silicon carbide semiconductor device. FIG. 7 is a top view showing the structure of a conventional silicon carbide semiconductor device.

[0016] The conventional silicon carbide semiconductor device 150 shown in FIGS. 6 and 7 has a general trench gate structure in the active region 110 of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide, and is a vertical MOSFET with an SJ structure in which the n-type drift layer 102 is a parallel pn layer 151. The semiconductor substrate 140 has a rectangular planar shape. The active region 110 has a substantially rectangular planar shape and is provided at the center (chip center) of the semiconductor substrate 140. The periphery of the active region 110 is surrounded by an edge termination region 130.

[0017] The semiconductor substrate 140 is formed by laminating an n ++ -type starting substrate 141, an n - -type buffer layer 103, and an n-type epitaxial layer 142 that becomes the n-type drift layer 102. The main surface on the side of the n-type epitaxial layer 142 of the semiconductor substrate 140 is defined as the front surface, and the main surface on the side of the n ++ -type drain region 101, which is the n ++ -type starting substrate 141 side, is defined as the back surface. The n-type epitaxial layer 142 is the portion that becomes the n-type drift layer (drift region) 102 and includes the parallel pn layer 151.

[0018] n ++ On the front surface (the surface on the side of the n-type drift layer 102) of the n-type starting substrate 141, a MOS gate structure composed of a p-type base region 104, an n + -type source region 105, a gate trench 107, a gate insulating film 108, and a gate electrode 109 is provided. Inside the n-type drift layer 102, p +A type region 111 is selectively provided. In the gate trench 107 on the edge terminal region 130 side of the active region 110, p + The mold region 111 extends from the side wall on the edge termination region 130 side of the gate trench 107 to the JTE structure 132, which will be described later. + Type region 112 is p + It is provided on the mold region 111 and is exposed on the surface of the semiconductor substrate 140.

[0019] The edge termination region 130 has a junction termination extension (JTE) structure 132 as a pressure-resistant structure, and n + A channel stopper region 134 and a JTE structure 132 are arranged. The JTE structure 132 surrounds the active region 110. The boundary T between the active region 110 and the edge termination region 130 is the inner end (inner circumference) of the JTE structure 132 and p + This is the boundary with type regions 111 and 112.

[0020] n + The channel stopper region 134 is located outside (towards the chip edge) of the JTE structure 132, away from the JTE structure 132, and reaches the edge of the semiconductor substrate 140. + The channel stopper region 134 extends along the edge of the semiconductor substrate 140 and surrounds the JTE structure 132.

[0021] The parallel pn layer 151 is uniformly provided across almost the entire semiconductor substrate 140, from the active region 110 to the edge termination region 130. The parallel pn layer 151 has an SJ structure in which n-type regions 152 and p-type regions 153 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 140. The n-type region 152 and p-type region 153 of the parallel pn layer 151 extend in a stripe-like manner in a second direction Y parallel to the front surface of the semiconductor substrate 140 and perpendicular to the first direction X.

[0022] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are directly beneath the JTE structure 132 (n ++It is arranged from the drain region 101 side to almost the entire edge termination region 130. The parallel pn layer 151 is in contact with the JTE structure 132 and is in contact with the JTE structure 132. + The channel stopper region 134 does not reach the front surface of the semiconductor substrate 140.

[0023] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are arranged at equal intervals across approximately the entire semiconductor substrate 140, from the active region 110 to the edge termination region 130. The carrier concentration (impurity concentration) and width (width in the first direction X) of the n-type region 152 and p-type region 153 of the parallel pn layer 151 are set so that a charge balance is achieved between adjacent n-type region 152 and p-type region 153 of the parallel pn layer 151.

[0024] A charge balance means that the charge amount, expressed as the product of the carrier concentration and width in the n-type region 152, and the charge amount, expressed as the product of the carrier concentration and width in the p-type region 153, are approximately the same within a range that includes tolerances due to process variations.

[0025] As shown in Figure 6, in the conventional silicon carbide semiconductor device 150, p + The edges of type regions 111 and 112 (the boundary T between the active region 110 and the edge termination region 130) are located directly above the center of the n-type region 152.

[0026] In the silicon carbide semiconductor device 150 with an SJ structure, the breakdown voltage of the edge termination region 130 is made higher than that of the active region 110 in order to improve breakdown voltage and avalanche breakdown voltage, so that the breakdown voltage of the chip is determined by the breakdown voltage of the cells in the active region 110. For this reason, a JTE structure 132 is formed near the surface of the edge termination region 130, which gradually changes the doping concentration, thereby eliminating localized electric field concentration points and dispersing the electric field.

[0027] However, p + If the edges of type regions 111 and 112 are located directly above the center of n-type region 152, then the p of the active region 110, which has a high impurity concentration, +A problem arose where the electric field tended to concentrate at the corners of the mold regions 111 and 112, which became the rate-limiting factor and caused a decrease in the breakdown voltage of the silicon carbide semiconductor device 150 with an SJ structure.

[0028] A preferred embodiment of the silicon carbide semiconductor device according to this disclosure, which solves the problems of the conventional silicon carbide semiconductor devices described above, will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, layers or regions prefixed with n or p mean that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p mean that they have a higher and lower impurity concentration than layers or regions without them, respectively. In the following description of embodiments and attached drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. It is preferable to include up to 5% in the description of the same or equivalent components to account for manufacturing variations.

[0029] (Embodiment) The structure of a silicon carbide semiconductor device according to the embodiment will be explained using a MOSFET as an example. Figure 1 is a cross-sectional view taken along the line X-X' in Figure 3, showing the structure of a silicon carbide semiconductor device according to the embodiment. Figure 2 is a cross-sectional view taken along the line Y-Y' in Figure 3, showing the structure of a silicon carbide semiconductor device according to the embodiment. Figure 3 is a top view showing the structure of a silicon carbide semiconductor device according to the embodiment. In Figure 3, the number of n-type regions 52 and p-type regions 53 of the parallel pn layer 51 is simplified, and the scale dimensions differ from those of Figures 1 and 2.

[0030] The silicon carbide semiconductor device 50 according to this embodiment comprises an active region 10 and an edge termination region (termination structure) 30 on a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and the impurity concentration from the active region 10 to the edge termination region 30 is 2 × 10 17 / cm 3 This is a vertical MOSFET with a trench gate structure (device structure) in an SJ structure, where the following n-type drift layer (first semiconductor layer of the first conductivity type) 2 is a parallel pn layer 51. The active region 10 is the region through which the main current flows when the MOSFET is ON, and is located in the center of the semiconductor substrate 40 (center of the chip).

[0031] The edge termination region 30 is the region between the active region 10 and the edge of the semiconductor substrate 40, and surrounds the active region 10. The active region 10 and the edge termination region 30 have an SJ structure in which the n-type drift layer 2 is a parallel pn layer 51.

[0032] The edge termination region 30 has the function of mitigating the electric field on the front side (first main surface) of the semiconductor substrate 40 of the n-type drift layer 2 in the active region 10, thereby maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which leakage current does not increase excessively and the element does not malfunction or break down. The boundary between the active region 10 and the edge termination region 30 is the inner end (inner circumference) of the JTE structure 32 described later and the p described later + This is the boundary with type regions 11 and 12. Near the boundary, in the active region 10, p + Type region 11 and p + The type region 12 consists of two layers, but the edge termination region 30 consists of a single layer of JTE structure 32.

[0033] As shown in Figures 1 and 2, the silicon carbide semiconductor device 50 according to this embodiment has a general trench gate structure on the front side of the semiconductor substrate 40 in the active region 10. The trench gate structure is a p-type base region (first semiconductor region of the second conductivity type) 4, n + It consists of a type source region (second semiconductor region of the first conductivity type) 5, a gate trench 7, a gate insulating film 8, and a gate electrode 9. ++ A type contact region (not shown) may be provided. The semiconductor substrate 40 is made of n ++ n - The structure consists of a type buffer layer 3 and an n-type epitaxial layer 42 which forms an n-type drift layer 2.

[0034] The main surface of the semiconductor substrate 40 on the n-type epitaxial layer 42 side is considered the front surface, ++ The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface). ++ The starting substrate 41 has an impurity concentration of 1 × 10⁻⁶ 18 / cm3 n ++ This is a type drain region 1. In this embodiment, n ++ Between the drain region 1 and the parallel pn layer 51, n - This is a semi-SJ structure in which a type buffer layer 3 is provided. The gate trench 7 penetrates the surface of the semiconductor substrate 40 in the depth direction Z and reaches into the n-type epitaxial layer 42.

[0035] The gate trenches 7 extend in a stripe-like manner in a direction parallel to the front surface of the semiconductor substrate 40 (here, in the second direction Y). A gate electrode 9 is provided inside the gate trenches 7 via a gate insulating film 8. The p-type base region 4 extends in a stripe-like manner in the second direction Y between adjacent gate trenches 7. + The type source regions 5 are selectively provided on the surface of the p-type base region 4 between adjacent gate trenches 7. ++ The type contact regions may be selectively provided on the surface of the p-type base regions 4 between adjacent gate trenches 7.

[0036] In the active region 10, between the p-type base region 4 and the parallel pn layer 51 (n-type drift layer 2), + Type region 11 is selectively provided. + The type region 11 has the function of mitigating the electric field applied to the bottom surface of the gate trench 7. + The type region 11 is positioned separately from the p-type base region 4 and faces the bottom surface of the gate trench 7 in the depth direction Z. + The p-type region 11 and the p-type base region 4 are periodically connected in a second direction Y (not shown). In the gate trench 7 on the edge terminal region 30 side of the active region 10, p + The mold region 11 extends from the side wall on the edge end region 30 side of the gate trench 7 to the JTE structure 32. + The type region 12 (third semiconductor region of the second conductivity type) is provided on the surface layer of the parallel pn layer 51 on the edge termination region 30 side, closer to the edge termination region 30 than the gate electrode 8 on the edge termination region 30 side. + It is in contact with the mold region 11 and exposed on the surface of the semiconductor substrate 40.

[0037] The edge termination region 30 has a pressure-resistant structure, a joint termination extension (JTE) structure 32, and n + A channel stopper region 34 and are located there. The JTE structure 32 surrounds the active region 10. For example, the effective doping concentration of the JTE structure 32 is 5 × 10⁻¹⁰. 16 ~5×10 17 / cm 3 Within the range, p of the active region 10 + The length of the JTE structure 32, relative to the end of the mold region 11, is in the range of 10 to 100 μm.

[0038] The JTE structure 32 is a structure in which multiple p-type regions are arranged concentrically adjacent to the active region 10, with the impurity concentration decreasing as they move away from the active region 10. The JTE structure 32 mitigates electric field concentration on the active region side, preventing device failure due to the application of a voltage below a predetermined voltage (the breakdown voltage of the edge termination region 30).

[0039] n + The channel stopper region 34 is located outside the JTE structure 32 and at a distance from the JTE structure 32, and reaches the edge of the semiconductor substrate 40, for example, along the four sides (straight sections) of the edge of the semiconductor substrate 40. + The channel stopper region 34 extends along the edge of the semiconductor substrate 40 and surrounds the JTE structure 32.

[0040] The parallel pn layer (parallel pn structure) 51 is an SJ structure in which n-type regions (first column regions of the first conductivity type) 52 and p-type regions (second column regions of the second conductivity type) 53 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 52 and p-type regions 53 of the parallel pn layer 51 extend in a stripe-like manner in a second direction Y parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X, up to near the edge of the edge termination region 30. Furthermore, the parallel pn layer 51 is arranged in the active region 10 and the edge termination region 30 in the first direction X.

[0041] In Figures 1 and 2, the n-type region 52 and p-type region 53 of the parallel pn layer 51 are n++ Although it is a semi-SJ structure that does not reach the type starting substrate 41, n ++ The structure may be a Full-SJ structure that reaches the starting substrate 41. Also, the lengths of the n-type region 52 and the p-type region 53 may differ between the active region 10 and other regions. Furthermore, as shown in Figure 1, the pitch of the pair of n-type region 52 and p-type region 53 is equal to the pitch of the gate trench 7, and in the active region 10 where the gate trench 7 is formed, the p-type region 53 is directly below the gate trench 7. The lengths of the n-type region 52 and p-type region 53 of the parallel pn layer 51 vary depending on the breakdown voltage class; for example, in a Full-SJ structure with a breakdown voltage of 1200V, the length is about 5 μm.

[0042] The adjacent n-type region 52 and p-type region 53 of the parallel pn layer 51 are approximately charge-balanced. Charge balance means that the charge amount, expressed as the product of the carrier concentration (impurity concentration) and width of the n-type region of the parallel pn layer, and the charge amount, expressed as the product of the carrier concentration and width of the p-type region, are approximately the same within a range that includes tolerances due to process variations. Therefore, the carrier concentration and width (width in the first direction X) of the n-type region 52 and p-type region 53 are set so that the adjacent n-type region 52 and p-type region 53 of the parallel pn layer 51 are approximately charge-balanced.

[0043] It is sufficient that the adjacent n-type region 52 and p-type region 53 of the parallel pn layer 51 are roughly charge-balanced, and the carrier concentration and width of the n-type region 52 and p-type region 53 of the parallel pn layer 51 are set as appropriate. For example, the width of the n-type region 52 and the width of the p-type region 53 of the parallel pn layer 51 may be approximately the same. In this case, the carrier concentration of the n-type region 52 and the carrier concentration of the p-type region 53 should be set to be approximately the same. Approximately the same width and carrier concentration means that they are the same width and the same carrier concentration, respectively, within a range that includes tolerances due to process variability. For example, the effective doping concentration of the n-type region 52 and the p-type region 53 is 2 × 10⁻⁶. 16 ~2×10 17 / cm 3The width is within the range of 0.5 to 3 μm. Furthermore, the concentration difference between the n-type region 52 and the p-type region 53 is within ±30%, and the width difference between the n-type region 52 and the p-type region 53 is within ±20%.

[0044] Furthermore, the parallel pn layers 51 are arranged to extend beyond the outer edge (periphery) of the JTE structure 32 in the first direction X, such that at least one p-type region 53 is located beyond the outer edge (periphery) of the JTE structure 32 in the first direction X.

[0045] By positioning the p-type region 53 of the parallel pn layer 51 beyond the outer edge of the JTE structure 32 in the first direction X, electric field concentration at the outer edge of the JTE structure 32 can be suppressed when the MOSFET is off. The outer edge of the JTE structure 32 refers to the outer edge of the outermost p-type region among the multiple p-type regions that constitute the JTE structure 32.

[0046] The range in which the parallel pn layers 51 are arranged is limited to the range from the outer edge of the JTE structure 32 in the first direction X, thereby reducing the number of floating p-type regions 53 arranged in the edge termination region 30. This reduces the amount of accumulated charge of minority carriers (holes) that accumulate in the edge termination region 30 due to MOSFET switching, etc., and remain without being discharged to the outside. For this reason, it is preferable to have a small number of p-type regions 53 arranged outside the outer edge of the JTE structure 32 in the first direction X.

[0047] The parallel pn layer 51 is within the above range from the outer end of the JTE structure 32 in the first direction X, and in the first direction X, n + Directly below the type channel stopper region 34 (n ++ It may be arranged up to the drain region 1 side. A normal n-type drift region 2 may be arranged between the parallel pn layer 51 and the edge of the semiconductor substrate 40 in the first direction X. The less this normal n-type drift region 2 is provided, or the narrower the width of this normal n-type drift region 2 is made, the smaller the semiconductor substrate 40 can be made.

[0048] The n-type region 52 and p-type region 53 of the parallel pn layer 51 in the edge termination region 30 are in contact with the JTE structure 32 in the depth direction Z. The p-type region 53 of the parallel pn layer 51 provided on the outside of the JTE structure 32 is located at a depth D1 from the surface of the semiconductor substrate 40 and is not exposed to the surface of the semiconductor substrate 40. The depth D1 is, for example, the same as the thickness of the JTE structure 32. Between the parallel pn layer 51 provided on the outside of the JTE structure 32 and the surface of the semiconductor substrate 40, there is an impurity region with a lower impurity concentration than the normal n-type drift region 2, for example, an impurity concentration of 2 × 10⁻¹⁶. 16 / cm 3 The following n - A layer 35 is present. This makes it easier for the depletion layer to spread outwards.

[0049] In this embodiment, in the silicon carbide semiconductor device 50 with an SJ structure, the p + By defining the positional relationship between the edges of the mold regions 11 and 12 and the p-type region 53 of the parallel pn layer 51, it is possible to ensure withstand voltage with a short edge length.

[0050] Figure 4 shows the active region p in the silicon carbide semiconductor device according to the embodiment. + This graph shows the relationship between the mold region edge position and edge breakdown voltage. Figure 4 shows the simulation results for a silicon carbide semiconductor device 50 with an SJ structure in the breakdown voltage class of 750V, and assumes silicon carbide semiconductor devices 50 with an SJ structure in the breakdown voltage class of 1200 to 3300V. Figure 5 shows the p of the active region in the silicon carbide semiconductor device according to the embodiment. + This is a cross-sectional view showing the edge position of the mold region. In Figure 4, the vertical axis represents the edge breakdown voltage of the silicon carbide semiconductor device 50 (breakdown voltage of the edge termination region 30), and the unit is V. The horizontal axis represents the p of the active region 10. + The position of the ends S of type regions 11 and 12 (see Figure 5) is shown as being displaced from the center X3 (see Figure 5) of the p-type region 53 located at the boundary between the active region 10 and the edge termination region 30. The unit is μm. A positive direction indicates displacement towards the edge termination region 30, and a negative direction indicates displacement towards the active region 10. In Figure 5, p + This figure illustrates the case where the ends S of type regions 11 and 12 are displaced by approximately -0.25 μm in the negative direction from the center X3 of the p-type region 53.

[0051] Furthermore, in Figures 4 and 5, the widths of both the n-type region 52 and the p-type region 53 are 1 μm. X1 in Figure 5 corresponds to -1 μm in Figure 4, and p + This is the case where the ends S of type regions 11 and 12 are located in the center of the n-type region 52. X2 in Figure 5 corresponds to -0.5 μm in Figure 4, and p + This is the case where the ends S of the n-type regions 11 and 12 are located at the boundary between the n-type region 52 and the p-type region 53. X3 in Figure 5 corresponds to 0 μm in Figure 4, and p + This is the case where the ends S of type regions 11 and 12 are located in the center of the p-type region 53. X4 in Figure 5 corresponds to 0.5 μm in Figure 4, and p + This is the case where the edges S of type regions 11 and 12 are located at the boundary between the p-type region 53 and the n-type region 52. X5 in Figure 5 corresponds to 1 μm in Figure 4, and p + This is the case when the ends S of the type regions 11 and 12 are located in the center of the n-type region 52. Also, in the conventional silicon carbide semiconductor device 150 shown in Figure 6, p + The ends S of type regions 111 and 112 are located in the center of the n-type region 152, corresponding to X5 in Figure 5.

[0052] As shown in Figure 4, p + If the edges S of type regions 11 and 12 are displaced by -1 μm to 0 μm from the center X3 of the p-type region 53, the edge breakdown voltage will increase, and p + If the edges S of mold regions 11 and 12 are displaced by 0 μm to 1 μm from the center X3 of the p-type region 53, the edge breakdown voltage will be lower.

[0053] Figure 4 shows the case where the width of both the n-type region 52 and the p-type region 53 is 1 μm. Therefore, in this embodiment, p +The end S of type regions 11 and 12 on the active region 10 side is located 50% of the width of the n-type region 52 from the end X2 of the p-type region 53 on the active region 10 side of the edge termination region 30, and 50% of the width of the p-type region 53 from the end X2, and 50% of the width of the p-type region 53 from the edge termination region 30, and is located 50% of the width of the p-type region 53 from the end X2, and is located 50% of the width of the p-type region 53, and is located on the active region 10 side of the edge termination region 30. In other words, the end S does not include positions X1 and X3, but is between positions X1 and X3. This makes it possible to increase the edge breakdown voltage of the silicon carbide semiconductor device 50 (approximately 1050V or more in the example of Figure 4). Furthermore, p + By positioning the end S of the type regions 11 and 12 on the active region 10 side, so that it is 30% of the width of the n-type region 52 from the end X2 of the p-type region 53 toward the edge termination region 30 beyond position X6 (see Figure 5) toward the active region 10, and 30% of the width of the p-type region 53 toward position X7 (see Figure 5) toward the active region 10 beyond position X7 (see Figure 5) toward the edge termination region 30, the edge breakdown voltage of the silicon carbide semiconductor device 50 can be further increased (approximately 1060V or more in the example of Figure 4). In this case, the end S does not include positions X6 and X7, but is located between positions X6 and X7.

[0054] Also, p + The p-type regions 53 located at the boundary between the active region 10 and the edge termination region 30, which define the ends S of the type regions 11 and 12, are preferably the 1st to 50th p-type regions 53 located outside the outermost gate trench 7, counting from the inside.

[0055] Thus, p + If the positions of the ends S of type regions 11 and 12 are within the above range, then p + The electric field applied to the corners of the type regions 11 and 12 is mitigated by the presence of the p-type region 53 immediately outside of it (on the edge termination region 30 side), making electric field concentration less likely and increasing the edge breakdown voltage. As a result, even when the edge length (length of the edge termination region) is shortened, creating a situation where the electric field is more likely to concentrate, a high edge breakdown voltage can be ensured. Therefore, in the silicon carbide semiconductor device 50 of this embodiment, the edge length required to ensure breakdown voltage can be shortened. This is particularly effective when the edge length of the silicon carbide semiconductor device 50 is shortened (for example, when the length of the JTE structure 32 is 10 μm).

[0056] Next, a method for manufacturing the silicon carbide semiconductor device 50 according to the embodiment will be described. First, n ++ type drain region 1, an n ++ type starting substrate (semiconductor wafer) 41, an n - type buffer layer 3 and an n-type drift layer 2 including parallel pn layers 51 are formed. For example, when using a multi-stage epitaxial method, each region to become an n-type region 52 and a p-type region 53 is selectively formed by ion implantation so that regions of the same conductivity type are adjacent to each other in the depth direction Z in the n-type epitaxial layer 42 that becomes the n-type buffer layer 3 or the n-type drift layer 2 each time the n-type epitaxial layer 42 is epitaxially grown in multiple stages (for example, 9 stages).

[0057] Also, the parallel pn layer 51 may be formed, for example, by using a trench implantation epitaxial method in which, after forming the n-type epitaxial layer 42 that becomes the n-type buffer layer 3 or the n-type drift layer 2, a trench (hereinafter referred to as an SJ trench) is formed in the n-type epitaxial layer 42, leaving a portion to become the n-type region 52, and the SJ trench is filled with a p-type epitaxial layer to become the p-type region 53.

[0058] Also, the p + type regions 11, 12, the n + type source region 5, the p ++ type contact region, the JTE structure 32, the n + type channel stopper region 34, and the n - type layer 35 can be formed by ion implantation. After that, a gate trench 7 is formed, and a gate insulating film 8 is formed along the front surface of the semiconductor substrate 40 and the inner wall of the gate trench 7. At this time, in the embodiment, the p + type regions 11, 12 ends S are the p + ​​​​The ends S of the type regions 11 and 12 on the active region 10 side are formed from the end X2 of the p-type region 53 on the active region 10 side of the edge termination region 30, on the edge termination region 30 side from the position X1 on the active region 10 side by 50% of the width of the n-type region 52, and from the end X2, on the active region 10 side from the position X3 on the edge termination region 30 side by 50% of the width of the p-type region 53. Preferably, from the end X2 of the p-type region 53, on the edge termination region 30 side from the position X6 on the active region 10 side by 30% of the width of the n-type region 52, and from the end X2, on the active region 10 side from the position X7 on the edge termination region 30 side by 30% of the width of the p-type region 53. Next, the polysilicon layer deposited on the front surface of the semiconductor substrate 40 is etched back so as to be embedded inside the gate trench 7, and the portion that becomes the gate electrode 9 is left inside the gate trench 7. Thereby, the silicon carbide semiconductor device 50 shown in FIGS. 1 and 2 can be formed.

[0059] As described above, according to the embodiment, p + The end on the active region side of the p-type region is, from the end of the p-type region on the active region side of the edge termination region, on the edge termination region side from the position on the active region side by 50% of the width of the n-type region, and from the end of the p-type region, on the active region side from the position on the edge termination region side by 50% of the width of the p-type region. Thereby, the electric field applied to the corner of the p + type region is relaxed by the presence of the p-type region immediately outside it, making it difficult for electric field concentration to occur, and the edge breakdown voltage becomes higher. As a result, even when the edge length is shortened and the situation where the electric field is more likely to concentrate occurs, a high edge breakdown voltage can be ensured.

[0060] In the above description, the present disclosure has explained the case in which a MOS gate structure is constructed on the first main surface of a silicon carbide substrate as an example, but it is not limited to this, and the surface orientation of the main surface of the substrate can be changed in various ways. Furthermore, although the embodiments of this disclosure have been explained using a trench-type MOSFET as an example, it is not limited to this, and can be applied to various semiconductor devices such as trench-type IGBTs and other MOS-type semiconductor devices. In addition, although the embodiments described above have been explained using silicon carbide as the semiconductor as an example, it can also be applied to semiconductors other than silicon carbide, such as silicon (Si) and gallium nitride (GaN). Furthermore, in the embodiments of this disclosure, the first conductivity type is set to n-type and the second conductivity type to p-type, but this disclosure is also valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0061] As described above, the silicon carbide semiconductor device according to this disclosure is useful for high-voltage semiconductor devices used in power supply equipment for power converters and various industrial machines. [Explanation of Symbols]

[0062] 1, 101 n ++ Type drain region 2. 10² n-type drift layer 3, 103 n - Type buffer layer 4, 104 p-type base region 5, 105 n + Type source area 7, 107 Gate Trench 8,108 Gate Insulator 9, 109 TT 10, 110 active area pp. 11, 12, 111, 112 + type area 30, 130 edge termination region 32, 132 JTE structure 34, 134 n + Type channel stopper region 35 n - mold layer 40, 140 semiconductor substrates 41, 141 n ++ Mold starting substrate 42, 142 n-type epitaxial layers 50, 150 Silicon Carbide Semiconductor Devices 51, 151 parallel pn layer 52, 152 parallel pn layer n-type region 53, 153 parallel pn layer p-type region X Direction parallel to the front surface of the semiconductor substrate (first direction) Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction). Z-direction (depth)

Claims

1. A semiconductor device having an active region and a terminal structure disposed outside the active region and surrounding the periphery of the active region, A first semiconductor layer of the first conductivity type, having a lower impurity concentration than the semiconductor substrate, is provided on the front surface of the first conductivity type semiconductor substrate. A parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type provided within the first semiconductor layer are repeatedly and alternately arranged in a direction parallel to the front surface, Equipped with, In the aforementioned active region, A first semiconductor region of a second conductivity type is provided on the surface layer of the parallel pn structure, A second semiconductor region of a first conductivity type is selectively provided on the surface layer of the first semiconductor region, A gate electrode is provided via a gate insulating film that is in contact with a part of the first semiconductor region and a part of the second semiconductor region, A third semiconductor region of a second conductivity type is provided on the surface layer of the parallel pn structure on the terminal structure side, which is closer to the terminal structure than the gate electrode on the terminal structure side, Equipped with, A semiconductor device characterized in that the end of the third semiconductor region on the terminal structure side is located 50% of the width of the first column region toward the terminal structure from the column end on the active region side of the second column region closest to the active region of the terminal structure, and 50% of the width of the second column region toward the active region from the column end toward the active region from the position toward the terminal structure side.

2. The semiconductor device according to claim 1, wherein the end of the third semiconductor region on the terminal structure side is located 30% of the width of the first column region toward the terminal structure side from the column end on the active region side of the second column region closest to the active region of the terminal structure, and 30% of the width of the second column region toward the active region side from the column end toward the active region side from the position on the terminal structure side.

3. In the aforementioned active region, The device comprises trenches that penetrate the first semiconductor region and the second semiconductor region and reach the first semiconductor layer, The gate insulating film is provided inside the trench, The semiconductor device according to claim 1, characterized in that the gate electrode is provided inside the trench via the gate insulating film.

4. The semiconductor device according to claim 1, characterized in that, in the terminal structure, the first column region and the second column region are not exposed on the surface of the first semiconductor layer opposite to the semiconductor substrate.

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