Indication device

Abstract

To provide a display device that includes pixels capable of high resolution. [Solution] The display device includes a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, each of the plurality of pixels having a first region, a second region adjacent to the first region, a third region adjacent to the second region, and a fourth region adjacent to the third region, the first region, the second region, the third region and the fourth region being provided along the first direction, and the second region and the fourth region each being superimposed on a plurality of different semiconductor layers arranged to be located along the first direction.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices containing light-emitting elements have been implemented in televisions, smartphones, and other devices, and are becoming widespread. For example, a display device includes multiple pixels and a control circuit for driving the multiple pixels. Each of the multiple pixels includes multiple transistors, capacitive elements, and light-emitting elements. The light-emitting elements are elements that emit light in a self-emissive manner (self-emissive light-emitting elements), such as light-emitting diodes (LEDs), tiny light-emitting diodes (micro-LEDs), or organic electroluminescence (EL) elements. The control circuit in the display device can supply a potential to each of the multiple pixels and allow a current corresponding to the supplied potential to flow through the light-emitting elements contained in each of the multiple pixels. Each light-emitting element emits light with a brightness corresponding to the current flowing through it, and the pixels containing the light-emitting elements can display an image with gradations corresponding to that brightness.

[0003] For example, Patent Document 1 discloses a display device including a light-emitting element. The pixels in the display device described in Patent Document 1 include nine transistors (T1 to T9), two series-connected capacitive elements (Chold, Cst), and one light-emitting element (LED). Furthermore, the driving method for the display device described in Patent Document 1 includes electrically connecting the gate electrode (Gate) of transistor T1 and one electrode-side node (D-node) of the capacitive element Chold with transistor T3 during the initialization period and the light-emitting period. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 11972726 [Overview of the project] [Problems that the invention aims to solve]

[0005] For example, in recent years, in order to accommodate the increasing resolution and larger screen size of display devices including light-emitting elements, there has been a demand for higher resolution pixels by reducing the number of elements within each pixel.

[0006] In view of these challenges, one embodiment of the present invention aims to provide a display device including pixels capable of high resolution. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, wherein the plurality of pixels have a first region, a second region adjacent to the first region, a third region adjacent to the second region, and a fourth region adjacent to the third region, and the first region, the second region, the third region and the fourth region are provided along the first direction, and the second region and the fourth region each superimpose a plurality of different semiconductor layers arranged to be located along the first direction. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram showing the configuration of a display device according to one embodiment of the present invention. [Figure 2] This is a schematic diagram showing the input signal to a pixel circuit according to one embodiment of the present invention. [Figure 3] This is a circuit diagram showing the configuration of a pixel circuit according to one embodiment of the present invention. [Figure 4] This is a plan view showing the pixel layout according to one embodiment of the present invention. [Figure 5] This is a plan view showing the pixel layout according to one embodiment of the present invention. [Figure 6] This is a plan view showing the pixel layout according to one embodiment of the present invention. [Figure 7] This is an end view showing the end face cut along A1-A2 in the layout shown in Figure 5 or Figure 6. [Figure 8] This is an end view showing the end face cut along B1-B2 in the layout shown in Figure 5 or Figure 6. [Figure 9] This is an end view showing the end face cut along C1-C2 in the layout shown in Figure 5 or Figure 6. [Figure 10] This is a sequence diagram showing a method for manufacturing a display device according to one embodiment of the present invention. [Figure 11] This is a sequence diagram showing a method for manufacturing a display device according to one embodiment of the present invention. [Figure 12] This is a plan view showing the pixel layout according to one embodiment of the present invention. [Figure 13] This is a plan view showing the pixel layout according to one embodiment of the present invention. [Figure 14] This is a plan view showing the pixel layout according to one embodiment of the present invention. [Figure 15] This is a plan view showing the layout of a modified pixel according to one embodiment of the present invention. [Figure 16] This is a plan view showing a part of the layout of a modified pixel according to one embodiment of the present invention. [Modes for carrying out the invention]

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in many different modes and is not to be construed as being limited to the description of the embodiments exemplified below. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, configuration, etc. of each part compared to the actual mode, but this is merely an example and does not limit the interpretation of the present invention. Note that the letters "first" and "second" appended to each element are for the sake of convenience in distinguishing each element and have no further meaning unless otherwise specified.

[0010] Also, in this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C", etc. do not exclude the case where α includes a plurality of combinations of A to C unless otherwise explicitly stated. Furthermore, these expressions do not exclude the case where α includes other elements.

[0011] In one embodiment of the present invention, the first direction D1 intersects the second direction D2, and the third direction D intersects the first direction D1 and the second direction D2 (D1D2 plane).

[0012] In the specification of this application, when the notations "identical (same)" and "coincident" are used, the identical and the coincident may include errors within the design range. Also, in one embodiment of the present invention, when errors within the design range are included, the expressions "substantially identical" and "substantially coincident" may be used.

[0013] A display device according to one embodiment of the present invention can use LEDs, micro-LEDs, EL elements, etc., as self-emissive light-emitting elements. However, the self-emissive light-emitting elements are not limited to LEDs, micro-LEDs, or EL elements. Depending on the application and specifications of the display device, a self-emissive light-emitting element can be appropriately selected within the scope of the display device according to one embodiment of the present invention. The display devices in each embodiment of the present invention described below are display devices that use EL elements as self-emissive light-emitting elements. For example, a display device that uses EL elements may be referred to as a self-emissive display device, an EL display device, etc.

[0014] [1. First Embodiment] [1-1. Overview of the display device 10] Referring to Figure 1, an overview of the display device 10 according to the first embodiment will be described. Figure 1 is a schematic diagram showing the configuration of the display device 10. The configuration of the display device 10 shown in Figure 1 is an example, and the configuration of the display device 10 is not limited to the configuration shown in Figure 1.

[0015] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC200), and an IC chip 110. The display device 10 also includes a display area 22 superimposed on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0016] In the display area 22, multiple pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. A pixel 180 is the smallest unit that constitutes a part of the image displayed in the display area 22. Each of the multiple pixels 180 may correspond to, for example, a sub-pixel R, sub-pixel G, and sub-pixel B. Three sub-pixels may form one pixel. There are no restrictions on the arrangement of the multiple pixels 180, and the arrangement of the multiple pixels 180 may be a delta arrangement, a pentile arrangement, etc. For example, the arrangement of the multiple pixels 180 in the display device 10 is a stripe arrangement.

[0017] Sub-pixels R, G, and B are configured to display images of different colors from each other. For example, each of sub-pixels R, G, and B includes a light-emitting element containing a light-emitting layer that emits red, green, and blue light, respectively. By supplying an arbitrary potential or current to each of the three sub-pixels, the display device 10 can display an image.

[0018] For example, the peripheral area 24 is provided with an IC chip 110 and two control circuits 120. The two control circuits 120 are located on the left and right sides of the display area 22. The IC chip 110 is connected to the terminal section 150 using connection wires 341. Each of the two control circuits 120 is connected to the IC chip 110 using connection wires 342. The peripheral area 24 is sometimes referred to as the frame area. The connection wire 341 may be referred to as connection wire 341 on its own, or as a bundle of multiple connection wires 341. Similarly to connection wire 341, connection wire 342 may be referred to as connection wire 342 on its own, or as a bundle of multiple connection wires 342.

[0019] The terminal area 26 is provided with a terminal section 150 and an FPC 200 electrically connected to the terminal section 150. The terminal area 26 is the area opposite to the area where the display area 22 is provided, along the first direction D1, relative to the peripheral area 24.

[0020] The FPC200 is connected to an external device (not shown) outside the display device 10. The display device 10 is connected to the external device via the FPC200 and the terminal section 150. Control signals and potentials are transmitted from the external device to the display device 10 via the FPC200 and the terminal section 150. The display device 10 uses the received control signals and potentials from the external device to drive each pixel 180 provided on the display device 10. As a result, the display device 10 can display an image in the display area 22.

[0021] The IC chip 110 supplies signals, potentials, etc., to drive each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via the FPC 200, terminal section 150, and connecting wiring 341.

[0022] Each of the IC chip 110 and the two control circuits 120 may be referred to as a control circuit individually, or a group of circuits including part or all of each of the IC chip 110 and the two control circuits 120 may be referred to as a control circuit.

[0023] [1-2. Configuration of IC chip 110] Referring to Figure 1, the outline of the IC chip 110 will be described. The IC chip 110 is located adjacent to the display area 22 along a first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0024] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on an ON signal and an OFF signal supplied to the selection signal. The selection circuit is selected by the ON signal supplied to the selection signal and supplies an image data signal SL(m), including the data signal VDATA, to the image data signal line 321 and the pixels 180 electrically connected to the image data signal line 321. For example, the selection signal and the image data signal SL(m) are transmitted as digital signals from an external device to the IC chip 110 via the FPC 200 and the terminal section 150. Also, for example, the data signal VDATA (image data signal SL(m)) is DA-converted by the IC chip 110 into an analog signal including a data potential between potential VSIGL (see Figure 5) and potential VSIGH (see Figure 5). Potential VSIGH is a higher potential than potential VSIGL.

[0025] For example, the ON signal is a signal that includes a potential that conducts the selection circuit (switch), and the OFF signal is a signal that includes a potential that blocks the selection circuit (switch). In the present invention, the ON signal may be a high-level potential (High, HI) and the OFF signal may be a low-level potential (Low, LO), or the ON signal may be a low-level potential (Low, LO) and the OFF signal may be a high-level potential (High, HI). A high-level potential is higher than a low-level potential. In one example of a display device according to one embodiment of this specification, the ON signal is a high-level potential and the OFF signal is a low-level potential.

[0026] [1-3. Configuration of Control Circuit 120] Referring to Figure 1, the control circuit 120 is outlined. Two control circuits 120 are located adjacent to each other on both sides of the display area 22 along a second direction D2. Scan signal lines 330, 331, 332, 333, and 334 extend from the control circuits 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. For example, each scan signal line of the display device 10 shown in Figure 1 is connected to both of the two control circuits 120. Each scan signal line may be connected to one of the two control circuits 120. For example, the nth scan signal line may be electrically connected to the control circuit 120 on the right side of the display area 22 along the second direction D2, and the (n+1)th scan signal line may be electrically connected to the control circuit 120 on the left side of the display area 22 along the second direction D2, where n is a positive integer.

[0027] The control circuit 120 includes a shift register circuit 130 and a scan driver circuit 160. For example, the control circuit 120 is a gate driver and receives control signals including a clock signal, a start pulse, and multiple enable signals, as well as potentials such as the drive potential VDDEL (see Figure 2) and the reference potential VSSEL (see Figure 2). The control circuit 120 can sequentially select scan lines based on the input of control signals and power supply.

[0028] The shift register circuit 130 is electrically connected to the scan driver circuit 160. The shift register circuit 130 includes multiple shift registers (not shown). The shift register circuit 130 is supplied with the above-mentioned multiple control signals via multiple connection wires 342, the drive potential VDDEL is supplied via the drive potential line PVDD (see Figure 2), and the reference potential VSSEL is supplied via the reference potential line PVSS (see Figure 2). Based on the above-mentioned multiple control signals, the shift register circuit 130 generates multiple output signals (not shown) that are shifted at different timings and outputs them sequentially to the scan driver circuit 160.

[0029] The scan driver circuit 160 includes multiple scan drivers (not shown). For example, multiple output signals are supplied to the multiple scan drivers from the shift register circuit 130, and the above-mentioned multiple enable signals are supplied from the IC chip 110 via multiple connection lines 342, the drive potential VDDEL is supplied via the drive potential line PVDD, and the reference potential VSSEL is supplied via the reference potential line PVSS. Based on the multiple output signals and multiple enable signals (not shown), the multiple scan drivers sequentially supply scan signals with different timings (for example, a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), and a fifth scan signal SC5(n)) to each scan signal line, and also drive the pixels 180 (pixel circuit 181) electrically connected to each scan signal line. For example, the third scan signal SC3(n) and the scan signal line 332 to which the third scan signal SC3(n) is supplied are so-called scan signal and scan signal line.

[0030] [1-4. 180-pixel configuration] The overview of the pixel 180 and pixel circuit 181 will be explained with reference to Figures 1 to 3. Figure 2 is a schematic diagram showing the input signals to the pixel circuit 181 included in the pixel 180. Figure 3 is a circuit diagram showing the configuration of the pixel circuit 181. Figures 2 and 3 show the configuration of the pixel circuit 181 of the pixel 180 shown in Figure 1 as an example. The configuration of the pixel 180 and pixel circuit 181 is not limited to the configurations shown in Figures 1 to 3. Configurations identical or similar to those in Figure 1 will be explained as necessary, and explanations of configurations identical or similar to those in Figure 1 may be omitted.

[0031] Pixel circuit 181 is a circuit for driving pixel 180. The pixel circuits of sub-pixels R, G, and B included in pixel 180 are the same as those of pixel circuit 181, but the colors emitted by the light-emitting element OLED are different.

[0032] As shown in Figure 2, the pixel circuit 181 is supplied with image data signal SL(m), first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), fourth scan signal SC4(n), fifth scan signal SC5(n), reset potential VRES, reference potential VREF, and initialization potential VINI. In addition, the pixel circuit 181 is supplied with drive potential VDDEL and reference potential VSSEL as power supplies to drive the pixel 180. For example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be constant potentials, or they may be variable potentials that fluctuate according to the timing of each signal.

[0033] The first scan signal SC1(n) is supplied to scan signal line 330, the second scan signal SC2(n) is supplied to scan signal line 331, the third scan signal SC3(n) is supplied to scan signal line 332, the fourth scan signal SC4(n) is supplied to scan signal line 333, and the fifth scan signal SC5(n) is supplied to scan signal line 334.

[0034] Furthermore, the reset potential VRES is supplied to the reset potential line SVRE, the reference potential VREF is supplied to the reference potential line SVR, the initialization potential VINI is supplied to the initialization potential line SVI, the drive potential VDDEL is supplied to the drive potential line PVDD, and the reference potential VSSEL is supplied to the reference potential line PVSS. For example, each of the reset potential line SVRE, the reference potential line SVR, the initialization potential line SVI, the drive potential line PVDD, and the reference potential line PVSS is electrically connected to a different connection wiring 342. Alternatively, each of the reset potential line SVRE, the reference potential line SVR, the initialization potential line SVI, the drive potential line PVDD, and the reference potential line PVSS may be connected to a different connection wiring 342.

[0035] For example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be supplied to the IC chip 110 from an external device via the FPC 200, terminal section 150, and connection wiring 341. Alternatively, for example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be generated by the IC chip 110 and supplied from the IC chip 110 to a plurality of pixels 180 (pixel circuits 181) via connection wiring 342, reset potential line SVRE, reference potential line SVR, initialization potential line SVI, drive potential line PVDD, and reference potential line PVSS. Although not shown in the diagram, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be connected from an external device via the FPC 200, terminal section 150, and connection wiring 341, without going through the IC chip 110 and connection wiring 342, to the reset potential line SVRE, reference potential line SVR, initialization potential line SVI, drive potential line PVDD, and reference potential line PVSS, and may be supplied to multiple pixels 180 (pixel circuit 181). For example, the reset potential VRES, reference potential VREF, initialization potential VINI, and reference potential VSSEL are lower than the drive potential VDDEL.

[0036] As shown in Figure 3, the pixel 180 (pixel circuit 181) includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitive element CV, a capacitive element CD, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source electrode and drain electrode) consisting of a first electrode and a second electrode. Each of the capacitive element CV, the capacitive element CD, and the light-emitting element OLED has a pair of electrodes consisting of a first electrode and a second electrode. Note that the capacitive element CV may be referred to as the first capacitive element, and the capacitive element CD may be referred to as the second capacitive element.

[0037] For example, the first transistor T1 is a selection transistor. The first transistor T1 has the function of supplying image data signal SL(m) to the second node N2.

[0038] For example, the second transistor T2 is a driving transistor. As will be described in detail later, a threshold voltage (a threshold potential difference Vgs) VTH is acquired between the first node N1 and the first electrode (source) 624 based on the reset potential VRES, and the acquired threshold voltage VTH is applied to the capacitive element CV, thereby performing the acquisition and retention (storage) of the threshold voltage VTH. Furthermore, the second transistor T2 controls the amount of current flowing from the driving potential line PVDD to the light-emitting element OLED based on the gate potential (potential between gate electrode 622 and the first electrode 624) corrected for variations in the threshold voltage VTH and the input image data signal SL(m). In other words, the second transistor T2 has the function of supplying current to the light-emitting element OLED from the driving potential VDDEL according to the display gradation (brightness), thereby causing the light-emitting element OLED to emit light.

[0039] For example, the third transistor T3 has the function of connecting the second node N2 and the reset potential line SVRE, supplying the reset potential VRES to the second node N2, and fixing the potential supplied to the second node N2 to the reset potential VRES. As will be described in detail later, when the potential supplied to the second node N2 is fixed to the reset potential VRES, current flows from the drive potential line PVDD to the fourth node N4 and the third node N3 via the fifth transistor T5, and the capacitive element CV (the first electrode 42 of the capacitive element CV) begins to charge. When the potential difference Vgs (the potential difference Vgs between the potential supplied to the gate electrode 622 (second node N2) and the potential supplied to the first electrode 624 (third node N3)) reaches the threshold voltage VTH, the charging stops.

[0040] The fourth transistor T4 has the function of supplying the initialization potential VINI to the third node N3 by conducting the initialization potential line SVI to the third node N3, thereby initializing the third node N3.

[0041] The fifth transistor T5 has the function of conducting the drive potential line PVDD and the fourth node N4.

[0042] The sixth transistor T6 conducts the first node N1 and the reference potential line SVR, supplying the reference potential VREF to the first node N1, and has the function of fixing the potential supplied to the first node N1 to the reference potential VREF during the initialization of the third node N3, when the threshold voltage VTH is acquired and held, and when the image data signal SL(m) is written.

[0043] The capacitive element CV has the function of holding (storing) a charge corresponding to the threshold voltage VTH of the second transistor T2. That is, the capacitive element CV has the function of holding (storing) the potential difference between the potential supplied to the first node N1 and the potential supplied to the third node N3, which includes information about the threshold voltage VTH of the second transistor T2. The driving method of the display device 10 includes obtaining the threshold voltage VTH by applying a driving potential VDDEL from the second electrode 626 (drain electrode) side of the second transistor T2 via the driving potential line PVDD.

[0044] The capacitive element CD has the function of holding (storing) the charge corresponding to the data potential (potential above VSIGL (see Figure 5) and below VSIGH (see Figure 5)) contained in the image data signal SL(m) supplied to the second node N2. In other words, the capacitive element CD has the function of holding (storing) the potential difference between the potential supplied to the second node N2 and the potential supplied to the first node N1, which includes the data potential information of the image data signal SL(m).

[0045] The light-emitting OLED has diode characteristics and emits light based on the current flowing through it. The current flowing through the light-emitting OLED is the drain current (current Ion) of the second transistor T2.

[0046] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 332. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, the second electrode 636 of the third transistor T3, and the second electrode 54 of the capacitive element CD. The switching of the first transistor T1 is controlled using the third scan signal SC3(n). In other words, the conduction state (on state) and non-conduction state (off state) of the first transistor T1 are controlled by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the first transistor T1 is in a non-conduction state. When the signal supplied to the third scan signal SC3(n) is HI, the first transistor T1 becomes conductive.

[0047] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The first electrode 624 is electrically connected to the third node N3, the first electrode 42 of the capacitive element CV, and the second electrode 34 of the light-emitting element OLED. The second electrode 626 is electrically connected to the fourth node N4 and the first electrode 654 of the fifth transistor T5. The threshold voltage of the second transistor T2 is the threshold voltage VTH. The second transistor T2 controls the amount of current flowing to the light-emitting element OLED according to the potential difference Vgs and the potential difference Vds between the potential supplied to the second electrode 626 (fourth node N4) and the potential supplied to the first electrode 624 (third node N3). For example, if the potential difference Vgs is less than the threshold voltage VTH, the second transistor T2 is in a non-conducting state. In this case, no current flows to the light-emitting element OLED, and the pixel 180 displays black. For example, when the potential difference Vgs is greater than or equal to the threshold voltage VTH and the potential difference Vds is greater than 0V, the second transistor T2 becomes conductive, and the current flowing through the light-emitting element OLED is controlled according to the magnitude of the displayed potential difference Vgs based on the grayscale level, causing the light-emitting element OLED to emit light at a brightness based on the displayed grayscale level.

[0048] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 331. The first electrode 634 is electrically connected to the reset potential line SVRE. The switching of the third transistor T3 is controlled using the second scan signal SC2(n). In other words, the conduction state (on state) and non-conduction state (off state) of the third transistor T3 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the third transistor T3 is in a non-conducting state, and when the signal supplied to the second scan signal SC2(n) is HI, the third transistor T3 is in a conduction state.

[0049] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 333. The first electrode 644 is electrically connected to the initialization potential line SVI. The switching of the fourth transistor T4 is controlled using the fourth scan signal SC4(n). In other words, the conduction state (on state) and non-conduction state (off state) of the fourth transistor T4 are controlled by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the fourth transistor T4 is in a non-conducting state, and when the signal supplied to the fourth scan signal SC4(n) is HI, the fourth transistor T4 is in a conduction state.

[0050] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 334. The second electrode 656 is electrically connected to the drive potential line PVDD. The switching of the fifth transistor T5 is controlled using the fifth scan signal SC5(n). In other words, the conduction state (on state) and non-conduction state (off state) of the fifth transistor T5 are controlled by the fifth scan signal SC5(n). When the signal supplied to the fifth scan signal SC5(n) is LO, the fifth transistor T5 is in a non-conducting state, and when the signal supplied to the fifth scan signal SC5(n) is HI, the fifth transistor T5 is in a conduction state.

[0051] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 330. The first electrode 664 is electrically connected to the reference potential line SVR. The second electrode 666 is electrically connected to the first node N1, the second electrode 44 of the capacitance element CV, and the first electrode 52 of the capacitance element CD. The switching of the sixth transistor T6 is controlled using the first scan signal SC1(n). In other words, the conduction state (on state) and non-conduction state (off state) of the sixth transistor T6 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the sixth transistor T6 is in a non-conducting state, and when the signal supplied to the first scan signal SC1(n) is HI, the sixth transistor T6 is in a conduction state.

[0052] The capacitive element CV includes a first electrode 42 and a second electrode 44.

[0053] The capacitive element CD includes a first electrode 52 and a second electrode 54.

[0054] The first electrode 32 of the light-emitting OLED is the cathode, and the second electrode 34 of the light-emitting OLED is the anode. The first electrode 32 is electrically connected to the reference potential line PVSS.

[0055] For example, the conduction state of a transistor in the display device 10 is defined as the source electrode and drain electrode of the transistor conducting, indicating that the transistor is ON, while the non-conducting state of a transistor in the display device 10 is defined as the source electrode and drain electrode of the transistor not conducting, indicating that the transistor is OFF. In each transistor, the source electrode and drain electrode may be swapped depending on the potential supplied to each electrode or the potential. Furthermore, it is easily understood by those skilled in the art that even when a transistor is OFF, a small current may flow, such as leakage current.

[0056] Each transistor shown in Figure 3 is an n-channel field-effect transistor. Each transistor includes a channel region. For example, the channel region is the region through which the current flows between the first electrode (for example, sometimes referred to as the drain or drain electrode) and the second electrode (for example, sometimes referred to as the source or source electrode) of each transistor. As will be described in detail later, for example, the channel region includes a group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties. Also, for example, each transistor in the display device 10 is formed using a thin-film transistor (TFT). Depending on the application and specifications, the transistor configuration, retention capacitance connection, power supply potential, etc., of the display device 10 may be appropriately adapted.

[0057] [1-5. Structure of Pixel 180] The structure of the pixel 180 will be explained with reference to Figures 4 to 14. Figures 4 to 6 are layout diagrams of the pixel 180 as seen from the surface (first surface 101A) side of the display device 10. Figure 6 is a plan view showing the semiconductor layer 122 shown in Figure 4. Figure 7 is an end view showing the end face cut along A1-A2 in the layout shown in Figure 4 or Figure 5. Figure 8 is an end view showing the end face cut along B1-B2 in the layout shown in Figure 4 or Figure 5. Figure 9 is an end view showing the end face cut along C1-C2 in the layout shown in Figure 4 or Figure 5. The layout of the pixel 180 shown in Figures 4 to 6, and the end faces of the pixel 180 shown in Figures 7 to 9 are examples, and the layout and end faces of the pixel 180 are not limited to the examples shown in Figures 4 to 9. Configurations identical or similar to those in Figures 1 to 3 will be explained as necessary.

[0058] First, we will explain the configuration of a 180-pixel image in a planar view.

[0059] The layout diagram of pixel 180 shown in Figure 4 includes the semiconductor layer 122, conductive layer 127, conductive layer 132, first contact hole opening 135, conductive layer 133, second contact hole opening 138, and third contact hole opening 137, while omitting all other components except for the semiconductor layer 122, conductive layer 127, conductive layer 132, first contact hole opening 135, conductive layer 133, second contact hole opening 138, and third contact hole opening 137, for the sake of clarity. In addition, the layout diagram of pixel 180 shown in Figure 4 omits the configuration of the layers above the insulating layer 141 along the third direction D3. The area where pixel 180 is laid out below the insulating layer 141 is inside the area 182A indicated by the thick dashed line.

[0060] Furthermore, in the layout of pixel 180 shown in Figure 5, to improve the clarity of the drawing, the elements shown in Figure 4 (semiconductor layer 122, conductive layer 127, conductive layer 132, first contact hole opening 135, and part of conductive layer 133) are omitted. The remaining elements shown in Figure 4, part of conductive layer 140, and the fourth contact hole opening 129 are shown with dashed lines, while part of conductive layer 132, part of conductive layer 140, conductive layer 142, and anode contact hole opening 147 shown in Figure 4 are shown with solid lines. Other elements and their reference numerals are omitted. In addition, the area where pixel 180 is laid out above the insulating layer 141 is inside the area 182B shown by the thick dashed line.

[0061] As shown in Figure 6, pixel 180 includes a first region L1(m), a second region L2(m) adjacent to the first region L1(m), a third region L3(m) adjacent to the second region L2(m), and a fourth region L4(m) adjacent to the third region L3(m). Each of the first region L1(m), the second region L2(m), the third region L3(m), and the fourth region L4(m) is provided along the first direction. For example, pixel 180 is one of a plurality of pixels 180 arranged in a matrix in the first direction D1 and the second direction D2, and located in the m-th column. For example, one of a plurality of pixels 180 located in the m-th column may be referred to as the first pixel or the second pixel. The numerical value m is a positive integer.

[0062] The first region L1(m) includes semiconductor layer 122BB aligned to the second direction, but does not include semiconductor layer 122. The second region L2(m) includes semiconductor layer 122C, semiconductor layer 122BC, and semiconductor layer 122D aligned to the first direction. The third region L3(m) does not include semiconductor layer 122. The fourth region L4(m) includes semiconductor layers 122E and 122A aligned to the first direction. The fourth region L4(m-1) includes semiconductor layer 122BA aligned to the first direction.

[0063] For example, the fourth region L4(m-1) is the region contained within one of the multiple pixels 180 arranged in a matrix in the first direction D1 and the second direction D2, specifically those arranged in the (m-1)th column. For example, one of the multiple pixels 180 arranged in the (m-1)th column may be referred to as the second pixel or the first pixel. Also, the first region L1(m+1) shown in Figure 6 is the first region of one of the multiple pixels 180 arranged in the (m+1)th column, specifically those arranged in a matrix in the first direction D1 and the second direction D2. For example, one of the multiple pixels 180 arranged in the (m+1)th column may be referred to as the third pixel. The second pixel is adjacent to the first pixel along the second direction D2, and the first pixel is adjacent to the third pixel along the second direction D2. In other words, the first pixel is positioned adjacent to the second and third pixels.

[0064] Since the display device 10 includes a plurality of pixels 180 arranged in a matrix in the first direction D1 and the second direction D2, region 182A is arranged and tiled in a matrix in the first direction D1 and the second direction D2. Similarly to region 182A, region 182B is arranged and tiled in a matrix in the first direction D1 and the second direction D2.

[0065] Therefore, the region AL4M-1 of a certain pixel aligns with the fourth region L4(m-1) of an adjacent pixel along the second direction D2, and the region AL4M of a certain pixel aligns with the fourth region L4(m) of an adjacent pixel. In other words, the multiple pixels 180 arranged in a matrix in the first direction D1 and the second direction D2 align to fill in the missing regions of adjacent pixels along the second direction D2. Although not shown in the diagram, adjacent pixels along the first direction D1 also align to fill in the missing regions of adjacent pixels along the second direction D2, similar to adjacent pixels along the second direction D2. For example, the length (pitch) of pixel 180 in the first direction D1 is length PX, and the length (pitch) of pixel 180 in the second direction D2 is length PY.

[0066] The display device 10 limits the region where the semiconductor layer is arranged along the first direction D1 to the second region L2(m) and the fourth region L4(m), and by shifting the position of region 182A along the third direction D3 and the position of region 182B along the third direction D3, multiple pixels 180 can be arranged most densely along the first direction D1 and the second direction D2. As a result, the display device 10 can achieve high resolution.

[0067] Next, we will describe the configuration of pixel 180 in an end-view perspective.

[0068] The end face of the pixel 180 shown in Figure 7 is an example of the end face of the pixel 180, and is the end face along the anode 143, functional layer 148, cathode 149, sealing film 165, cover film 158, anode contact hole opening 147A, first wiring 132B, first electrode 140C, first wiring 132G, second wiring 133B, third contact hole opening 137C, end of second electrode 142E, second electrode 142A, end of first electrode 140AE, first electrode 140A, gate wiring 127A, third contact hole opening 137B, second contact hole opening 138C, and first wiring 132C.

[0069] The end face of pixel 180 shown in Figure 8 is an example of an end face of pixel 180, and is the end face along the first wiring 132B, gate wiring 127B, first contact hole opening 135B, semiconductor layer 122A, and gate wiring 127A.

[0070] The end face of the pixel 180 shown in Figure 9 is an example of an end face of the pixel 180, and is the end face along the second electrode 142A, the first electrode 140B, the gate wiring 127G, the end of the first electrode 140BE, the end of the second electrode 142E, the gate wiring 127G, the second wiring 133F, the second contact hole opening 138G, the first wiring 132I, and the first wiring 132J. Note that in the end faces of the pixel 180 shown in Figures 8 and 9, the structure of the layers above the insulating layer 141 is omitted along the third direction D3.

[0071] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via a base layer 121. The semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, and 122D (see Figures 6, 12, and 13). Semiconductor layer 122B includes a channel region 123 (see Figures 6, 12, and 13) and an impurity region 124A (see Figures 6, 12, and 13). For example, the impurity region may be denoted as the source region or drain region. Also, for example, a second transistor T2 includes semiconductor layer 122B, and a first electrode 624 (see Figure 12) and a second electrode 626 (see Figure 12) include the impurity region 124A. In other words, semiconductor layer 122B includes the channel region of the second transistor T2. Similarly to the second transistor T2, the first transistor T1 includes semiconductor layer 122A, and the first electrode 614 (see Figure 12) and the second electrode 616 (see Figure 12) include impurity regions. In other words, semiconductor layer 122A includes the channel region of the first transistor T1.

[0072] On the semiconductor layer 122, a gate insulating layer 125, a conductive layer 127, an insulating layer 128, and a conductive layer 132 are provided in this order. The conductive layer 127 includes gate wiring 127A (scan signal line 332, gate electrode 612, see Figures 12 and 13), gate wiring 127B (gate electrode 622, see Figures 12 and 13), and gate wiring 127G (signal line to which scan signal SC4(n-1) is supplied, see Figures 12 and 13). The conductive layer 132 includes first wiring 132B, first wiring 132G, first wiring 132C, first wiring 132B, first wiring 132I, and first wiring 132J. The region where the conductive layer 127 and the semiconductor layer 122 overlap is the channel region. In other words, the region where the gate electrode of each transistor and the semiconductor layer overlap is the channel region.

[0073] Each transistor in the pixel 180 is formed using a semiconductor layer 122 (e.g., semiconductor layer 122B, channel region 123, and impurity region 124A, see Figure 12), a gate insulating layer 125, and a conductive layer 127 (e.g., gate wiring 127B, see Figures 12 and 13).

[0074] A first contact hole opening 135B that reaches the semiconductor layer 122 and the conductive layer 127 penetrates the gate insulating layer 125 and the insulating layer 128 and is provided in the gate insulating layer 125 and the insulating layer 128. For example, the first contact hole opening 135B exposes the semiconductor layer 122A (for example, the second electrode 616, see Figure 12) and the gate wiring 127B, and the first wiring 132B is electrically connected to the semiconductor layer 122A and the gate wiring 127B by the first contact hole opening 135B. That is, the first contact hole opening may penetrate and open the gate insulating layer 125 and the insulating layer 128 to expose the semiconductor layer 122, or the first contact hole opening may penetrate and open the insulating layer 128 to expose the conductive layer 127.

[0075] The insulating layer 139 is provided on top of the insulating layer 128, which does not have a conductive layer 132, and is provided so as to cover the conductive layer 132.

[0076] A second contact hole opening is provided in the insulating layer 139. For example, the second contact hole opening includes second contact hole openings 138C and 138G. A conductive layer 133 is provided on the insulating layer 139 and in the second contact hole opening 138. The conductive layer 133 includes second wiring 133B and second wiring 133F. The second contact hole opening 138C penetrates the insulating layer 139 and exposes the first wiring 132C. The second wiring 133B is electrically connected to the first wiring 132C via the second contact hole opening 138C. Similar to the second contact hole opening 138C, the second contact hole opening 138G penetrates the insulating layer 139 and exposes the first wiring 132I. The second wiring 133F is electrically connected to the first wiring 132I via the second contact hole opening 138G. Although not shown in the diagram, for example, the second contact hole opening 138 exposes some of the multiple terminals (not shown) included in the terminal portion 150.

[0077] The insulating layer 136 is provided on top of the insulating layer 139, which does not have a conductive layer 133, and is provided so as to cover the conductive layer 133.

[0078] A third contact hole opening is provided in the insulating layer 136. For example, the third contact hole opening 137 includes third contact hole openings 137B and 137C. A conductive layer 140 is provided on the insulating layer 136 and in the third contact hole opening 137. The conductive layer 140 includes a first electrode 140C (second electrode 34, see Figures 5 and 14), a first electrode 140A (first electrode 42, see Figures 5 and 14), and a first electrode 140B (second electrode 54, see Figures 5 and 14). The third contact hole opening 137C penetrates the insulating layer 136 and exposes the second wiring 133B. The first electrode 140C is electrically connected to the second wiring 133B via the third contact hole opening 137C. For example, the first electrode 140C also serves as a pixel electrode. The third contact hole opening 137B penetrates the insulating layer 136 and exposes the second wiring 133B. The first electrode 140A is electrically connected to the second wiring 133B via the third contact hole opening 137B. Although not shown in the diagram, for example, the third contact hole opening 137 exposes some of the multiple terminals (not shown) included in the terminal section 150. The exposed terminals are electrically connected to the FPC 200 using a conductive film such as an anisotropic conductive film (not shown). Furthermore, pixel electrodes are provided independently for each pixel.

[0079] The insulating layer 131 is provided on an insulating layer 136 that does not have a conductive layer 140, and is provided so as to cover the conductive layer 140. A fourth contact hole opening 129 is provided on the insulating layers 131 and 136. The conductive layer 142 is provided on the insulating layer 131 and in the fourth contact hole opening 129. The conductive layer 142 includes a second electrode 142A (first electrode 52, second electrode 44). The fourth contact hole opening 129 penetrates the insulating layers 131 and 136 and exposes the second wiring 133F. The second electrode 142A is electrically connected to the second wiring 133F via the fourth contact hole opening 129.

[0080] For example, the capacitive element CV is formed using an insulating layer 131 as the dielectric, with a first electrode 140A (first electrode 42, see Figures 5 and 14) and a second electrode 142A (second electrode 44, see Figures 5 and 14), and the capacitive element CD is formed using an insulating layer 131 as the dielectric, with a first electrode 140B (second electrode 54, see Figures 5 and 14) and a second electrode 142A (first electrode 52, see Figures 5 and 14). The capacitive element CV is arranged adjacent to the capacitive element CD along the first direction D1.

[0081] The insulating layer 141 is provided on top of the insulating layer 131, which does not have a conductive layer 142, and is provided so as to cover the conductive layer 142.

[0082] For example, the base layer 121, semiconductor layer 122, gate insulating layer 125, conductive layer 127, insulating layer 128, conductive layer 132, insulating layer 139, conductive layer 133, insulating layer 136, conductive layer 140, insulating layer 131, conductive layer 142, and insulating layer 141 are collectively referred to as the array section 170.

[0083] Next, a plurality of layers laminated on the insulating layer 141 will be described. A contact hole opening 147 for the anode is provided in the insulating layer 141. The contact hole opening 147 for the anode includes a contact hole opening 147A for the anode. The contact hole opening 147A for the anode penetrates the insulating layers 141 and 131 and is provided in the insulating layers 141 and 131, exposing the conductive layer 140 (for example, the first electrode 140C).

[0084] The anode 143 is provided so as to cover the exposed first electrode 140C, the contact hole opening 147A for the anode, and the insulating layers 141 and 131. The functional layer 148 is provided on top of the anode 143. The cathode 149 (first electrode 32 of the light-emitting OLED, see Figure 3) is provided on top of the functional layer 148 so as to cover the functional layer 148. The cathode 149 is electrically connected to the reference potential line PVSS. Here, the light-emitting OLED is composed of the anode 143, the functional layer 148, and the cathode 149.

[0085] The configuration of the functional layer 148 can be selected as appropriate. For example, the functional layer 148 can be composed of a combination of a carrier injection layer, a carrier transport layer, an emissive layer, a carrier blocking layer, an exciton blocking layer, and so on. For example, the functional layer 148 shown in Figure 7 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is an emissive layer, and the third layer 146 is a carrier (electron) injection and transport layer. For example, the functional layer 148 can be provided independently for each pixel, similar to the pixel electrodes.

[0086] A sealing film 165 is provided on the cathode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed to cover at least the display area 22. A cover film 158 is placed on the second inorganic insulating layer 156.

[0087] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146 included in the functional layer 148, as well as the anode 143, are not placed on top of the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 are placed on top of the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED and each transistor from outside the display device 10.

[0088] Furthermore, as shown in Figure 5, for example, the second electrode 142A also serves as the second electrode 44 of the capacitive element CV and the first electrode 52 of the capacitive element CD. The area of ​​the second electrode 142A is larger than the sum of the areas of the first electrode 140A and the first electrode 140B, and the second electrode 142A overlaps with the first electrode 140A and the first electrode 140B. As shown in Figure 7, the end 142E of the second electrode 142A covers the end 140E of the first electrode 140A. Also, as shown in Figure 9, the end 142E of the second electrode 142A covers the end 140BE of the first electrode 140B.

[0089] As a result, capacitance is formed by the end 142E of the second electrode 142A, the end 140E of the first electrode 140A, and the insulating layer 131 sandwiched between the end 142E of the second electrode 142A and the end 140E of the first electrode 140A. Therefore, a pixel 180 that includes a configuration that covers the ends of the electrodes that form capacitance can increase the capacitance value of the capacitive element compared to a pixel that includes a configuration that does not cover the ends of the electrodes that form capacitance. As a result, a decrease in the potential held by the capacitive element, or a loss of the potential held by the capacitive element, can be suppressed.

[0090] [1-6. Method for manufacturing the display device 10] The manufacturing method of the display device 10 (pixel 180) will be described with reference to Figures 4 to 6 and Figures 10 to 14. Figures 10 and 11 are sequence diagrams showing the manufacturing method of the display device 10. Figures 12 to 14 are layout diagrams of the pixels 180 as viewed from the surface (first surface 101A) side of the display device 10. Configurations identical or similar to those in Figures 1 to 13 will be described as necessary, and descriptions of identical or similar configurations may be omitted. The manufacturing method of the display device 10 includes, as an example, an oxide semiconductor layer formed using an oxide semiconductor.

[0091] When the manufacturing of the display device 10 (180 pixels) begins, the underlayer 121 (see Figures 7-9) is formed on the first surface 101A (see Figures 7-9) of the substrate 101 (see Figures 7-9) (step 10 (S10) in Figure 10). For example, the substrate 101 is a glass substrate.

[0092] As shown in Figure 12, semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, 122D, and 122E. Semiconductor layer 122A is the semiconductor layer of the first transistor T1. Semiconductor layer 122B includes semiconductor layer 122BA provided along the first direction D1, semiconductor layer 122BB provided along the second direction D2 and connected to semiconductor layer BA, and semiconductor layer 122BC provided along the first direction D1 and connected to semiconductor layer BB, and serves as both the semiconductor layer of the second transistor T2 and the semiconductor layer of the fifth transistor T5. Semiconductor layer 122C is the semiconductor layer of the third transistor T3. Semiconductor layer 122D is the semiconductor layer of the fourth transistor T4. Semiconductor layer 122E is the semiconductor layer of the sixth transistor T6. In other words, semiconductor layer 122A includes the channel region of the first transistor T1, semiconductor layer 122B includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5, semiconductor layer 122C includes the channel region of the third transistor T3, semiconductor layer 122D includes the channel region of the fourth transistor T4, and semiconductor layer 122E includes the channel region of the sixth transistor T6. Furthermore, the first and second electrodes of each transistor include an impurity region. That is, the first electrodes 614 and 616 of the first transistor T1, the first electrodes 624 and 626 of the second transistor T2, the first electrodes 634 and 636 of the third transistor T3, the first electrodes 644 and 646 of the fourth transistor T4, and the first electrodes 654 and 656 of the fifth transistor T5 include an impurity region. In other words, semiconductor layer 122A includes the channel region of the first transistor T1, semiconductor layer 122B includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5, semiconductor layer 122C includes the channel region of the third transistor T3, semiconductor layer 122D includes the channel region of the fourth transistor T4, and semiconductor layer 122E includes the channel region of the sixth transistor T6.

[0093] A gate insulating layer 125 (see Figures 7 to 9) is formed on top of the semiconductor layer 122 and on top of the underlayer 121 on which the semiconductor layer 122 is not formed (step 12 (S12) in Figure 10).

[0094] A conductive layer 127 (see Figures 7 to 13) is formed on top of the gate insulating layer 125 (see Figures 7 to 9) (step 13 (S13) in Figure 10). As shown in Figures 4, 12 and 13, the conductive layer 127 includes gate wiring 127A (scan signal line 332), gate wiring 127B (gate electrode 622), gate wiring 127C (scan signal line 331), gate wiring 127D (scan signal line 333), gate wiring 127E (scan signal line 334), gate wiring 127F (scan signal line 330), and gate wiring 127G (signal line to which scan signal SC4(n-1) is supplied). Gate wiring 127A includes gate electrode 612, gate wiring 127B includes gate electrode 632, gate wiring 127C includes gate electrode 632, gate wiring 127D includes gate electrode 642, gate wiring 127E includes gate electrode 652, and gate wiring 127F includes gate electrode 662.

[0095] The region where the gate electrode 622 and semiconductor layer 122B of the second transistor T2 overlap is the channel region 123, and the channel region 123 corresponds to the channel length of the second transistor T2. Similarly to the second transistor T2, the region where the gate electrode 612 and semiconductor layer 122A of the first transistor T1 overlap is the channel region of the first transistor T1 and corresponds to its channel length. For transistors other than the second transistor T2 and the first transistor T1, similarly to the second transistor T2 and the first transistor T1, the region where the gate electrode and semiconductor layer overlap is the channel region of the transistor and corresponds to its channel length.

[0096] As shown in Figure 12, in plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. That is, the channel length of the second transistor T2 is longer than the channel length of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. Since the second transistor T2 operates in the saturation region, it is necessary to suppress the kink effect. Furthermore, it is preferable that the resistance of the second transistor T2 to hot carriers is higher than that of the other transistors in the pixel 180. To suppress the kink effect and ensure reliability (hot carrier resistance), the channel length of the second transistor T2 is longer than that of the other transistors in the pixel 180.

[0097] An insulating layer 128 (see Figures 7 to 9) is formed on top of the conductive layer 127 and on top of the gate insulating layer 125 on which the conductive layer 127 is not formed (step 14 (S14) in Figure 10).

[0098] As shown in Figures 4, 12, and 13, the first contact hole openings 135A to 135J are opened (step 15 (S15) in Figure 10). Each opening may open the gate insulating layer 125 and the insulating layer 128 to expose the semiconductor layer, and each opening may open the insulating layer 128 to expose the gate wiring. For example, the first contact hole openings 135A and 135B expose semiconductor layer 122A, the first contact hole opening 135C exposes semiconductor layer 122B, the first contact hole openings 135D and 135E expose semiconductor layer 122C, the first contact hole openings 135F and 135G expose semiconductor layer 122D, the first contact hole opening 135H exposes semiconductor layer 122B, and the first contact hole openings 135I and 135J expose semiconductor layer 122E. In addition, the first contact hole opening 135B exposes gate wiring 127B. Other openings also expose the corresponding semiconductor layer or gate wiring.

[0099] A conductive layer 132 (see Figures 7 to 9) is formed on the insulating layer 128 or in the first contact hole opening 135 (step 16 (S16) in Figure 10). As shown in Figures 4 and 13, the conductive layer 132 includes the first wiring 132A (image data signal line 321), the first wiring 132B, the first wiring 132C, the first wiring 132D, the first wiring 132E, the first wiring 132F, the first wiring 132G (drive potential line PVDD), the first wiring 132H, the first wiring 132I, and the first wiring 132J (drive potential line PVDD).

[0100] As shown in Figure 13, in a plan view, for example, the first wiring 132A is electrically connected to the first transistor T1 via the first contact hole opening 135A. The first wiring 132B is electrically connected to the first transistor T1 and the gate wiring 127B via the first contact hole opening 135B. The first wiring 132C is electrically connected to the second transistor T2 via the first contact hole opening 135C and also to the fourth transistor T4 via the first contact hole opening 135F. The first wiring 132D is electrically connected to the third transistor T3 via the first contact hole opening 135D. The first wiring 132E is electrically connected to the third transistor T3 via the first contact hole opening 135E. The first wiring 132F is electrically connected to the fourth transistor T4 via the first contact hole opening 135G. The first wiring 132G is electrically connected to the fifth transistor T5 via the first contact hole opening 135H. The first wiring 132H is electrically connected to the sixth transistor T6 via the first contact hole opening 135I. The first wiring 132I is electrically connected to the sixth transistor T6 via the first contact hole opening 135J. The first wiring 132J is electrically connected to the first transistor T1 (not shown) located in the first region of one of the multiple pixels 180 arranged in the m+1th column. The other first wirings are also electrically connected to gate wiring or transistors (semiconductor layer 122) via their respective openings.

[0101] An insulating layer 139 (see Figures 7 to 9) is formed on top of the conductive layer 132 and on top of the insulating layer 128 on which the conductive layer 132 is not formed (step 17 (S17) in Figure 10).

[0102] As shown in Figures 4 and 13, the second contact hole opening 138 is opened (step 18 (S18) in Figure 10). The second contact hole opening 138 includes the second contact hole openings 138A to 138H.

[0103] As shown in Figure 13, in a plan view, for example, the second contact hole opening 138A exposes the first wiring 132B. The second contact hole opening 138B exposes the first wiring 132E. The second contact hole opening 138C exposes the first wiring 132C. The second contact hole opening 138D exposes the first wiring 132D. The second contact hole opening 138E exposes the first wiring 132F. The second contact hole opening 138E exposes the first wiring 132F. The second contact hole opening 138F exposes the first wiring 132I. The second contact hole opening 138G exposes the first wiring 132H. Each opening opens the insulating layer 136 and exposes the first wiring corresponding to each opening.

[0104] A conductive layer 133 (see Figures 7-9) is formed on the insulating layer 139 (see Figures 7-9) and in the second contact hole opening 138 (step 19 (S19) in Figure 10). As shown in Figures 4, 5, 14 and 15, the conductive layer 133 includes a second wiring 133A, a second wiring 133B, a second wiring 133C (reset potential line SVRE), a second wiring 133D (initialization potential line SVI), a second wiring 133E (reference potential line SVR), and a second wiring 133F.

[0105] As shown in Figures 4, 5, 14, and 15, in a plan view, for example, the second wiring 133A is electrically connected to the first wiring 132B via the second contact hole opening 138A. The second wiring 133B is electrically connected to the second transistor T2 and the fourth transistor T4 via the second contact hole opening 138C. The second wiring 133C is electrically connected to the first wiring 132D via the second contact hole opening 138D. The second wiring 133D is electrically connected to the fourth transistor T4 via the second contact hole opening 138E. The second wiring 133E is electrically connected to the first wiring 132H via the second contact hole opening 138H. The second wiring 133F is electrically connected to the first wiring 132I via the second contact hole opening 138F. The other second wires are also electrically connected to the first wires through their respective corresponding openings.

[0106] An insulating layer 136 (see Figures 7 to 9) is formed on top of the conductive layer 133 and on top of the insulating layer 139 on which the conductive layer 133 is not formed (step 20 (S20) in Figure 10).

[0107] As shown in Figures 4, 5 and 14, the third contact hole opening 137 is opened (step 21 (S21) in Figure 10). The third contact hole opening 137 includes the third contact hole openings 137A to 137C.

[0108] As shown in Figures 4, 5, and 14, in a plan view, for example, the third contact hole opening 137A exposes the second wiring 133A. The third contact hole openings 137B and 137C expose the second wiring 133B. Each opening opens the insulating layer 136 and exposes the first wiring corresponding to each opening.

[0109] A conductive layer 140 (see Figures 7 and 9) is formed on the insulating layer 136 (see Figures 7 to 13) and in the second contact hole opening 138 (step 22 (S22) in Figure 11). As shown in Figures 4, 5 and 14, the conductive layer 140 includes a first electrode 140A (first electrode 42), a first electrode 140B (second electrode 54), and a first electrode 140C (second electrode 34).

[0110] As shown in Figure 5 or Figure 14, in a plan view, for example, the first electrode 140A is electrically connected to the second wiring 133B via the third contact hole opening 137B. The first electrode 140B is electrically connected to the second wiring 133A via the third contact hole opening 137A. The first electrode 140C is electrically connected to the second wiring 133B via the third contact hole opening 137C. The other first electrodes are also electrically connected to the second wiring via their respective corresponding openings. The first electrode 140A is positioned adjacent to the second electrode 140B along the first direction D1.

[0111] An insulating layer 131 (see Figures 7 and 9) is formed on top of the conductive layer 140 and on top of the insulating layer 136 where the conductive layer 140 is not provided (step 23 (S23) in Figure 10).

[0112] As shown in Figure 5 or Figure 14, the fourth contact hole opening 129 is opened (step 24 (S24) in Figure 10). The fourth contact hole opening 129 opens the insulating layers 131 and 136 and exposes the conductive layer 133.

[0113] For example, the fourth contact hole opening 129 exposes the second wiring 133F. The other third contact hole openings also expose the corresponding insulating layer, wiring, or electrode.

[0114] A conductive layer 142 (see Figure 7 or Figure 9) is formed on the insulating layer 131 (see Figures 7 to 9) and in the fourth contact hole opening 129 (step 25 (S25) in Figure 10). For example, as shown in Figure 5, the conductive layer 140 includes a second electrode 142A (second electrode 44, first electrode 52). The second electrode 142A is electrically connected to the second wiring 133F via the fourth contact hole opening 129. Other conductive layers 140 are electrically connected to the corresponding second wiring, as well as to the corresponding gate wiring or transistor, similar to the second electrode 142A.

[0115] An insulating layer 141 (organic insulating layer) (see Figures 7 to 9) is formed on top of the conductive layer 142 and on top of the insulating layer 131 on which the conductive layer 142 is not formed (step 26 (S26) in Figure 10).

[0116] Furthermore, the insulating layer 141 (organic insulating layer) and the insulating layer 131 (see Figure 8) are opened (step 27 (S27) in Figure 10). In the opening of S27, the anode contact hole opening portion 147A is opened. The anode contact hole opening portion 147A removes the insulating layers 141 and 131 on the first electrode 140C, exposing the first electrode 140C. The anode contact hole opening portion 147A may sometimes be referred to as the organic insulating layer opening portion.

[0117] An anode 143 (see Figure 7) is provided on the exposed first electrode 140C, on the anode contact hole opening 147A, and on the insulating layers 141 and 131 (step 28 (S28) in Figure 10). A functional layer 148 (see Figure 7) is provided on the anode 143. A cathode 149 (see Figure 7) is provided on the functional layer 148. For example, an anode 143 may be provided for each pixel, a functional layer 148 may be provided for each pixel, and the cathode 149 may be provided so as to overlap the display area 22.

[0118] After S28, the sealing film 165 is placed on the cathode 149, and the cover film 158 is placed on the sealing film 165 (see Figure 7). That is, the sealing film 165 and the cover film 158 are placed on the cathode 149 in this order (see Figure 7).

[0119] With the above steps completed, the manufacturing of the display device 10 (180 pixels) is finished.

[0120] The manufacturing method for the display device 10 (pixel 180) includes forming a semiconductor layer 122 in a second region L2(m), a fourth region L4(m), and a fourth region L4(m-1) along a first direction D1 (see Figures 4 and 6), forming a conductive layer 132 along a first direction D1 (see Figures 4 and 6), forming a conductive layer 127 along a second direction D2 (see Figures 4 and 6), and forming a conductive layer 133 along a second direction D2. The manufacturing method for the display device 10 (pixel 180) also includes forming a conductive layer 140 and a conductive layer 142. The wiring routed within the display device 10 is mainly formed from conductive layers 127, 132, and 133, while the capacitive elements CV and CD, and the anode 143 are formed using conductive layer 140 or 142. In other words, the manufacturing method of the display device 10 (pixel 180) allows for the formation of routing wiring and capacitive elements using different wiring or electrodes. Therefore, the manufacturing method of the display device 10 (pixel 180) allows for the placement of capacitive elements CV and CD in one pixel and capacitive elements CV and CD in adjacent pixels in extremely close proximity. Furthermore, since the conductive layers 140 and 142 are generally used to form the capacitive elements CV and CD, the manufacturing method of the display device 10 (pixel 180) can increase the capacitance value of the capacitive elements.

[0121] As a result, the manufacturing method of the display device 10 (pixels 180) allows for higher resolution than when the routing wiring and capacitive elements are not formed using different wiring or electrodes, and also suppresses a decrease in the potential held by the capacitive elements or a loss of the potential held by the capacitive elements.

[0122] [1-7. Materials of each component of the display device 10] As the substrate 101, a rigid substrate that is translucent and inflexible can be used, such as a glass substrate, a quartz substrate, or a sapphire substrate. If the substrate 101 needs to be flexible, a flexible substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used. Impurities may be introduced into the resin to improve the heat resistance of the substrate SUB.

[0123] For example, the semiconductor layer 122 includes a channel region and contains Group 14 elements such as silicon (Si) and germanium (Ge), or an oxide exhibiting semiconductor properties. As the oxide exhibiting semiconductor properties, a metal oxide having semiconductor properties can be used. For example, as described in "1-6. Method for Manufacturing the Display Device 10", the semiconductor layer 122 includes an oxide semiconductor as the metal oxide exhibiting semiconductor properties. For example, the oxide semiconductor contains two or more metals, including indium (In). In addition to indium, the metal oxide having semiconductor properties may include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanides. Furthermore, the metal oxide having semiconductor properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline materials.

[0124] Furthermore, for example, the semiconductor layer 122 containing group 14 elements may contain crystalline silicon. The crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. Also, the crystalline silicon may be impregnated with impurities. For example, if the transistor is an n-channel field-effect transistor, the crystalline silicon may be impregnated with impurities (e.g., phosphorus (P)) to become n-type. In addition, the channel region of each transistor included in the display device 10 may be formed using single-crystal silicon such as a silicon wafer or SOI substrate.

[0125] For example, the leakage current of a transistor made of a metal oxide with semiconductor properties is extremely small. Therefore, when using a transistor made of a metal oxide with semiconductor properties, the charge corresponding to the potential written to the capacitive element is less likely to escape from the capacitive element. As a result, by using a transistor made of a metal oxide with semiconductor properties, it is possible to retain the charge written to the capacitive element for a long time. Also, under the same conditions for the gate-source potential difference (potential difference between the gate electrode and the source electrode) and the source-drain potential difference, the drain current of a transistor made of a metal oxide with semiconductor properties may be greater than the drain current of a transistor made of crystalline silicon (e.g., low-temperature polysilicon (LTPS)). As a result, under the same conditions for the drain current, the gate-source potential difference and source-drain potential difference of a transistor made of a metal oxide with semiconductor properties can be made smaller than those of a transistor made of crystalline silicon. Therefore, by using a transistor made of a metal oxide with semiconductor properties, the power consumption of the display device 10 can be suppressed.

[0126] Common metallic materials are used as conductive layers 127, 132, 133, 140, and 142. For example, common metallic materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. Depending on the application and specifications of the display device 10, each conductive layer may consist of a single layer of the above metallic material or a multilayer structure in which the above metallic material is laminated. For example, conductive layer 140, which includes the first electrode, may consist of a single layer of the metallic material, and conductive layer 142, which includes the second electrode, may consist of a multilayer structure in which the metallic material is laminated.

[0127] The materials forming the base layer 121, gate insulating layer 125, insulating layer 131, first inorganic insulating layer 152, and second inorganic insulating layer 156 can be general insulating materials. For example, silicon oxide (SiO₂) can be used as these insulating layers.x ) Silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ) and other inorganic insulating layers are used. SiO x N y is a silicon compound and an aluminum compound containing nitrogen (N) in a ratio (x>y) less than that of oxygen (O). SiN x O y is a silicon compound and an aluminum compound containing oxygen in a ratio (x>y) less than that of nitrogen.

[0128] For example, the materials for forming the insulating layer 128, insulating layer 139, insulating layer 136, insulating layer 141 and organic insulating layer 154 can use an organic compound material with excellent surface flatness. The insulating layer 128, insulating layer 136 and insulating layer 141 may be referred to as organic insulating layers.

[0129] The material for forming the cathode 152 uses a conductive oxide that transmits visible light. For example, the material for forming the cathode 152 is a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO), etc. As the conductive oxide that transmits visible light, materials other than the above may also be used.

[0130] The material for forming the anode 143 uses a metal or its alloy with high reflectivity. For example, the material for forming the anode 143 is a metal such as silver (Ag), aluminum (Al), magnesium (Mg), etc. or their alloys. The material for forming the anode 143 may include a configuration in which a film containing a metal is sandwiched by a film containing the above-mentioned conductive oxide.

[0131] [1-8. Modified examples of the structure of pixel 180] A modified example of the structure of pixel 180 will be described with reference to Figures 15 and 16. Figure 15 is a plan view showing the semiconductor layer 122 extracted in a modified example of the structure of pixel 180. Figure 16 is a layout diagram showing the area around the fifth transistor T5 and the second transistor T2 shown in Figure 15, illustrating steps S13 to S19 in "1-6. Method for Manufacturing the Display Device 10". Configurations identical or similar to those in Figures 1 to 14 will be described as necessary.

[0132] The variations in the structure of pixel 180 mainly involve configurations 1 to 3 shown below, which differ from the configuration described in "1-5. Structure of Pixel 180". (Configuration 1) This configuration includes a configuration in which the semiconductor layer 122B of the configuration described in "1-5. Structure of Pixel 180" with reference to Figure 6 is separated into semiconductor layer 122BD and semiconductor layer 122BE. (Configuration 2) Configuration of gate wiring 127B (gate electrode 622). (Configuration 3) Configuration 1 includes first contact hole openings 135L and 135K, first wiring 132L and 132K, second contact hole openings 138H and 138I, and second wiring 133G.

[0133] Configurations other than those shown in Configurations 1 to 3, and configurations other than those related to those shown in Configurations 1 to 3, are the same as the configurations described in "1-1. Overview of the Display Device 10" to "1-7. Materials of Each Component of the Display Device 10". When describing the configuration and function of modified versions of the structure of pixel 180, configurations and functions similar to those of pixel 180 will be described as necessary.

[0134] As shown in Figure 15, in a modified example of the structure of pixel 180, the first region L1(m) does not contain a semiconductor layer. The second region L2(m) includes semiconductor layers 122C, 122BE, and 122D along the first direction. The third region L3(m) does not contain a semiconductor layer. The fourth region L4(m) includes semiconductor layers 122E and 122A along the first direction. The fourth region L4(m-1) includes semiconductor layer 122BD along the first direction.

[0135] The semiconductor layer 122 includes semiconductor layers 122A, 122BD, 122BE, 122C, 122D, and 122E. The configuration of semiconductor layers 122A, 122C, 122D, and 122E is the same as the configuration described in "1-5. Structure of Pixel 180".

[0136] The semiconductor layer 122BE provided along the first direction D1 is the semiconductor layer of the second transistor T2. Similarly, the semiconductor layer 122BD provided along the first direction D1 is the semiconductor layer of the fifth transistor T5. In other words, the semiconductor layer 122BE includes the channel region of the second transistor T2, and the semiconductor layer 122BD includes the channel region of the fifth transistor T5. The semiconductor layer 122BE has a serpentine shape including multiple bends along the first direction D1.

[0137] As shown in STEP 13 of Figure 16 (S13 shown in Figure 10), gate wiring 127E (scan signal line 334) and gate wiring 127B (gate electrode 622) are formed. Gate wiring 127B overlaps with a portion of the semiconductor layer 122BE, excluding the vicinity of the first contact hole openings 135K and 135C, and covers a portion of the semiconductor layer 122BE. Referring to Figures 4, 6, and 15, gate wiring 127B slightly overlaps with the first region L1(m), overlaps with the second region L2(m), the third region L3(m), and the fourth region L4(m), but does not overlap with the fourth region L4(m-1).

[0138] In STEP 14 (S14 shown in Figure 10), an insulating layer 128 (Figures 7 to 9) is formed. As shown in STEP 15 of Figure 16 (S13 shown in Figure 10), first contact hole openings 135H, 135L, 135K, and 135C are formed. The first contact hole openings 135H and 135L open the semiconductor layer 122BD and expose it, while the first contact hole openings 135K and 135C open the semiconductor layer 122BE and expose it.

[0139] As shown in STEP 16 of Figure 16 (S16 shown in Figure 10), the first wiring 132G (drive potential line PVDD), first wirings 132L, 132K, and 132C are formed. The first wiring 132G is formed on the first contact hole opening 135H and the semiconductor layer 122BD and is electrically connected to the semiconductor layer 122BD. The first wiring 132L is formed on the first contact hole opening 135L and the semiconductor layer 122BD and is electrically connected to the semiconductor layer 122BD. The first wiring 132K is formed on the first contact hole opening 135K and the semiconductor layer 122BE and is electrically connected to the semiconductor layer 122BE. The first wiring 132C is formed on the first contact hole opening 135C and the semiconductor layer 122BE and is electrically connected to the semiconductor layer 122BE.

[0140] In STEP 17 (S17 shown in Figure 10), an insulating layer 139 (Figures 7 to 9) is formed. As shown in STEP 18 (S18 shown in Figure 10) in Figure 16, second contact hole openings 138H and 138I are formed. The second contact hole opening 138H opens for the first wiring 132K and exposes the first wiring 132K, while the second contact hole opening 138I opens for the first wiring 132L and exposes the first wiring 132L.

[0141] As shown in STEP 19 of Figure 16 (S19 shown in Figure 10), the second wiring 133G is formed. The second wiring 133G is formed on the second contact hole openings 138H and 138I and is electrically connected to the semiconductor layers 122BD and 122BE. In other words, the second wiring 133G overlaps with a portion of the first wiring 132G and spans the first wiring 132G, forming a bridge wiring that electrically connects the second transistor T2 and the fifth transistor T5.

[0142] A modified version of the pixel 180 structure allows for the electrical connection of the second transistor T2 and the fifth transistor T5 across the first wiring 132G using the second wiring 133G, thus enabling a configuration in which the second region L2(m) does not contain a semiconductor layer.

[0143] The other configurations in the modified structure of pixel 180 are the same as those described in "1-1. Overview of the Display Device 10" to "1-7. Materials of Each Component of the Display Device 10". The modified structure of pixel 180 has the same effects as the configuration described in "1-1. Overview of the Display Device 10" to "1-7. Materials of Each Component of the Display Device 10".

[0144] As embodiments of the present invention, each embodiment or part of each embodiment described above can be combined and implemented as appropriate, insofar as they do not contradict each other.

[0145] Even if an effect is different from the effects brought about by the embodiments described above, if it is clear from the description herein or can be easily predicted by a person skilled in the art, it is naturally understood that it is brought about by the present invention. [Explanation of symbols]

[0146] 10: Display device, 22: Display area, 24: Peripheral area, 26: Terminal area, 32: First electrode, 34: Second electrode, 42: First electrode, 44: Second electrode, 52: First electrode, 54: Second electrode, 100: Array substrate, 101: Substrate, 101A: First surface, 101B: Second surface, 110: IC chip, 120: Control circuit, 121: Underlayer, 122: Semiconductor layer, 122A: Semiconductor layer, 122B: Semiconductor layer, 122BA: Semiconductor layer, 122BB: Semiconductor layer, 122BC: Semiconductor layer, 122BD: Semiconductor layer, 122BE: Semiconductor layer, 122C: Semiconductor layer, 1 22D: Semiconductor layer, 122E: Semiconductor layer, 123: Channel region, 124A: Impurity region, 125: Gate insulating layer, 127: Conductive layer, 127A: Gate wiring, 127B: Gate wiring, 127C: Gate wiring, 127D: Gate wiring, 127E: Gate wiring, 127F: Gate wiring, 127G: Gate wiring, 128: Insulating layer, 129: Fourth contact hole opening, 130: Shift register circuit, 131: Insulating layer, 132: Conductive layer, 132A: First wiring, 132B: First wiring, 132C: First wiring, 132D: First wiring, 132E: First Wiring, 132F: First wiring, 132G: First wiring, 132H: First wiring, 132I: First wiring, 132J: First wiring, 132K: First wiring, 132L: First wiring, 133: Conductive layer, 133A: Second wiring, 133B: Second wiring, 133C: Second wiring, 133D: Second wiring, 133E: Second wiring, 133F: Second wiring, 133G: Second wiring, 135: First contact hole opening, 135A: First contact hole opening, 135B: First contact hole opening, 135C: First contact hole opening, 1 35D: First contact hole opening, 135E: First contact hole opening, 135F: First contact hole opening, 135G: First contact hole opening, 135H: First contact hole opening, 135I: First contact hole opening, 135J: First contact hole opening, 135K: First contact hole opening, 135L: First contact hole opening, 136: Insulating layer, 137: Third contact hole opening, 137A: Third contact hole opening, 137B: Third contact hole opening,137C: Third contact hole opening, 138: Second contact hole opening, 138A: Second contact hole opening, 138B: Second contact hole opening, 138C: Second contact hole opening, 138D: Second contact hole opening, 138E: Second contact hole opening, 138F: Second contact hole opening, 138G: Second contact hole opening, 138H: Second contact hole opening, 138I: Second contact Contact hole opening, 139: insulating layer, 140: conductive layer, 140A: first electrode, 140AE: end, 140B: first electrode, 140BE: end, 140C: first electrode, 140E: end, 141: insulating layer, 142: conductive layer, 142A: second electrode, 142E: end, 143: anode, 144: first layer, 145: second layer, 146: third layer, 147: contact hole opening, 147A: contact hole opening, 148: functional layer, 149: cathode, 150: terminal part, 152: 154: First inorganic insulating layer, 156: Organic insulating layer, 158: Cover film, 160: Scan driver circuit, 165: Sealing film, 170: Array section, 180: Pixel, 181: Pixel circuit, 182A: Area, 182B: Area, 200: Flexible printed circuit board, 321: Image data signal line, 322: Image data signal line, 323: Image data signal line, 330: Scan signal line, 331: Scan signal line, 332: Scan signal line, 333: Scan signal Line, 334: scan signal line, 341: connection wire, 342: connection wire, 612: gate electrode, 614: first electrode, 616: second electrode, 622: gate electrode, 624: first electrode, 626: second electrode, 632: gate electrode, 634: first electrode, 636: second electrode, 642: gate electrode, 644: first electrode, 646: second electrode, 652: gate electrode, 654: first electrode, 656: second electrode, 662: gate electrode, 664: first electrode, 666: second electrode,

Claims

1. It includes a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting the first direction, Each of the plurality of pixels has a first region, a second region adjacent to the first region, a third region adjacent to the second region, and a fourth region adjacent to the third region. The first region, the second region, the third region, and the fourth region are provided along the first direction, Each of the second and fourth regions is superimposed on a plurality of different semiconductor layers arranged to be located along the first direction. Display device.

2. The plurality of distinct semiconductor layers superimposed on the second region include a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer. The plurality of distinct semiconductor layers superimposed on the fourth region include a first semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer. The display device according to claim 1.

3. Each of the plurality of pixels includes a first transistor to a sixth transistor, a first capacitive element, a second capacitive element, and a light-emitting element. The first transistor includes the first semiconductor layer, the second transistor includes the second semiconductor layer, the third transistor includes the third semiconductor layer, the fourth transistor includes the fourth semiconductor layer, the fifth transistor includes the fifth semiconductor layer, and the sixth transistor includes the sixth semiconductor layer. The display device according to claim 2.

4. In a plan view, it includes a second conductive layer superimposed on the plurality of mutually different semiconductor layers, The second conductive layer includes a first portion and a second portion, The first portion of the second conductive layer overlaps with the third region and is an image data signal line for supplying a data potential to the first transistor. The second portion of the second conductive layer overlaps with the first region and is a drive potential line for supplying a drive potential to the fifth transistor for driving the plurality of pixels. The display device according to claim 3.

5. The first conductive layer is provided between the plurality of different semiconductor layers and the second conductive layer along the second direction, The first conductive layer includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, and a sixth portion. The first portion of the first conductive layer is superimposed on the first to fourth regions and the first transistor, and is a signal line for supplying a first control signal for controlling the switching of the first transistor. The second portion of the first conductive layer is superimposed on the second to fourth regions and the second transistor, and is a gate electrode for controlling the switching of the second transistor. The third portion of the first conductive layer is superimposed on the first to fourth regions and the third transistor, and is a signal line for supplying a second control signal for controlling the switching of the third transistor. The fourth portion of the first conductive layer is superimposed on the first to fourth regions and the fourth transistor, and is a signal line for supplying a third control signal for controlling the switching of the fourth transistor. The fifth portion of the first conductive layer is superimposed on the first to fourth regions and the fifth transistor, and is a signal line for supplying a fourth control signal for controlling the switching of the fifth transistor. The sixth portion of the first conductive layer is superimposed on the first to fourth regions and the sixth transistor, and is a signal line for supplying a fifth control signal for controlling the switching of the sixth transistor. The display device according to claim 4.

6. The third conductive layer is provided on the plurality of different gate wirings along a third direction intersecting the first and second directions, The third conductive layer includes a first portion, a second portion, and a third portion. The first portion of the third conductive layer overlaps with the first to fourth regions, is electrically connected to the third transistor, and is a reset potential line for supplying a reset potential to supply a reference potential to the third transistor. The second portion of the third conductive layer overlaps with the first to fourth regions, is electrically connected to the fourth transistor, and is an initialization potential line for supplying an initialization potential to the fourth transistor. The third portion of the third conductive layer overlaps with the first to fourth regions, is electrically connected to the sixth transistor, and is a reference potential line for supplying a reference potential to the sixth transistor. The display device according to claim 5.

7. The third conductive layer includes, along the third direction, a fourth conductive layer provided on the third conductive layer, a fifth conductive layer provided on the fourth conductive layer, and an insulating layer provided between the fourth conductive layer and the fifth conductive layer. The fourth conductive layer includes a first portion, a second portion and a third portion, The fifth conductive layer includes the first portion, The display device according to claim 6.

8. The first portion of the fourth conductive layer is positioned adjacent to the second portion of the fourth conductive layer along the first direction, The first capacitive element includes a first portion of the fourth conductive layer, a part of the insulating layer, and a part of the first portion of the fifth conductive layer. The second capacitive element includes a second portion of the fourth conductive layer, another portion of the insulating layer, and another portion of the first portion of the fifth conductive layer. The display device according to claim 7.

9. The first portion of the fifth conductive layer overlaps with the first and second portions of the fourth conductive layer and covers the first and second portions of the fourth conductive layer. The display device according to claim 7.

10. The fifth conductive layer includes an anode layer provided on top of the fifth conductive layer, The light-emitting element includes a third portion of the fourth conductive layer and a portion of the anode layer electrically connected to the third portion of the fourth conductive layer. The display device according to claim 7.

11. The plurality of pixels include at least a first pixel and a second pixel that are adjacent to each other along the second direction, The fifth semiconductor layer of the second pixel is provided in the fourth region of the first pixel. The display device according to claim 3.

12. The first to sixth transistors are n-channel field-effect transistors. The display device according to claim 3.

13. The first to sixth semiconductor layers have an oxide semiconductor. The display device according to claim 12.

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