Semiconductor package, core substrate, and method for manufacturing a semiconductor package

Abstract

The present invention provides a semiconductor package, a core substrate, and a method for manufacturing a semiconductor package that suppress the planar area of ​​recesses formed in a core substrate for arranging semiconductor elements. [Solution] The semiconductor package 10 includes a core substrate 12 having a first surface 13 and a second surface 14 located opposite to the first surface, and a semiconductor element 40 mounted on the core substrate. The core substrate includes a first recess 21 located on the first surface and a second recess 22 located at the bottom of the first recess. The semiconductor element is located in the second recess.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor packages, core substrates, and methods of manufacturing semiconductor packages.

Background Art

[0002] Packaging technologies for densely mounting a plurality of semiconductor elements with different functions, such as CPUs and memories, on a single substrate have attracted attention. A substrate for electrically connecting a plurality of semiconductor elements is also referred to as an interposer. For example, Patent Document 1 discloses a semiconductor package including an interposer including through electrodes and semiconductor elements mounted on the interposer.

[0003] In the semiconductor package of Patent Document 1, the semiconductor element is disposed in a recess formed on the surface of the substrate. Such a recess can be formed by etching. Typically, the recess can be formed by wet etching. The recess is formed deep enough to accommodate the semiconductor element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, since wet etching is isotropic etching, when forming a recess deep enough to accommodate the semiconductor element, the width of the recess also increases due to side etching. Therefore, the planar area (area in a plan view) of the recess may become larger than necessary. As a result, it may be required to secure a large area for the recess on the substrate.

[0006] The embodiments of this disclosure aim to provide a semiconductor package, a core substrate, and a method for manufacturing a semiconductor package that can effectively solve the aforementioned problems. [Means for solving the problem]

[0007] Embodiments of this disclosure relate to the following [1] to

[17] .

[0008] [1] A semiconductor package, A core substrate including a first surface and a second surface located on the opposite side of the first surface, The core substrate comprises a semiconductor element mounted on the core substrate, The core substrate includes a first recess located on the first surface and a second recess located at the bottom of the first recess. The semiconductor element is a semiconductor package located in the second recess.

[0009] [2] The semiconductor package according to [1], wherein the semiconductor element is located from the second recess to the first recess.

[0010] [3] The semiconductor package according to [1] or [2], wherein the depth of the second recess is smaller than the depth of the first recess.

[0011] [4] The semiconductor package according to any one of [1] to [3], wherein the depth of the first recess is 20 μm or more and 200 μm or less.

[0012] [5] The depth of the second recess is 2 μm or more. 20 A semiconductor package described in any of [1] to [4], having a size of μm or less.

[0013] [6] The side wall portion of the first recess includes a first end located on the side of the first surface and a second end located on the side of the bottom, The semiconductor package according to any one of [1] to [5], wherein the inclination angle of the straight line connecting the first end and the second end with respect to the first plane is 45 degrees or more and 85 degrees or less.

[0014] [7] The semiconductor package according to any one of [1] to [6], wherein the core substrate is a glass substrate.

[0015] [8] The semiconductor package according to any one of [1] to [6], comprising a wiring layer located on the first surface, the wiring layer including an insulating layer and a conductive layer electrically connected to the semiconductor element.

[0016] [9] The core substrate includes a through hole penetrating the core substrate from the first surface to the second surface, The semiconductor package according to [8], wherein a through electrode electrically connected to the conductive layer is located in the through hole.

[0017]

[10] The core substrate includes a through hole penetrating the core substrate from the bottom of the second recess to the second surface, The semiconductor package according to [8], wherein a through electrode electrically connected to the conductive layer is located in the through hole.

[0018]

[11] The semiconductor package according to any one of [8] to

[10] , wherein the semiconductor element is covered by the insulating layer.

[0019]

[12] The semiconductor package according to any one of [1] to

[11] , wherein an adhesive layer is located between the semiconductor element and the bottom of the second recess.

[0020]

[13] A core substrate on which a semiconductor element is mounted, a first surface, a second surface located on the opposite side of the first surface, a first recess located on the first surface, a second recess located at the bottom of the first recess, the second recess being the one in which the semiconductor element is disposed.

[0021]

[14] A method for manufacturing a semiconductor package, A step of preparing a core substrate including a first surface and a second surface located on the opposite side of the first surface; A step of forming a first recess on the first surface by wet etching; A step of forming a second recess at the bottom of the first recess by wet etching; A method for manufacturing a semiconductor package, including a step of disposing a semiconductor element in the second recess.

[0022]

[15] The method for manufacturing a semiconductor package according to

[14] , including a step of forming a wiring layer including an insulating layer and a conductive layer electrically connected to the semiconductor element on the first surface.

[0023]

[16] A step of forming a through hole penetrating the core substrate from the first surface to the second surface in the core substrate; The method for manufacturing a semiconductor package according to

[15] , including a step of forming a through electrode electrically connected to the conductive layer in the through hole.

[0024]

[17] A step of forming a through hole penetrating the core substrate from the bottom of the second recess to the second surface in the core substrate; The method for manufacturing a semiconductor package according to

[15] , including a step of forming a through electrode electrically connected to the conductive layer in the through hole.

Advantages of the Invention

[0025] According to the embodiment of the present disclosure, the planar area of the recess formed in the core substrate for disposing the semiconductor element can be suppressed.

Brief Description of the Drawings

[0026] [Figure 1] It is a plan view showing a semiconductor package according to an embodiment. [Figure 2] It is a cross-sectional view taken along the line II-II of the semiconductor package in FIG. 1. [Figure 3] It is an enlarged cross-sectional view showing the through electrode in FIG. 2. [Figure 4]This is a cross-sectional view showing a magnified view of the recess in Figure 2. [Figure 5] This is a cross-sectional view showing an example of the process for preparing a core substrate. [Figure 6] This is a cross-sectional view showing an example of the process for forming through holes and recesses. [Figure 7] This is a cross-sectional view showing an example of the process for forming the first recess. [Figure 8] This is a cross-sectional view showing an example of the process for forming the first recess. [Figure 9] This is a cross-sectional view showing an example of the process for forming the first recess. [Figure 10] This is a cross-sectional view showing an example of the process for forming the second recess. [Figure 11] This is a cross-sectional view showing an example of the process for forming the second recess. [Figure 12] This is a cross-sectional view showing an example of the process for forming the second recess. [Figure 13] This is a cross-sectional view showing an example of the process for forming through electrodes. [Figure 14] This is a cross-sectional view showing an example of the process for forming an adhesive layer. [Figure 15] This is a cross-sectional view showing an example of the process for arranging semiconductor elements. [Figure 16] This is a cross-sectional view showing an example of the process for forming a redistribution layer. [Figure 17] This is a cross-sectional view showing an example of the process for forming a redistribution layer. [Figure 18] This is a cross-sectional view showing a magnified view of a recess in a semiconductor package in a comparative example. [Figure 19] This is a cross-sectional view showing a semiconductor package according to the first modified example. [Figure 20] This is a cross-sectional view showing a magnified view of the through-electrode of a semiconductor package according to a second modification. [Figure 21] This is a cross-sectional view showing a semiconductor package according to a third modified example. [Figure 22] This is a cross-sectional view showing a semiconductor package according to a fourth modified example. [Figure 23] This figure shows examples of products that incorporate semiconductor packages. [Modes for carrying out the invention]

[0027] In this specification, unless otherwise specified, terms such as "substrate," "base material," "board," "sheet," and "film," which refer to the base material, are not distinguished from each other solely on the basis of differences in name. For example, "substrate" is a concept that includes materials such as sheets and films.

[0028] In this specification, unless otherwise specified, the term "plane" refers to the plane of a plate-like member in question that coincides with the planar direction of the member when viewed as a whole and in a broad sense. The term "normal direction" as used with respect to a plate-like member refers to the direction normal to the plane of the member.

[0029] In this specification, unless otherwise specified, terms relating to shape and geometric conditions, as well as values ​​that specify the degree of shape and geometric conditions, may be interpreted based on the function they achieve, without being bound by their strict meaning. Examples of terms relating to shape and geometric conditions include "parallel" and "orthogonal." Examples of values ​​that specify the degree of shape and geometric conditions include length values ​​and angle values.

[0030] In this specification, unless otherwise specified, when the positional relationship of a second component to a first component is described using terms such as "above," "below," "upper side," "lower side," "above," or "downward," the second component may or may not be in contact with the first component. Furthermore, when the positional relationship of a second component to a first component is described using terms such as "above," "upper side," or "upward," depending on the usage conditions of the product, the second component may be located "below," "upper side," or "downward" of the first component. Similarly, when the positional relationship of a second component to a first component is described using terms such as "below," "downper side," or "downward," depending on the usage conditions of the product, the second component may be located "above," "upper side," or "upward" of the first component.

[0031] In this specification, if multiple upper limit candidates and multiple lower limit candidates are given for a certain parameter, the numerical range of that parameter may be constructed by combining any one upper limit candidate and any one lower limit candidate. For example, consider the case where it is stated that "Parameter B is, for example, A1 or greater, and may be A2 or greater, and may be A3 or greater. Parameter B is, for example, A4 or less, and may be A5 or less, and may be A6 or less." In this case, the numerical range of parameter B may be A1 or greater and A4 or less, A1 or greater and A5 or less, and A1 or greater and A6 or less. Also, the numerical range of parameter B may be A2 or greater and A4 or less, A2 or greater and A5 or less, A2 or greater and A6 or less, A3 or greater and A4 or less, A3 or greater and A5 or less, and A3 or greater and A6 or less.

[0032] In this specification and these drawings, unless otherwise specified, identical parts or components having similar functions are denoted by the same or similar reference numerals. Dimensional ratios in the drawings may differ from actual ratios for illustrative purposes. In this specification and these drawings, some components may be omitted from the drawings.

[0033] In this specification and these drawings, unless otherwise specified, one embodiment of this specification may be combined with other embodiments or modifications, to the extent that it does not contradict the original. Other embodiments or modifications may also be combined with each other, to the extent that it does not contradict the original.

[0034] In this specification and these drawings, unless otherwise specified, when multiple steps are disclosed regarding a method such as a manufacturing method, other steps not disclosed may be performed between the disclosed steps. The order of the disclosed steps may be changed to the extent that it does not create a contradiction.

[0035] Hereinafter, a semiconductor package, a core substrate, and a method for manufacturing the semiconductor package according to embodiments of this disclosure will be described in detail with reference to the drawings. However, the technical concept of the embodiments of this disclosure shall not be construed as being limited to the following specific embodiments.

[0036] (Semiconductor package) Figure 1 is a plan view showing a semiconductor package 10. The semiconductor package 10 includes at least a core substrate 12 and semiconductor elements 40. The semiconductor elements 40 are mounted on the core substrate 12. The semiconductor package 10 may include a plurality of semiconductor elements 40. The plurality of semiconductor elements 40 may be arranged in the plane direction of the core substrate 12. The plurality of semiconductor elements 40 may be arranged in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are included in the plane direction of the core substrate 12. The second direction D2 intersects the first direction D1. The second direction D2 may be perpendicular to the first direction D1. The first direction D1 and the second direction D2 may be the directions in which the edges of the core substrate 12 extend.

[0037] The semiconductor package 10 may include a core substrate 12, a semiconductor element 40, a through-electrode 25, and a redistribution layer 30. The individual components of the semiconductor package 10 will be described below.

[0038] (Core board) Figure 2 is a cross-sectional view of the semiconductor package 10 in Figure 1 along line II-II. The core substrate 12 includes a first surface 13 and a second surface 14. The second surface 14 is located on the opposite side of the first surface 13 in the thickness direction of the core substrate 12. The thickness direction is also referred to as the third direction D3. The third direction D3 is perpendicular to the first direction D1 and the second direction D2. In this specification, observing an object along the third direction D3 is also referred to as a "plan view".

[0039] The core substrate 12 includes a recess 20. The recess 20 is located on the first surface 13. A semiconductor element 40 is located in the recess 20. The core substrate 12 may include a plurality of recesses 20. A plurality of semiconductor elements 40 may each be located in a recess 20. A single semiconductor element 40 may be placed in a single recess 20. A plurality of semiconductor elements 40 may be placed in a single recess 20. Details of the configuration of the recess 20 will be described later.

[0040] The number of recesses 20 contained in the core substrate 12 that constitutes one semiconductor package 10 may be, for example, one or more, two or more, or three or more. The number of recesses 20 contained in the core substrate 12 that constitutes one semiconductor package 10 may be, for example, 10 or less, eight or less, or six or less.

[0041] The core substrate 12 may include through holes 15 that penetrate the core substrate 12 from the first surface 13 to the second surface 14. The core substrate 12 may include a plurality of through holes 15. The through holes 15 include a wall surface 16. The wall surface 16 extends from the first surface 13 to the second surface 14. The wall surface 16 may extend straight along the third direction D3 from the first surface 13 to the second surface 14. The through holes 15 may have a circular contour in plan view. In this case, the through holes 15 may be formed in a cylindrical shape. The through holes 15 may have a contour other than circular in plan view. A core substrate 12 including through holes 15, in which through electrodes 25 described later are formed, is also referred to as a through electrode substrate.

[0042] The core substrate 12 may be a glass substrate. The glass substrate may include alkali-free glass or borosilicate glass. Alkali-free glass is glass that does not contain 0.2% or more of alkaline components such as sodium or potassium. Alkali-free glass may, for example, contain boric acid instead of alkaline components. Alkali-free glass may also contain alkaline earth metal oxides such as calcium oxide or barium oxide.

[0043] The core substrate 12 may be a quartz substrate, sapphire substrate, resin substrate, silicon substrate, metal substrate, silicon carbide substrate, alumina (Al2O3) substrate, aluminum nitride (AlN) substrate, zirconia oxide (ZrO2) substrate, lithium niobate substrate, tantalum niobate substrate, etc. The resin substrate may contain organic materials. The resin substrate may contain, for example, epoxy resin, polyethylene, polypropylene, etc. The metal substrate may contain, for example, copper, aluminum, nickel, SUS, etc. The metal substrate may be composed of conductive metals such as copper, aluminum, and nickel. The metal substrate may be composed of multiple metals such as SUS.

[0044] The core substrate 12 has a thickness T0. The thickness T0 of the core substrate 12 is, for example, 100 μm or more, may be 200 μm or more, or 500 μm or more. The thickness T0 of the core substrate 12 is, for example, 2000 μm or less, may be 1500 μm or less, or 1000 μm or less.

[0045] (Semiconductor element) The semiconductor element 40 is located in the recess 20. The semiconductor element 40 includes an upper surface 41, a lower surface 42, and a side surface 43 (see Figure 4). The upper surface 41 is located opposite the lower surface 42 in the third direction D3. The lower surface 42 faces the core substrate 12. The side surface 43 is located between the upper surface 41 and the lower surface 42. The side surface 43 extends from the upper surface 41 to the lower surface 42. The semiconductor element 40 may include a terminal 44 exposed on the upper surface 41.

[0046] The semiconductor element 40 may include a transistor formed from a semiconductor such as silicon. The semiconductor element 40 may be, for example, a CPU, GPU, FPGA, sensor, memory, etc. The semiconductor element 40 may be a chiplet in which semiconductor elements such as a CPU, GPU, FPGA, sensor, memory, etc. are divided according to function. The semiconductor element 40 may be a passive element such as a resistor, capacitor, etc.

[0047] (Through electrode) The through-electrode 25 is located in the through-hole 15. The through-electrode 25 may be located in each of the multiple through-holes 15. The through-electrode 25 may cover the wall surface 16 of the through-hole 15. The through-electrode 25 may at least partially close the through-hole 15. "Closing" means shielding the space of the through-hole 15 with a solid material in any plane perpendicular to the third direction D3. As shown in Figure 2, the through-electrode 25 may close the entire through-hole 15 in the third direction D3. The through-electrode 25 may fill the through-hole 15. That is, the through-electrode 25 may fill the through-hole 15 without any gaps. The through-electrode 25 is electrically connected to the conductive layers 33, 38, which will be described later.

[0048] Figure 3 is an enlarged cross-sectional view of the through electrode 25 in Figure 2. As shown in Figure 3, the through electrode 25 may include a seed layer 251 and a plating layer 252. The seed layer 251 is located on the wall surface 16 of the through hole 15. The seed layer 251 may cover the entire wall surface 16 of the through hole 15 or a portion thereof. The seed layer 251 may cover the entire wall surface 16 of the through hole 15 in the third direction D3. The seed layer 251 is located between the wall surface 16 of the through hole 15 and the plating layer 252. The seed layer 251 is formed by physical deposition such as sputtering. The seed layer 251 is conductive. The seed layer 251 may include, for example, a metallic material such as copper, nickel, titanium, chromium, or zinc, or a compound of these metallic materials.

[0049] The plating layer 252 is located on the seed layer 251. The plating layer 252 is formed on the seed layer 251 by electroplating. The plating layer 252 may constitute a large portion of the through electrode 25. The plating layer 252 is electrically conductive. The plating layer 252 may contain metals such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc, or alloys using these metals. The plating layer 252 may contain these metals or alloys using these metals as its main component. The "main component" is a component that constitutes 50 atomic percent or more of the plating layer 252. For example, the plating layer 252 may contain copper as its main component.

[0050] (Rewiring layer) As shown in Figure 2, the redistribution layer 30 is located on the core substrate 12. The redistribution layer 30 may include a first redistribution layer 31 located on the first surface 13 of the core substrate 12 and a second redistribution layer 36 located on the second surface 14 of the core substrate 12.

[0051] The first redistribution layer 31 includes at least one wiring layer. In the example shown in Figure 2, the first redistribution layer 31 includes a first wiring layer 311. The first wiring layer 311 is located on the first surface 13 of the core substrate 12. Wiring layers such as the first wiring layer 311 include an insulating layer 32 and a conductive layer 33.

[0052] The insulating layer 32 includes a layer made of an insulating material having insulating properties. For example, the insulating layer 32 may include an organic layer made of an organic material having insulating properties. Examples of organic materials include polyimide and epoxy. For example, the insulating layer 32 may include an inorganic layer made of an inorganic material having insulating properties. Examples of inorganic materials include silicon nitride and silicon oxide.

[0053] The insulating layer 32 may include an opening 321. The opening 321 may penetrate the insulating layer 32 in the third direction D3. The insulating layer 32 may include a plurality of openings 321.

[0054] The conductive layer 33 is electrically connected to the semiconductor element 40. The conductive layer 33 is also electrically connected to the through-electrode 25. The semiconductor element 40 and the through-electrode 25 are electrically connected via the conductive layer 33.

[0055] The conductive layer 33 may include vias 34. The vias 34 are located at the opening 321 of the insulating layer 32. The vias 34 extend in a third direction D3. The conductive layer 33 may include a plurality of vias 34. The vias 34 may include vias 34 connected to terminals 44 of the semiconductor element 40. The vias 34 may include vias 34 connected to through electrodes 25.

[0056] The conductive layer 33 may include wiring 35. The wiring 35 extends in the planar direction of the core substrate 12. The wiring 35 may extend at least partially in the first direction D1 or the second direction D2. The wiring 35 may be located on the upper surface of the insulating layer 32. The "upper surface" is the surface located opposite the "lower surface" in the third direction D3. The "lower surface" is the surface facing the core substrate 12 in the third direction D3.

[0057] The conductive layer 33 is conductive. The conductive layer 33 may contain metallic materials such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc. The conductive layer 33 may also contain compounds of these metallic materials.

[0058] The second redistribution layer 36 includes at least one wiring layer. In the example shown in Figure 2, the second redistribution layer 36 includes the first wiring layer 361. The first wiring layer 361 is located on the second surface 14 of the core substrate 12. The wiring layer, such as the first wiring layer 361, includes an insulating layer 37 and a conductive layer 38.

[0059] The insulating layer 37 includes a layer made of an insulating material having insulating properties. For example, the insulating layer 37 may include an organic layer made of an organic material having insulating properties. Examples of organic materials include polyimide and epoxy. For example, the insulating layer 37 may include an inorganic layer made of an inorganic material having insulating properties. Examples of inorganic materials include silicon nitride and silicon oxide.

[0060] The insulating layer 37 may include an opening 371. The opening 371 may penetrate the insulating layer 37 in the third direction D3. The insulating layer 37 may include a plurality of openings 371.

[0061] The conductive layer 38 is electrically connected to the through electrode 25. The conductive layer 38 and the semiconductor element 40 are electrically connected via the conductive layer 33 and the through electrode 25.

[0062] The conductive layer 38 may include vias 39. The vias 39 are located at the opening 371 of the insulating layer 37. The vias 39 extend in a third direction D3. The conductive layer 38 may include a plurality of vias 39. The vias 39 may include vias 39 connected to the through electrode 25.

[0063] The conductive layer 38 is conductive. The conductive layer 38 may contain metallic materials such as copper, gold, silver, platinum, rhodium, tin, aluminum, nickel, titanium, chromium, and zinc. The conductive layer 33 may contain compounds of these metallic materials.

[0064] (recess) The configuration of the recess 20 will now be described in detail. Figure 4 is an enlarged cross-sectional view of the recess 20 in Figure 2. As shown in Figure 4, the recess 20 includes a first recess 21 and a second recess 22. That is, the core substrate 12 includes the first recess 21 and the second recess 22.

[0065] The first recess 21 is located on the first surface 13. The first recess 21 is formed in a concave shape on the first surface 13. The first recess 21 is formed by wet etching the first surface 13.

[0066] The first recess 21 includes a side wall portion 211 and a bottom portion 212. The side wall portion 211 includes a first end portion 213, a second end portion 214, and a curved surface 215. The first end portion 213 is the end of the side wall portion 211 located on the side of the first surface 13 (upper in Figure 4). The first end portion 213 can also be described as the boundary between the first surface 13 and the first recess 21. The second end portion 214 is the end of the side wall portion 211 located on the side of the bottom portion 212 (lower in Figure 4). The second end portion 214 can also be described as the boundary between the side wall portion 211 and the bottom portion 212. The curved surface 215 is a concave curved surface. The curved surface 215 is located between the first end portion 213 and the second end portion 214. The curved surface 215 extends from the first end portion 213 to the second end portion 214. The bottom portion 212 may be a flat surface parallel to the first surface 13.

[0067] The second recess 22 is located at the bottom 212 of the first recess 21. The second recess 22 is formed in a concave shape at the bottom 212 of the first recess 21. The second recess 22 may be formed over the entire bottom 212 of the first recess 21. The second recess 22 may be formed in a part of the bottom 212 of the first recess 21. In this case, the second recess 22 may be formed in the central part of the bottom 212 of the first recess 21. The second recess 22 is formed by wet etching the bottom 212 of the first recess 21.

[0068] The second recess 22 includes a side wall portion 221 and a bottom portion 222. The side wall portion 221 includes a third end portion 223, a fourth end portion 224, and a curved surface 225. The third end portion 223 is the end of the side wall portion 221 located on the side of the first surface 13 (upper in Figure 4). The third end portion 223 can also be described as the boundary between the first recess 21 and the second recess 22. The fourth end portion 224 is the end of the side wall portion 221 located on the side of the bottom portion 222 (lower in Figure 4). The fourth end portion 224 can also be described as the boundary between the side wall portion 221 and the bottom portion 222. The curved surface 225 is a concave curved surface. The curved surface 225 is located between the third end portion 223 and the fourth end portion 224. The curved surface 225 extends from the third end portion 223 to the fourth end portion 224. The bottom portion 222 may be a flat surface parallel to the first surface 13.

[0069] The semiconductor element 40 described above is located in the second recess 22. The semiconductor element 40 may be located extending from the second recess 22 to the first recess 21. The lower surface 42 of the semiconductor element 40 may be located within the second recess 22. The upper surface 41 of the semiconductor element 40 may be located within the first recess 21. The upper surface 41 of the semiconductor element 40 may be located in the same plane as the first surface 13. The upper surface 41 of the semiconductor element 40 may be located above the first surface 13. The side surface 43 of the semiconductor element 40 may be located straddling the inside of the second recess 22 and the inside of the first recess 21.

[0070] The insulating layer 32 may be located within the first recess 21 and the second recess 22. The insulating layer 32 may fill the first recess 21 and the second recess 22. That is, the insulating layer 32 may completely fill the first recess 21 and the second recess 22 without any gaps. The semiconductor element 40 may be covered with the insulating layer 32. The top surface 41 and side surface 43 of the semiconductor element 40 may be in contact with the insulating layer 32.

[0071] The lower surface 42 of the semiconductor element 40 does not have to be in contact with the bottom 222 of the second recess 22. For example, the adhesive layer 45 may be located between the semiconductor element 40 and the bottom 222 of the second recess 22. The lower surface of the adhesive layer 45 may be in contact with the bottom 222 of the second recess 22. The upper surface of the adhesive layer 45 may be in contact with the lower surface 42 of the semiconductor element 40. The adhesive layer 45 adheres the semiconductor element 40 and the bottom 222 of the second recess 22.

[0072] The adhesive layer 45 may be placed over the entire bottom 222 of the second recess 22. The adhesive layer 45 may be placed over a portion of the bottom 222 of the second recess 22. In this case, the adhesive layer 45 may be placed over the central portion of the bottom 222 of the second recess 22. The entire lower surface 42 of the semiconductor element 40 may be in contact with the adhesive layer 45. A portion of the lower surface 42 of the semiconductor element 40 may be in contact with the adhesive layer 45.

[0073] The adhesive layer 45 may be configured to cure by some trigger. The adhesive layer 45 may contain a resin material and a curing agent. Examples of triggers include heating and light irradiation. The resin material of the adhesive layer 45 may be a polymer such as epoxy resin, acrylic resin, polyurethane, silicone resin, polyimide, or polyester. The resin material of the adhesive layer 45 may contain monomers. The resin material of the adhesive layer 45 may be the same as the material of the insulating layer 32. The resin material of the adhesive layer 45 may be different from the material of the insulating layer 32. The curing agent is, for example, a polymerization initiator. The polymerization initiator may generate radicals or cations by heating or light irradiation. The adhesive layer 45 may contain a plurality of fillers. The fillers may consist of inorganic materials such as silica or glass.

[0074] The first recess 21 has a depth T1. The depth T1 of the first recess 21 is, for example, 20 μm or more, may be 40 μm or more, or 60 μm or more. The depth T1 of the first recess 21 is, for example, 200 μm or less, may be 150 μm or less, or 100 μm or less. The depth T1 of the first recess 21 is the distance between the first surface 13 and the bottom 212 of the first recess 21 in the third direction D3.

[0075] The second recess 22 has a depth T2. The depth T2 of the second recess 22 is, for example, 2 μm or more, may be 4 μm or more, or 6 μm or more. The depth T2 of the second recess 22 is, for example, 20 μm or less, may be 15 μm or less, or 10 μm or less. The depth T2 of the second recess 22 is the distance between the bottom 212 of the first recess 21 and the bottom 222 of the second recess 22 in the third direction D3.

[0076] The depth T2 of the second recess 22 is smaller than the depth T1 of the first recess 21. The ratio T1 / T2 of depth T1 to depth T2 is, for example, 1 or more, may be 5 or more, or may be 10 or more. The ratio T1 / T2 is, for example, 100 or less, may be 50 or less, or may be 20 or less.

[0077] As shown in Figure 1, the first recess 21 may have a rectangular shape in plan view. The first recess 21 may have a first dimension S1 along the first direction D1 and a second dimension S2 along the second direction D2. The first dimension S1 can also be said to be the width of the first recess 21 in the first direction D1. The second dimension S2 can also be said to be the width of the first recess 21 in the second direction D2. The first dimension S1 and the second dimension S2 are, for example, 2000 μm or more, may be 4000 μm or more, or may be 6000 μm or more. The first dimension S1 and the second dimension S2 are, for example, 20000 μm or less, may be 15000 μm or less, or may be 10000 μm or less. The first dimension S1 and the second dimension S2 are dimensions at the boundary between the first surface 13 and the first recess 21.

[0078] The first dimension S1 is greater than the depth T1 of the first recess 21. The ratio S1 / T1 of the first dimension S1 to the depth T1 is, for example, 10 or more, may be 20 or more, or 50 or more. The ratio S1 / T1 is, for example, 1000 or less, may be 500 or less, or 150 or less. Similarly, the second dimension S2 is greater than the depth T1 of the first recess 21. The numerical range of the ratio S2 / T1 of the second dimension S2 to the depth T1 may be the same as the numerical range of the ratio S1 / T1 described above.

[0079] As shown in Figure 1, the second recess 22 may be located within the first recess 21 in a plan view. As shown in Figure 1, the second recess 22 may have a rectangular shape in a plan view. The second recess 22 may have a third dimension S3 along the first direction D1 and a fourth dimension S4 along the second direction D2. The third dimension S3 can also be defined as the width of the second recess 22 in the first direction D1. The fourth dimension S4 can also be defined as the width of the second recess 22 in the second direction D2. The third dimension S3 and the fourth dimension S4 are, for example, 200 μm or more, may be 300 μm or more, or 400 μm or more. The third dimension S3 and the fourth dimension S4 are, for example, 18000 μm or less, may be 14000 μm or less, or 9000 μm or less. The third dimension S3 and the fourth dimension S4 are dimensions at the boundary between the first recess 21 and the second recess 22.

[0080] The third dimension S3 is greater than the depth T2 of the second recess 22. The numerical range of the ratio S3 / T2 of the third dimension S3 to the depth T2 may be the same as the numerical range of the ratio S1 / T1 described above. Similarly, the fourth dimension S4 is greater than the depth T2 of the second recess 22. The numerical range of the ratio S4 / T2 of the fourth dimension S4 to the depth T2 may be the same as the numerical range of the ratio S2 / T1 described above.

[0081] The third dimension S3 is smaller than the first dimension S1. The numerical range of the ratio S1 / S3, which is the ratio of the first dimension S1 to the third dimension S3, may be the same as the numerical range of the ratio T1 / T2 described above. Similarly, the fourth dimension S4 is smaller than the second dimension S2. The numerical range of the ratio S2 / S4, which is the ratio of the second dimension S2 to the fourth dimension S4, may be the same as the numerical range of the ratio T1 / T2 described above.

[0082] As shown in Figure 4, the side wall portion 211 of the first recess 21 may form a steeply inclined surface. The inclination angle θ1 of the straight line L1 connecting the first end portion 213 and the second end portion 214 of the side wall portion 211 of the first recess 21 with respect to the first surface 13 is, for example, 45 degrees or more, may be 50 degrees or more, or may be 65 degrees or more. The inclination angle θ1 is, for example, 85 degrees or less, may be 80 degrees or less, or may be 75 degrees or less.

[0083] Similarly, the side wall portion 221 of the second recess 22 may form a steeply inclined surface. The inclination angle θ2 of the straight line L2 connecting the third end portion 223 and the fourth end portion 224 of the side wall portion 221 of the second recess 22 with respect to the first surface 13 is, for example, 45 degrees or more, may be 50 degrees or more, or may be 65 degrees or more. The inclination angle θ2 is, for example, 85 degrees or less, may be 80 degrees or less, or may be 75 degrees or less.

[0084] The dimensions described above are calculated based on images of the cross-section of the core substrate 12 obtained by electron microscopy. The cross-section is obtained by cutting the core substrate 12 along a cutting plane that passes through the center point of the through-hole 15 in a plan view and is perpendicular to the first surface 13.

[0085] (Manufacturing method for semiconductor packages) A method for manufacturing the semiconductor package 10 will be described.

[0086] The method for manufacturing the semiconductor package 10 includes a core substrate preparation step, a recess formation step, a through-hole formation step, a through-electrode formation step, a semiconductor element placement step, and a redistribution layer formation step.

[0087] First, a core substrate preparation process is carried out. In the core substrate preparation process, a core substrate 12 is prepared as shown in Figure 5. This core substrate 12 includes a first surface 13 and a second surface 14 located on the opposite side of the first surface 13.

[0088] Next, a recess formation process is carried out. In the recess formation process, as shown in Figure 6, a recess 20 is formed on the first surface 13 of the core substrate 12. The recess formation process includes a first recess formation process and a second recess formation process.

[0089] In the first recess formation step, a first recess 21 is formed on the first surface 13 of the core substrate 12. The first recess 21 is formed by wet etching. In the first recess formation step, first, as shown in Figure 7, a resist layer 71 is formed on the first surface 13 of the core substrate 12. Next, an opening 711 is provided in the resist layer 71 at the position where the first recess 21 will be formed. Then, wet etching is performed at the opening 711 of the resist layer 71. As a result, as shown in Figure 8, the first recess 21 is formed on the first surface 13 of the core substrate 12. Here, since wet etching is isotropic etching, the first recess 21 is formed by side etching, extending beyond the opening 711 of the resist layer 71 in the planar direction of the core substrate 12. That is, in a plan view, the first recess 21 is wider than the opening 711 of the resist layer 71. After that, as shown in Figure 9, the resist layer 71 is removed.

[0090] In the second recess formation process, a second recess 22 is formed at the bottom 212 of the first recess 21. The second recess 22 is also formed by wet etching. In the second recess formation process, first, as shown in Figure 10, a resist layer 72 is formed on the first surface 13 of the core substrate 12 and on the side walls 211 and bottom 212 of the first recess 21. Next, an opening 721 is made in the resist layer 72 at the position where the second recess 22 will be formed (a position that overlaps with the bottom 212 in a plan view). Then, wet etching is performed at the opening 721 of the resist layer 72. As a result, as shown in Figure 11, the second recess 22 is formed at the bottom 212 of the first recess 21. Here again, since wet etching is isotropic etching, the second recess 22 is formed by side etching, extending beyond the opening 721 of the resist layer 72 in the planar direction of the core substrate 12. That is, in a plan view, the second recess 22 is wider than the opening 721 of the resist layer 72. Subsequently, the resist layer 72 is removed, as shown in Figure 12.

[0091] Next, a through-hole formation process is carried out. In the through-hole formation process, as shown in Figure 6, a through-hole 15 is formed in the core substrate 12, penetrating from the first surface 13 to the second surface 14. The through-hole 15 may be formed by etching, such as wet etching or dry etching. In this case, first, a resist layer is formed on the first surface 13. Subsequently, an opening is made in the resist layer at the position where the through-hole 15 will be formed. Next, etching is performed at the opening in the resist layer. As a result, as shown in Figure 6, a through-hole 15 is formed in the core substrate 12. The through-hole 15 may also be formed by machining using a tool such as a drill.

[0092] The through-hole formation process may be performed after the recess formation process. The through-hole formation process may be performed before the recess formation process. The through-hole formation process may be performed simultaneously with the recess formation process.

[0093] Next, a through-electrode formation process is carried out. In the through-electrode formation process, as shown in Figure 13, a through-electrode 25 is formed in the through-hole 15. The through-electrode formation process may also include a seed layer formation process and a plating layer formation process.

[0094] In the seed layer formation process, a seed layer 251 is formed on the wall surface 16 of the through hole 15. The seed layer 251 is formed by physical deposition such as sputtering. The seed layer 251 may cover the entire wall surface 16.

[0095] In the plating process, a plating layer 252 is formed on the seed layer 251 by electroplating. For example, the core substrate 12 is immersed in an electroplating solution, and an electric current is passed through the seed layer 251 to deposit plating on the seed layer 251. In this way, a through electrode 25 including the seed layer 251 and the plating layer 252 is formed in the through hole 15.

[0096] Next, a semiconductor element placement process is carried out. In the semiconductor element placement process, the semiconductor element 40 is placed in the second recess 22. The semiconductor element placement process may include an adhesive layer formation process and a placement process.

[0097] In the adhesive layer formation process, as shown in Figure 14, an adhesive layer 45 is formed at the bottom 222 of the second recess 22. The adhesive layer 45 is formed, for example, by applying a solution containing the material of the adhesive layer 45 to the bottom 222 of the second recess 22. The solution contains, for example, a resin material and a curing agent that constitute the adhesive layer 45. The solution may further contain a solvent.

[0098] In the placement step, the semiconductor element 40 is placed on the adhesive layer 45 as shown in Figure 15. The semiconductor element 40 may be placed on the adhesive layer 45 before it is cured. The placement step may include a curing step in which the adhesive layer 45 is cured after the semiconductor element 40 has been placed on the adhesive layer 45. In the curing step, a trigger is applied to the adhesive layer 45 so that the curing agent contained in the adhesive layer 45 generates radicals or cations. For example, the adhesive layer 45 may be heated. For example, the adhesive layer 45 may be irradiated with light. The light may be ultraviolet light, for example. As the adhesive layer 45 cures, the lower surface 42 of the semiconductor element 40 and the bottom 222 of the second recess 22 are bonded together via the adhesive layer 45.

[0099] Subsequently, a redistribution layer formation process is carried out. In the redistribution layer formation process, a redistribution layer 30 is formed on the core substrate 12. More specifically, a first redistribution layer 31 is formed on the first surface 13 of the core substrate 12, and a second redistribution layer 36 is formed on the second surface 14 of the core substrate 12.

[0100] In the redistribution layer formation process, first, as shown in Figure 16, an insulating layer 32 is formed on the first surface 13 of the core substrate 12. The insulating layer 32 may be formed in the first recess 21 and the second recess 22. The insulating layer 32 may be filled into the first recess 21 and the second recess 22. That is, the insulating layer 32 may fill the first recess 21 and the second recess 22 without any gaps. The insulating layer 32 may be formed to cover the semiconductor element 40. Also, as shown in Figure 16, an insulating layer 37 is formed on the second surface 14 of the core substrate 12.

[0101] Next, as shown in Figure 17, an opening 321 is formed in the insulating layer 32. If the material of the insulating layer 32 is photosensitive, the opening 321 may be formed in the insulating layer 32 by exposure and development. Alternatively, the opening 321 may be formed in the insulating layer 32 by partially etching the insulating layer 32. Also, as shown in Figure 17, an opening 371 is formed in the insulating layer 37. If the material of the insulating layer 37 is photosensitive, the opening 371 may be formed in the insulating layer 37 by exposure and development. Alternatively, the opening 371 may be formed in the insulating layer 37 by partially etching the insulating layer 37.

[0102] Next, a conductive layer 33 is formed. For example, a via 34 is formed in the opening 321, and wiring 35 is formed on the insulating layer 32. As a result, the first rewiring layer 31 shown in Figure 2 is obtained. Then, a conductive layer 38 is formed. For example, a via 39 is formed in the opening 371. As a result, the second rewiring layer 36 shown in Figure 2 is obtained.

[0103] In this way, a semiconductor package 10 as shown in Figure 2 is obtained.

[0104] Figure 18 is a cross-sectional view showing an enlarged view of the recess 20' of the semiconductor package 10' according to the comparative example. As shown in Figure 18, the semiconductor package 10' according to the comparative example includes a recess 20' formed on the first surface 13' of the core substrate 12'. In the semiconductor package 10' according to the comparative example, unlike the semiconductor package 10 according to this embodiment described above, the recess 20' is composed of a single recess. The recess 20' includes a side wall portion 21' and a bottom portion 22'. The semiconductor element 40' is placed in the bottom portion 22' of the recess 20'.

[0105] The recess 20' is formed by wet etching the first surface 13'. The recess 20' is formed deep enough to accommodate the semiconductor element 40'. Here, since wet etching is isotropic etching, when the recess 20' is formed deep enough to accommodate the semiconductor element 40', the width W' of the recess 20' also widens due to side etching (see Figure 18). As a result, the planar area of ​​the recess (area in plan view) may become unnecessarily large. Consequently, it may be required to secure a large area for the recess 20' on the core substrate 12'.

[0106] In contrast, according to this embodiment, the core substrate 12 includes a first recess 21 located on the first surface 13 and a second recess 22 located at the bottom 212 of the first recess 21, and the semiconductor element 40 is located in the second recess 22. By forming these two recesses, it is possible to secure the depth for arranging the semiconductor element 40 while suppressing the widening of the recess 20. Therefore, the planar area of ​​the recess 20 can be reduced.

[0107] The embodiment described above can be modified in various ways. Modifications will be described below with reference to the drawings as needed. In the following description and the drawings used therein, parts that can be configured similarly to the embodiment described above will be given the same reference numerals as those used for the corresponding parts in the embodiment described above. Duplicate explanations will be omitted. If it is clear that the effects and advantages obtained in the embodiment described above can also be obtained in the modification, that explanation may be omitted.

[0108] (First variation) Figure 19 is a cross-sectional view showing a semiconductor package 10 according to a first modification. The first redistribution layer 31 may include a plurality of wiring layers stacked in a third direction D3. For example, as shown in Figure 19, the first redistribution layer 31 may include a first wiring layer 311 and a second wiring layer 312 located on the first wiring layer 311. The first wiring layer 311 and the second wiring layer 312 may each include an insulating layer 32 and a conductive layer 33. Each insulating layer 32 may include an opening 321. Each conductive layer 33 may include a via 34. The vias 34 may be located in each of the openings 321 of the plurality of insulating layers 32.

[0109] The second redistribution layer 36 may include a plurality of wiring layers stacked in the third direction D3. For example, as shown in Figure 19, the second redistribution layer 36 may include a first wiring layer 361 and a second wiring layer 362 located on the first wiring layer 361. The first wiring layer 361 and the second wiring layer 362 may each include an insulating layer 37 and a conductive layer 38. Each insulating layer 37 may include an opening 371. Each conductive layer 38 may include a via 39. The vias 39 may be located in each of the openings 371 of the plurality of insulating layers 37.

[0110] (Second variation) Figure 20 is an enlarged cross-sectional view showing a through-electrode 25 of a semiconductor package 10 according to a second modification. The through-electrode 25 may be configured to partially close the through-hole 15. For example, as shown in Figure 20, the through-electrode 25 may include a wall portion 253 and a closing portion 254. The wall portion 253 is the portion that extends along the wall surface 16. The closing portion 254 is the portion that closes the through-hole 15 in part of the through-hole 15.

[0111] The closing portion 254 may be located between the first surface 13 and the second surface 14 in the third direction D3. The closing portion 254 may be located in the central part between the first surface 13 and the second surface 14 in the third direction D3. The resin material 26 may be located in the space between the closing portion 254 and the first surface 13, and in the space between the closing portion 254 and the second surface 14. The resin material 26 may fill these spaces. That is, the resin material 26 may fill these spaces without any gaps. The resin material 26 may contain the same material as the insulating layer 32.

[0112] (Third variation) Figure 21 is a cross-sectional view showing a semiconductor package 10 according to a third modification. As shown in Figure 21, the core substrate 12 may include a through hole 15 that penetrates the core substrate 12 from the bottom 222 of the second recess 22 to the first surface 13. A through electrode 25 may be located in this through hole 15. The through electrode 25 is electrically connected to the conductive layers 33, 38. Although not shown, the core substrate 12 may further include a through hole 15 that penetrates the core substrate 12 from the first surface 13 to the second surface 14. A through electrode 25 may also be located in this through hole 15.

[0113] In the manufacturing method of the semiconductor package 10 according to this modified example, the through-hole formation step is performed after the recess formation step. In the through-hole formation step, a through-hole 15 is formed in the core substrate 12, penetrating the core substrate 12 from the bottom 222 of the second recess 22 to the first surface 13. In the through-hole formation step, further through-holes 15 may be formed penetrating the core substrate 12 from the first surface 13 to the second surface 14. In the through-electrode formation step, through-electrodes 25 are formed in these through-holes 15, electrically connected to the conductive layers 33 and 38.

[0114] (Fourth variation) Figure 22 is a cross-sectional view showing a semiconductor package 10 according to a fourth modification. As shown in Figure 22, the core substrate 12 does not have to include through holes 15. That is, the core substrate 12 does not have to have through holes 15. Also, the redistribution layer 30 does not have to include a second redistribution layer 36. That is, the second surface 14 of the core substrate 12 does not have to have a wiring layer formed thereon.

[0115] (Examples of products that incorporate semiconductor packages) Figure 23 shows an example of a product in which the semiconductor package 10 is mounted. The semiconductor package 10 may be used in a variety of products. For example, the semiconductor package 10 is mounted in a notebook personal computer 110, a tablet terminal 120, a mobile phone 130, a smartphone 140, a digital video camera 150, a digital camera 160, a digital clock 170, a server 180, etc.

[0116] Although several modifications of the above-described embodiment have been explained, it is naturally possible to combine multiple modifications as appropriate and apply them to the above-described embodiment. [Explanation of Symbols]

[0117] 10 Semiconductor Packages 12 Core board 13 Page 1 14 Side 2 15 Through holes 20 recesses 21 First recess 211 Side wall section 212 Bottom 213 First end 214 Second end 22 Second recess 221 Side wall section 222 Bottom 223 Third end 224 4th end 25 Through electrode 30 Redistribution layer 31 1st redistribution layer 32 Insulating layer 33 Conductive layer 36 2nd redistribution layer 37 Insulating layer 38 Conductive layer 40 Semiconductor elements 45 Adhesive layer

Claims

1. A semiconductor package, A core substrate including a first surface and a second surface located on the opposite side of the first surface, The core substrate comprises a semiconductor element mounted on the core substrate, The core substrate includes a first recess located on the first surface and a second recess located at the bottom of the first recess. The semiconductor element is a semiconductor package located in the second recess.

2. The semiconductor package according to claim 1, wherein the semiconductor element is located from the second recess to the first recess.

3. The semiconductor package according to claim 1, wherein the depth of the second recess is smaller than the depth of the first recess.

4. The semiconductor package according to claim 1, wherein the depth of the first recess is 20 μm or more and 200 μm or less.

5. The semiconductor package according to claim 1, wherein the depth of the second recess is 2 μm or more and 20 μm or less.

6. The side wall portion of the first recess includes a first end located on the side of the first surface and a second end located on the side of the bottom, The semiconductor package according to claim 1, wherein the angle of inclination of the straight line connecting the first end and the second end with respect to the first plane is 45 degrees or more and 85 degrees or less.

7. The semiconductor package according to claim 1, wherein the core substrate is a glass substrate.

8. The semiconductor package according to claim 1, comprising a wiring layer located on the first surface, the wiring layer including an insulating layer and a conductive layer electrically connected to the semiconductor element.

9. The core substrate includes through holes that penetrate the core substrate from the first surface to the second surface. The semiconductor package according to claim 8, wherein a through electrode electrically connected to the conductive layer is located in the through hole.

10. The core substrate includes a through hole that penetrates the core substrate from the bottom of the second recess to the second surface. The semiconductor package according to claim 8, wherein a through electrode electrically connected to the conductive layer is located in the through hole.

11. The semiconductor package according to claim 8, wherein the semiconductor element is covered with the insulating layer.

12. The semiconductor package according to claim 1, wherein an adhesive layer is located between the semiconductor element and the bottom of the second recess.

13. A core substrate on which semiconductor elements are mounted, Page 1 and, The second surface is located on the opposite side from the first surface, The first recess located on the aforementioned first surface, A core substrate comprising a second recess located at the bottom of the first recess, the second recess on which the semiconductor element is arranged.

14. A method for manufacturing semiconductor packages, A step of preparing a core substrate including a first surface and a second surface located on the opposite side of the first surface, A step of forming a first recess on the first surface by wet etching, A step of forming a second recess at the bottom of the first recess by wet etching, A method for manufacturing a semiconductor package, comprising the step of arranging a semiconductor element in the second recess.

15. A method for manufacturing a semiconductor package according to claim 14, comprising the step of forming a wiring layer on the first surface, the wiring layer including an insulating layer and a conductive layer electrically connected to the semiconductor element.

16. The process of forming a through hole in the core substrate that penetrates the core substrate from the first surface to the second surface, A method for manufacturing a semiconductor package according to claim 15, comprising the step of forming a through-hole in which an electrode electrically connected to the conductive layer is formed.

17. The process of forming a through hole in the core substrate that penetrates the core substrate from the bottom of the second recess to the second surface, A method for manufacturing a semiconductor package according to claim 15, comprising the step of forming a through-hole in which an electrode electrically connected to the conductive layer is formed.

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