Method for receiving bit 1 and bit 0 signals transmitted from LTE and WiMAX base stations via microcarrier phase modulation on a mobile terminal.

Abstract

This invention provides a receiving method for a mobile terminal that enables high-speed transmission of microwave wireless communication. [Solution] The method is a method for receiving bit 1 and bit 0 signals of transmitted data or packets, which are transmitted by microwave carrier phase modulation sent from an LTE or WiMAX base station, where the signal consists of L (L: natural number) wavelengths of positive-phase carrier followed by (mL) (m: natural number) wavelengths of inverse-phase carrier, with bit 1 of the transmitted data, and (m) wavelengths of positive-phase carrier, with bit 0 of the transmitted data. The method includes a synchronous counter that counts up to (m)*J with a clock that is J times the carrier frequency clock. If an event occurs within the carrier m wavelength period where the time difference between peaks of the received microwave wavelength amplitude is 1.5 carrier wavelengths, the method determines that bit 1 of the received data occurs when the event occurs, sets all flip-flops of the synchronous counter to all bits 0, and synchronizes the clock with the received data.

Description

[Technical Field]

[0001] This invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microcarrier phase modulation from a fading-resistant LTE or WiMAX base station, which does not use OFDMA, to a mobile terminal.

[0002] Conventional LTE handover (Non-Patent Documents 1 and 2) involved selecting a wireless channel and then transmitting data packets, similar to IEEE 802.11b handover. Access from mobile nodes to LTE base stations was transmitted via CSMA / CD, resulting in delays due to collisions. Consequently, the number of mobile terminals that could switch LTE stations was limited. After switching, communication occurred within the allocated time slot of the channel, eliminating collisions like those in CSMA / CD, and the channel limit was determined solely by speed. The OFDMA described in Non-Patent Document 1 does not generate relatively high harmonics because the time frame for performing the FFT is long. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] M. Vijayalakshmi, et al. “A Cross Layer Scheduling Algorithm in IEEE 802.16e WiMAX Standard to Support RTPS Traffic Class”, 2014 fourth International Conference on Communication Systems and Network Technologies, 07-09 April 2014 [Non-Patent Document 2] RFC5270, ``Mobile IPv6 Fast handovers over 802.16e networks,'' [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Non-patent documents 1 and 2 are robust against fading due to the integration effect of the FFT, but when a mobile terminal accesses a new base station, they use CSMA / CD for L2 handover LTE access, resulting in a large handover delay. OFMDA in Non-patent document 1 has the drawback that when the mobile terminal moves at high speed, the sampling points for the FFT cannot be determined, leading to errors. Also, when there are many subcarriers, the computational complexity of the FFT increases. Furthermore, since only 2 bits can be transmitted per 20MHz subcarrier, it has the drawback of not being able to transmit high-speed bits. In addition, it has the drawback that the boundaries of the FFT window frame on the mobile terminal are difficult to determine. Moreover, when multiplexed on the time axis with IFFT, the peak positions of the subcarrier signals are different and do not cancel each other out, but points other than the peaks are canceled out, so if the sampling position of the signal after low-pass filtering on the receiving side is shifted from the peak position, the S / N ratio will decrease.

[0005] The object of the present invention is to provide a microwave 10 signal transmission method that is resistant to fading, which involves phase-modulating a continuous carrier wave of microwaves, sending it to a mobile terminal, and reconstructing the data at the receiving end without using FFT. [Means for solving the problem]

[0006] The present invention has been made in view of the problems of the prior art described above, and the means of the present invention are shown from the first and 21st aspects of the present invention. A first aspect of the present invention is a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station, using bit 1 and bit 0, wherein the transmitted data or packet is transmitted using bit 1 and bit 0, wherein the transmitted data is transmitted using bit 1 and bit 0, where bit 1 is a signal consisting of L (L: natural number) wavelengths of microwave carrier wave followed by (mL) (m: natural number) wavelengths of carrier wave wave in opposite phase to the L wavelength signals, and bit 0 is a signal consisting of (m) wavelengths of carrier wave wave in phase with the L wavelength signals. This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station via microwave carrier phase modulation is characterized by determining that received data bit 1 has been received when the time difference between peaks of the amplified microwave signal received by the antenna is equal to 1.5 carrier wavelengths and this event occurs within the carrier m wavelength period, and determining that received data bit 0 has been received when the time difference between peaks is equal to 1.5 carrier wavelengths and this event does not occur within the carrier m wavelength period.

[0007] A second aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation as described in the first aspect of the present invention, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that, if an event in which the time difference between peaks of the wavelength amplitude is 1.5 wavelengths of the carrier wave occurs within the carrier wave m wavelength period, then the peak position in which the time difference between peaks of the wavelength amplitude is approximately 1.5 wavelengths is characterized when there are ((m-2)+L) or more peaks in which the time difference between peaks of the wavelength amplitude is approximately 1 wavelength between two peak detection positions in which the time difference between peaks of the wavelength amplitude is approximately 1.5 wavelengths.

[0008] A third aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station as described in the first aspect of the present invention, If an event occurs within the carrier wave m wavelength period where the time difference between peaks of the aforementioned wavelength amplitude is 1.5 wavelengths of the carrier wave, a self-operating synchronous counter, which counts up to (m)*J with a clock that is J times the carrier frequency clock and outputs an output clock with the count value Y, is used when there is no clear signal input. Approximately 1.5 wavelengths after detecting a positively convex voltage peak of the wavelength amplitude at the output of a one-stage or two-stage amplifier of the microwave received by the antenna, if there is a positively convex peak in the wavelength amplitude value, the number of wavelength amplitude peaks ((m-2)+L) or more where the time interval between detecting a positively convex voltage peak of the wavelength amplitude at the output of the one-stage or two-stage amplifier is approximately 1.5 wavelengths is counted before a peak of approximately 1.5 wavelengths is detected. This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that, when a subsequent peak point with a time difference between wavelength peaks of approximately 1.5 wavelengths is reached, all flip-flops of the synchronization counter are set to 0, and all flip-flops of the second m*J counter are set to 0, and when the counter value of the second m*J counter is near m*J and a peak in wavelength amplitude is detected, all flip-flops of the synchronization counter are set to 0, and all flip-flops of the second m*J counter are set to 0 to obtain the synchronization clock of the received data as the output clock, and the received data is determined to be bit 1.

[0009] A fourth aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station as described in the first aspect of the present invention, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that, if the event in which the time difference between peaks of the wavelength amplitude is 1.5 carrier wavelengths occurs within the carrier m wavelength period, the amplifier output voltage half a carrier wavelength before the detection time position where the time difference between peaks of the wavelength amplitude is 1.5 carrier wavelengths is near 0V or less.

[0010] A fifth aspect of the present invention is a method for a mobile terminal to receive bit 1 and bit 0 signals by microwave carrier phase modulation transmitted from the LTE or WIMAX base station described in the first aspect of the present invention. In this method, when an event where the time difference between the peaks of the wavelength amplitude is 1.5 wavelengths of the carrier wave is within the m wavelength period of the carrier wave, a self-running synchronous counter that counts up to (m)*J at a clock that is J times the carrier wave frequency clock and outputs an output clock with a count value Y is provided. When there is no signal input set to all bits 0, from the detection of a positive convex voltage peak of the wavelength amplitude of the output of the one-stage or two-stage amplifier of the microwave received by the antenna, when the wavelength amplitude of the output of the one-stage or two-stage amplifier is near 0V after a delay of approximately one wavelength, and when there is an event where there is a peak convex to the positive of the wavelength amplitude value after a delay of approximately 1.5 wavelengths from the detection of the positive convex voltage peak of the wavelength amplitude of the output of the one-stage or two-stage amplifier, it is determined as bit 1 of the received data, and all flip-flops of the synchronous counter are set to all bits 0. The received data clock is obtained as the output clock, and it is characterized in that it is a case where it is determined as bit 1 of the received data. This is a method for a mobile terminal to receive bit 1 and bit 0 signals by microwave carrier phase modulation transmitted from an LTE or WIMAX base station.

[0011] A sixth aspect of the present invention is a method for a mobile terminal to receive bit 1 and bit 0 signals by microwave carrier phase modulation transmitted from the LTE or WIMAX base station described in the fifth aspect of the present invention. In this method, When the event does not occur for a certain period of time, all flip-flops of the synchronous counter are set to all bits 0 by an AND signal between the Q output of the set - reset flip - flop set at that time and the signal when the event occurs, and the set - reset flip - flop is reset by a delayed signal of the AND signal. Thereafter, when the NOT signal of the Q output of the set - reset flip - flop, the signal when the event occurs, and the counter value of the synchronous counter are within the specified range, all flip - flops of the synchronous counter are set to all bits 0, and the set - reset flip - flop is reset by the delayed signal of the AND signal, so as to obtain the clock of the received data as the output clock and determine that it is bit 1 of the received data. A receiving method for a mobile terminal of bit 1 and bit 0 signals by microwave carrier phase modulation transmitted from an LTE, WIMAX base station is characterized by the above.

[0012] The seventh aspect of the present invention is in the receiving method for a mobile terminal of bit 1 and bit 0 signals by microwave carrier phase modulation transmitted from an LTE, WIMAX base station as described in the sixth aspect of the present invention, When synchronization of the packet created from the received data cannot be achieved, the set - reset flip - flop is set to the set state. A receiving method for a mobile terminal of bit 1 and bit 0 signals by microwave carrier phase modulation transmitted from an LTE, WIMAX base station is characterized by the above.

[0013] The eighth aspect of the present invention is in the receiving method for a mobile terminal of bit 1 and bit 0 signals by microwave carrier phase modulation transmitted from an LTE, WIMAX base station as described in the first aspect of the present invention, The system includes a self-operating synchronous counter that, when there is no signal input to set all bits to 0, counts up to (m)*J with a clock that is J times the carrier frequency clock, and outputs an output clock with the count value Y, when the event in which the time difference between peaks of the wavelength amplitude is 1.5 wavelengths of the carrier wave occurs within the period of the carrier wave m wavelength, and sets all bits to 0. At t1,i, when a positively convex voltage peak of the amplitude of the first L consecutive carrier waves is detected after the guard time at the output of the one-stage or two-stage amplifier of the microwave received by the antenna, all flipflops of the counter that outputs the 1.5 wavelength counter value are set to all bits. The steps include setting the clock to 0, and if a positively convex peak in the wavelength amplitude value is detected approximately (1.5) wavelengths after the peak detection position, clearing all flipflops of the synchronous counter and setting all flipflops of the second m*J counter to all bits 0; if the counter value of the second m*J counter is within the range of m*J-α to β and a positively convex peak in the wavelength amplitude value, setting all flipflops of the synchronous counter to all bits 0, obtaining the clock of the received data as the output clock of the synchronous counter, and determining that bit 1 of the received data is... A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, characterized in that the method includes a step of determining that bit 1 of the received data is bit 0 of the received data if bit 1 is not at the output clock position.

[0014] The ninth aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station as described in any third, fifth, or eighth aspect of the present invention, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that, when a positively convex voltage peak of the amplitude of the carrier wavelength is detected, the capacitor output signal of the bandpass LCR filter of the signal received by the antenna after the guard time is applied as Vin to the positive input terminal of the operational amplifier, the ground voltage is applied to the negative input terminal of the operational amplifier via resistor R1, and a resistor R2 is used between the negative input terminal and the output of the operational amplifier, and the output voltage of a single-stage amplifier configured to increase R2 / R1 is (Vin-0v)*R2 / R1+Vin, and the voltage of the signal obtained by delaying the signal, which is initially simply the amplitude value of the first L wavelength signals, by a delay line or delay circuit for a certain period of time after the guard time, changes from a state where the voltage of the signal is lower than the voltage of the signal before the delay line or delay circuit to a state where it is higher than the voltage of the signal before the delay line or delay circuit, which is defined as t1,i (i: current position).

[0015] A tenth aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station as described in any third, fifth, or eighth aspect of the present invention, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier amplitude modulation is characterized in that, when a positive voltage peak of the amplitude of the L-th wavelength of the carrier wave is detected, the voltage of the LCR capacitor grounded to the ground of the LCR resonator of the signal received by the antenna after the guard time is applied to the gate of the NMOS of the first-stage amplifier with a 0 bias voltage, the drain output of the NMOS is directly connected to the gate of the PMOS of the second-stage amplifier, the drain of the PMOS transistor is connected to ground via a drain resistor, and the voltage at the drain connection point is at the position t1,i (i: current position) when the voltage of the signal, which is initially simply the amplitude value of the first L wavelength signals, is delayed for a certain period of time by a delay line or delay circuit, changes from a state where it is lower to a state where it is higher than the voltage of the signal before the delay line or delay circuit.

[0016] An eleventh aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station as described in any third, fifth, or eighth aspect of the present invention, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier amplitude modulation is characterized in that, when detecting a positive voltage peak in the amplitude of the L-th wavelength of the L continuous carrier waves, the voltage of the LCR capacitor grounded to the ground of the LCR resonator of the signal received by the antenna after the guard time is added to the source of the npn transistor of the first-stage amplifier with a 0 bias voltage, the collector output of the npn transistor is directly connected to the gate of the PMOS of the second-stage amplifier, the drain of the PMOS transistor is connected to ground via a drain resistor, and the voltage at the drain connection point is at the position t1,i (i: current position) when the voltage of the signal, which is initially simply the amplitude value of the first L wavelength signals, is delayed for a certain period of time by a delay line or delay circuit, changes from a state where it is lower to a state where it is higher than the voltage of the signal before the delay line or delay circuit.

[0017] A twelfth aspect of the present invention is a method for synchronizing the clock of a mobile terminal using bit 1 and bit 0 signals of microwave carrier phase modulation, wherein bit 1 of the transmitted data consists of a signal in which L (L: a natural number) wavelengths of microwave carrier waves are followed by (mL) (m: a natural number) wavelengths of carrier waves in opposite phase to the L wavelength signals, and bit 0 of the transmitted data consists of a signal in which L wavelengths of carrier waves in phase to the L wavelength signals, and the method includes a synchronization counter that counts up to (m)*J with a clock that is J times the carrier frequency clock and outputs an output clock with a count value Y, and which operates autonomously when there is no set signal input for all bits 0, and the one-stage amplifier or two-stage amplifier that receives microwaves from an LTE, WiMAX base station to a mobile terminal, wherein the one-stage amplifier detects a voltage peak with a positive convex amplitude of the wavelength of the output of the microwaves received by the antenna, with a delay of approximately 1 wavelength from the time of detection of the positive convex voltage peak of the wavelength amplitude of the output of the one-stage amplifier Alternatively, if the amplitude of the wavelength of the output of the two-stage amplifier is near 0V, and there is an event where there is a positively convex peak in the wavelength amplitude value approximately 1.5 wavelengths after the detection of a positively convex voltage peak in the wavelength amplitude of the output of the one-stage or two-stage amplifier, then it is determined to be bit 1 of the received data. If the event does not occur for a certain period of time, the entire flip-flop of the synchronous counter is set to all bits 0 by an AND signal of the Q output of the set reset flip-flop and the signal when the event occurs, and the set reset flip-flop is reset by the delay signal of the AND signal. Thereafter, if the NOT signal of the Q output of the set reset flip-flop, the signal when the event occurs, and the counter value of the synchronous counter are within the specified range, the entire flip-flop of the synchronous counter is set to all bits 0, and the set reset flip-flop is reset by the delay signal of the AND signal. This method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that the clock of the received data is obtained as the output clock, and the received data is determined to be bit 1.

[0018] A thirteenth aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station as described in any third, fifth, or eighth aspect of the present invention, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that the counter value Y of the output clock output at the aforementioned counter value Y is ((m*J-2*J).

[0019] A fourteenth aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE, WiMAX base station as described in any of the first, third, fifth, or eighth aspects of the present invention, for a mobile terminal, The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that J is 8.

[0020] A fifteenth aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE, WiMAX base station as described in any of the first, third, fifth, or eighth aspects of the present invention, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that m is 4 and L is 2.

[0021] A sixteenth aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted by microwave carrier phase modulation from an LTE, WiMAX base station as described in any of the first, third, fifth, or eighth aspects of the present invention, for a mobile terminal, This method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that L is 3 and m is 5.

[0022] A seventeenth aspect of the present invention relates to a method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station using microwave carrier phase modulation, as described in the 12th aspect of the present invention, This method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that the counter value Y of the output clock output with the aforementioned counter value Y is ((m*J-2*J).

[0023] The eighteenth aspect of the present invention relates to a method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station using microwave carrier phase modulation as described in the 12th aspect of the present invention, The method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that J is 8.

[0024] A 19th aspect of the present invention relates to a method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station using microwave carrier phase modulation, as described in 12 of the present invention. This method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that m is 4 and L is 2.

[0025] A 20th aspect of the present invention relates to a method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station using microwave carrier phase modulation, as described in 12 of the present invention, This method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation is characterized in that L is 3 and m is 5.

[0026] A 21st aspect of the present invention relates to a method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation as described in the 8th aspect of the present invention, The guard time is characterized in that the output of the second amplifier is 0V when no event is detected for a certain period of time in which the time difference between peaks of wavelength amplitude is 1.5 wavelengths of the carrier wave, or when the time difference between peaks of wavelength amplitude remains approximately 1 wavelength of the carrier wave for a certain period of time, or when there is no carrier wave antenna reception signal for a certain period of time. This is a method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation. [Effects of the Invention]

[0027] As described above, the present invention provides a method for receiving data 1 and data 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station, comprising an oscillator A that generates a microwave sine carrier and an oscillator B that generates an inverse sine carrier, and after a guard time or without a guard time, after L (L: natural number) consecutive wavelengths of the carrier wave from oscillator A, a signal of (mL) (m: natural number) consecutive wavelengths of the inverse carrier wave from oscillator B is used as bit 1 of the transmitted data, and a signal of (m) consecutive wavelengths of the carrier wave from oscillator A is used as bit 0 of the transmitted data, and after a delimiter beginning with bit 1, bit 0, bit 1, the transmitted data or fixed-length frame is transmitted, and the method provides a method for receiving data 1 and data 0 signals transmitted by microwave carrier phase modulation from an LTE or WiMAX base station, wherein if there is a peak in the wavelength amplitude value approximately 1.5 wavelengths after a delay of about 1.5 wavelengths from the time detection of the peak of the wavelength amplitude of the output of a one-stage or two-stage amplifier of microwaves received by the antenna, the next position where the time difference between peaks of wavelength amplitude is approximately 1.5 wavelengths Before detecting the peak of the wavelength amplitude, if the number of wavelength amplitude peaks with a time difference between peaks of approximately 1 wavelength is ((m-2)+L) or more, when detecting a peak with a time difference between peaks of approximately 1.5 wavelengths, all flipflops of a synchronous counter that counts up with an m*J clock are set to all bits 0, and all flipflops of a second m*J counter are set to all bits 0. If there is a positively convex peak of wavelength amplitude within the lock range value near the m*J counter value of the output of the m*J counter that outputs the lock range value of the second m*J counter, all flipflops of the synchronous counter are set to all bits 0, the clock of the received data is obtained as the output clock, and the received data is determined to be bit 1. This method has the advantage that, whether or not there is a guard time, synchronization can be restored with a signal consisting of bits 1, 0, and 1 of the transmitted data when the received data is out of sync. Furthermore, since the first-stage amplifier receives the voltage of the LCR capacitor that integrates the current from the antenna voltage source to the LCR filter, even if a fading signal is applied, the peak voltage position at the peak detection point will have only one peak, although there will be a slight phase shift. This method has the advantage of being resistant to fading. It also has the advantage of enabling high-speed bit transmission. [Brief explanation of the drawing]

[0028] [Figure 1] This figure illustrates an example of a microwave phase-modulated transmission circuit that transmits bit 1 of transmission data with different microwave frequencies for each base station, transmitted from an LTE (WiMAX) station according to the first embodiment of the present invention, using a positive-phase digital sine carrier generation circuit A and an inverted-phase digital sine carrier generation circuit B. [Figure 2] This figure illustrates an example of a microwave phase-modulated transmission circuit that transmits bit 1 of transmission data with a different microwave frequency for each base station, transmitted from an LTE (WiMAX) station according to the first embodiment of the present invention, using an analog sine carrier generation circuit and a 1 / 2 wavelength delayed coaxial cable. [Figure 3] This figure illustrates an example of a receiving circuit for a mobile terminal that receives bit 1 of transmission data with a different microwave frequency for each base station, transmitted from an LTE (WiMAX) station according to the first embodiment of the present invention. [Figure 4] This figure illustrates an example of the input signal operation of the first-stage amplifier of the receiving circuit of a mobile terminal that receives bit 1 of transmission data with a different microwave frequency for each base station transmitted from an LTE (WiMAX) station according to the first embodiment of the present invention. [Figure 5] This figure illustrates an example of a receiving circuit for a mobile terminal that receives bit 1 of transmission data with a different microwave frequency for each base station, transmitted from an LTE (WiMAX) station according to the first embodiment of the present invention. [Figure 6] This figure illustrates an example of the operation of receiving data playback using a synchronous counter synchronized with the received data clock, which receives signals that have passed through different wavelength filters for each microfrequency received by the antenna of the first embodiment of the present invention. [Figure 7] This figure illustrates an example of operational amplifier operation in which the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of the microwave receiving circuit of a mobile terminal in the first embodiment of the present invention is set to the point in time when the output signal changes from a negative voltage to a positive voltage by delaying the input signal of the operational amplifier. [Figure 8]This figure illustrates an example of operational amplifier operation in which the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of the microwave receiving circuit of a mobile terminal in the first embodiment of the present invention is set to the point in time when the output signal changes from a negative voltage to a positive voltage by delaying the input signal of the operational amplifier. [Figure 9] A diagram illustrating an example of the operation of two comparators to determine the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of the microwave receiving circuit of a mobile terminal in the first embodiment of the present invention. This position is determined by delaying the input signals of the two comparators and delaying one of the two resulting output signals, so that both signals change from a negative voltage to a positive voltage. [Figure 10] This figure illustrates an example of the operation of receiving data playback using a synchronous counter synchronized with the received data clock, which receives signals that have passed through different wavelength filters for each microfrequency received by the antenna of the second embodiment of the present invention. [Figure 11] This figure illustrates an example of operational amplifier operation in which the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of the microwave receiving circuit of a mobile terminal in a second embodiment of the present invention is set to the point in time when the output signal changes from a negative voltage to a positive voltage by delaying the input signal of the operational amplifier. [Figure 12] This figure illustrates an example of operational amplifier operation in which the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of the microwave receiving circuit of a mobile terminal in a second embodiment of the present invention is set to the point in time when the output signal changes from a negative voltage to a positive voltage by delaying the input signal of the operational amplifier. [Figure 13] A diagram illustrating an example of the operation of two comparators to determine the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of a microwave receiving circuit in a mobile terminal of the second embodiment of the present invention. This position is determined by delaying the input signals of the two comparators and delaying one of the two resulting output signals, so that both signals change from a negative voltage to a positive voltage. [Figure 14]This figure illustrates an example of operational amplifier operation in which the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of the microwave receiving circuit of a mobile terminal in the third embodiment of the present invention is set to the point in time when the output signal changes from a negative voltage to a positive voltage by delaying the input signal of the operational amplifier. [Figure 15] This figure illustrates an example of operational amplifier operation in which the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of the microwave receiving circuit of a mobile terminal in the third embodiment of the present invention is set to the point in time when the output signal changes from a negative voltage to a positive voltage by delaying the input signal of the operational amplifier. [Figure 16] A diagram illustrating an example of the operation of two comparators to determine the maximum voltage time position of the input wavelength amplitude for peak detection of the wavelength amplitude of a microwave receiving circuit in a mobile terminal of the third embodiment of the present invention. This position is determined by delaying the input signals of the two comparators and delaying one of the two resulting output signals, so that both signals change from a negative voltage to a positive voltage. [Modes for carrying out the invention]

[0029] A first embodiment of the present invention will be explained with reference to Figures 1, 2, 3, 4, 5, 6, 7, 8, and 9. First, the microwave transmission circuit of the LTE station in Figure 1 of Example 1 will be described. In Figure 1, 215-1 is a digital sine carrier oscillator A, 215-2 is an inverse-phase digital sine carrier oscillator B, 223-3 is a circuit that outputs a high-level signal only between the two positive-phase wavelengths at the front of the four-carrier wavelength frame that transmits data bit 1 and between the four consecutive positive-phase carriers that transmit data bit 0, 223-4 is a circuit that outputs a high-level signal only between the two inverse-phase wavelengths at the rear of the four-carrier wavelength frame that transmits data bit 1, 222-2 is an AND circuit of the high output signal of 223-3 and the multi-level output of circuit 215-1, and 222-4 is the high output signal of 223-4 218 is a high-power emitter-follower npn bipolar transistor, 227 is a coaxial cable that transmits the signal to the antenna, 224 is a clock that is 8 times the carrier frequency, 225 is a 1 / 8 frequency divider, and 226 is the carrier frequency clock. After a guard time, multiple bits 1 are sent, then a delimiter consisting of repeating bits 1 and 0 is sent, and then the data is sent.

[0030] Next, the operation of Figure 1 will be explained. Digital sine wave generation memory circuits A and 215-1 repeatedly generate a single-wavelength digital sine wave. Digital sine wave generation memory circuits B and 215-2 repeatedly generate an inverted-phase digital sine wave. The AND circuit 222-2 sends the multi-level signals of the guard time and the two-wavelength interval of bit 1 and the four-wavelength interval of bit 0, excluding the two inverted-phase intervals of bit 1, to the adder circuit 234. The AND circuit 222-4 sends the multi-level signals of the guard time and the two inverted-phase intervals of bit 1, excluding the two-wavelength interval of bit 1 and the four-wavelength interval of bit 0, to the adder circuit 234. The multi-level adder circuit 234 sends the AC amplitude with the DC component of the bias voltage of transistor 218 added to it to the DA converter 235. The output of the DA converter 235 is directly input to the base of the high-power bipolar transistor 218 and supplied as the emitter output between the transmitting antenna and ground via coaxial cable 227. In some cases, bit 1 of the transmitted data is a signal consisting of three positive-sequence wavelengths followed by two negative-sequence wavelengths, and bit 0 of the transmitted data is a signal consisting of five positive-sequence wavelengths. This operation is the same as in Figure 1. In other cases, bit 1 of the transmitted data is a signal consisting of three positive-sequence wavelengths followed by one negative-sequence wavelength, and bit 0 of the transmitted data is a signal consisting of four positive-sequence wavelengths. This operation is the same as in Figure 1.

[0031] Next, Figure 2 shows the microwave transmission circuit of the LTE station in Example 1. Figure 2 differs from Figure 1 in that it uses an analog sine carrier generation circuit, whereas Figure 1 uses a digital sine carrier generation circuit. In Figure 3, 520 is a carrier oscillator, 522 and 523 are bipolar NPN transistors, 526 is a coaxial cable that delays the carrier wave by half a wavelength, 528 and 530 are analog switches, 524, 525 and 527 are NMOS transistors, 540 is a high-power bipolar NPN transistor, 141 is a coaxial cable for transmitting the signal to the antenna, 532 is a binary counter that counts up on the rising edge of the output signal of oscillator 520, 533 is a circuit that obtains the differential signals of the rising and falling edges of the output of circuit 532 and outputs a carrier frequency clock, 540 is a signal that switches on analog switch 528 for only the last two out-of-phase wavelengths of the four wavelengths indicating transmit data bit 1, and 541 is a signal that switches on analog switch 530 for only the first two wavelengths of the four wavelengths indicating transmit data bit 1 and for the four wavelength interval of transmit data bit 0.

[0032] Next, the circuit operation of Figure 2 will be explained. The oscillator's output signal is applied to the gate of NMOS524 as an inverted-phase carrier wave delayed by half a wavelength via analog switch 528 and coaxial cable 526. On the other hand, the oscillator's output signal is applied to the gate of NMOS525 as a carrier wave with no delay via analog switch 530. If the gate voltage of NMOS524 is v1 and the gate voltage of NMOS525 is v2, then a current of v1*gm + v2*gm flows through the gate resistor R of NMOS527, so the two signals are added together over time to obtain the gate voltage of NMOS527. When the analog switch is OFF, the ground voltage is applied to the gate through the resistor 150Ω. The bias resistors of NMOS524, 525, and 527 are not shown in the figure. The emitter output of NMOS527 is input to the biased base of the high-power transistor 540, so the output signal is supplied between the antenna and ground.

[0033] Next, FIG. 3 shows a receiving circuit for bit 1 and bit 0 signals of microwaves transmitted from the LTE and WiMAX base stations of the mobile terminal or tablet terminal of Example 1. In FIG. 3, 20 is an antenna, 21 is an NMOS transistor with an LCR resonance filter in front, 22 is a PMOS transistor, R20, R9, R10 are resistors, c20 is a capacitor, L20 is an inductance, 28 is another branch signal line, and 102 is an output signal from the drain voltage peak detection circuit of the PMOS transistor 22.

[0034] The operation of FIG. 3 will be described. The voltage of the capacitor C20 of the carrier frequency resonator composed of L20, R20, and C20 of the carrier wave received by the antenna 20 is input to the gate of the NMOS transistor 21. Here, the transient response of the LCR filter will be described using Laplace transform. Let the voltage source of the antenna received signal be v(t)=SIN(t), the impedance of the LCR filter be Z, and the current be I(t). If these relationships are expressed in Laplace transform, V(s)=I(s)*Z(s), I(S)=V(S) / Z(s)=1 / (S 2 +1)*S / (L*S 2 +R*S+1 / C). This can be expressed as (aS+b) / (S 2 +1)+(c1*S+d) / (L*S 2 +R*S+1 / C). By finding a, b, c1, and d, I(S)=C*S / (S 2 +1)+RC 2 / (S 2 +1)-C*S / (S 2 +R*S / L+1 / (L*C))+(R*C / L) / (S 2 +R*S / L+1 / (LC)). Here, S 2 +RS / L+1 / (LC)=(S+R / L) 2 +1 / (LC)-RS / L-(R / L) 2 and 1 / (LC)-RS / L-(R / L) 2 =1. Assuming that the term of RS / L is smaller than the others and can be ignored, it holds when C = L / R 2 . In this case, I(S)=C*S / (S 2 +1)+RC 2 / (S 2+1)-C*S / ((S+R / L) 2 +1)+(RC / L) / ((S+R / L) 2 +1) is obtained, and the inverse Laplace transform is I(t)=C*COS(t)+RC 2 *SIN(t)-C*e (-R / L)t *COS(t)+(RC / L)*e (-R / L)t *This becomes SIN(t). C = L / R 2 If you enter the condition, I(t) = C*COS(t) + RC 2 *SIN(t)-C*e (-1 / (CR))t *COS(t)+(1 / R)*e (-1 / (CR))t *SIN(t). The voltage across the capacitor can be found by integrating 1 / C*I(t), Vc = SIN(t) - RC*COS(t) + 1 / (1 / (CR)) 2 +1)* e (-1 / (CR))t * ((-1 / (CR)*COS(t)+SIN(t))+ 1 / (CR)*( 1 / (1 / (CR) 2 +1)* e (-1 / (CR))t * This becomes ((-1 / (CR)*SIN(t)-COS(t)). The second term on the right-hand side is multiplied by C, and the third term is (CR) 2 If the value of C is around pF, the second and third terms can be ignored, and although the fourth term is multiplied by CR, it cancels out with the 1 / (CR) before SIN(t), so -e (-1 / (CR))t *SIN(t) remains. Here, 1 / (CR)*t = 1 / ((10 (-12) *75)*1 / (2.4*10 9 ) = 5.6 * 1, where *1 is 1 wavelength and C = 10 (-12) ,R=75. 1 / R*e (-5.6*1) =4.95*10 (-5) Therefore, only the first term, SIN(t), remains after half a wavelength or one wavelength. This is the same as the voltage source of the antenna's received signal. Furthermore, the third and fourth terms of the above equation can be ignored when t is 2.4G half a wavelength or longer, even when using the Taylor expansion method, compared to the first term.

[0035] The drain of the NMOS transistor 21 is directly connected to the gate of the PMOS transistor 22. The drain voltage of the PMOS transistor is as shown in the waveform 102 in the figure. The output signal 102 becomes the output signal 102 to the peak detection circuit. A coupling capacitor may be used between the NMOS transistor and the PMOS transistor, but in that case DC balance is required, so a bias voltage must be applied to the NMOS transistor so that the AC signal oscillating up and down through the coupling capacitor can pass through. The drain voltage of the PMOS transistor is as shown in waveform 102 in the figure. In the two-wavelength section of data bit 1 after the guard time, only the positive voltage of the wavelength signal received by the antenna appears with a phase delay of 90 degrees across capacitor C20 (indicated as Vs2 in the figure). In the following two-wavelength section, since it is an inverse-phase carrier wave, only the latter half of the wavelength appears as a positive signal (indicated as Vr1 in the figure). The positive signal of the second wavelength in inverse phase lags the phase of the capacitor C20 by 90 degrees compared to the cos(t) of the current I(t) obtained by the Laplace transform above, resulting in a sine signal. However, since this signal is outside the resonant state of the LCR, its amplitude is attenuated. The exact voltage change across capacitor C20 is shown in Figure 4. Figure 4 shows the relationship between the signal 700 (V(t)=SIN(t)) received by the antenna, the current (I(t)=COS(t)), and the voltages 701 (SIN(t)) and 702 applied to the gate of the NMOS21 capacitor C20 due to the positive-sequence antenna received wavelength signal and the negative-sequence antenna received wavelength signal. 702 is the integral of (1 / C)*I(t), which is (1 / C)*∫I(t). Point P is the positively convex peak point of capacitor C20. At the transition points from the positive-sequence antenna received signal to the negative-sequence antenna received signal and from the negative-sequence antenna received signal to the positive-sequence antenna received signal, the P amplitude is attenuated by about half a wavelength by the LCR filter. The attenuation time varies depending on the LCR value. The time of 1.5 wavelengths indicated by the arrow 704 is the time difference from the peak point of the positive-sequence signal to the peak point of the negative-sequence signal. 706 indicates a positive-sequence two-wavelength interval, and 707 indicates an inverse-sequence (180-degree phase-shifted signal) two-wavelength interval. 703 indicates a bit 1 signal interval of transmitted data, and 708 indicates a bit 0 signal interval of transmitted data. The voltage across capacitor C20 due to the second wavelength signal in the inverse-sequence two-wavelength interval peaks (let's call it point Y) 90 degrees later than the antenna-received signal due to the capacitor's integrating effect. The latter half of this inverse-sequence second wavelength is a signal that is synchronous with the positive signal of the next positive-sequence wavelength, so it contains a DC component and may not be transmitted from the antenna's microwave receiving voltage source to the LCR filter. Alternatively, the signal may be attenuated because it deviates from the resonant state. This is because the LCR is a carrier frequency resonant circuit, and the antenna also has a resonant circuit element.To ensure that the resonance condition is not broken down by more than half a wavelength before or after the wavelength signal, the L and C values ​​of the LCR filter are selected to be small, around μH and pF, respectively. At point Y, a small peak appears if the mobile terminal is close to the base station, and does not appear if it is far from the base station. Therefore, the only point where clock synchronization is possible regardless of the distance from the base station is the point where the wavelength changes from positive-sequence to negative-sequence. In the figure, an example is shown where the voltage of the capacitor drops due to the discharge of charge from C20, and a peak is detected at point Y. However, in reality, the peak at point Y is attenuated, so the peak disappears at long distances. On the other hand, point 705 is the point where the peak is detected at a time position 1.5 wavelengths later than the peak detection point, and it is the signal that sets all bits of the sync counter 45 from the peak detection circuit to 0. The signal half a wavelength before this peak point, if there is no attenuation of the initial wavelength, will be a negative signal even if a fading signal is added, and will be at ground level in the waveform diagram of 102 in Figure 3. Therefore, when the drain voltage of the PMOS 22 is approximately 0V after a delay of about 1 wavelength from the detection of the positive peak of the capacitor voltage, and the peak is detected 1.5 wavelengths later from the peak detection point, a clock synchronization method in which all flip-flops of the synchronous counter 45 in Figure 6 are set to all bits 0 is preferable. The received signal at this time is bit 1. The method for detecting the approximately 0V signal involves applying the approximately 0V sample voltage to the positive input terminal of the operational amplifier, applying the ground voltage to the negative terminal via resistor R1, inserting resistor R2 between the negative input terminal and the output terminal of the operational amplifier to make R2 / R1 a large value, and applying the output of the operational amplifier to the negative input terminal of the comparator which has a small positive voltage applied to the positive input terminal of the first comparator, and if the output of the comparator is a positive voltage, then 0V is detected. The waveform diagram at the bottom of Figure 4 is the antenna-received signal of a signal consisting of transmitted data bit 1, bit 0, and bit 1.Similar to the upper diagram in Figure 4, when the voltage across capacitor C20 approximately one wavelength after the peak detection point of the wavelength signal is negative and the drain voltage of PMOS 22 is 0V, and when the voltage across capacitor C20 approximately 1.5 wavelengths after the peak detection point of the wavelength signal is a positive peak voltage and the drain voltage of PMOS 22 is positively peaked, all flipflops of the synchronous counter 45 in Figure 6 are set to all bits 0. This is an example demonstrating that synchronization can be restored when the receiving circuit experiences a synchronization loss. Therefore, it operates regardless of the presence or absence of a guard time. Note that if there is a fading signal, the voltage across capacitor C20 is integrated together with the fading signal, so there is only one peak, but the phase of the peak point is shifted by the fading signal, so it is necessary to widen the lock range of the peak point slightly.

[0036] Section (8) in Figure 3 represents the negative current section of the wavelength signal received by the antenna. The maximum voltage position of the peak for each wavelength amplitude is indicated as P in the figure. The position (57) where all bits of the synchronous counter 45 shown in Figure 6 are set to 0 is the position where peak P falls within the time range from (1.5J-5) to (1.5J+6) of the counter value of the 4J counter shown in Figures 7, 8, and 9, at a position (point Vr1 in the figure) that is 1.5 wavelengths delayed (indicated as δ in the figure) from point P (Vs2), the maximum voltage position of the second wavelength amplitude of the two wavelengths. In this case, there may or may not be two points where the peak position is delayed by 1.5 wavelengths from the peak position: one where the signal changes from positive-sequence two wavelengths to negative-sequence two wavelengths, and another where it changes from negative-sequence two wavelengths to positive-sequence two wavelengths, depending on the distance between the mobile terminal and the base station. Therefore, one method is to set the 4*J counter to all bits 0 at the first 1.5 wavelength difference detection point after the guard time, and then set the 4*J counter to all bits 0 at subsequent 4*J cycles. However, when synchronization is lost, there is a problem in that it is uncertain which of the two mobile terminals will regain synchronization when the distance between the two mobile terminals and the base station is short.

[0037] Next, Figure 5 shows another example of the receiving circuit for the microwave bit 1 and bit 0 signals transmitted from the LTE / WiMAX base station of the mobile terminal or tablet terminal of Example 1. In Figure 5, the circuit is the same as in Figure 3 except that a bipolar npn transistor 21 is used instead of the NMOS 21, so the explanation of the operation of parts unrelated to the npn transistor will be omitted. The difference between the bipolar npn transistor 21 and the NMOS 21 in Figure 3 is that the source input impedance is about 1000Ω, which is lower than the high input impedance of the gate of the NMOS 21. As a result, the charge of capacitor C20 discharges. Consequently, the potential of peak point Y shown in Figure 4 decreases on the right side due to discharge. However, the voltage at point Y drops because it deviates from the resonant state of the LCR, and may not be detected as a peak.

[0038] Next, Figure 6 shows an example of the operation of a synchronous counter that is clock-synchronized to the wavelength signal of the collector output signal 102 of the PMOS transistor 22 in Figure 3 of Example 1. In Figure 6, 102 is the input signal, 41 is a clock that is J times the carrier frequency f (J=8), 45 is a synchronous counter with a counter value of 4J that operates autonomously when there is no input signal, setting all flip-flops in the counter configuration to all bits 0, 55 is a peak detection circuit that detects the peak of the maximum voltage value of the input signal wavelength using an operational amplifier, 48 is the output clock (data clock) of the synchronous counter 45 (counter value 4J-2J), 47 are the five bit lines indicating the counter value of the synchronous counter 45, and 57 is all the flip-flops that make up the synchronous counter. 54 is the signal to set all bits of the flop to 0, 51 is bit 1 or bit 0 of the playback data, 52 is the packet data detection circuit, 59 and 65 are AND gates, 61 is an OR gate, 58 is the set-reset flip-flop, 64 is the guard time or packet synchronization out signal (66), 62 is the signal to set all bits of the sync counter 45 flip-flops to 0, 63 is the signal that goes high when the counter value of the sync counter 45 is between 4J-5 and 4J+7, and 59 is the sampling signal.

[0039] The peak detection circuit 55 determines the guard time by observing that the sampling value of the drain voltage of the NMOS22 of the amplified signal of the antenna received signal is at ground voltage for a certain period of time or longer. The guard time is set to a value such that the wavelength signal immediately following the guard time is not affected by fading of about 1 μsec. After the guard time, the first wavelength must identify the beginning of the transmitted data, so either multiple consecutive bits 1 before the delimiter signal containing the wavelength signal, or the first bit 1 of the delimiter, is used. The system clock is an example of a 2.4G multiplier clock with a frequency of approximately 4G microcarrier. Figure 6 shows an example where the synchronous counter 45 has a data signal with bits 1 and 0 of length of 4 wavelengths. Upon guard time detection, the set-reset flip-flop 48 is set to the set state, and the output of the AND circuit 59 of the Q output and signal 57, which sets all flip-flops of the synchronous counter 45 to all bits 0, sets all flip-flops of the synchronous counter 45 to all bits 0. After a certain time delay, the set-reset flip-flop is reset, and the output of the AND circuit 65 of the Q output NOT signal and signal 57, which sets all flip-flops of the synchronous counter to all bits 0, and signal 63, which is high when the counter value of the synchronous counter 45 is (from 4J-5 to 4J+7), sets all flip-flops of the synchronous counter 45 to all bits 0. This is a circuit configuration in which all flip-flops of the synchronous counter 45 are set to all bits 0 only at the 4J period position.

[0040] The output signal of the synchronous clock-generating asynchronous counter 45 is synchronized with the clock component of the input signal. If the counter 45 is composed of D-type flip-flops that can set all bits to 0, the countdown will start from 4J-1 with a clock input, but for the sake of simplicity, it is explained as a count-up. In the circuit of Figure 6, all flip-flops of the synchronous counter 45 are set to 0 each time there is a peak detection signal of the input signal wavelength at the 4J counter period, so there is no problem even if the mobile terminal moves at very high speeds.

[0041] Unlike OFMDA, Figure 6 has the advantage of high-speed bit transmission because it quickly corrects the phase shift of the synchronization clock caused by the movement of the mobile terminal. Figure 6 deals with the effects of fading in the case of a direct wave. In Rayleigh fading without a direct wave, if we lock onto the fading with the shortest delay, if the wavelength amplitude of the second fading is added to the wavelength amplitude of the first fading in opposite phase, the signal will disappear and an error will occur. Therefore, when added in opposite phase, interpolation is used for audio and video signals. The system identifies an Ethernet frame from the playback data in Figure 6, reads the base station MAC address from the frame header, and if the MAC address is equal to the MAC address of a neighboring base station advertised by the source base station, the mobile terminal sends the base station MAC address to the source base station as the MAC address of the candidate destination base station.

[0042] Next, Figure 7 shows a detailed operation diagram example of the peak detection circuit 55 in Figure 6 of Example 1. In Figure 7, 102 is the connection point of the drain resistor of the PMOS transistor 22 in Figure 3, and is the voltage signal that appears between the drain resistor R10 and ground when a positive-sequence signal is input to the PMOS transistor 22 in Figure 3. R1 in 101 is a resistor that sets the amplification value of the op-amp 100 to -1. 70 is a delay line with a constant delay time. Rh in 71 and 73 is a high resistance that allows the input voltage Vin to pass through the delay line 70 and add Vin / 2 to the positive terminal of the op-amp 100. 104 is the point where the output of the op-amp 100 changes from negative to positive output voltage when the voltage decreases from the maximum value of the peak of the input signal wavelength, and at that time the output changes from HIGH to LOW. 307 is a comparator, 307 is a differentiating circuit, 310 is a 4*J (J=8) counter, 313 is a set-reset flip-flop set with the counter value of counter 310 of 1.5*J-5 (J=8) (321) and reset with the counter value of 1.5*J+6 (322), 319 is an AND circuit, 57 is a signal that sets all flip-flops of the synchronous counter 45 in Figure 6 to all bits 0 and a signal for data bit 1, 59 is a sampling signal of the drain voltage of PMOS22 in Figure 3 when the counter value is 1*J, and 60 is a detection signal of 0V voltage from the sampling circuit of the drain voltage of PMOS22 in Figure 3.

[0043] Next, let's explain the operation shown in Figure 7. The input voltage 102 is applied to the positive terminal of the op-amp 100 with a delay of a certain time via the delay line 70. Therefore, if the voltage at the left input point of R1 before the delay line is higher than the voltage before the delay (the current voltage at the positive terminal), the output of op-amp 100 will be a negative differential voltage. Two resistors of the same resistance value Rh apply Vin1 / 2, which is half of the voltage Vin1 before the delay line 70, to the positive input terminal of the op-amp. If the voltage of the input voltage 102 at that time is Vin2, then (Vin1 / 2-Vin2)*1+Vin1 / 2 will appear at the output of op-amp 100. The comparator 104 outputs a signal that changes from HIGH to LOW, which is the inverted signal of the output signal of op-amp 100, indicating the point where the drain voltage of NMOS22 becomes a positive peak, and the output voltage of op-amp 100 changes from negative to positive. The output 331 of the differentiating circuit 307, which differentiates the falling edge signal of the output of comparator 104, sets all the flip-flops of the 4*J counter 310 to all bits 0. When the output of the differentiating circuit 307 is within the range of (1.5*J-5) to (1.5*J+6) of the counter value of the 4*J counter 310, and a detection signal 60 of 0V voltage from the sampling circuit of the drain voltage of PMOS 22 in Figure 3 is input, the output of the AND circuit 319 becomes high, which is the signal 57 that sets all the flip-flops of the synchronous counter 45 in Figure 6 to all bits 0.

[0044] Next, Figure 8 shows a different detailed operation diagram example of the peak detection circuit 55 in Figure 6 of Example 1, distinct from Figure 7. In Figure 8, 78 is an operational amplifier, R2 of 76 and R2 / 3 of 75 are resistors that supply Vin / 2, which is 1 / 4 of the output voltage of operational amplifier 78 and twice the input voltage Vin of 102, to the positive terminal of operational amplifier 100, and 77 is a resistor that sets the output voltage of operational amplifier 78 to 2Vin. The operation of Figure 8 is the same as in Figure 7 except for operational amplifier 78, so the explanation is omitted.

[0045] Next, Figure 9 shows a different detailed operation diagram example of the peak detection circuit 55 in Figure 6 of Example 1, distinct from Figures 7 and 8. Figure 9 is an example in which the time position at which the drain voltage of the PMOS transistor 22 in Figure 3 peaks is detected using two comparators and a delay line or delay circuit instead of an operational amplifier. In Figure 9, 301 and 302 are comparators, 300 and 303 are delay circuits, and 304 is an AND gate. The rest are the same as in Figure 7, so the operation explanation of the same parts is omitted.

[0046] Next, the operation of Figure 9 will be explained. The input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3 is applied to the negative input terminal of comparator 301 and the positive input terminal of comparator 302. The output of the delay circuit 300 is applied to the positive input terminal of comparator 301 and the negative input terminal of comparator 302. Now, if the voltage of the wavelength amplitude value, which is the input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3, is increasing, the positive input terminal voltage of comparator 302 becomes greater than the negative input terminal voltage, and the output of comparator 302 becomes positive. On the other hand, if the voltage of the wavelength amplitude value, which is the input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3, is increasing, the positive input terminal voltage of comparator 301 becomes less than the negative input terminal voltage, and the output of comparator 302 becomes negative. When the voltage of the wavelength amplitude value, which is the input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3, exceeds its peak and is decreasing, the positive input terminal voltage of comparator 301 becomes greater than the negative input terminal voltage, and the output of comparator 301 becomes positive. Therefore, by delaying the output of comparator 302 and applying the positive signals of the two comparators to the AND circuit 304, both signals become high on either side of the peak, so the output of the AND circuit 304 becomes high, and the time position of the peak of the signal wavelength amplitude value can be detected.

[0047] Next, Figure 10 shows an example of the operation of a synchronous counter that is clock-synchronized to the wavelength signal of the drain output signal 102 of the PMOS transistor 22 in Figure 3 of the second embodiment. In this case, the sampling detection operation of the drain output of the PMOS transistor 22 being 0V after a delay of approximately 1 wavelength from the peak value detection in Figure 3 is not performed. In Figure 10, 102 is the input signal, 41 is a clock that is J times the carrier frequency f (J=8), 45 is a synchronous counter with a self-propelled 8J counter value if there is no clear signal, 55 is a circuit that detects the peak position of the maximum voltage value of the input signal wavelength using an operational amplifier built into the ASIC, 48 is the output clock (data clock) of the synchronous counter 45 (counter value 4J-2j), 47 is the five bit lines that indicate the counter value of the synchronous counter 45, 57 is a signal that sets all bits of all flip-flops constituting the synchronous counter to 0, 54 is an 8-bit data clock, 51 is bit 1 or bit 0 of the regenerated data, 52 is a packet data detection circuit, and 59 is a sampling start signal. The peak position detection circuit 55 determines the guard time by checking that the sample value is at ground voltage for a certain period of time or longer. The guard time is set to a value such that the wavelength signal immediately following the guard time is not affected by fading of about 1 μsec. After the guard time, the first wavelength must identify the beginning of the transmitted data, so a delimiter is used in which the beginning of the wavelength signal is bit 1. The system clock is an example of a 2.4G J-times clock with a frequency of approximately 4G microcarrier. Figure 10 shows an example where the synchronous counter 45 detects that in Figures 1, 2, and 3, bit 1 of the transmitted data is followed by a two-wavelength signal and then a two-wavelength inverse-phase carrier section. Note that the guard time also includes cases where a continuous positive-phase carrier continues and an event where the peak-to-peak time difference of wavelength amplitude is 1.5 wavelengths is not detected for a certain period of time or longer.

[0048] The output signal of the synchronous clock-generating asynchronous counter 45 is synchronized with the clock component of the input signal. If counter 45 is configured with a D-type flip-flop that can be cleared, it will count down from 8J-1 with a clock input, but for the sake of simplicity, it is explained as counting up. The circuit in Figure 6 is cleared each time there is a certain wavelength of the input signal at the 8J counter period, so there is no problem even if the mobile terminal moves at very high speeds.

[0049] Unlike OFMDA, Figure 10 has the advantage of high-speed bit transmission because it quickly corrects the phase shift of the synchronization clock caused by the movement of the mobile terminal. Figure 10 considers the effect of fading when a direct wave is present. In Rayleigh fading without a direct wave, if we lock onto the fading with the shortest delay, if the wavelength amplitude of the second fading is added to the wavelength amplitude of the first fading in opposite phase, the signal will disappear and an error will occur. Therefore, when added in opposite phase, interpolation is used for audio and video signals. The system identifies an Ethernet frame from the playback data in Figure 10, reads the base station MAC address from the frame header, and if the MAC address is equal to the MAC address of a neighboring base station advertised by the source base station, the mobile terminal sends the base station MAC address to the source base station as the MAC address of the candidate destination base station.

[0050] Next, Figure 11 shows a detailed operation diagram example of the peak position detection circuit 55 of Figure 10 in the second embodiment. In Figure 11, 102 is the signal appearing at the connection point of the drain resistor of the PMOS transistor 22 in Figure 3, R1 of 101 is a resistor that sets the amplification value of the op-amp 100 to -1, 70 is a delay line with a constant delay time, Rh of 71 and 73 is a high resistance that allows the input voltage Vin to pass through the delay line 70 and add Vin / 2 to the positive terminal of the op-amp 100, 104 is a comparator that changes the output from HIGH to LOW when the output of the op-amp 100 changes from LOW to HIGH when the voltage decreases from the maximum value of the peak of the input signal wavelength, 307 is a differentiating circuit, and 811 is 4* The set-reset flip-flop 812 and 813 are set with the counter value 4*J-5 (J=8) (825) of J counter 1 (808) and reset with the counter value 6 (826). The set-reset flip-flops 812 and 813 are set with the counter values ​​1.5*J-5 of 4*J counter 2 (809) and 4*J counter 3 (810) and reset with 1.5*J+6. AND circuits 818 and 819 are AND circuits of the Q outputs of set-reset flip-flops 812 and 813, the output of the differentiater circuit 307, and the Q output of set-reset flip-flop 814, respectively. AND circuit 820 is an AND circuit of the Q output of set-reset flip-flop 811, the output of the differentiater circuit 307, and the NOT signal of the Q output of set-reset flip-flop 814. 817 is an OR gate formed from the outputs of AND gates 818, 819, and 820; 830 is a clock signal that is J times the carrier frequency; 831 is the output of the differentiating gate 307, which sequentially sets all flip-flops in the 4*J counters 2 and 3 to bit 0; and 814 is a set-reset flip-flop that is set with a guard time (continuous sampling value of 0V) and reset by the delay signal (816) from the output of OR gate 817.

[0051] Next, the operation of Figure 11 will be explained. The input voltage 102 is applied to the positive terminal of the operational amplifier 100 with a delay of a certain time by the delay line 70. If the voltage at the left input point of R1 before the delay line is lower than the voltage before the delay (the current voltage at the positive terminal), the output of the operational amplifier 100 will be a positive differential voltage. The comparator 104 outputs a signal that changes from HIGH to LOW, which is the inverted signal of the output signal that goes from negative to positive. When the Q output of the set-reset flip-flop 814 is high after the guard time, if there is a wavelength amplitude peak that is high in the output of the differentiating circuit 307 approximately 1.5 wavelengths after the peak of the wavelength amplitude is detected by the AND circuit 818 or 819, a high-level signal is output, so the output 57 of the OR circuit 817 becomes high, all the flip-flops of the synchronous counter 45 in Figure 10 are set to all bits, all the flip-flops of the 4*J counter 1 (808) are set to all bits 0, and the set-reset flip-flop 814 is reset by the delay signal (816). This activates the AND gate 820, and if the output of the differentiating gate 307 is within a range of 6 from the counter value (4*J-5) of the output of the 4*J counter 1 (808), signal 57 is output. This signal 57 is output when a peak in wavelength amplitude is detected at the 4*J period position, and synchronizes the synchronous counter 45 in Figure 10 with the received data. The signal 57 also contains information that the received data is bit 1.

[0052] Next, Figure 12 shows a different detailed operation diagram example of the peak position circuit 55 of Figure 10 in the second embodiment, distinct from Figure 11. In Figure 12, 78 is an operational amplifier, R2 of 76 and R2 / 3 of 75 are resistors that supply Vin / 2, which is 1 / 4 of the output voltage of operational amplifier 78 and twice the input voltage Vin, to the positive terminal of operational amplifier 100, and 77 is a resistor that sets the output voltage of operational amplifier 78 to 2Vin. The operation of Figure 12 is the same as in Figure 11 except for operational amplifier 78, so the explanation is omitted.

[0053] Next, Figure 13 shows a detailed operation diagram example of the sampling circuit 55 of Figure 10 in the second embodiment, different from Figures 11 and 12. Figure 13 is an example in which the time position at which the drain voltage of the PMOS transistor 22 in Figure 3 peaks is detected using two comparators and a delay line or delay circuit instead of an operational amplifier. In Figure 13, 301 and 302 are comparators, 300 and 303 are delay circuits, and 304 is an AND circuit. The rest are the same as in Figure 11, so the operation explanation of the same parts will be omitted.

[0054] Next, the operation of Figure 13 will be explained. The input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3 is applied to the negative input terminal of comparator 301 and the positive input terminal of comparator 302. The output of the delay circuit 300 is applied to the positive input terminal of comparator 301 and the negative input terminal of comparator 302. Now, if the voltage of the wavelength amplitude value, which is the input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3, is increasing, the positive input terminal voltage of comparator 302 becomes greater than the negative input terminal voltage, and the output of comparator 302 becomes positive. On the other hand, if the voltage of the wavelength amplitude value, which is the input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3, is increasing, the positive input terminal voltage of comparator 301 becomes less than the negative input terminal voltage, and the output of comparator 302 becomes negative. When the voltage of the wavelength amplitude value, which is the input signal 102 of the drain voltage of the PMOS transistor 22 in Figure 3, exceeds its peak and is decreasing, the positive input terminal voltage of comparator 301 becomes greater than the negative input terminal voltage, and the output of comparator 302 becomes positive. Therefore, by delaying the output of comparator 302 and applying the signals of the two comparators to the AND circuit 304, both signals will be high on either side of the peak, so the output of the AND circuit 304 will be high, and the time position of the peak of the signal wavelength amplitude value can be detected. Furthermore, unlike the area near the 0V amplitude peak, the amplitude changes very little over time near the wavelength amplitude peak. Therefore, when detecting the peak position, it is easier to use a comparator than an operational amplifier.

[0055] Next, Figure 14 shows a detailed operation diagram example of the peak position detection circuit 55 of Figure 10 in the third embodiment. In Figure 14, 102 is the signal appearing at the connection point of the drain resistor of the PMOS transistor 22 in Figure 3, R1 of 101 is a resistor that sets the amplification value of the op-amp 100 to -1, 70 is a delay line with a constant delay time, Rh of 71 and 73 is a high resistance that allows the input voltage Vin to pass through the delay line 70 and add Vin / 2 to the positive terminal of the op-amp 100, 104 is a comparator that changes the output from HIGH to LOW when the output of the op-amp 100 changes from LOW to HIGH when the voltage decreases from the maximum value of the peak of the input signal wavelength, 307 is a differentiating circuit, and 811 is the counter value 4*J-5(J= of the 4*J counter 1 (808) 8) A set-reset flip-flop set at (825) and reset at counter value 6 (826). 812 is a set-reset flip-flop set at the counter value of 4*J counter 2 (809) of 1.5*J-5 and reset at 1.5*J+6. 840 is a set-reset flip-flop set at the counter value of 4*J counter 2 (810) of 1.0*J-5 and reset at 1.0*J+6. AND circuits 818 and 819 are AND circuits of the Q outputs of set-reset flip-flops 812 and 840, the output of the differentiater circuit 307, and the Q output of set-reset flip-flop 814, respectively. AND circuit 820 is an AND circuit of the Q output of set-reset flip-flop 811, the output of the differentiater circuit 307, and the NOT signal of the Q output of set-reset flip-flop 814.834 is a counter where all flip-flops are set to all bits 0 by the output of AND circuit 818, and the counter value (IN) is counted up by the output of AND circuit 819 and output to digital comparator 835. 835 is a digital value comparison circuit that compares the counter value (IN) of counter 834 with a reference value (m-3+L) by the output of AND circuit 818, and outputs a high-level output signal to OR circuit 836 and delay circuit 816 if (IN>(m-3+L)). 836 is an OR circuit of the output of AND circuit 820 and the output of comparator 835. 830 is a clock J times the carrier frequency. 831 is the output of differentiator 307, a signal that sets all flip-flops of 4*J counters 2 and 3 to bit 0. 814 is a set-reset flip-flop that is set by the guard time (continuous sampling value of 0V) or packet synchronization out signal and reset by the delay (816) signal from the output of comparator 835.

[0056] Next, the operation of Figure 14 will be explained. The input voltage 102 is applied to the positive terminal of the operational amplifier 100 with a delay of a certain time by the delay line 70. Therefore, if the voltage at the left input point of R1 before the delay line is lower than the voltage before the delay (the current voltage at the positive terminal), the output of the operational amplifier 100 will be a positive differential voltage. The comparator 104 outputs a signal that changes from HIGH to LOW, which is the inverted signal of the output signal that goes from negative to positive. When the Q output of the set reset flip-flop 814 is high after the guard time, the AND gates 818 and 819 will output a high-level signal if there is a wavelength amplitude peak whose output is high, approximately 1.5 wavelengths and approximately 1 wavelength after the peak of the wavelength amplitude is detected, respectively. When the AND circuit 818 detects a peak in wavelength amplitude, and there is a delay of approximately 1.5 wavelengths after the peak detection, the output becomes high. This sets all the flip-flops of the continuous peak count counter 834, where the time difference between peaks of wavelength amplitude is approximately 1 wavelength, to bit 0. The detection signal from the AND circuit 819, where the time difference between peaks of wavelength amplitude is approximately 1 wavelength, counts up the counter 834. The counter value (IN) of the counter 834 is sent to the digital value comparison circuit 835, which compares it with a reference value (m-3+L) at the time of output of the AND circuit 818. If IN > (m-3+L), a high output signal is output, so all the flip-flops of the synchronous counter 45 in Figure 10 are set to all bits, all the flip-flops of the 4*J counter 1 (808) are set to all bits 0, and the delay signal (816) resets the set-reset flip-flop 814. This activates the AND gate 820, and if the output of the differentiating gate 307 is within the range of 6 from the counter value (4*J-5) of the output of the 4*J counter 1 (808), signal 57 is output. This signal 57 is output when a peak in wavelength amplitude is detected at the 4*J period position, and synchronizes the synchronous counter 45 in Figure 10 with the received data. The signal 57 also contains information that the received data is bit 1. In Figure 14, only one counter 2 (809) and one counter 3 (810) are shown due to space limitations, but it is desirable to use two of each and alternately set all flip-flops to all bits 0 with the output of the differentiating gate 307.Figure 14 shows a method that uses the position where the positive-sequence wavelength of the wavelength signal, consisting of transmitted data bits 1, 0, and 1, continues for (m-2)+L or longer, as shown in Figure 4.

[0057] Next, Figure 15 shows a different detailed operation diagram example of the peak position circuit 55 of Figure 10 in the third embodiment, distinct from Figure 14. In Figure 15, 78 is an operational amplifier, R2 of 76 and R2 / 3 of 75 are resistors that supply Vin / 2, which is 1 / 4 of the output voltage of operational amplifier 78 and twice the input voltage Vin, to the positive terminal of operational amplifier 100, and 77 is a resistor that sets the output voltage of operational amplifier 78 to 2Vin. The operation of Figure 15 is the same as in Figure 14 except for operational amplifier 78, so the explanation is omitted.

[0058] Next, Figure 16 shows a different detailed operation diagram example of the sampling circuit 55 of Figure 10 in the third embodiment, distinct from Figures 14 and 15. Figure 16 is an example in which the time position at which the drain voltage of the PMOS transistor 22 in Figure 3 peaks is detected using two comparators and a delay line or delay circuit instead of an operational amplifier. In Figure 16, 301 and 302 are comparators, 300 and 303 are delay circuits, and 304 is an AND gate. The rest are the same as in Figure 14, so the operation explanation of the same parts is omitted. The operation of the comparator in Figure 16 is the same as in Figure 13, so the explanation is omitted.

[0059] Comparing the first, second, and third embodiments, the first embodiment allows synchronization recovery at any position, while the second embodiment requires recovery after a guard time in the event of synchronization loss. However, the first embodiment requires sampling, while the second embodiment does not. The third embodiment does not require sampling and has the advantage of not requiring recovery after a guard time in the event of synchronization loss. While there is also a method of detecting the point where the amplitude signal crosses 0V instead of peak position detection, this method presents many problems because the 0V position is undetermined. [Explanation of Symbols]

[0060] 215-1 Digital sine carrier oscillator A 215-2 Inverted-Phase Digital Sine Carrier Oscillator B 223-3 A circuit that outputs a high-level output signal only between the two positive-phase wavelengths in the leading position of the four carrier wavelength frame used to transmit data bit 1, and between the four consecutive positive-phase carrier wavelengths used to transmit data bit 0. 223-4 A circuit that outputs a high-level output signal only during the last two out-of-phase wavelengths within the four-carrier wavelength frame used to transmit data bit 1. AND circuit between the high output signal of 222-2 and 223-3 and the multi-level output of circuit 215-1 AND circuit between the high output signal of 222-4 and 223-4 and the multi-level output of the inverted-phase oscillator circuit 215-2 235 DA conversion circuit for a multi-level signal of a two-wavelength continuous carrier with the cut-off transmit data bit 1 and a four-wavelength multi-level signal of transmit data bit 0 from the output of a digital sine carrier oscillator A, and the inverse phase of the two-wavelength continuous carrier with the transmit data bit 1. 218 High-power emitter-follower NPN bipolar transistor 227 Coaxial cable that transmits signals to an antenna 224 A clock with a frequency 8 times that of the carrier. 225 1 / 8 frequency divider 226 Carrier frequency clock 20 antennas R20, R9, R10 resistors c20 Capacitor L20 Inductance 28 Other branch signal lines 102 Output signal to the peak detection circuit of the drain voltage of PMOS transistor 22 41. A clock with a carrier frequency f multiplied by J (J=8). 45 If there is no set signal with all bits set to 0, the synchronous counter of the 4J counter will operate automatically. 55 Peak detection circuit using an operational amplifier to detect the peak of the maximum voltage value of the input signal wavelength 48 Output clock (data clock) of synchronous counter 45 (counter value 4J-2J) 47 Five bit lines indicating the counter value of the synchronization counter 45 57 A signal that sets all flip-flops constituting the synchronous counter to all bits 0. 54 8-bit data clock 51 Bit 1 or bit 0 of the playback data 52 Packet data detection circuit

Claims

1. A method for receiving data or packets transmitted by a mobile terminal using bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station, wherein the transmitted data or packets are transmitted using bit 1 and bit 0, wherein the transmitted data consists of a signal in which L (L: a natural number) wavelengths of microwave carrier wave are followed by (m-L) (m: a natural number) wavelengths of carrier wave in opposite phase to the L wavelength signals, and bit 0 consists of a signal in which (m) wavelengths of carrier wave are in phase with the L wavelength signals, and the transmitted data or packets are transmitted using bit 1 and bit 0, wherein the transmitted data or packets are transmitted using bit 1 and bit 0 signals transmitted by microwave carrier wave phase modulation from an LTE or WiMAX base station. A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station via microwave carrier phase modulation, characterized in that the device determines that received data bit 1 has been received when the time difference between peaks of the wavelength amplitude of the amplified microwave signal received by the antenna is equal to 1.5 carrier wavelengths, and that received data bit 0 has been received when the time difference between peaks is equal to 1.5 carrier wavelengths, and the device determines does not occur within the period of the carrier.

2. The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, according to claim 1, is characterized in that if the event in which the time difference between peaks of the wavelength amplitude is 1.5 wavelengths of the carrier wave occurs within the carrier wave m wavelength period, then the peak position in which the time difference between peaks of the wavelength amplitude is approximately 1.5 wavelengths is characterized in that there are ((m-2)+L) or more peaks in which the time difference between peaks of the wavelength amplitude is approximately 1 wavelength between two peak detection positions in which the time difference between peaks of the wavelength amplitude is approximately 1.5 wavelengths.

3. If an event occurs within the carrier wave m wavelength period where the time difference between peaks of the wavelength amplitude is 1.5 wavelengths, a self-operating synchronous counter, which counts up to (m)*J with a clock that is J times the carrier frequency clock and outputs an output clock with the count value Y, is used when there is no clear signal input. If a positively convex peak in the wavelength amplitude value is detected approximately 1.5 wavelengths after the detection of a positively convex voltage peak in the wavelength amplitude output of a one-stage or two-stage amplifier of microwaves received by the antenna, and the subsequent time interval for detecting positively convex voltage peaks in the wavelength amplitude output of the one-stage or two-stage amplifier is approximately 1.5 wavelengths, then the number of wavelength amplitude peaks with a time difference between peaks of approximately 1 wavelength ((m-2)+L) or more has been counted before a peak of approximately 1.5 wavelengths is detected. The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation to a mobile terminal, characterized in that, at a subsequent peak point with a time difference between wavelength peaks of approximately 1.5 wavelengths, all flip-flops of the synchronization counter are set to all bits 0, and all flip-flops of the second m*J counter are set to all bits 0, and when the counter value of the second m*J counter is near m*J and a peak in wavelength amplitude is detected, all flip-flops of the synchronization counter are set to all bits 0, and all flip-flops of the second m*J counter are set to all bits 0 to obtain the synchronization clock of the received data as the output clock, and to determine that the received data is bit 1, as described in claim 1.

4. The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, according to claim 1, is characterized in that, if the event in which the time difference between peaks of the wavelength amplitude is 1.5 wavelengths of the carrier wave occurs within the carrier wave m wavelength period, the amplifier output voltage half a wavelength before the detection time position in which the time difference between peaks of the wavelength amplitude is 1.5 wavelengths of the carrier wave is near 0V or less.

5. The system includes a self-operating synchronous counter that sets all bits to 0 if there is no signal input, and if the event in which the time difference between peaks of the wavelength amplitude is 1.5 wavelengths of the carrier wave occurs within the period of m wavelengths of the carrier wave, it counts up to (m)*J with a clock that is J times the carrier frequency clock, and outputs an output clock with the count value Y. The system also includes a self-operating synchronous counter that sets all bits to 0, and if the wavelength amplitude of the output of the one-stage or two-stage amplifier of the microwave received by the antenna is near 0V approximately one wavelength after the detection of a positively convex voltage peak in the wavelength amplitude of the output of the one-stage or two-stage amplifier, and if there is an event in which there is a positively convex peak in the wavelength amplitude value approximately 1.5 wavelengths after the detection of a positively convex voltage peak in the wavelength amplitude of the output of the one-stage or two-stage amplifier, it determines that bit 1 of the received data and sets all the flip-flops of the synchronous counter to 0. The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 1, characterized in that the clock of the received data is obtained as the output clock and the received data is determined to be bit 1.

6. A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 5, characterized in that, if the aforementioned event does not occur for a certain period of time, the entire flip-flop of the synchronization counter is set to all bits 0 by an AND signal between the Q output of the set reset flip-flop and the signal when the aforementioned event occurs, and the set reset flip-flop is reset by a delay signal of the AND signal, and thereafter, if the NOT signal of the Q output of the set reset flip-flop, the signal when the aforementioned event occurs, and the counter value of the synchronization counter are within a specified range, the entire flip-flop of the synchronization counter is set to all bits 0, and the set reset flip-flop is reset by a delay signal of the AND signal, thereby obtaining the clock of the received data as the output clock, and determining that the received data is bit 1.

7. The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 6, is characterized in that if the packets created from the received data cannot be synchronized, the set reset flip is set to the set state.

8. The system includes a self-operating synchronous counter that, when there is no signal input to set all bits to 0, counts up to (m)*J with a clock that is J times the carrier frequency clock, and outputs an output clock with the count value Y, and when there is no signal input to set all bits to 0, at t1,i when a positively convex voltage peak is detected in the amplitude of the first L consecutive carrier wavelengths after the guard time of the output of the one-stage or two-stage amplifier of the microwave received by the antenna, all flipflops of the counter that outputs the 1.5 wavelength counter value are set to all bits. The steps include setting the clock to 0, and if a positively convex peak in the wavelength amplitude value is detected approximately (1.5) wavelengths after the peak detection position, clearing all flipflops of the synchronization counter and setting all flipflops of the second m*J counter to all bits 0, and if the counter value of the second m*J counter is within the range of m*J-α to β where a positively convex peak in the wavelength amplitude value is detected, setting all flipflops of the synchronization counter to all bits 0, obtaining the clock of the received data as the output clock of the synchronization counter, and determining that bit 1 of the received data is... The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation to a mobile terminal, as described in claim 1, wherein the step of determining that bit 1 of the received data is not at the output clock position is bit 0 of the received data.

9. A method for receiving bit 1 and bit 0 signals transmitted from an LTE, WiMAX base station by microwave carrier phase modulation, as described in claim 3, 5, or 8, characterized in that when a positively convex voltage peak of the amplitude of the carrier wavelength is detected, the capacitor output signal of the bandpass LCR filter of the signal received by the antenna after the guard time is applied as Vin to the positive input terminal of the operational amplifier, the ground voltage is applied to the negative input terminal of the operational amplifier via resistor R1, and a resistor R2 is used between the negative input terminal and the output of the operational amplifier, with the output voltage (Vin-0v) * R2 / R1 + Vin being the position of t1,i (i: current position) when the voltage of the signal, which is initially simply the amplitude value of the first L wavelength signals, is delayed for a certain period of time by a delay line or delay circuit, changes from a state where it is lower to a state where it is higher than the voltage of the signal before the delay line or delay circuit, after the guard time.

10. A method for receiving bit 1 and bit 0 signals transmitted from an LTE, WiMAX base station by microwave carrier amplitude modulation, as described in claim 3, 5, or 8, characterized in that when a positive voltage peak of the amplitude of the Lth wavelength of the carrier wave is detected, the voltage of the LCR capacitor grounded to the ground of the LCR resonator of the signal received by the antenna after the guard time is applied to the gate of the NMOS of the first-stage amplifier with a 0 bias voltage, the drain output of the NMOS is directly connected to the gate of the PMOS of the second-stage amplifier, the drain of the PMOS transistor is connected to ground via a drain resistor, and the voltage at the drain connection point is at the position t1,i (i: current position) when the voltage of the signal obtained by delaying the signal obtained by delaying the amplitude values ​​of the first L wavelength signals by a delay line or delay circuit for a certain period of time after the guard time changes from a state where it is lower to a state where it is higher than the voltage of the signal before the delay line or delay circuit.

11. A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier amplitude modulation, as described in claim 3, 5, or 8, characterized in that when detecting a positive voltage peak in the amplitude of the L-th wavelength of the L continuous carrier waves, the voltage of the LCR capacitor grounded to the ground of the LCR resonator of the signal received by the antenna after the guard time is added to the source of the npn transistor of the first-stage amplifier with a 0 bias voltage, the collector output of the npn transistor is directly connected to the gate of the PMOS of the second-stage amplifier, the drain of the PMOS transistor is connected to ground via a drain resistor, and the voltage at the drain connection point is at the position t1,i (i: current position) when, after the guard time, the voltage of the signal obtained by delaying the signal obtained by delaying the amplitude values ​​of the first L wavelength signals by a delay line or delay circuit for a certain period of time changes from a state where it is lower to a state where it is higher than the voltage of the signal before the delay line or delay circuit.

12. A method for synchronizing the clock of a mobile terminal using bit 1 and bit 0 signals of microwave carrier phase modulation, wherein bit 1 of the transmitted data consists of a signal in which L (L: natural number) wavelengths of microwave carrier waves are followed by (m-L) (m: natural number) wavelengths of carrier waves in opposite phase to the L wavelength signals, and bit 0 of the transmitted data consists of a signal in which (m) wavelengths of carrier waves in phase with the L wavelength signals, and the transmitted data is sent from an LTE, WiMAX base station to a mobile terminal. The method includes a synchronization counter that counts up to (m)*J with a clock that is J times the carrier frequency clock and outputs an output clock with a count value Y, and which operates autonomously when there is no set signal input for all bits 0, and the one-stage or two-stage amplifier receives microwaves from an antenna, and the one-stage or two-stage amplifier receives the microwaves from an antenna, with a delay of approximately one wavelength from the detection of a positively convex voltage peak of the amplitude of the wavelength of the output of the one-stage or two-stage amplifier. When the amplitude of the output wavelength of the amplifier is near 0V, and there is an event where there is a positively convex peak in the wavelength amplitude value approximately 1.5 wavelengths after the detection of a positively convex voltage peak in the output wavelength amplitude of the one-stage amplifier or two-stage amplifier, it is determined to be bit 1 of the received data. If the event does not occur for a certain period of time, the entire flipflop of the synchronous counter is set to all bits 0 by the AND signal of the Q output of the set reset flipflop and the signal when the event occurs, and the set reset flipflop is reset by the delay signal of the AND signal. Thereafter, when the NOT signal of the Q output of the set reset flipflop, the signal when the event occurs, and the counter value of the synchronous counter are within the specified range, the entire flipflop of the synchronous counter is set to all bits 0, and the set reset flipflop is reset by the delay signal of the AND signal. A method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 1, characterized in that the clock of the received data is obtained as the output clock and is determined to be bit 1 of the received data.

13. A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 3, claim 5, or claim 8, characterized in that the counter value Y of the output clock output at the aforementioned counter value Y is ((m*J-2*J).

14. A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 1, claim 3, claim 5, or claim 8, characterized in that J is 8. 。

15. A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 1, claim 3, claim 5, or claim 8, characterized in that m is 4 and L is 2.

16. A method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 1, claim 3, claim 5, or claim 8, characterized in that L is 3 and m is 5.

17. The method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in 12, characterized in that the counter value Y of the output clock output with the aforementioned counter value Y is ((m*J-2*J).

18. The method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in claim 12, characterized in that J is 8. 。

19. A method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in 12, characterized in that m is 4 and L is 2.

20. A method for synchronizing the clock of bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation, as described in 12, characterized in that L is 3 and m is 5.

21. The method for receiving bit 1 and bit 0 signals transmitted from an LTE or WiMAX base station by microwave carrier phase modulation to a mobile terminal, as described in claim 8, characterized in that the guard time is 0V when no event is detected for a certain period of time in which the time difference between peaks of wavelength amplitude is 1.5 wavelengths of the carrier wave, or when the time difference between peaks of wavelength amplitude remains approximately 1 wavelength of the carrier wave for a certain period of time, or when there is no carrier wave antenna reception signal for a certain period of time.

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