Multilayer ceramic capacitor and method for manufacturing the same

Abstract

We provide multilayer ceramic capacitors with high capacitance and excellent dielectric breakdown voltage and mean time of failure. [Solution] The multilayer ceramic capacitor includes an active region A and margin regions S1 and S2 on both sides thereof. The active region is divided into three equal parts in the stacking direction and has a central portion Ac and surface portions As located on both sides of the central portion. The internal electrode layers 121 and 122 include an internal electrode layer interface region including the interface with the dielectric layer 111. The dielectric layer includes a dielectric layer interface region including the interface with the internal electrode layer. At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region contains sulfur (S). At least one of the internal electrode layer interface region and the dielectric layer interface region located in the surface portion of the active region and at least one of the margin regions contains sulfur (S).

Description

Technical Field

[0001] The present disclosure relates to a multilayer ceramic capacitor and a method for manufacturing the same.

Background Art

[0002] As electronic components using ceramic materials, there are capacitors, inductors, piezoelectric elements, varistors, thermistors, and the like. Among such ceramic electronic components, a multilayer ceramic capacitor (MLCC) can be used in various electronic devices due to its advantages of being small, having a high capacitance, and being easy to mount.

[0003] For example, a multilayer ceramic capacitor (MLCC) can be used as a chip-shaped capacitor that is attached to the substrate of various electronic products such as video devices such as liquid crystal display (LCD), plasma display panel (PDP), and organic light-emitting diode (OLED), computers, personal mobile terminals, and smartphones, and serves to charge or discharge electricity.

[0004] Recently, with the development of electronic devices and autonomous vehicles, miniaturization and large capacitance of multilayer ceramic capacitors have been strongly demanded. In order to achieve a higher capacitance in the same volume, thinning of the dielectric layer and the internal electrode layer is essential. For this reason, research for atomization of the internal electrode layer made of nickel (Ni) material, control of shrinkage behavior, and the like is in progress.

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment provides a multilayer ceramic capacitor having excellent electrical characteristics and reliability.

[0006] Another embodiment provides a method for manufacturing the multilayer ceramic capacitor. [Means for solving the problem]

[0007] One embodiment provides a multilayer ceramic capacitor comprising a capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, wherein the capacitor body includes an active region in which the dielectric layer and the internal electrode layer are alternately stacked with respect to each other, and margin regions disposed on both opposite ends of the active region in a direction perpendicular to the stacking direction, the active region is divided into three equal parts in the stacking direction and has a central portion and surface portions located on both sides of the central portion, the internal electrode layer includes an internal electrode layer interface region including the interface with the dielectric layer, the dielectric layer includes a dielectric layer interface region including the interface with the internal electrode layer, at least one of the internal electrode layer interface region and the dielectric layer interface region located in the central portion of the active region contains sulfur (S), and at least one of the internal electrode layer interface region and the dielectric layer interface region located in the surface portion and at least one of the margin region of the active region contains sulfur (S).

[0008] At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region may contain sulfur (S) in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in that region.

[0009] At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region further contains nickel (Ni), and when performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in the central part of the active region, the internal electrode layer interface region in the central part of the active region may be a region from a point where the total amount of elements present in the same region is 1 / 2 to 9 / 10 of the maximum value of the molar percentage of nickel (Ni).

[0010] At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region further contains nickel (Ni), and when performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in the central part of the active region, the dielectric layer interface region in the central part of the active region may be a region from a point where the maximum value of the molar percentage of nickel (Ni) is 1 / 2 to 1 / 4, based on the total amount of elements present in the same region.

[0011] At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region may contain sulfur (S) in an amount of 0.1 mol% to 1.2 mol% relative to the total amount of elements present in that region.

[0012] The surface portion of the active region and at least one of the margin regions, the internal electrode layer interface region and the dielectric layer interface region, may each contain sulfur (S) in an amount greater than 0 mol% to 1.0 mol% or less relative to the total amount of elements present in that region.

[0013] The internal electrode layer interface region and the dielectric layer interface region located in at least one of the surface portion of the active region and the margin region further contain nickel (Ni), and when performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in at least one of the surface portion of the active region and the margin region, the internal electrode layer interface region in at least one of the surface portion of the active region and the margin region may be a region from a point where the maximum value of the molar percentage of nickel (Ni) is 1 / 2 to 9 / 10, based on the total amount of elements present in the same region.

[0014] The internal electrode layer interface region and the dielectric layer interface region located in at least one of the surface portion of the active region and the margin region further contain nickel (Ni), and when performing TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis on a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in at least one of the surface portion of the active region and the margin region, the dielectric layer interface region in at least one of the surface portion of the active region and the margin region may be a region from a point where the maximum value of the mole percent of nickel (Ni) is 1 / 2 to 1 / 10, based on the total amount of elements present in the same region.

[0015] Another embodiment includes a capacitor body comprising a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, wherein the capacitor body comprises an active region in which the dielectric layer and the internal electrode layer are alternately stacked, and margin regions disposed on opposite ends of the active region perpendicular to the stacking direction, the active region being divided into three equal parts in the stacking direction and having a central portion and surface portions located on both sides of the central portion, and in the central portion of the active region, 15 extends from the interface between the internal electrode layer and the dielectric layer into the interior of the internal electrode layer The present invention provides a multilayer ceramic capacitor in which at least one of a region having a depth of 15 nm to 25 nm and a region having a depth of 15 nm to 25 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer contains sulfur (S), and in at least one of the surface portion of the active region and the margin region, a region having a depth of 5 nm to 15 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and a region having a depth of 5 nm to 15 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer contains sulfur (S).

[0016] In the central part of the active region, at least one of the regions having a depth of 15 nm to 25 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and the region having a depth of 15 nm to 25 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer, may contain sulfur (S) in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in that region.

[0017] In the central part of the active region, at least one of the regions having a depth of 15 nm to 25 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and the region having a depth of 15 nm to 25 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer, may contain sulfur (S) in an amount of 0.1 mol% to 1.2 mol% relative to the total amount of elements present in that region.

[0018] In at least one of the surface portion of the active region and the margin region, at least one of the regions having a depth of 5 nm to 15 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and at least one of the regions having a depth of 5 nm to 15 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer, may contain sulfur (S) in an amount of more than 0 mol% to 1.0 mol% or less relative to the total amount of elements present in that region.

[0019] Another embodiment provides a method for manufacturing the multilayer ceramic capacitor described above, comprising the steps of: manufacturing a conductive paste using sulfur-containing nickel; manufacturing a dielectric green sheet using a dielectric slurry and printing the conductive paste onto the surface of the dielectric green sheet to form a conductive paste layer; laminating the dielectric green sheets on which the conductive paste layer is formed to manufacture a dielectric green sheet laminate; heat-treating the dielectric green sheet laminate to desulfurize the sulfur-containing nickel; firing the dielectric green sheet laminate after the heat treatment to manufacture a capacitor body including a dielectric layer and an internal electrode layer; and forming external electrodes on the outside of the capacitor body.

[0020] The sulfur-containing nickel may have a form in which sulfur (S) is coated on the surface of nickel (Ni).

[0021] The aforementioned sulfur-containing nickel may contain 100 ppm to 2000 ppm of sulfur (S).

[0022] The heat treatment can be carried out at a temperature of 900°C to 1500°C.

[0023] The heat treatment can be carried out for 0.01 hours to 2.0 hours. [Effects of the Invention]

[0024] The multilayer ceramic capacitor according to one embodiment has excellent internal electrode layer connectivity and can improve electrical characteristics and reliability.

Brief Description of the Drawings

[0025] [Figure 1] FIG. 1 is a perspective view showing a multilayer ceramic capacitor according to one embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor cut along the line I-I' of FIG. 1. [Figure 3] FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor cut along the line II-II' of FIG. 1. [Figure 4] FIG. 4 is an exploded perspective view showing the laminated structure by disassembling the capacitor body of FIG. 1. [Figure 5] FIG. 5 is an enlarged view of the X region in FIG. 2. [Figure 6] FIG. 6 is an enlarged view of the Y region in FIG. 2. [Figure 7] FIG. 7 is a TEM-EDS (transmission electron microscope - energy dispersive spectroscopy) line analysis graph of the internal electrode layer and the dielectric layer at the center of the active region according to Example 1. [Figure 8] FIG. 8 is a TEM-EDS (transmission electron microscope - energy dispersive spectroscopy) line analysis graph of the internal electrode layer and the dielectric layer at the center of the active region according to Example 2. [Figure 9] FIG. 9 is a TEM-EDS (transmission electron microscope - energy dispersive spectroscopy) line analysis graph of the internal electrode layer and the dielectric layer at the center of the active region according to Example 3. [Figure 10] FIG. 10 is a TEM-EDS (transmission electron microscope - energy dispersive spectroscopy) line analysis graph of the internal electrode layer and the dielectric layer at the center of the active region according to Example 4. [Figure 11] FIG. 11 is a TEM-EDS (transmission electron microscope - energy dispersive spectroscopy) line analysis graph of the internal electrode layer and the dielectric layer in the margin region according to Example 1. [Figure 12] Figure 12 shows a TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) analysis image of the central part of the active region according to Example 2. [Modes for carrying out the invention]

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. In the drawings, parts that are not necessary for the clear explanation of the present invention have been omitted, and the same or similar components are denoted by the same reference numerals throughout the specification. In addition, some components in the attached drawings are exaggerated, omitted, or shown schematically, and the size of each component does not fully reflect its actual size.

[0027] The accompanying drawings are provided solely to facilitate understanding of the embodiments disclosed herein, and should not be understood as limiting the technical ideas disclosed herein, and should be understood to include any modifications, equivalents, or substitutions that fall within the concept and scope of the invention.

[0028] Terms including ordinal numbers, such as "first," "second," etc., can be used to describe a variety of components, but the components are not limited by such terms. These terms are used solely for the purpose of distinguishing one component from another.

[0029] Furthermore, when we say that a layer, membrane, region, plate, or other part is "on top of" another part, this includes not only the case where it is "directly above" the other part, but also the case where the other part is in between. Conversely, when we say that one part is "directly above" another part, it means that there is no other part in between. Also, being "on top of" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the opposite direction of gravity.

[0030] Throughout the specification, terms such as “includes” or “have” are intended to indicate the presence of features, figures, steps, actions, components, parts, or combinations thereof described in the specification, and should not be understood to preemptively exclude the presence or possibility of adding one or more other features, figures, steps, actions, components, parts, or combinations thereof. Therefore, when a part “includes” a component, this does not exclude other components unless specifically contradicted, and may further include other components.

[0031] Furthermore, throughout the specification, "on a plane" refers to the view of the part in question from above, and "on a cross-section" refers to the view of a cross-section obtained by cutting the part in question perpendicularly, as seen from the side.

[0032] Furthermore, throughout the specification, the term "connected" does not only mean that two or more components are directly connected, but may also mean that two or more components are indirectly connected through other components, that they are not only physically connected but can also be electrically connected, or that they are a single unit, even though they are referred to by different names depending on their location or function.

[0033] Hereinafter, a multilayer ceramic capacitor according to one embodiment will be described with reference to Figures 1 to 4.

[0034] Figure 1 is a perspective view showing a multilayer ceramic capacitor according to one embodiment; Figure 2 is a cross-sectional view of the multilayer ceramic capacitor cut along the line I-I' in Figure 1; Figure 3 is a cross-sectional view of the multilayer ceramic capacitor cut along the line II-II' in Figure 1; and Figure 4 is a separated perspective view showing the laminated structure of the internal electrode layers in the capacitor body of Figure 1.

[0035] The L-axis, W-axis, and T-axis shown in Figures 1 to 4 represent the length, width, and thickness directions of the capacitor body 110, respectively. Here, the thickness direction (T-axis direction) may be perpendicular to the wide surface (circumferential surface) of the sheet-like component, and for example, it can be used with the same concept as the stacking direction in which the dielectric layers 111 are stacked. The length direction (L-axis direction) may be a direction that is approximately perpendicular to the thickness direction (T-axis direction) in the direction extending alongside the wide surface (circumferential surface) of the sheet-like component, and for example, it may be a direction in which the first external electrode 131 and the second external electrode 132 are located on both sides. The width direction (W-axis direction) may be a direction that is approximately perpendicular to the thickness direction (T-axis direction) and the length direction (L-axis direction) in the direction extending alongside the wide surface (circumferential surface) of the sheet-like component, and the length in the length direction (L-axis direction) of the sheet-like component may be even longer than the length in the width direction (W-axis direction).

[0036] Referring to Figures 1 to 4, a multilayer ceramic capacitor 100 according to one embodiment includes a capacitor body 110 and external electrodes 131 and 132 disposed on the outside of the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposing ends of the capacitor body 110 in the longitudinal direction (L-axis direction).

[0037] The capacitor body 110 may, for example, have a roughly hexahedral shape.

[0038] For the convenience of explaining one embodiment, the two surfaces of the capacitor body 110 that face each other in the thickness direction (T-axis direction) are defined as the first and second surfaces, the two surfaces connected to the first and second surfaces and facing each other in the length direction (L-axis direction) are defined as the third and fourth surfaces, and the two surfaces connected to the first and second surfaces and connecting to the third and fourth surfaces and facing each other in the width direction (W-axis direction) are defined as the fifth and sixth surfaces.

[0039] For example, the first surface, which is the bottom surface, may be the surface facing the mounting direction. Also, the first to sixth surfaces may be flat, but this embodiment is not limited to this. For example, the first to sixth surfaces may be curved surfaces with a convex central portion, and the corners that form the boundaries of each surface may be rounded.

[0040] The shape, size, and number of dielectric layers 111 of the capacitor body 110 are not limited to those shown in the drawings of this embodiment.

[0041] The capacitor body 110 includes a plurality of dielectric layers 111 and internal electrode layers 121 and 122. Specifically, the capacitor body 110 includes a plurality of dielectric layers 111 and first internal electrode layers 121 and second internal electrode layers 122 that are alternately arranged in the thickness direction (T-axis direction) with the dielectric layers 111 in between.

[0042] At this time, the boundaries between adjacent dielectric layers 111 of the capacitor body 110 can become so integrated that they are difficult to confirm without using a scanning electron microscope (SEM).

[0043] The capacitor body 110 may include an active region (A), margin regions (S1, S2), and cover regions 112, 113.

[0044] The active region (A) is a region in which the dielectric layer 111 and the internal electrode layers 121 and 122 are arranged alternately, and is a portion that contributes to the formation of the capacitance of the multilayer ceramic capacitor 100. Specifically, the active region (A) may be a region in which the first internal electrode layer 121 or the second internal electrode layer 122, which are stacked along the thickness direction (T-axis direction), overlap.

[0045] The active region (A) can be divided into three equal parts in the thickness direction (T-axis direction), that is, in the stacking direction, and may have a central portion (Ac) and surface portions (As) located on both sides of the central portion (Ac).

[0046] The margin regions (S1, S2) can be located on opposite ends of the active region (A) in the longitudinal direction (L-axis direction), that is, perpendicular to the stacking direction, i.e., on the third and fourth surfaces, respectively. Such margin regions (S1, S2) may also be regions where the ends of internal electrode layers 121, 122 that can be electrically connected to the external electrodes 131, 132 are located. Specifically, the margin regions may include a first margin region (S1) where the end of the first internal electrode layer 121 electrically connected to the first external electrode 131 is located, and a second margin region (S2) where the end of the second internal electrode layer 122 electrically connected to the second external electrode 132 is located.

[0047] The cover regions 112 and 113 are thickness-direction margins and can be located on the first and second surfaces of the active region, respectively, in the thickness direction (T-axis direction), that is, in the stacking direction. Such cover regions 112 and 113 may be formed by a single dielectric layer 111 or by two or more dielectric layers 111 stacked on the upper and lower surfaces of the active region, respectively.

[0048] Furthermore, the capacitor body 110 may further include a widthwise side margin region.

[0049] The widthwise side margin region can be located at the opposite ends of the active region in the widthwise direction (W-axis direction), i.e., on the fifth and sixth surfaces, respectively. The widthwise side margin region may be formed by applying the conductive paste layer for the internal electrode layer to the surface of the dielectric green sheet, applying the conductive paste layer to only a portion of the surface of the dielectric green sheet, and then laminating dielectric green sheets without the conductive paste layer on both sides of the dielectric green sheet surface, followed by firing; however, the method of formation is not limited to this.

[0050] The cover regions 112, 113 and the widthwise side margin regions serve to prevent damage to the first internal electrode layer 121 and the second internal electrode layer 122 due to physical or chemical stress.

[0051] The internal electrode layers 121 and 122, that is, the first internal electrode layer 121 and the second internal electrode layer 122, are electrodes having opposite polarities and are arranged alternately facing each other along the T-axis direction with the dielectric layer 111 in between, with one end of each being exposed through the third and fourth surfaces of the capacitor body 110.

[0052] The first internal electrode layer 121 and the second internal electrode layer 122 can be electrically insulated from each other by the dielectric layer 111 placed in between them.

[0053] The ends of the first internal electrode layer 121 and the second internal electrode layer 122, which are alternately exposed through the third and fourth surfaces of the capacitor body 110, can be electrically connected to the first external electrode 131 and the second external electrode 132, respectively.

[0054] The internal electrode layers 121 and 122 and the dielectric layer 111 will be explained with reference to Figures 5 and 6.

[0055] Figure 5 is an enlarged view of the X region in Figure 2, showing a portion of the active region (A), specifically a portion of the central part (Ac) of the active region (A). Figure 6 is an enlarged view of the Y region in Figure 2, showing a portion of the margin regions (S1, S2).

[0056] Referring to Figures 5 and 6, the internal electrode layers 121 and 122 include an internal electrode layer internal region 10 and an internal electrode layer interface region 20 which is located on at least one surface of the internal electrode layer internal region 10 in the stacking direction and includes the interface with the dielectric layer 111. The dielectric layer 111 also includes an internal dielectric layer region 30 and a dielectric layer interface region 40 which is located on at least one surface of the internal dielectric layer internal region 30 in the stacking direction and includes the interface with the internal electrode layers 121 and 122.

[0057] According to one embodiment, sulfur (S) may be included at the interface between the internal electrode layers 121, 122 located in the central part (Ac) of the active region (A) and the dielectric layer 111. Specifically, at least one of the internal electrode layer interface region 20 and the dielectric layer interface region 40 located in the central part (Ac) of the active region (A) may contain sulfur (S). In this case, the sulfur (S) may be included in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in each region. In this case, the internal electrode layer interface region 20 in the central part (Ac) of the active region (A) includes the interface between the internal electrode layers 121, 122 and the dielectric layer 111, and the dielectric layer interface region 40 in the central part (Ac) of the active region (A) includes the interface between the dielectric layer 111 and the internal electrode layers 121, 122, and each of these interfaces may be at a point where the maximum value of the mole% of nickel (Ni), which is the main component of the internal electrode layers 121, 122, is approximately 1 / 2.

[0058] In other words, the internal electrode layer interface region 20 located in the central part (Ac) of the active region (A) contains sulfur (S) in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in the internal electrode layer interface region 20, or the dielectric layer interface region 40 located in the central part (Ac) of the active region (A) contains sulfur (S) in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in the dielectric layer interface region 40, or both the internal electrode layer interface region 20 and the dielectric layer interface region 40 located in the central part (Ac) of the active region (A) contain sulfur (S), in which case the sulfur (S) may be contained in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in each region.

[0059] As an example, at least one of the internal electrode layer interface region 20 and the dielectric layer interface region 40 located in the central part (Ac) of the active region (A) may contain sulfur (S) in amounts of 0.1 mol% to 1.8 mol%, 0.1 mol% to 1.5 mol%, or 0.1 mol% to 1.2 mol%, respectively, relative to the total amount of elements present in that region.

[0060] Sulfur (S) may originate from sulfur-containing nickel used as the main material when forming the internal electrode layers 121 and 122. In other words, sulfur-containing nickel can have a form in which sulfur (S) is coated on the surface of nickel (Ni). According to one embodiment, when manufacturing a multilayer ceramic capacitor, a multilayer ceramic capacitor can be obtained in which the sulfur (S) content at the interface between the internal electrode layer and the dielectric layer is adjusted by adjusting the sulfur (S) content by a desulfurization process of sulfur-containing nickel before firing. The adjustment of the sulfur (S) content during manufacturing can be done by changing the heat treatment conditions of the desulfurization process.

[0061] Sulfur-containing nickel has the effect of delaying Ni shrinkage in the initial stages of firing due to the sulfur (S) present on the nickel (Ni) surface. However, SO2 decomposition occurs in the high-temperature range above 850°C, and rapid shrinkage due to Ni surface exposure proceeds. When sulfur (S), which causes rapid shrinkage in the high-temperature firing range, is removed through a desulfurization process before firing, the sulfur (S) content at the interface between the internal electrode layers 121, 122 and the dielectric layer 111 can be reduced to the predetermined range mentioned above.

[0062] Therefore, in one embodiment, when the sulfur (S) content at the interface between the internal electrode layers 121, 122 and the dielectric layer 111 is adjusted to a predetermined range, that is, when sulfur (S) is contained in a content of 0.1 mol% or more and less than 2.0 mol% in at least one of the internal electrode layer interface region 20 and the dielectric layer interface region 40 in the central part (Ac) of the active region (A), the shrinkage behavior of Ni changes, improving the microstructure of the internal electrode layer and the dielectric layer, and thereby improving the connectivity and electrical properties of the internal electrode layer. Specifically, when sulfur (S) is contained in the region at a concentration of 2.0 mol% or more, rapid shrinkage of Ni occurs during the high-temperature firing section, which not only reduces the connectivity of the internal electrode layer but also reduces capacitance characteristics and can lead to a decrease in reliability, such as degradation of the dielectric breakdown voltage (BDV). Furthermore, when sulfur (S) is contained in the region at a concentration of less than 0.1 mol%, an excessive heat treatment process is required to completely remove the sulfur, which may reduce the microstructure characteristics of the internal electrode layer.

[0063] According to one embodiment, sulfur (S) may be present not only in the central part (Ac) of the active region (A), but also at the interface between the internal electrode layers 121, 122 and the dielectric layer 111, specifically at least one of the internal electrode layer interface region 20 and the dielectric layer interface region 40, located in at least one of the surface portion (As) and margin regions (S1, S2) of the active region (A).

[0064] At least one of the internal electrode layer interface region 20 and dielectric layer interface region 40 located in at least one of the surface region (As) and margin regions (S1, S2) of the active region (A) may contain sulfur (S) in an amount greater than 0 mol% to 1.0 mol% or less relative to the total amount of elements present in that region. In this case, the internal electrode layer interface region 20 in at least one of the surface region (As) and margin regions (S1, S2) of the active region (A) includes the interface between the internal electrode layers 121, 122 and the dielectric layer 111, and the dielectric layer interface region 40 in at least one of the surface region (As) and margin regions (S1, S2) of the active region (A) includes the interface between the dielectric layer 111 and the internal electrode layers 121, 122, and each of these interfaces may be located at a point where the maximum value of the mol% of nickel (Ni), which is the main component of the internal electrode layers 121, 122, is approximately 1 / 2.

[0065] In other words, the internal electrode layer interface region 20 located in at least one of the surface portion (As) and margin regions (S1, S2) of the active region (A) contains sulfur (S) in an amount exceeding 0 mol% to 1.0 mol% or less relative to the total amount of elements present in the internal electrode layer interface region 20, or the dielectric layer interface region 40 located in at least one of the surface portion (As) and margin regions (S1, S2) of the active region (A) contains sulfur (S) in an amount exceeding 0 mol% to 1.0 mol% or less relative to the total amount of elements present in the dielectric layer interface region 40, or both the internal electrode layer interface region 20 and the dielectric layer interface region 40 located in at least one of the surface portion (As) and margin regions (S1, S2) of the active region (A) contain sulfur (S), in which case the sulfur (S) may be contained in an amount exceeding 0 mol% to 1.0 mol% or less relative to the total amount of elements present in each region.

[0066] When sulfur (S) is present in an amount exceeding 0 mol% to 1.0 mol% or less in at least one of the internal electrode layer interface region 20 and dielectric layer interface region 40 in at least one of the surface region (As) of the active region (A) and margin regions (S1, S2), the shrinkage behavior of Ni changes, thereby improving the microstructural characteristics of the internal electrode layer and dielectric layer, and thus improving the connectivity and electrical properties of the internal electrode layer.

[0067] As an example, at least one of the internal electrode layer interface region 20 and dielectric layer interface region 40 located in at least one of the surface region (As) and margin regions (S1, S2) of the active region (A) may contain sulfur (S) in amounts of 0.01 mol% to 0.8 mol%, 0.01 mol% to 0.6 mol%, or 0.01 mol% to 0.4 mol%, respectively, relative to the total amount of elements present in that region.

[0068] Thus, according to one embodiment, the sulfur (S) content at the interface between the internal electrode layers 121 and 122 and the dielectric layer 111 may differ depending on the location within the capacitor body 110. In other words, the sulfur (S) content at the interface between the central part (Ac) of the active region (A) and at least one of the surface portion (As) and margin regions (S1, S2) of the active region (A) may differ. This improves the microstructure characteristics of the internal electrode layer and the dielectric layer, enhances the connectivity of the internal electrode layer, and improves electrical characteristics and reliability.

[0069] At least one of the internal electrode layer interface region 20 and dielectric layer interface region 40 located in the central part (Ac) of the active region (A) may further contain nickel (Ni) in addition to sulfur (S). Furthermore, at least one of the internal electrode layer interface region 20 and dielectric layer interface region 40 located in at least one of the surface region (As) and margin regions (S1, S2) of the active region (A) may further contain nickel (Ni) in addition to sulfur (S).

[0070] The sulfur (S) component and content at the interface between the internal electrode layers 121 and 122 and the dielectric layer 111 can be confirmed by TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) analysis.

[0071] TEM-EDS analysis can be performed in the following way:

[0072] After curing the multilayer ceramic capacitor 100 in an epoxy mixture, the L-axis and T-axis surfaces (LT surfaces) of the capacitor body 110 are polished to half a depth in the W-axis direction to expose the LT cross-section. A cross-sectional sample A is obtained in which the active region (A) where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect is observed in the exposed LT cross-section, and a cross-sectional sample S is obtained in which the margin regions (S1, S2) located at one end of the active region (A) in the L-axis direction (perpendicular to the stacking direction) are observed. Next, the active region (A) of cross-sectional sample A is divided into three equal parts in the T-axis direction (stacking direction) to form the outer surface portion (As) and the central portion (Ac) located between them. In each region, the dielectric layer 111 and the internal electrode layers 121 and 122 are each visible, and the samples are measured by TEM under acceleration voltage of 200kV and magnification conditions of 10k to 100k. Furthermore, the cross-sectional sample S is measured by TEM under an acceleration voltage of 200kV and a magnification of 10k to 100k, such that at least one dielectric layer 111 and internal electrode layers 121 and 122 are visible in the margin regions (S1, S2) of the sample.

[0073] Next, by performing EDS analysis on each TEM image of the cross-sectional sample, the components present at the interface between the dielectric layer 111 and the internal electrode layers 121 and 122 in each region can be confirmed.

[0074] Furthermore, by performing EDS line analysis on the linear section from one point on the internal electrode layers 121 and 122 to one point on the dielectric layer 111 adjacent to the internal electrode layers 121 and 122, using the TEM images of each cross-sectional sample A and the TEM image of cross-sectional sample S, it is possible to confirm the component content at the interface between the internal electrode layers 121 and 122 and the dielectric layer 111 located in the central (Ac) and surface (As) parts of the active region (A), respectively, and the component content at the interface between the internal electrode layers 121 and 122 and the dielectric layer 111 located in the margin regions (S1, S2).

[0075] For example, the component content measured in the central part (Ac) of the active region (A) is obtained by selecting three different sets of internal electrode layers and dielectric layers in the central part of the active region, specifying three arbitrary points within the interface between the internal electrode layer and the dielectric layer for each set of internal electrode layers and dielectric layers, and taking the average value of the component content at a total of nine points. Similarly, the component content measured in the margin regions (S1, S2) is obtained by selecting three different sets of internal electrode layers and dielectric layers in the margin regions, specifying three arbitrary points within the interface between the internal electrode layer and the dielectric layer for each set of internal electrode layers and dielectric layers, and taking the average value of the S content at a total of nine points.

[0076] Furthermore, the EDS line analysis allows us to confirm the internal electrode layer interface region 20 and the dielectric layer interface region 40 in the central (Ac) and surface (As) parts of the active region (A), as well as in the margin regions (S1, S2).

[0077] As an example, when performing TEM-EDS line analysis on a linear section from one point on the internal electrode layers 121 and 122 to one point on the dielectric layer 111 adjacent to the internal electrode layers 121 and 122 in the central part (Ac) of the active region (A), the internal electrode layer interface region 20 in the central part (Ac) of the active region (A) can be defined as the region from a point where the total amount of elements present in the same region is approximately 1 / 2 to 9 / 10 of the maximum value of nickel (Ni) mole percent, and the dielectric layer interface region 40 in the central part (Ac) of the active region (A) can be defined as the region from a point where the total amount of elements present in the same region is approximately 1 / 2 to 1 / 4 of the maximum value of nickel (Ni) mole percent.

[0078] For example, the internal electrode layer interface region 20 in the central part (Ac) of the active region (A) may be a region with a depth of approximately 15 nm to approximately 25 nm, for example, approximately 20 nm, extending from a point that is, for example, approximately 1 / 2 of the maximum value of nickel (Ni) moles, within the internal electrode layers 121 and 122, from the interface between the internal electrode layers 121 and 122. The dielectric layer interface region 40 in the central part (Ac) of the active region (A) may be a region with a depth of approximately 15 nm to approximately 25 nm, for example, approximately 20 nm, extending from a point that is, for example, approximately 1 / 2 of the maximum value of nickel (Ni) moles, within the dielectric layer 111, from the interface between the dielectric layer 111 and the internal electrode layers 121 and 122, from the interface between the dielectric layer 111 and internal electrode layers 121 and 122, within the internal electrode layers 111, from the point that is, for example, approximately 1 / 2 of the maximum value of nickel (Ni) moles.

[0079] Furthermore, from the TEM-EDS line analysis, the internal electrode layer region 10 and the internal electrode layer interface region 20 can be separated from each other based on a point where the maximum value of nickel (Ni) mole percent is approximately 9 / 10, and the internal dielectric layer region 30 and the dielectric layer interface region 40 can be separated from each other based on a point where the maximum value of nickel (Ni) mole percent is approximately 1 / 4.

[0080] As another example, when performing TEM-EDS line analysis on a linear section from one point in the internal electrode layers 121, 122 to one point in the dielectric layer 111 adjacent to the internal electrode layers 121, 122 in at least one of the surface (As) and margin regions (S1, S2) of the active region (A), the internal electrode layer interface region 20 in at least one of the surface (As) and margin regions (S1, S2) of the active region (A) can be defined as the region from a point where the total amount of elements present in the same region is approximately 1 / 2 to 9 / 10 of the maximum value of nickel (Ni) mole percent, and the dielectric layer interface region 40 in at least one of the surface (As) and margin regions (S1, S2) of the active region (A) can be defined as the region from a point where the total amount of elements present in the same region is approximately 1 / 2 to 1 / 10 of the maximum value of nickel (Ni) mole percent.

[0081] For example, the internal electrode layer interface region 20 in at least one of the surface region (As) and margin regions (S1, S2) of the active region (A) may be a region with a depth of approximately 5 nm to approximately 15 nm, for example, approximately 10 nm, extending from a point at which the maximum value of the mole percent of nickel (Ni) is approximately 1 / 2 of the interface between the internal electrode layers 121, 122 and the dielectric layer 111. Similarly, the dielectric layer interface region 40 in at least one of the surface region (As) and margin regions (S1, S2) of the active region (A) may be a region with a depth of approximately 5 nm to approximately 15 nm, for example, approximately 10 nm, extending from a point at which the maximum value of the mole percent of nickel (Ni) is approximately 1 / 2 of the interface between the dielectric layer 111 and the internal electrode layers 121, 122.

[0082] Furthermore, from the TEM-EDS line analysis, the internal electrode layer region 10 and the internal electrode layer interface region 20 can be separated from each other based on a point where the maximum value of nickel (Ni) mole percent is approximately 9 / 10, and the internal dielectric layer region 30 and the dielectric layer interface region 40 can be separated from each other based on a point where the maximum value of nickel (Ni) mole percent is approximately 1 / 10.

[0083] The internal electrode layers 121 and 122 may further contain one or more conductive metals selected from copper (Cu), silver (Ag), palladium (Pd), gold (Au), and alloys thereof, in addition to sulfur-containing nickel.

[0084] The internal electrode layers 121 and 122 can be formed using a conductive paste containing sulfur-containing nickel. The conductive paste can be printed using screen printing or gravure printing.

[0085] The average thickness of the internal electrode layers 121 and 122 may be 0.1 μm to 2 μm.

[0086] The average thickness of the internal electrode layers 121 and 122 can be measured by scanning electron microscopy (SEM) analysis. Specifically, the multilayer ceramic capacitor 100 can be measured by ion milling after curing in an epoxy mixture and then polishing. The SEM can be used to measure the thickness under conditions such as 10kV and 100x magnification, and the measurement can be performed so that at least one, three, five, or ten layers of the internal electrode layers 121 and 122 are shown in the active region where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect. Using the SEM image, the average thickness of the internal electrode layers 121 and 122 can be determined at 10 points separated by a predetermined interval from the reference point, with the reference point being the center point in the length direction (L-axis direction) or width direction (W-axis direction) of the internal electrode layers 121 and 122. The spacing between the 10 points can be adjusted by the scale of the SEM image, for example, between 1 μm and 100 μm, 1 μm and 50 μm, or 1 μm and 10 μm. In this case, all 10 points must be located within the internal electrode layers 121 and 122. If all 10 points are not located within the internal electrode layers 121 and 122, the position of the reference point can be changed or the spacing between the 10 points can be adjusted. Furthermore, by extending this average value measurement to all 10 internal electrode layers and measuring the average value, the average thickness of the internal electrode layers can be further generalized.

[0087] The dielectric layer 111 may mainly contain a barium titanate-based compound containing barium (Ba) and titanium (Ti).

[0088] Barium titanate compounds are dielectric base materials that have a high dielectric constant and contribute to the formation of the dielectric constant of the multilayer ceramic capacitor 100.

[0089] As an example, barium titanate compounds may include one or more selected from BaTiO3, Ba(Ti,Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3, and (Ba,Sr)(Ti,Sn)O3.

[0090] The dielectric layer 111 may further contain minor components. These minor components may further include one or more selected from, for example, manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), and vanadium (V).

[0091] The average thickness (average length in the T-axis direction) of the dielectric layer 111 may be 0.2 μm to 10 μm, for example, 0.2 μm to 8.0 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor is excellent.

[0092] The average thickness of the dielectric layer 111 can be measured by scanning electron microscopy (SEM) analysis. Specifically, the multilayer ceramic capacitor 100 can be cured in an epoxy mixture, polished, ion milled, and then measured by SEM analysis. The SEM can be used to measure under conditions such as 10kV and 100x magnification, and the measurement can be performed so that at least one, three, five, or ten layers of the dielectric layer 111 are shown in the active region where the dielectric layer 111 and the internal electrode layers 121 and 122 intersect. Using the SEM image, the average thickness of the dielectric layer 111 can be determined at 10 points separated by a predetermined interval from the reference point, with the reference point being the center point in the length direction (L-axis direction) or width direction (W-axis direction) of the dielectric layer 111. The interval between the 10 points can be adjusted by the scale of the SEM image, and may be, for example, 1 μm to 100 μm, 1 μm to 50 μm, or 1 μm to 10 μm. In this case, all 10 points must be located within the dielectric layer 111. If all 10 points are not located within the dielectric layer 111, the position of the reference point can be changed or the spacing between the 10 points can be adjusted. Furthermore, by extending this average value measurement to 10 dielectric layers and measuring the average value, the average thickness of the dielectric layers can be further generalized.

[0093] The capacitor body 110 can be formed by firing a laminate in which multiple dielectric layers 111 and internal electrode layers 121 and 122 are stacked.

[0094] The external electrodes 131 and 132, namely the first external electrode 131 and the second external electrode 132, are supplied with voltages of different polarities and can be electrically connected to the exposed portions of the first internal electrode layer 121 and the second internal electrode layer 122, respectively.

[0095] With the above configuration, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge is accumulated between the first internal electrode layer 121 and the second internal electrode layer 122, which are opposite each other. At this time, the capacitance of the multilayer ceramic capacitor 100 will be proportional to the overlapping area of ​​the first internal electrode layer 121 and the second internal electrode layer 122, which overlap each other along the T-axis in the active region.

[0096] The first external electrode 131 and the second external electrode 132 are arranged on the third and fourth surfaces of the capacitor body 110, respectively, and may include first and second connecting portions that connect to the first internal electrode layer 121 and the second internal electrode layer 122, and first and second band portions that are arranged at the corners where the third and fourth surfaces of the capacitor body 110 meet the first and second surfaces or the fifth and sixth surfaces.

[0097] The first and second band portions can extend from the first and second connection portions to the first and second surfaces or the fifth and sixth surfaces of the capacitor body 110, respectively. The first and second band portions can serve to improve the adhesion strength of the first external electrode 131 and the second external electrode 132.

[0098] The external electrodes 131 and 132 may include a sintered metal layer in contact with the capacitor body 110, a conductive resin layer positioned to cover the sintered metal layer, and a plating layer positioned to cover the conductive resin layer.

[0099] The sintered metal layer may contain conductive metals and glass.

[0100] The conductive metal may include one or more selected from copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, copper (Cu) may include copper (Cu) alloys. If the conductive metal includes copper, other metals may be included in amounts of 5 moles or less per 100 moles of copper.

[0101] The glass may contain a composition of mixed oxides, for example, one or more selected from the group consisting of silicon oxide, boron oxide, aluminum oxide, transition metal oxide, alkali metal oxide, and alkaline earth metal oxide. The transition metal may be selected from the group consisting of zinc (Zn), titanium (Ti), copper (Cu), vanadium (V), manganese (Mn), iron (Fe), and nickel (Ni); the alkali metal may be selected from the group consisting of lithium (Li), sodium (Na), and potassium (K); and the alkaline earth metal may be one or more selected from the group consisting of magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba).

[0102] Selectively, the conductive resin layer can be formed on a sintered metal layer, for example, in a form that completely covers the sintered metal layer. On the other hand, the external electrodes 131 and 132 may not include a sintered metal layer, in which case the conductive resin layer can be in direct contact with the capacitor body 110.

[0103] The conductive resin layer extends over the first and second or fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the band portion) in which the conductive resin layer extends over the first and second or fifth and sixth surfaces of the capacitor body 110 may be longer than the length of the region (i.e., the band portion) in which the sintered metal layer extends over the first and second or fifth and sixth surfaces of the capacitor body 110. In other words, the conductive resin layer can be formed on the sintered metal layer and can be formed in a manner that completely covers the sintered metal layer.

[0104] The conductive resin layer contains a resin and a conductive metal.

[0105] The resin contained in the conductive resin layer is not particularly limited as long as it has bonding properties and shock absorption and can be mixed with conductive metal powder to form a paste, and may include, for example, phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0106] The conductive metal contained in the conductive resin layer serves to electrically connect with the internal electrode layers 121, 122, or the sintered metal layer.

[0107] The conductive metal contained in the conductive resin layer may be spherical, flake-shaped, or a combination of these forms. In other words, the conductive metal may consist solely of flake-shaped elements, solely of spherical elements, or a mixture of flake-shaped and spherical elements.

[0108] Here, "spherical" can include forms that are not perfectly spherical, for example, forms in which the ratio of the length of the major axis to the length of the minor axis (major axis / minor axis) is 1.45 or less. "Flake-shaped powder" means powder having a flat and elongated shape and is not particularly limited, but for example, the ratio of the length of the length of the major axis to the length of the minor axis (major axis / minor axis) may be 1.95 or more.

[0109] The external electrodes 131 and 132 may further include a plating layer disposed on the outside of the conductive resin layer.

[0110] The plating layer may include nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), or lead (Pb), either alone or in alloys thereof. For example, the plating layer may be a nickel (Ni) plating layer or a tin (Sn) plating layer, or it may be a configuration in which nickel (Ni) plating layers and tin (Sn) plating layers are sequentially laminated, or it may be a configuration in which tin (Sn) plating layers, nickel (Ni) plating layers, and tin (Sn) plating layers are sequentially laminated. Furthermore, the plating layer may include multiple nickel (Ni) plating layers and / or multiple tin (Sn) plating layers.

[0111] The plating layer can improve the mountability of the multilayer capacitor 100 on the substrate, structural reliability, durability against external elements, heat resistance, and equivalent series resistance (ESR).

[0112] The manufacturing method for the multilayer ceramic capacitor 100 described above will be explained below.

[0113] A multilayer ceramic capacitor 100 according to one embodiment can be manufactured by the following steps: manufacturing a conductive paste using sulfur-containing nickel; manufacturing a dielectric green sheet using a dielectric slurry and printing the conductive paste onto the surface of the dielectric green sheet to form a conductive paste layer; manufacturing a dielectric green sheet laminate by stacking the dielectric green sheets on which the conductive paste layer is formed; heat-treating the dielectric green sheet laminate to desulfurize the sulfur-containing nickel; firing the dielectric green sheet laminate after the heat treatment to manufacture a capacitor body including a dielectric layer and an internal electrode layer; and forming external electrodes on the outside of the capacitor body.

[0114] Sulfur-containing nickel can have a form in which sulfur (S) is coated on the surface of nickel (Ni).

[0115] Sulfur-containing nickel may contain sulfur (S) in amounts ranging from 100 ppm to 2000 ppm, for example, 300 ppm to 1700 ppm, or 500 ppm to 1500 ppm.

[0116] The heat treatment in the desulfurization step can be carried out at a temperature of 900°C to 1500°C, for example, 1000°C to 1300°C, for a period of 0.01 hours to 2.0 hours, for example, 0.1 hours to 2.0 hours. When heat treatment is performed at the above temperature and time range, sulfur (S) can be sufficiently removed from the sulfur-containing nickel, and the sulfur (S) content at the interface between the internal electrode layer and the dielectric layer can be adjusted to a predetermined range.

[0117] In addition to sulfur-containing nickel, conductive paste can also be manufactured by further mixing one or more conductive metals selected from copper (Cu), silver (Ag), palladium (Pd), gold (Au), and their alloys.

[0118] Furthermore, conductive paste can be manufactured by further mixing conductive powder, binder, and solvent. Additionally, barium titanate powder can be mixed in as a co-material if necessary. The co-material can suppress the sintering of the conductive powder during the firing process.

[0119] Dielectric slurry can be manufactured by selectively mixing a barium titanate-based compound, which is the main component powder, with a secondary component powder. The secondary component powder may be an oxide or a salt compound, or it may be used in sol form dispersed in an organic solvent.

[0120] Furthermore, dielectric slurry can be manufactured by further mixing a solvent with additives such as dispersants, binders, plasticizers, lubricants, and antistatic agents.

[0121] The dispersant may include at least one selected from, for example, phosphate ester-based dispersants and polycarboxylic acid-based dispersants. The dispersant can be mixed in an amount of 0.1 to 5 parts by weight per 100 parts by weight of the barium titanate compound, for example, 0.3 to 3 parts by weight. When the dispersant is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0122] The binder may be, for example, an acrylic resin, a polyvinyl butyral resin, a polyvinyl acetal resin, or an ethyl cellulose resin. The binder can be added in an amount of 0.1 to 50 parts by weight per 100 parts by weight of the barium titanate compound, for example, 3 to 30 parts by weight. When the binder is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0123] The plasticizer may be, for example, phthalate compounds such as dioctyl phthalate, benzyl butyl phthalate, dibutyl phthalate, dihexyl phthalate, di(2-ethylhexyl) phthalate, and di(2-ethylbutyl) phthalate; adipic acid compounds such as dihexyl adipic acid and di(2-ethylhexyl) adipic acid; glycol compounds such as ethylene glycol, diethylene glycol, and triethylene glycol; or glycol ester compounds such as triethylene glycol dibutyrate, triethylene glycol di(2-ethylbutyrate), and triethylene glycol di(2-ethylhexanoate). The plasticizer can be added in an amount of 0.1 to 20 parts by weight per 100 parts by weight of the barium titanate compound, for example, 1 to 10 parts by weight. When the plasticizer is mixed within the above content range, the dispersibility of the dielectric slurry is excellent, and the amount of impurities contained in the manufactured dielectric layer can be reduced.

[0124] The solvent may be an aqueous solvent such as water; an alcohol solvent such as ethanol, methanol, benzyl alcohol, or methoxyethanol; a glycol solvent such as ethylene glycol or diethylene glycol; a ketone solvent such as acetone, methyl ethyl ketone, methyl isobutyl ketone, or cyclohexanone; an ester solvent such as butyl acetate, ethyl acetate, carbitol acetate, or butyl carbitol acetate; an ether solvent such as methyl cellosolve, ethyl cellosolve, butyl ether, or tetrahydrofuran; or an aromatic solvent such as benzene, toluene, or xylene. The solvent can be an alcohol or aromatic solvent, for example, considering the solubility and dispersibility of various additives contained in the dielectric slurry. The solvent can be mixed with 50 to 1000 parts by weight of the barium titanate compound per 100 parts by weight, for example, 100 to 500 parts by weight. When the solvent is mixed within the above content range, the dielectric slurry components can be thoroughly mixed, and subsequent removal of the solvent is also easy.

[0125] The aforementioned dielectric slurry can be mixed using a wet ball mill or a stirring mill. When using a wet ball mill with zirconia balls, a large number of zirconia balls with diameters from 0.1 mm to 10 mm can be used for wet mixing for 8 to 48 hours, or 10 to 24 hours.

[0126] The manufactured dielectric slurry is formed into the dielectric layer after firing.

[0127] Methods for forming the manufactured dielectric slurry into a sheet include tape molding methods such as the doctor blade method and the calender roll method, or, for example, an on-roll molding coater with a head discharge system. A dielectric green sheet can then be obtained by drying the molded body.

[0128] A conductive paste layer is formed on the surface of a dielectric green sheet by applying a conductive paste in a predetermined pattern using various printing methods such as screen printing or transfer methods.

[0129] Next, a dielectric green sheet laminate is manufactured by stacking multiple dielectric green sheets with internal electrode patterns formed on them in layers and then pressing them in the stacking direction. At this time, dielectric green sheets and internal electrode patterns can be stacked such that dielectric green sheets are positioned on the upper and lower surfaces of the dielectric green sheet laminate in the stacking direction.

[0130] The step of cutting the manufactured dielectric green sheet laminate to a predetermined size by dicing or other means can be selectively performed.

[0131] Furthermore, the dielectric green sheet laminate can be solidified and dried to remove plasticizers and other substances as needed, and after solidification and drying, it can be barrel polished using a horizontal centrifugal barrel polishing machine or the like. In barrel polishing, the dielectric green sheet laminate is placed in a barrel container along with media and polishing fluid, and rotational motion or vibration is applied to the barrel container to polish away unnecessary parts such as burrs generated during cutting. After barrel polishing, the dielectric green sheet laminate can be washed with a cleaning solution such as water and then dried.

[0132] Next, the dielectric green sheet laminate can be subjected to a binder removal process and firing to manufacture a capacitor body.

[0133] The debinding treatment conditions can be appropriately adjusted depending on the composition of the dielectric layer and the internal electrode layer. For example, the heating rate during debinding may be 5°C / hour to 300°C / hour, the support temperature may be 180°C to 400°C, and the temperature maintenance time may be 0.5 hours to 24 hours. The atmosphere during debinding may be air or a reducing atmosphere.

[0134] The firing conditions can be appropriately adjusted depending on the main component composition of the dielectric layer and the main component composition of the internal electrodes. For example, firing can be carried out at a temperature of 1100°C to 1400°C, for example, at a temperature of 1200°C to 1350°C. Furthermore, firing can be carried out for 0.5 hours to 8 hours, for example, 1 hour to 3 hours. Also, firing can be carried out in a reducing atmosphere, for example, a humidified atmosphere of a mixed gas of nitrogen and hydrogen. Furthermore, firing can be carried out for 10 -12 atm~10 -8 The process can be carried out under atm oxygen partial pressure conditions. When firing is performed under oxygen partial pressure conditions within the aforementioned range, the interfacial resistance between the dielectric layer and the internal electrode layer is high, thus enabling the production of highly reliable multilayer ceramic capacitors.

[0135] After firing, annealing can be performed as needed. Annealing is a process to re-oxidize the dielectric layer, and it can be performed when firing is carried out in a reducing atmosphere. The conditions for the annealing process can also be appropriately adjusted depending on the composition of the dielectric layer. For example, the temperature during annealing may be 950°C to 1150°C, the time may be 0 to 20 hours, and the heating rate may be 50°C / hour to 500°C / hour. The annealing atmosphere may be a humidified nitrogen gas (N2) atmosphere, and the oxygen partial pressure may be 1.0 × 10⁻⁶. -9 MPa to 1.0×10 -5 MPa is also acceptable.

[0136] For humidifying nitrogen gas or mixed gases during debinding, calcination, or annealing, a wetter, for example, can be used, in which case the water temperature may be between 5°C and 75°C. Debinding, calcination, and annealing can be performed continuously or independently.

[0137] Selectively, the third and fourth surfaces of the manufactured capacitor body 110 can be subjected to surface treatments such as sandblasting, laser irradiation, and barrel polishing. By performing such surface treatments, the edges of the first and second internal electrode layers may be exposed on the outermost surfaces of the third and fourth surfaces, thereby improving the electrical connection between the first and second external electrodes and the first and second internal electrode layers, and facilitating the formation of alloy parts.

[0138] Next, an external electrode is formed on one surface of the manufactured capacitor body 110.

[0139] For example, a paste for forming a sintered metal layer can be applied to an external electrode, and then sintered to form a sintered metal layer.

[0140] The paste for forming a sintered metal layer may contain conductive metals and glass. The explanation of conductive metals and glass is the same as described above, so a repeated explanation will be omitted. The paste for forming a sintered metal layer may also selectively contain binders, solvents, dispersants, plasticizers, oxide powders, etc. Binders can be, for example, ethyl cellulose, acrylic, butyral, etc., and solvents can be organic solvents or aqueous solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, toluene, etc.

[0141] Methods for applying the sintered metal layer-forming paste to the outer surface of the capacitor body 110 include various printing methods such as dipping and screen printing, application methods using dispensers, and spraying methods using sprayers. The sintered metal layer-forming paste is applied to at least the third and fourth surfaces of the capacitor body 110, and can also be selectively applied to a portion of the first, second, fifth, or sixth surfaces where the band portions of the first and second external electrodes are formed.

[0142] Subsequently, the capacitor body 110 coated with the paste for forming a sintered metal layer is dried and sintered at a temperature of 700°C to 1000°C for 0.1 to 3 hours to form a sintered metal layer.

[0143] Selectively, a conductive resin layer can be formed by applying a conductive resin layer-forming paste to the outer surface of the obtained capacitor body 110 and then curing it.

[0144] The paste for forming a conductive resin layer may contain a resin and, selectively, a conductive metal or a non-conductive filler. The explanations of conductive metals and resins are the same as those described above, so a repetition of those explanations will be omitted. The paste for forming a conductive resin layer may also selectively contain a binder, solvent, dispersant, plasticizer, oxide powder, etc. Binders can be, for example, ethyl cellulose, acrylic, or butyral, and solvents can be organic solvents such as terpineol, butyl carbitol, alcohol, methyl ethyl ketone, acetone, or toluene, or aqueous solvents.

[0145] As an example, the conductive resin layer can be formed by dipping the capacitor body 110 into a conductive resin layer forming paste and then curing it, printing the conductive resin layer forming paste onto the surface of the capacitor body 110 using screen printing or gravure printing, or applying the conductive resin layer forming paste to the surface of the capacitor body 110 and then curing it.

[0146] Next, a plating layer is formed on the outside of the conductive resin layer.

[0147] For example, the plating layer can be formed by a plating method, and can also be formed by sputtering or electroplating (electric deposition).

[0148] The embodiments described above will be explained in more detail below through the examples. However, the following examples are for illustrative purposes only and do not limit the scope of rights.

[0149] (Manufacturing of multilayer ceramic capacitors) [Example 1] A conductive paste was manufactured using sulfur-containing nickel containing 1000 ppm of sulfur (S).

[0150] Next, a dielectric slurry was prepared using barium titanate (BaTiO3) powder. The dielectric slurry was produced by mechanical milling after adding zirconia balls (ZrO2 balls) as a dispersion medium, along with ethanol / toluene, a dispersant, and a binder.

[0151] Next, a dielectric green sheet was manufactured using a head-dispensing type on-roll molding coater with the manufactured dielectric slurry. The manufactured conductive paste was printed onto the surface of the dielectric green sheet to form a conductive paste layer.

[0152] A dielectric green sheet laminate was manufactured by laminating and pressing dielectric green sheets, each having a conductive paste layer formed on it.

[0153] Each dielectric green sheet laminate underwent a calcination process at 400°C or below and in a nitrogen atmosphere, followed by a desulfurization process at 1100°C. Subsequently, under conditions of a calcination temperature of 1300°C or below, a hydrogen concentration of 1.0%H2 or below, and an oxygen partial pressure of 10% -12 atm~10 -8 The baking process was adjusted within the ATM range.

[0154] Next, external electrodes were formed to manufacture a multilayer ceramic capacitor.

[0155] [Example 2] A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that a desulfurization process was performed by heat treatment at 1000°C.

[0156] [Example 3] A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that a desulfurization process was performed by heat treatment at 1300°C.

[0157] [Example 4] A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that a desulfurization process was performed by heat treatment at 1200°C.

[0158] [Comparative Example 1] A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that the desulfurization process was omitted.

[0159] [Evaluation 1: TEM-EDS line analysis] TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis was performed on the multilayer ceramic capacitors manufactured in Examples 1 to 4 and Comparative Example 1 using the following method.

[0160] After curing the multilayer ceramic capacitor in an epoxy mixture, the L-axis and T-axis surfaces (LT surfaces) of the capacitor body were polished to half a depth in the W-axis direction to expose the LT cross-section. Cross-sectional sample A was obtained, allowing observation of the active region where the dielectric layer and the internal electrode layer intersect in the exposed LT cross-section, and cross-sectional sample S was obtained, allowing observation of the margin region located at one end of the active region in the L-axis direction (perpendicular to the stacking direction). Next, the active region of cross-sectional sample A was divided into three equal parts in the T-axis direction (stacking direction), separating the outer surface portion from the central portion located between them. In each region, TEM measurements were taken under conditions of an acceleration voltage of 200kV and a magnification of 79k, so that at least one dielectric layer and internal electrode layer were visible. Similarly, in the margin region of cross-sectional sample S, TEM measurements were taken under conditions of an acceleration voltage of 200kV and a magnification of 79k, so that at least one dielectric layer and internal electrode layer were visible.

[0161] EDS line analysis was performed on the linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer using the TEM images of each measured cross-sectional sample A and the TEM image of cross-sectional sample S. The results are shown in Figures 7 to 11 and Table 1 below.

[0162] Figures 7 to 10 are TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis graphs for the internal electrode layer and dielectric layer in the central part of the active region according to Examples 1 to 4, respectively. Figure 11 is a TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis graph for the internal electrode layer and dielectric layer in the margin region according to Example 1.

[0163] Referring to Figures 7 to 10 and Table 1 below, in Examples 1 to 4, sulfur (S) is found to be present at the interface between the internal electrode layer and the dielectric layer in the central part of the active region, that is, at the internal electrode layer interface region and the dielectric layer interface region. Furthermore, at least one of the internal electrode layer interface region and the dielectric layer interface region is found to contain sulfur (S) in a content of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in each region. In this case, the S content was obtained by selecting three different sets of internal electrode layers and dielectric layers in the central part of the active region, specifying three arbitrary points within the interface between the internal electrode layer and the dielectric layer for each set of internal electrode layers and dielectric layers, and taking the average value of the S content at a total of nine points.

[0164] Furthermore, according to the obtained EDS line analysis, in the central part of the active region, the internal electrode layer interface region can be identified as the area from approximately 1 / 2 to approximately 9 / 10 of the maximum value of nickel (Ni) mole percent, based on the total amount of elements present in the same region, and the dielectric layer interface region can be identified as the area from approximately 1 / 2 to approximately 1 / 4 of the maximum value of nickel (Ni) mole percent, based on the total amount of elements present in the same region.

[0165] Furthermore, referring to Figure 11, in Example 1, sulfur (S) is found to be present not only at the interface between the internal electrode layer and the dielectric layer in the central part of the active region, but also at the interface between the internal electrode layer and the dielectric layer in the margin region, i.e., in both the internal electrode layer interface region and the dielectric layer interface region. In addition, at least one of the internal electrode layer interface region and the dielectric layer interface region is found to contain sulfur (S) in an amount exceeding 0 mol% to 1.0 mol% or less relative to the total amount of elements present in each region. At this time, the S content was obtained by selecting three different sets of internal electrode layers and dielectric layers in the margin region, specifying three arbitrary points within the interface between the internal electrode layer and the dielectric layer for each set of internal electrode layers and dielectric layers, and taking the average value of the S content at a total of nine points.

[0166] Furthermore, according to the obtained EDS line analysis, in the margin region, the internal electrode layer interface region can be identified as the area from approximately 1 / 2 to approximately 9 / 10 of the maximum value of nickel (Ni) mole percent, based on the total amount of elements present in the same region, and the dielectric layer interface region can be identified as the area from approximately 1 / 2 to approximately 1 / 10 of the maximum value of nickel (Ni) mole percent, based on the total amount of elements present in the same region.

[0167] In Table 1 below, the interface between the internal electrode layer and the dielectric layer refers to at least one of the internal electrode layer interface region within the internal electrode layer and the dielectric layer interface region within the dielectric layer. The sulfur content (mol%) is shown based on the total amount of the element present in each region.

[0168] [Table 1]

[0169] [Evaluation 2: Microstructure of the internal electrode layer] TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) analysis was performed on the multilayer ceramic capacitors manufactured in Example 2, and the results are shown in Figure 12.

[0170] EDS analysis was performed on a TEM image of the central part of the active region of cross-sectional sample A obtained in Evaluation 1.

[0171] Figure 12 shows a TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) analysis image of the central part of the active region according to Example 2.

[0172] Referring to Figure 12, it can be confirmed that in Example 2, the microstructure of the internal electrode layer is improved, and the connectivity of the internal electrode layer is excellent.

[0173] [Evaluation 3: Electrical Characteristics] Capacitance and dielectric breakdown voltage were measured for the multilayer ceramic capacitors manufactured in Examples 1 to 4 and Comparative Example 1, and the results are shown in Table 2 below.

[0174] Capacitance was measured under conditions of a frequency of 1 kHz and a voltage of 0.5 V. In Table 2 below, the capacitance is shown as a percentage relative to the reference capacitance of 220 μF.

[0175] The dielectric breakdown voltage (BDV) was measured for each multilayer ceramic capacitor at room temperature (25°C) under a 100V / s boost condition, and was determined by the voltage value at which the insulation resistance (IR) value dropped to 10,000Ω or less.

[0176] [Rating 4: Reliability] The MTTF (mean time to failure) of the multilayer ceramic capacitors manufactured in Examples 1 to 4 and Comparative Example 1 was measured using the method described below, and the results are shown in Table 2 below.

[0177] The mean time to failure (MTTF) was calculated by measuring the mean time to failure (hr) under conditions of 125°C, 6V voltage, and 48 hours.

[0178] [Table 2]

[0179] Referring to Table 2 above, it can be confirmed that Examples 1 to 4 exhibit superior electrical characteristics and reliability compared to Comparative Example 1. From this, it can be confirmed that, in one embodiment, sulfur (S) is present at the interface between the internal electrode layer and the dielectric layer in the central part of the active region, as well as at least one position in the surface part of the active region and the margin region, and that the sulfur (S) content at the interface between the internal electrode layer and the dielectric layer in the central part of the active region is adjusted to 0.1 mol% or more and less than 2.0 mol%, thereby resulting in superior electrical characteristics and reliability.

[0180] Although preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and can be implemented in various ways within the scope of the claims, description of the invention, and attached drawings, and these also naturally fall within the scope of the present invention. [Explanation of Symbols]

[0181] 10: Internal electrode layer internal area 20: Internal electrode layer interface area 30: Dielectric layer internal region 40: Dielectric layer interface region 100: Multilayer ceramic capacitor 110: Capacitor body 111: Dielectric layer 121: First internal electrode layer 122: Second internal electrode layer 131: 1st external electrode 132:Second external electrode

Claims

1. A capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, The capacitor body includes an active region in which the dielectric layer and the internal electrode layer are alternately stacked, and margin regions arranged at opposite ends of the active region in a direction perpendicular to the stacking direction. The active region is divided into three equal parts in the stacking direction and has a central portion and surface portions located on both sides of the central portion. The internal electrode layer includes an internal electrode layer interface region including the interface with the dielectric layer, The dielectric layer includes a dielectric layer interface region including the interface with the internal electrode layer, At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region contains sulfur (S), A multilayer ceramic capacitor in which at least one of the internal electrode layer interface region and the dielectric layer interface region located in at least one of the surface portion of the active region and the margin region contains sulfur (S).

2. The multilayer ceramic capacitor according to claim 1, wherein at least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region contains sulfur (S) in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in that region.

3. At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region further contains nickel (Ni), During TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis of a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in the central part of the active region, The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layer interface region in the central part of the active region is a region from a point where the total amount of elements present in the same region is 1 / 2 to 9 / 10 of the maximum value of the mole percent of nickel (Ni).

4. At least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region further contains nickel (Ni), During TEM-EDS (transmission electron microscope-energy dispersive spectroscopy) line analysis of a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in the central part of the active region, The multilayer ceramic capacitor according to claim 1, wherein the dielectric layer interface region in the central part of the active region is a region from a point where the total amount of elements present in the same region is 1 / 2 to 1 / 4 of the maximum value of the mole percent of nickel (Ni).

5. The multilayer ceramic capacitor according to claim 1, wherein at least one of the internal electrode layer interface region and the dielectric layer interface region located in the central part of the active region contains sulfur (S) in an amount of 0.1 mol% to 1.2 mol% relative to the total amount of elements present in that region.

6. The multilayer ceramic capacitor according to claim 1, wherein at least one of the internal electrode layer interface region and the dielectric layer interface region located in at least one of the surface portion of the active region and the margin region contains sulfur (S) in an amount of more than 0 mol% to 1.0 mol% or less relative to the total amount of elements present in the region.

7. The surface portion of the active region and at least one of the margin regions, the internal electrode layer interface region and the dielectric layer interface region, further contain nickel (Ni), During TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) line analysis of a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in at least one of the surface portion of the active region and the margin region, The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layer interface region in at least one of the surface portion of the active region and the margin region is a region from a point where the total amount of elements present in the same region is 1 / 2 to 9 / 10 of the maximum value of the mole percent of nickel (Ni).

8. The surface portion of the active region and at least one of the margin regions, the internal electrode layer interface region and the dielectric layer interface region, further contain nickel (Ni), During TEM-EDS (transmission electron microscopy-energy dispersive spectroscopy) line analysis of a linear section from one point in the internal electrode layer to one point in the dielectric layer adjacent to the internal electrode layer in at least one of the surface portion of the active region and the margin region, The multilayer ceramic capacitor according to claim 1, wherein the dielectric layer interface region in at least one of the surface portion of the active region and the margin region is a region from a point where the total amount of elements present in the same region is 1 / 2 to 1 / 10 of the maximum value of the mole percent of nickel (Ni).

9. A capacitor body including a dielectric layer and an internal electrode layer, and an external electrode disposed on the outside of the capacitor body, The capacitor body includes an active region in which the dielectric layer and the internal electrode layer are alternately stacked, and margin regions arranged at opposite ends of the active region in a direction perpendicular to the stacking direction. The active region is divided into three equal parts in the stacking direction and has a central portion and surface portions located on both sides of the central portion. In the central part of the active region, at least one of the regions having a depth of 15 nm to 25 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and the region having a depth of 15 nm to 25 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer, contains sulfur (S). A multilayer ceramic capacitor in which at least one of the surface portion of the active region and the margin region contains sulfur (S), and at least one of the regions having a depth of 5 nm to 15 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and a region having a depth of 5 nm to 15 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer.

10. The multilayer ceramic capacitor according to claim 9, wherein in the central part of the active region, at least one of the regions having a depth of 15 nm to 25 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and the region having a depth of 15 nm to 25 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer, contains sulfur (S) in an amount of 0.1 mol% or more and less than 2.0 mol% relative to the total amount of elements present in each region.

11. The multilayer ceramic capacitor according to claim 9, wherein in the central part of the active region, at least one of the regions having a depth of 15 nm to 25 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and the region having a depth of 15 nm to 25 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer, contains sulfur (S) in an amount of 0.1 mol% to 1.2 mol% relative to the total amount of elements present in each region.

12. The multilayer ceramic capacitor according to claim 9, wherein at least one of the surface portion of the active region and the margin region contains sulfur (S) in an amount greater than 0 mol% to 1.0 mol% or less relative to the total amount of elements present in the region, in a region having a depth of 5 nm to 15 nm from the interface between the internal electrode layer and the dielectric layer into the internal electrode layer, and at least one of the regions having a depth of 5 nm to 15 nm from the interface between the dielectric layer and the internal electrode layer into the dielectric layer.

13. A method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 12, A step of manufacturing a conductive paste using sulfur-containing nickel, The process involves manufacturing a dielectric green sheet using a dielectric slurry, and printing the conductive paste onto the surface of the dielectric green sheet to form a conductive paste layer. The steps include: manufacturing a dielectric green sheet laminate by stacking the dielectric green sheets on which the conductive paste layer is formed; The steps include: heat-treating the dielectric green sheet laminate to desulfurize the sulfur-containing nickel; The steps include: after the heat treatment, firing the dielectric green sheet laminate to manufacture a capacitor body including a dielectric layer and an internal electrode layer; The steps include forming an external electrode on the outside of the capacitor body, A method for manufacturing multilayer ceramic capacitors, including [the specified part of the method].

14. The method for manufacturing a multilayer ceramic capacitor according to claim 13, wherein the sulfur-containing nickel has a form in which sulfur (S) is coated on the surface of nickel (Ni).

15. The method for manufacturing a multilayer ceramic capacitor according to claim 13, wherein the sulfur-containing nickel contains 100 ppm to 2000 ppm of sulfur (S).

16. The method for manufacturing a multilayer ceramic capacitor according to claim 13, wherein the heat treatment is performed at a temperature of 900°C to 1500°C.

17. The method for manufacturing a multilayer ceramic capacitor according to claim 13, wherein the heat treatment is performed for 0.01 hours to 2.0 hours.

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