Memory device

Abstract

This invention provides a memory device for compensating for distance differences and voltage differences to different power sources that cause delays in the enable signal for activating a repeater. [Solution] In the semiconductor system 1, the first control circuit of the memory device generates an output enable signal driven by a first internal voltage based on an output control pulse generated during data output operation, receives a delayed output enable signal driven by a second internal voltage, generates output data from the internal data placed on the global line via a repeater, and outputs it to the data input / output circuit. The second control circuit is located adjacent to the first control circuit and includes a data storage circuit that outputs internal data to the global line during data output operation, and is located adjacent to the data storage circuit and generates a delayed output enable signal based on the output enable signal during data output operation.

Description

Technical Field

[0001] The present invention relates to a memory device for compensating for a distance difference in which an enable signal for activating a repeater is delayed, and a voltage difference with respect to a heterogeneous power supply.

Background Art

[0002] Generally, a memory device such as a DDR SDRAM (Double Data Rate Synchronous DRAM) performs data read and write operations in response to a command input from an external chip set. In order for the memory device to perform such read and write operations, various circuits must be provided inside, and among them, a plurality of repeaters for outputting data placed on input / output lines to the outside are provided. Generally, a plurality of repeaters are arranged in the middle of a long input / output line to drive and output data.

[0003] An enable signal for activating such a repeater is generated by compensating for a distance difference at which data is output. However, when a heterogeneous power supply is used in the memory device, a method for compensating for a voltage difference with respect to the heterogeneous power supply is required.

Summary of the Invention

Means for Solving the Problems

[0004] To this end, the present invention provides a memory device comprising: a first control circuit arranged adjacent to a data input / output circuit, which generates an output enable signal driven by a first internal voltage based on an output control pulse generated during data output operation, receives a delayed output enable signal driven by a second internal voltage, generates the output data from internal data placed on a global line via a repeater, and outputs it to the data input / output circuit; a data storage circuit arranged adjacent to the first control circuit, which outputs the internal data to the global line during the data output operation; and a second control circuit arranged adjacent to the data storage circuit, which generates the delayed output enable signal based on the output enable signal during the data output operation.

[0005] Furthermore, the present invention provides a memory device comprising: a first control circuit arranged adjacent to a data input / output circuit, which detects the edge of the level transition of the output control pulse generated during data output operation, generates a rising-edge output enable signal and a falling-edge output enable signal driven by a first internal voltage, receives a rising-edge delayed output enable signal and a falling-edge delayed output enable signal driven by a second internal voltage, generates the output data from the internal data carried on the global line via a repeater, and outputs it to the data input / output circuit; a data storage circuit arranged adjacent to the first control circuit, which outputs the internal data to the global line during the data output operation; and a second control circuit arranged adjacent to the data storage circuit, which generates the rising-edge delayed output enable signal and the falling-edge delayed output enable signal based on the rising-edge output enable signal and the falling-edge output enable signal during the data output operation.

[0006] Furthermore, the present invention provides a memory device comprising: a first control circuit arranged adjacent to a data input / output circuit, which generates an even output enable signal and an odd output enable signal driven by a first internal voltage based on output control pulses generated during continuously performed first and second data output operations, receives an even delayed output enable signal and an odd delayed output enable signal driven by a second internal voltage, and sequentially generates first and second output data from first and second internal data placed on the global line via a repeater and outputs them to the data input / output circuit; a data storage circuit arranged adjacent to the first control circuit, which outputs the internal data to the global line during the data output operation; and a second control circuit arranged adjacent to the data storage circuit, which generates the even delayed output enable signal based on the even output enable signal during the first data output operation, and generates the odd delayed output enable signal based on the odd output enable signal during the second data output operation. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of a semiconductor system according to an example of the present invention. [Figure 2] This is a block diagram showing an example of a memory device included in a semiconductor system. [Figure 3] This is a block diagram showing an example of a first control circuit included in a memory device. [Figure 4] This is a circuit diagram showing an example of the first data receiver included in the first control circuit. [Figure 5] This block diagram shows an example of a second control circuit included in a memory device. [Figure 6] This is a timing diagram illustrating the operation of a memory device according to an example of the present invention. [Figure 7] This is a block diagram showing an example of a memory device included in a semiconductor system. [Figure 8] This is a block diagram showing an example of a first control circuit included in a memory device. [Figure 9] This is a circuit diagram showing an example of the first data receiver included in the first control circuit. [Figure 10] This block diagram shows an example of a second control circuit included in a memory device. [Figure 11] This is a timing diagram illustrating the operation of a memory device according to an example of the present invention. [Figure 12] This is a timing diagram illustrating the operation of a memory device according to an example of the present invention. [Figure 13] This is a block diagram showing an example of a memory device included in a semiconductor system. [Figure 14] This is a block diagram showing an example of a first control circuit included in a memory device. [Figure 15] This is a block diagram showing an example of an edge detection circuit included in the first control circuit. [Figure 16] This is a circuit diagram showing an example of an even output enable signal generation circuit and an odd output enable signal generation circuit included in an output enable signal generation circuit. [Figure 17] This is a circuit diagram showing an example of the first data receiver included in the first control circuit. [Figure 18] This figure shows an example of a repeater enable signal generation circuit included in the first control circuit. [Figure 19] This block diagram shows an example of a second control circuit included in a memory device. [Figure 20] This is a circuit diagram showing an example of an internal pulse generation circuit included in the second control circuit. [Figure 21] This is a timing diagram illustrating the operation of a memory device according to an example of the present invention. [Figure 22] This is a timing diagram illustrating the operation of a memory device according to an example of the present invention. [Modes for carrying out the invention]

[0008] In the following description of embodiments, the term "predetermined" means that when using parameters in a process or algorithm, the numerical values of the parameters are predetermined. Depending on the embodiment, the numerical values of the parameters may be set when the process or algorithm starts, or may be set during the period when the process or algorithm is performed.

[0009] Terms such as "first" and "second" used to distinguish various components are not limited by the components. For example, the first component may be named the second component, and conversely, the second component may be named the first component.

[0010] When one component is said to be "coupled" or "connected" to another component, it should be understood that it may be directly coupled or coupled through other intervening components. In contrast, the descriptions "directly coupled" and "directly connected" should be understood to mean that one component is directly coupled to another component without further intervening components.

[0011] "Logic high level" and "logic low level" are used to describe the logic level of a signal. A signal having a "logic high level" is distinguished from a signal having a "logic low level". For example, when a signal having a first voltage corresponds to a "logic high level", a signal having a second voltage can correspond to a "logic low level". According to one embodiment, the "logic high level" may be set to a voltage higher than the "logic low level". On the other hand, depending on the embodiment, the logic level of the signal may be set to different logic levels or opposite logic levels. For example, a signal having a logic high level may be set to have a logic low level according to an embodiment, and a signal having a logic low level may be set to have a logic high level according to an embodiment.

[0012] Hereinafter, the present invention will be described in more detail through embodiments. These embodiments are merely for illustrating the present invention, and the scope of protection of the rights of the present invention is not limited by these embodiments.

[0013] As shown in FIG. 1, a semiconductor system 1 according to an embodiment of the present invention can include a controller 10 and a memory device 20.

[0014] The controller 10 can transmit a clock CLK to the memory device 20. The controller 10 can transmit a command address CA to the memory device 20. The controller 10 can transmit data DATA to the memory device 20. The controller 10 can receive data DATA from the memory device 20. The clock CLK can be set as a signal that is periodically toggled to synchronize the operations of the controller 10 and the memory device 20. The command address CA includes a plurality of bits and can be set as a signal including a command for controlling the operation of the memory device 20 and an address for selecting a plurality of memory cells included in the memory circuit 240. The data DATA can be set as a signal for being stored in a plurality of memory cells included in the memory circuit 240.

[0015] The memory device 20 can include a memory circuit 240 and a data input / output circuit 250.

[0016] The memory circuit 240 can include a first control circuit 241, a second control circuit 242, and a data storage circuit 243.

[0017] The first control circuit 241 may be located adjacent to the data input / output circuit 250. Based on the command address CA, the first control circuit 241 can generate an output enable signal (OEN in Figure 2) driven by a first internal voltage (VPERI in Figure 2) using an output control pulse (OCP in Figure 3) that occurs during data output operation. The first control circuit 241 can output the output enable signal (OEN in Figure 2) to the second control circuit 242. The first control circuit 241 can receive a delayed output enable signal (OEND in Figure 2) driven by a second internal voltage (VGIO in Figure 2) from the second control circuit 242. Upon receiving the delayed output enable signal (OEND in Figure 2), the first control circuit 241 can activate the repeater (350A in Figure 3). The first control circuit 241 can generate output data (OUTD in Figure 2) from internal data (ID1 and ID2 in Figure 3) transmitted on the global line (GIO in Figure 3) via a repeater (350A in Figure 3) and output it to the data input / output circuit 250. The first control circuit 241 can adjust the timing at which the repeater (350A in Figure 3) is activated by compensating for the distance difference between the output enable signal (OEN in Figure 2) and the delayed output enable signal (OEND in Figure 2), and the voltage difference between the first internal voltage (VPERI in Figure 2) and the second internal voltage (VGIO in Figure 2).

[0018] The distance difference can be set to the sum of the distance over which the output enable signal (OEN in Figure 2) is output from the first control circuit 241 to the data storage circuit 243 and the second control circuit 242, and the distance over which the delayed output enable signal (OEND in Figure 2) is output from the second control circuit 242 to the data storage circuit 243 and the first control circuit 241.

[0019] The second control circuit 242 may be located adjacent to the data storage circuit 243. When data output operation is performed based on command address CA, the second control circuit 242 can generate a delayed output enable signal (OEND in Figure 2) based on the output enable signal (OEN in Figure 2). When data output operation is performed, the second control circuit 242 can receive an output enable signal (OEN in Figure 2) driven by a first internal voltage (VPERI in Figure 2) from the first control circuit 241. Based on the output enable signal (OEN in Figure 2), the second control circuit 242 can generate a delayed output enable signal (OEND in Figure 2) driven by a second internal voltage (VGIO in Figure 2). The second control circuit 242 can output the delayed output enable signal (OEND in Figure 2) to the first control circuit 241. The second control circuit 242 may be located at a distance from the data input / output circuit 250 equal to the distance between the first control circuit 241 and the data storage circuit 243.

[0020] The data storage circuit 243 may be located adjacent to the first control circuit 241. When the data storage circuit 243 performs a data output operation based on the command address CA, it can output the internal data (ID1 and ID2 in Figure 3) stored inside it via the global line (GIO in Figure 3). Although the data storage circuit 243 is implemented to perform a data output operation, it may also be implemented as a general data storage circuit that stores the internal data (ID1 and ID2 in Figure 3) in multiple memory cells during a data storage operation.

[0021] The data input / output circuit 250 can receive output data (OUTD in Figure 2) from the first control circuit 241 during data output operation. The data input / output circuit 250 can generate data DATA from the output data (OUTD in Figure 2) during data output operation. The data input / output circuit 250 can output data DATA to the controller 10.

[0022] The memory device 20 can perform data output operations based on the command address CA, which is input in synchronization with the clock CLK. During data output operations, the memory device 20 can adjust the timing at which the repeater (350A in Figure 3) is activated by compensating for the distance difference between the output enable signal (OEN in Figure 2) for activating the repeater (350A in Figure 3) and the generation of the delayed output enable signal (OEND in Figure 2), and the voltage difference between the first internal voltage (VPERI in Figure 2) and the second internal voltage (VGIO in Figure 2). During data output operations, when the repeater (350A in Figure 3) is activated, the memory device 20 can generate output data (OUTD in Figure 2) from the internal data (ID1, ID2 in Figure 3) carried on the global line (GIO in Figure 3). During data output operations, the memory device 20 can generate data DATA from the output data (OUTD in Figure 2). The memory device 20 can output data DATA to the controller 10.

[0023] Figure 2 is a block diagram showing an example configuration of a memory device 20 included in semiconductor system 1. The memory device 20A may include a command generation circuit 210A, an internal voltage generation circuit 220A, an output control signal generation circuit 230A, a memory circuit 240A, and a data input / output circuit 250A.

[0024] The command generation circuit 210A can generate an output command OCMD, which is enabled when the command address CA, input in synchronization with the clock CLK, is a combination of logic levels necessary for data output operation. Although the command generation circuit 210A is implemented to generate the output command OCMD, it can be implemented to generate commands to control various operations of the memory device 20, such as active operation, data storage operation, and precharge operation.

[0025] The internal voltage generation circuit 220A can generate a first internal voltage VPERI and a second internal voltage VGIO by receiving an externally supplied power supply voltage VDD and a ground voltage VSS. The internal voltage generation circuit 220A can be implemented as a general voltage generation circuit and can generate the first internal voltage VPERI and the second internal voltage VGIO by reducing the voltage level of the externally supplied power supply voltage VDD. The first internal voltage VPERI can be set to a voltage having a higher voltage level than the second internal voltage VGIO.

[0026] The output control signal generation circuit 230A can receive a first internal voltage VPERI. The output control signal generation circuit 230A can generate an output control signal OCTR that is enabled when the output command OCMD is input. When the output command OCMD is input, the output control signal generation circuit 230A can generate an output control signal OCTR that is driven at the voltage level of the first internal voltage VPERI.

[0027] The memory circuit 240A may include a first control circuit 241A, a second control circuit 242A, a first data storage circuit 243A, and a second data storage circuit 244A.

[0028] The first control circuit 241A may be located adjacent to the data input / output circuit 250A. The first control circuit 241A can receive a first internal voltage VPERI and a second internal voltage VGIO. During data output operation, the first control circuit 241A can generate an output enable signal OEN driven by the first internal voltage VPERI, based on the output control pulse (OCP in Figure 3) that occurs when the output control signal OCTR is enabled. The first control circuit 241A can output the output enable signal OEN to the second control circuit 242A. The first control circuit 241A can receive a delayed output enable signal OEND driven by the second internal voltage VGIO from the second control circuit 242A. Upon receiving the delayed output enable signal OEND, the first control circuit 241A can activate the repeater (350A in Figure 3). The first control circuit 241A can generate output data OUTD from internal data ID1 and ID2 carried on the global line (GIO in Figure 3) via a repeater (350A in Figure 3) and output it to the data input / output circuit 250A. The first control circuit 241A can adjust the timing at which the repeater (350A in Figure 3) is activated by compensating for the distance difference between the output enable signal OEN and the delayed output enable signal OEND, and the voltage difference between the first internal voltage VPERI and the second internal voltage VGIO.

[0029] The distance difference can be set to the sum of the distance over which the output enable signal OEN is output from the first control circuit 241A to the first data storage circuit 243A, the second data storage circuit 244A, and the second control circuit 242A, and the distance over which the delayed output enable signal OEND is output from the second control circuit 242A to the second data storage circuit 244A, the first data storage circuit 243A, and the first control circuit 241A.

[0030] The second control circuit 242A may be located adjacent to the second data storage circuit 244A. The second control circuit 242A can receive the first internal voltage VPERI and the second internal voltage VGIO. When data output is in operation, the second control circuit 242A can generate a delayed output enable signal OEND based on the output enable signal OEN. The second control circuit 242A can generate a delayed output enable signal OEND driven by the second internal voltage VGIO based on the output enable signal OEN. The second control circuit 242A can output the delayed output enable signal OEND to the first control circuit 241A. The second control circuit 242A may be located at a distance from the data input / output circuit 250A equal to the distance between the first control circuit 241A, the first data storage circuit 243A, and the second data storage circuit 244A. When the output control signal OCTR is enabled, the second control circuit 242A can output the second internal data ID2 output from the second data storage circuit 244A to the global line (GIO in Figure 3).

[0031] The first data storage circuit 243A may be located adjacent to the first control circuit 241A. During data output operation, the first data storage circuit 243A can output the first internal data ID1 stored inside it via the global line (GIO in Figure 3). Although the first data storage circuit 243A is implemented to perform data output operation, during data storage operation, it may be implemented as a general data storage circuit that stores the first internal data ID1 in multiple memory cells.

[0032] The second data storage circuit 244A may be located adjacent to the first data storage circuit 243A. During data output operation, the second data storage circuit 244A can output the second internal data ID2 stored inside it via the global line (GIO in Figure 3). Although the second data storage circuit 244A is implemented to perform data output operation, it may also be implemented as a general data storage circuit that stores the second internal data ID2 in multiple memory cells during data storage operation.

[0033] The data input / output circuit 250A can receive output data OUTD from the first control circuit 241A during data output operation. The data input / output circuit 250A can generate data DATA from the output data OUTD during data output operation. The data input / output circuit 250A can output data DATA to the controller 10.

[0034] In one example of the present invention, the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA may be generated at the voltage level of the ground voltage VSS or the second internal voltage VGIO. When the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA are generated at the voltage level of the ground voltage VSS, it signifies a logic low level. When the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA are generated at the voltage level of the second internal voltage VGIO, it signifies a logic high level.

[0035] The memory device 20A can perform data output operations based on the command address CA, which is input in synchronization with the clock CLK. During data output operations, the memory device 20A can adjust the timing at which the repeater (350A in Figure 3) is activated by compensating for the distance difference between the output enable signal OEN, which is used to activate the repeater, and the delayed output enable signal OEND, and the voltage difference between the first internal voltage VPERI and the second internal voltage VGIO. During data output operations, when the repeater (350A in Figure 3) is activated, the memory device 20A can generate output data OUTD from the internal data ID1 and ID2 placed on the global line (GIO in Figure 3). During data output operations, the memory device 20A can generate data DATA from the output data OUTD. The memory device 20A can output data DATA to the controller 10.

[0036] Figure 3 is a block diagram showing an example of a first control circuit 241A included in the memory device 20A. The first control circuit 241A may include a first data control circuit 310A, an edge detection circuit 320A, a first data receiver 330A, a repeater enable signal generation circuit 340A, and a repeater 350A.

[0037] The first data control circuit 310A can receive a first internal voltage VPERI. The first data control circuit 310A can generate an output control pulse OCP which includes a pulse generated based on an output control signal OCTR. The first data control circuit 310A can generate an output control pulse OCP which includes a pulse generated when the output control signal OCTR is enabled. When the output control signal OCTR is enabled, the first data control circuit 310A can generate an output control pulse OCP which includes a pulse generated at the voltage level of the first internal voltage VPERI.

[0038] The edge detection circuit 320A can receive a first internal voltage VPERI. The edge detection circuit 320A can detect the edge where the output control pulse OCP undergoes a level transition and generate an output enable signal OEN. The edge detection circuit 320A can detect the rising edge where the output control pulse OCP undergoes a level transition from a logic low level to a logic high level and generate an output enable signal OEN. When the output control pulse OCP undergoes a level transition from a logic low level to a logic high level, the edge detection circuit 320A can generate an output enable signal OEN that occurs at the voltage level of the first internal voltage VPERI.

[0039] The first data receiver 330A can receive a first internal voltage VPERI. The first data receiver 330A can generate a data control signal DCTR based on a delayed output enable signal OEND driven by a second internal voltage VGIO during the period in which the enable period signal ENT is enabled. The first data receiver 330A can generate a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI when the delayed output enable signal OEND is input to the second internal voltage VGIO during the period in which the enable period signal ENT is enabled. The enable period signal ENT can be set to a signal that is enabled for a predetermined period during data output operation.

[0040] The repeater enable signal generation circuit 340A can receive a first internal voltage VPERI. The repeater enable signal generation circuit 340A can generate a repeater enable signal RPEN by delaying the data control signal DCTR by a delay amount adjusted by the delay code DCD<1:N>. The repeater enable signal generation circuit 340A can generate a repeater enable signal RPEN that occurs at the voltage level of the first internal voltage VPERI by delaying the data control signal DCTR by a delay amount adjusted by the delay code DCD<1:N>. The delay code DCD<1:N> may be generated by a combination of various logic levels to adjust the distance difference. The delay code DCD<1:N> can be set by a signal input from the controller 10 or from a circuit such as a mode register set (MRS) provided inside the memory device 20A.

[0041] Repeater 350A can be activated when the repeater enable signal RPEN is enabled. When the repeater enable signal RPEN is enabled, Repeater 350A can generate output data OUTD from the first internal data ID1 or the second internal data ID2 placed on the global line GIO. When the repeater enable signal RPEN is enabled, Repeater 350A can generate output data OUTD by driving the input / output line IO depending on the logic level of the first internal data ID1 or the second internal data ID2. Repeater 350A can output the output data OUTD to the data input / output circuit 250A via the input / output line IO. The first internal data ID1, the second internal data ID2, and the output data OUTD may be set to general data containing multiple bits.

[0042] Figure 4 is a circuit diagram showing an example of the first data receiver 330A included in the first control circuit 241A.

[0043] The first data receiver 330A may be implemented by a PMOS transistor P31 located between a first internal voltage VPERI and node ND31, which drives node ND31 with the first internal voltage VPERI when the enable period signal ENT is disabled at a logic low level; an NMOS transistor N31 located between node ND31 and node ND32, which discharges the charge of node ND31 when the delayed output enable signal OEND is input to the second internal voltage VGIO; an NMOS transistor N32 located between node ND32 and ground voltage VSS, which discharges the charge of node ND32 to ground voltage VSS when the enable period signal ENT is enabled at a logic high level; and inverters IV31 and IV32 that receive the first internal voltage VPERI, generate a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI when node ND31 is driven at ground voltage VSS, and latch the voltage level of node ND31 when the enable period signal ENT is enabled at a logic high level.

[0044] The first data receiver 330A can generate a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI when the enable period signal ENT is enabled at a logic high level and the delayed output enable signal OEND is input to the second internal voltage VGIO. The first data receiver 330A can generate a data control signal DCTR that is disabled at a logic low level when the enable period signal ENT is disabled at a logic low level.

[0045] Figure 5 is a block diagram showing an example of a second control circuit 242A included in the memory device 20A. The second control circuit 242A may include a second data receiver 410A, an internal pulse generation circuit 420A, a delayed output enable signal generation circuit 430A, a second data control circuit 440A, and a global input / output line driver 450A.

[0046] The second data receiver 410A can receive a first internal voltage VPERI. The second data receiver 410A can generate an internal control signal ICTR based on an output enable signal OEN. When the output enable signal OEN is input to the first internal voltage VPERI, the second data receiver 410A can generate an internal control signal ICTR that occurs at the voltage level of the first internal voltage VPERI. The second data receiver 410A can delay the output enable signal OEN, which has the voltage level of the first internal voltage VPERI, to generate an internal control signal ICTR that has the voltage level of the first internal voltage VPERI.

[0047] The internal pulse generation circuit 420A can receive a first internal voltage VPERI. The internal pulse generation circuit 420A can generate an internal pulse IP based on an internal control signal ICTR. When the internal control signal ICTR is input to the first internal voltage VPERI, the internal pulse generation circuit 420A can generate an internal pulse IP that occurs at the voltage level of the first internal voltage VPERI. The internal pulse generation circuit 420A can delay the internal control signal ICTR having the voltage level of the first internal voltage VPERI to generate an internal pulse IP having the voltage level of the first internal voltage VPERI.

[0048] The delayed output enable signal generation circuit 430A can receive a second internal voltage VGIO. The delayed output enable signal generation circuit 430A can generate a delayed output enable signal OEND based on an internal pulse IP. The delayed output enable signal generation circuit 430A can generate a delayed output enable signal OEND that occurs at the voltage level of the second internal voltage VGIO when an internal pulse IP is input to a first internal voltage VPERI. The delayed output enable signal generation circuit 430A can convert the voltage level of the internal pulse IP having the voltage level of the first internal voltage VPERI to the voltage level of the second internal voltage VGIO, delay the internal pulse IP, and generate a delayed output enable signal OEND having the voltage level of the second internal voltage VGIO.

[0049] The second data control circuit 440A can generate a drive signal GDRV that includes pulses generated based on the output control signal OCTR. The second data control circuit 440A can generate a drive signal GDRV that includes pulses generated when the output control signal OCTR is enabled. The second data control circuit 440A can generate a drive signal GDRV that includes pulses generated when the output control signal OCTR occurs at the voltage level of the first internal voltage VPERI.

[0050] The global input / output line driver 450A can be turned on when a pulse of the drive signal GDRV is input. When a pulse of the drive signal GDRV is input, the global input / output line driver 450A can output the second internal data ID2, which is output from the second data storage circuit 244A, to the global input / output line GIO.

[0051] Figure 6 is a timing diagram illustrating the operation of a memory device 20A according to an example of the present invention. Referring to Figure 6, the data output operation of the memory device 20A will be explained, but after the data output operation to the first data storage circuit 243A is performed, the data output operation to the second data storage circuit 244A will be explained as follows.

[0052] At time T1, when the output control signal OCTR is enabled, the first data control circuit 310A generates an output control pulse OCP which includes a pulse that occurs at the voltage level of the first internal voltage VPERI.

[0053] The edge detection circuit 320A generates an output enable signal OEN, which occurs at the voltage level of the first internal voltage VPERI, when the output control pulse OCP transitions from a logic low level to a logic high level.

[0054] At time T2, the second data receiver 410A delays the output enable signal OEN, which has the voltage level of the first internal voltage VPERI generated at time T1, and generates an internal control signal ICTR, which has the voltage level of the first internal voltage VPERI.

[0055] At time T3, the internal pulse generation circuit 420A delays the internal control signal ICTR, which has the voltage level of the first internal voltage VPERI generated at time T2, to generate an internal pulse IP having the voltage level of the first internal voltage VPERI.

[0056] The first data storage circuit 243A outputs the first internal data ID1 stored inside it via the global line GIO.

[0057] At time T4, the delayed output enable signal generation circuit 430A converts the voltage level of the internal pulse IP, which has the voltage level of the first internal voltage VPERI generated at time T3, to the voltage level of the second internal voltage VGIO, delays the internal pulse IP, and generates a delayed output enable signal OEND, which has the voltage level of the second internal voltage VGIO.

[0058] The first data receiver 330A generates a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI when the delayed output enable signal OEND is input to the second internal voltage VGIO during the period when the enable period signal ENT is enabled at a logic high level.

[0059] At time T5, the repeater enable signal generation circuit 340A delays the data control signal DCTR generated at time T4 by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN which occurs at the voltage level of the first internal voltage VPERI.

[0060] When the repeater enable signal RPEN is enabled, repeater 350A drives the input / output line IO according to the logic level of the first internal data ID1 to generate output data OUTD. Repeater 350A outputs the output data OUTD to the data input / output circuit 250A via the input / output line IO.

[0061] At time T6, the first data control circuit 310A generates an output control pulse OCP which includes a pulse that occurs at the voltage level of the first internal voltage VPERI when the output control signal OCTR is enabled.

[0062] The edge detection circuit 320A generates an output enable signal OEN, which occurs at the voltage level of the first internal voltage VPERI, when the output control pulse OCP transitions from a logic low level to a logic high level.

[0063] At time T7, the second data receiver 410A delays the output enable signal OEN, which has the voltage level of the first internal voltage VPERI generated at time T6, and generates an internal control signal ICTR, which has the voltage level of the first internal voltage VPERI.

[0064] At time T8, the internal pulse generation circuit 420A delays the internal control signal ICTR, which has the voltage level of the first internal voltage VPERI generated at time T7, to generate an internal pulse IP having the voltage level of the first internal voltage VPERI.

[0065] The second data storage circuit 244A outputs the second internal data ID2 stored inside it via the global line GIO.

[0066] At time T9, the delayed output enable signal generation circuit 430A converts the voltage level of the internal pulse IP, which has the voltage level of the first internal voltage VPERI generated at time T8, to the voltage level of the second internal voltage VGIO, delays the internal pulse IP, and generates a delayed output enable signal OEND, which has the voltage level of the second internal voltage VGIO.

[0067] The first data receiver 330A generates a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI when the delayed output enable signal OEND is input to the second internal voltage VGIO during the period when the enable period signal ENT is enabled at a logic high level.

[0068] At time T10, the repeater enable signal generation circuit 340A delays the data control signal DCTR generated at time T9 by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN which occurs at the voltage level of the first internal voltage VPERI.

[0069] When the repeater enable signal RPEN is enabled, repeater 350A drives the input / output line IO according to the logic level of the second internal data ID2 to generate output data OUTD. Repeater 350A outputs the output data OUTD to the data input / output circuit 250A via the input / output line IO.

[0070] A memory device 20A according to this example of the present invention can ensure a margin between data and the enable signal by outputting data while compensating for the distance difference that causes a delay in the enable signal for activating the repeater 350A, and the voltage difference with respect to the different power supplies VPERI and VGIO. By outputting data while compensating for the distance difference that causes a delay in the enable signal for activating the repeater 350A, and the voltage difference with respect to the different power supplies VPERI and VGIO, the memory device 20A can prevent errors from occurring in the data.

[0071] Figure 7 is a block diagram showing an example configuration of a memory device 20 included in the semiconductor system 1. The memory device 20B may include a command generation circuit 210B, an internal voltage generation circuit 220B, an output control signal generation circuit 230B, a memory circuit 240B, and a data input / output circuit 250B.

[0072] The command generation circuit 210B can generate an output command OCMD, which is enabled when the command address CA, input in synchronization with the clock CLK, is a combination of logic levels necessary for data output operation. Although the command generation circuit 210B is implemented to generate the output command OCMD, it can be implemented to generate commands to control various operations of the memory device 20B, such as active operation, data storage operation, and precharge operation.

[0073] The internal voltage generation circuit 220B can generate a first internal voltage VPERI and a second internal voltage VGIO by receiving an externally supplied power supply voltage VDD and a ground voltage VSS. The internal voltage generation circuit 220B can be implemented as a general voltage generation circuit and can generate the first internal voltage VPERI and the second internal voltage VGIO by reducing the voltage level of the externally supplied power supply voltage VDD. The first internal voltage VPERI can be set to a voltage having a higher voltage level than the second internal voltage VGIO.

[0074] The output control signal generation circuit 230B can receive a first internal voltage VPERI. The output control signal generation circuit 230B can generate an output control signal OCTR that is enabled when the output command OCMD is input. When the output command OCMD is input, the output control signal generation circuit 230B can generate an output control signal OCTR that is driven at the voltage level of the first internal voltage VPERI.

[0075] The memory circuit 240B may include a first control circuit 241B, a second control circuit 242B, a first data storage circuit 243B, and a second data storage circuit 244B.

[0076] The first control circuit 241B may be located adjacent to the data input / output circuit 250B. The first control circuit 241B can receive a first internal voltage VPERI and a second internal voltage VGIO. During data output operation, the first control circuit 241B can detect the level transition edge of the output control pulse (OCP in Figure 8) that occurs when the output control signal OCTR is enabled, and generate a rising output enable signal OEN and a falling output enable signal OENF driven by the first internal voltage VPERI. During data output operation, the first control circuit 241B can detect the rising edge of the output control pulse (OCP in Figure 8) that occurs when the output control signal OCTR is enabled, and generate a rising output enable signal OEN driven by the first internal voltage VPERI. During data output operation, the first control circuit 241B can detect the falling edge of the output control pulse (OCP in Figure 8) that occurs when the output control signal OCTR is enabled, and generate a falling output enable signal OENF driven by the first internal voltage VPERI. The first control circuit 241B can output a rising-point output enable signal OEN and a falling-point output enable signal OENF to the second control circuit 242B. The first control circuit 241B can receive a rising-point delayed output enable signal OEND and a falling-point delayed output enable signal OENFD, which are driven by a second internal voltage VGIO, from the second control circuit 242B. Upon receiving the rising-point delayed output enable signal OEND and the falling-point delayed output enable signal OENFD, the first control circuit 241B can activate the repeater (350B in Figure 8). The first control circuit 241B can generate output data OUTD from internal data ID1 and ID2 carried on the global line (GIO in Figure 8) via the repeater (350B in Figure 8) and output it to the data input / output circuit 250B.The first control circuit 241B can adjust the timing at which the repeater (350B in Figure 8) is activated by compensating for the distance difference between the rising-rise output enable signal OEN and the falling-fall output enable signal OENF, which generate the rising-rise delayed output enable signal OEND and the falling-fall delayed output enable signal OENFD, and the voltage difference between the first internal voltage VPERI and the second internal voltage VGIO.

[0077] The distance difference can be set to the sum of the distance over which the rising edge output enable signal OEN and falling edge output enable signal OENF are output from the first control circuit 241B to the first data storage circuit 243B, the second data storage circuit 244B, and the second control circuit 242B, and the distance over which the rising edge delayed output enable signal OEND and falling edge delayed output enable signal OENFD are output from the second control circuit 242B to the second data storage circuit 244B, the first data storage circuit 243B, and the first control circuit 241B.

[0078] The second control circuit 242B may be located adjacent to the second data storage circuit 244B. The second control circuit 242B can receive the first internal voltage VPERI and the second internal voltage VGIO. When data output is in operation, the second control circuit 242B can generate a rising-point delayed output enable signal OEND and a falling-point delayed output enable signal OENFD based on the rising-point output enable signal OEN and the falling-point output enable signal OENF. The second control circuit 242B can generate a rising-point delayed output enable signal OEND and a falling-point delayed output enable signal OENFD driven by the second internal voltage VGIO based on the rising-point output enable signal OEN and the falling-point output enable signal OENF. The second control circuit 242B can output the rising-point delayed output enable signal OEND and the falling-point delayed output enable signal OENFD to the first control circuit 241B. The second control circuit 242B may be located at a distance from the data input / output circuit 250B equal to the distance between the first control circuit 241B, the first data storage circuit 243B and the second data storage circuit 244B. When the output control signal OCTR is enabled, the second control circuit 242B can output the second internal data ID2, which is output from the second data storage circuit 244B, to the global line (GIO in Figure 8).

[0079] The first data storage circuit 243B may be located adjacent to the first control circuit 241B. During data output operation, the first data storage circuit 243B can output the first internal data ID1 stored inside it via the global line (GIO in Figure 8). Although the first data storage circuit 243B is implemented to perform data output operation, during data storage operation, it may be implemented as a general data storage circuit that stores the first internal data ID1 in multiple memory cells.

[0080] The second data storage circuit 244B may be located adjacent to the first data storage circuit 243B. During data output operation, the second data storage circuit 244B can output the second internal data ID2 stored inside it via the global line (GIO in Figure 8). Although the second data storage circuit 244B is implemented to perform data output operation, during data storage operation, it may be implemented as a general data storage circuit that stores the second internal data ID2 in multiple memory cells.

[0081] The data input / output circuit 250B can receive output data OUTD from the first control circuit 241B during data output operation. The data input / output circuit 250B can generate data DATA from the output data OUTD during data output operation. The data input / output circuit 250B can output data DATA to the controller 10.

[0082] In one example of the present invention, the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA may be generated at the voltage level of the ground voltage VSS or the second internal voltage VGIO. When the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA are generated at the voltage level of the ground voltage VSS, it signifies a logic low level. When the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA are generated at the voltage level of the second internal voltage VGIO, it signifies a logic high level.

[0083] The memory device 20B can perform data output operations based on the command address CA, which is input in synchronization with the clock CLK. During data output operation, the memory device 20B detects the level transition edge of the output control pulse (OCP in Figure 8) and generates a rising-side output enable signal OEN and a falling-side output enable signal OENF, which are driven by the first internal voltage VPERI. The memory device 20B can adjust the timing at which the repeater (350B in Figure 8) is activated by compensating for the distance difference between the rising-side output enable signal OEN and the falling-side output enable signal OENF, which generate the rising-side delayed output enable signal OEND and the falling-side delayed output enable signal OENFD, and the voltage difference between the first internal voltage VPERI and the second internal voltage VGIO. During data output operation, when the repeater (350B in Figure 8) is activated, the memory device 20B can generate output data OUTD from the internal data ID1 and ID2 carried on the global line (GIO in Figure 8). During data output operation, the memory device 20B can generate data DATA from the output data OUTD. The memory device 20B can output data DATA to the controller 10.

[0084] Figure 8 is a block diagram showing an example of a first control circuit 241B included in the memory device 20B. The first control circuit 241B may include a first data control circuit 310B, an edge detection circuit 320B, a first data receiver 330B, a repeater enable signal generation circuit 340B, and a repeater 350B.

[0085] The first data control circuit 310B can receive a first internal voltage VPERI. The first data control circuit 310B can generate an output control pulse OCP which includes a pulse generated based on an output control signal OCTR. The first data control circuit 310B can generate an output control pulse OCP which includes a pulse generated when the output control signal OCTR is enabled. When the output control signal OCTR is enabled, the first data control circuit 310B can generate an output control pulse OCP which includes a pulse generated at the voltage level of the first internal voltage VPERI.

[0086] The edge detection circuit 320B can receive a first internal voltage VPERI. The edge detection circuit 320B can detect the edge where the output control pulse OCP undergoes a level transition and generate a rising output enable signal OEN and a falling output enable signal OENF. The edge detection circuit 320B can detect the rising edge where the output control pulse OCP undergoes a level transition from a logic low level to a logic high level and generate a rising output enable signal OEN. When the output control pulse OCP undergoes a level transition from a logic low level to a logic high level, the edge detection circuit 320B can generate a rising output enable signal OEN that occurs at the voltage level of the first internal voltage VPERI. The edge detection circuit 320B can detect the falling edge where the output control pulse OCP undergoes a level transition from a logic high level to a logic low level and generate a falling output enable signal OENF. The edge detection circuit 320A can generate a falling-fall output enable signal OENF that occurs at the voltage level of the first internal voltage VPERI when the output control pulse OCP transitions from a logic high level to a logic low level.

[0087] The first data receiver 330B can receive a first internal voltage VPERI. The first data receiver 330B can generate a data control signal DCTR based on a rising-floor delayed output enable signal OEND and a falling-floor delayed output enable signal OENFD, which are driven by a second internal voltage VGIO, during the period in which the enable period signal ENT is enabled. The first data receiver 330B can generate a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI when the rising-floor delayed output enable signal OEND is input to the second internal voltage VGIO and the falling-floor delayed output enable signal OENFD is input to the second internal voltage VGIO, during the period in which the enable period signal ENT is enabled.

[0088] The repeater enable signal generation circuit 340B can receive a first internal voltage VPERI. The repeater enable signal generation circuit 340B can generate a repeater enable signal RPEN by delaying the data control signal DCTR by a delay amount adjusted by the delay code DCD<1:N>. The repeater enable signal generation circuit 340B can generate a repeater enable signal RPEN that occurs at the voltage level of the first internal voltage VPERI by delaying the data control signal DCTR by a delay amount adjusted by the delay code DCD<1:N>. The delay code DCD<1:N> may be generated by a combination of various logic levels to adjust the distance difference. The delay code DCD<1:N> can be set by a signal input from the controller 10 or from a circuit such as a mode register set (MRS) provided inside the memory device 20B.

[0089] Repeater 350B can be activated when the repeater enable signal RPEN is enabled. When the repeater enable signal RPEN is enabled, Repeater 350B can generate output data OUTD from the first internal data ID1 or the second internal data ID2 placed on the global line GIO. When the repeater enable signal RPEN is enabled, Repeater 350B can generate output data OUTD by driving the input / output line IO depending on the logic level of the first internal data ID1 or the second internal data ID2. Repeater 350B can output the output data OUTD to the data input / output circuit 250B via the input / output line IO. The first internal data ID1, the second internal data ID2, and the output data OUTD may be set to general data containing multiple bits.

[0090] Figure 9 is a circuit diagram showing an example of a first data receiver 330B included in the first control circuit 241B. The first data receiver 330B may include a first drive circuit 331, a second drive circuit 332, and a signal combining circuit 333.

[0091] The first drive circuit 331 may be implemented by a PMOS transistor P32 located between a first internal voltage VPERI and node ND33, which drives node ND33 with the first internal voltage VPERI when the enable period signal ENT is disabled at a logic low level; an NMOS transistor N33 located between node ND33 and node ND34, which discharges the charge of node ND33 when the rise-delay output enable signal OEND is input to the second internal voltage VGIO; an NMOS transistor N34 located between node ND34 and ground voltage VSS, which discharges the charge of node ND34 to ground voltage VSS when the enable period signal ENT is enabled at a logic high level; and inverters IV33 and IV34 that receive the first internal voltage VPERI, generate a rise-off drive signal RDRV that occurs at the voltage level of the first internal voltage VPERI when node ND33 is driven at ground voltage VSS, and latch the voltage level of node ND33 when the enable period signal ENT is enabled at a logic high level.

[0092] The first drive circuit 331 can receive a first internal voltage VPERI. When the enable period signal ENT is disabled at a logic low level, the first drive circuit 331 can generate a rising-side drive signal RDRV that is disabled at a logic low level. When the enable period signal ENT is enabled at a logic high level and the rising-side delayed output enable signal OEND, which is driven by a second internal voltage VGIO, is enabled, the first drive circuit 331 can drive node ND33 to generate a rising-side drive signal RDRV that is enabled at the first internal voltage VPERI.

[0093] The second drive circuit 332 may be implemented by a PMOS transistor P33 located between the first internal voltage VPERI and node ND35, which drives node ND35 with the first internal voltage VPERI when the enable period signal ENT is disabled at a logic low level; an NMOS transistor N35 located between node ND35 and node ND36, which discharges the charge of node ND35 when the falling-fall delayed output enable signal OENFD is input to the second internal voltage VGIO; an NMOS transistor N36 located between node ND36 and ground voltage VSS, which discharges the charge of node ND36 to ground voltage VSS when the enable period signal ENT is enabled at a logic high level; and inverters IV35 and IV36 that receive the first internal voltage VPERI, generate a falling-fall drive signal FDRV that occurs at the voltage level of the first internal voltage VPERI when node ND35 is driven at ground voltage VSS, and latch the voltage level of node ND35 when the enable period signal ENT is enabled at a logic high level.

[0094] The second drive circuit 332 can receive the first internal voltage VPERI. The second drive circuit 332 can generate a falling-fall drive signal FDRV, which is disabled at a logic low level, when the enable period signal ENT is disabled at a logic low level. The second drive circuit 332 can drive node ND35 to generate a falling-fall drive signal FDRV, which is enabled at the first internal voltage VPERI, when the enable period signal ENT is enabled at a logic high level and the falling-fall delayed output enable signal OENFD, which is driven by the second internal voltage VGIO, is enabled.

[0095] The signal synthesis circuit 333 may be implemented using a NAND gate 31 and an inverter IV37.

[0096] The signal combining circuit 333 can receive a first internal voltage VPERI. The signal combining circuit 333 can combine the rising-point drive signal RDRV and the falling-point drive signal FDRV to generate a data control signal DCTR. When the rising-point drive signal RDRV is enabled and the falling-point drive signal FDRV is enabled, the signal combining circuit 333 can generate a data control signal DCTR that is enabled by the first internal voltage VPERI. When either the rising-point drive signal RDRV or the falling-point drive signal FDRV is disabled, the signal combining circuit 333 can generate a data control signal DCTR that is disabled by the ground voltage VSS.

[0097] Figure 10 is a block diagram showing an example of a second control circuit 242B included in the memory device 20B. The second control circuit 242B may include a second data receiver 410B, an internal pulse generation circuit 420B, a delayed output enable signal generation circuit 430B, a second data control circuit 440B, and a global input / output line driver 450B.

[0098] The second data receiver 410B can receive a first internal voltage VPERI. The second data receiver 410B can generate a rising internal control signal ICTR and a falling internal control signal ICTF based on a rising output enable signal OEN and a falling output enable signal OENF. When the rising output enable signal OEN is input to the first internal voltage VPERI, the second data receiver 410B can generate a rising internal control signal ICTR that occurs at the voltage level of the first internal voltage VPERI. The second data receiver 410B can delay the rising output enable signal OEN, which has the voltage level of the first internal voltage VPERI, to generate a rising internal control signal ICTR that has the voltage level of the first internal voltage VPERI. When the falling output enable signal OENF is input to the first internal voltage VPERI, the second data receiver 410B can generate a falling internal control signal ICTF that occurs at the voltage level of the first internal voltage VPERI. The second data receiver 410B can delay the falling-fall output enable signal OENF, which has the voltage level of the first internal voltage VPERI, to generate a falling-fall internal control signal ICTF, which has the voltage level of the first internal voltage VPERI.

[0099] The internal pulse generation circuit 420B can receive a first internal voltage VPERI. The internal pulse generation circuit 420B can generate a rising internal pulse IPR and a falling internal pulse IPF based on a rising internal control signal ICTR and a falling internal control signal ICTF. When the rising internal control signal ICTR is input to the first internal voltage VPERI, the internal pulse generation circuit 420B can generate a rising internal pulse IPR that occurs at the voltage level of the first internal voltage VPERI. The internal pulse generation circuit 420B can delay the rising internal control signal ICTR, which has the voltage level of the first internal voltage VPERI, to generate a rising internal pulse IPR that has the voltage level of the first internal voltage VPERI. When the falling internal control signal ICTF is input to the first internal voltage VPERI, the internal pulse generation circuit 420B can generate a falling internal pulse IPF that occurs at the voltage level of the first internal voltage VPERI. The internal pulse generation circuit 420B can delay a falling internal control signal ICTF having a voltage level of the first internal voltage VPERI to generate a falling internal pulse IPF having a voltage level of the first internal voltage VPERI.

[0100] The delayed output enable signal generation circuit 430B can receive a second internal voltage VGIO. Based on the rising internal pulse IPR and the falling internal pulse IPF, the delayed output enable signal generation circuit 430B can generate a rising delayed output enable signal OEND and a falling delayed output enable signal OENFD. When the rising internal pulse IPR is input to the first internal voltage VPERI, the delayed output enable signal generation circuit 430B can generate a rising delayed output enable signal OEND that occurs at the voltage level of the second internal voltage VGIO. The delayed output enable signal generation circuit 430B can convert the voltage level of the rising internal pulse IPR, which has the voltage level of the first internal voltage VPERI, to the voltage level of the second internal voltage VGIO, delay the rising internal pulse IPR, and generate a rising delayed output enable signal OEND that has the voltage level of the second internal voltage VGIO. The delayed output enable signal generation circuit 430B can generate a falling-down delayed output enable signal OENFD that occurs at the voltage level of the second internal voltage VGIO when a falling-down internal pulse IPF is input to the first internal voltage VPERI. The delayed output enable signal generation circuit 430B can convert the voltage level of the falling-down internal pulse IPF, which has the voltage level of the first internal voltage VPERI, to the voltage level of the second internal voltage VGIO, delay the falling-down internal pulse IPR, and generate a falling-down delayed output enable signal OENFD that has the voltage level of the second internal voltage VGIO.

[0101] The second data control circuit 440B can generate a drive signal GDRV that includes pulses generated based on the output control signal OCTR. The second data control circuit 440B can generate a drive signal GDRV that includes pulses generated when the output control signal OCTR is enabled. The second data control circuit 440B can generate a drive signal GDRV that includes pulses generated when the output control signal OCTR occurs at the voltage level of the first internal voltage VPERI.

[0102] The global input / output line driver 450B can be turned on when a pulse of the drive signal GDRV is input. When a pulse of the drive signal GDRV is input, the global input / output line driver 450B can output the second internal data ID2, which is output from the second data storage circuit 244B, to the global input / output line GIO.

[0103] Figures 11 and 12 are timing diagrams illustrating the operation of a memory device 20B according to an example of the present invention. Referring to Figures 11 and 12, the data output operation of the memory device 20B will be explained, but after the data output operation to the first data storage circuit 243B is performed, the data output operation to the second data storage circuit 244B will be explained as follows.

[0104] At time T11, the first data control circuit 310B generates an output control pulse OCP which includes a pulse that occurs at the voltage level of the first internal voltage VPERI when the output control signal OCTR is enabled.

[0105] The edge detection circuit 320B generates a rising output enable signal OEN that occurs at the voltage level of the first internal voltage VPERI when the output control pulse OCP transitions from a logic low level to a logic high level.

[0106] At T12, the edge detection circuit 320B generates a falling-down output enable signal OENF that occurs at the voltage level of the first internal voltage VPERI when the output control pulse OCP transitions from a logic high level to a logic low level.

[0107] The second data receiver 410B delays the rising-point output enable signal OEN, which has the voltage level of the first internal voltage VPERI generated at time T11, to generate a rising-point internal control signal ICTR, which has the voltage level of the first internal voltage VPERI.

[0108] At time T13, the second data receiver 410B delays the falling-fall output enable signal OENF, which has the voltage level of the first internal voltage VPERI generated at time T12, to generate a falling-fall internal control signal ICTF, which has the voltage level of the first internal voltage VPERI.

[0109] The internal pulse generation circuit 420B delays the rising internal control signal ICTR, which has the voltage level of the first internal voltage VPERI generated at time T12, to generate a rising internal pulse IPR having the voltage level of the first internal voltage VPERI.

[0110] At time T14, the internal pulse generation circuit 420B delays the falling internal control signal ICTF, which has the voltage level of the first internal voltage VPERI generated at time T13, to generate a falling internal pulse IPF, which has the voltage level of the first internal voltage VPERI.

[0111] The delayed output enable signal generation circuit 430B converts the voltage level of the rising internal pulse IPR, which has the voltage level of the first internal voltage VPERI generated at time T13, to the voltage level of the second internal voltage VGIO, delays the rising internal pulse IPR, and generates a rising delayed output enable signal OEND, which has the voltage level of the second internal voltage VGIO.

[0112] The first data receiver 330B generates a rising drive signal RDRV that occurs at the voltage level of the first internal voltage VPERI when the rising delay output enable signal OEND is input to the second internal voltage VGIO during the period when the enable period signal ENT is enabled at a logic high level.

[0113] At time T15, the delayed output enable signal generation circuit 430B converts the voltage level of the falling internal pulse IPF, which has the voltage level of the first internal voltage VPERI generated at time T14, to the voltage level of the second internal voltage VGIO, delays the falling internal pulse IPF, and generates a falling delayed output enable signal OENFD, which has the voltage level of the second internal voltage VGIO.

[0114] The first data receiver 330B generates a falling drive signal FDRV that occurs at the voltage level of the first internal voltage VPERI when the falling delay output enable signal OENFD is input to the second internal voltage VGIO during the period when the enable period signal ENT is enabled at a logic high level.

[0115] The first data receiver 330B combines a rising-point drive signal RDRV that occurs at the voltage level of the first internal voltage VPERI and a falling-point drive signal FDRV that occurs at the voltage level of the first internal voltage VPERI to generate a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI.

[0116] At time T16, the repeater enable signal generation circuit 340B delays the data control signal DCTR generated at time T15 by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN which occurs at the voltage level of the first internal voltage VPERI.

[0117] When the repeater enable signal RPEN is enabled, repeater 350B drives the input / output line IO according to the logic level of the first internal data ID1 to generate output data OUTD. Repeater 350B outputs the output data OUTD to the data input / output circuit 250A via the input / output line IO.

[0118] At time T17, the first data control circuit 310B generates an output control pulse OCP which includes a pulse that occurs at the voltage level of the first internal voltage VPERI when the output control signal OCTR is enabled.

[0119] The edge detection circuit 320B generates a rising output enable signal OEN that occurs at the voltage level of the first internal voltage VPERI when the output control pulse OCP transitions from a logic low level to a logic high level.

[0120] At T18, the edge detection circuit 320B generates a falling-fall output enable signal OENF that occurs at the voltage level of the first internal voltage VPERI when the output control pulse OCP transitions from a logic high level to a logic low level.

[0121] The second data receiver 410B delays the rising-point output enable signal OEN, which has the voltage level of the first internal voltage VPERI generated at time T17, to generate a rising-point internal control signal ICTR, which has the voltage level of the first internal voltage VPERI.

[0122] At time T19, the second data receiver 410B delays the falling-fall output enable signal OENF, which has the voltage level of the first internal voltage VPERI generated at time T18, to generate a falling-fall internal control signal ICTF, which has the voltage level of the first internal voltage VPERI.

[0123] The internal pulse generation circuit 420B delays the rising internal control signal ICTR, which has the voltage level of the first internal voltage VPERI generated at time T18, to generate a rising internal pulse IPR, which has the voltage level of the first internal voltage VPERI.

[0124] At time T20, the internal pulse generation circuit 420B delays the falling-down internal control signal ICTF, which has the voltage level of the first internal voltage VPERI generated at time T19, to generate a falling-down internal pulse IPF, which has the voltage level of the first internal voltage VPERI.

[0125] The delayed output enable signal generation circuit 430B converts the voltage level of the rising internal pulse IPR, which has the voltage level of the first internal voltage VPERI generated at time T19, to the voltage level of the second internal voltage VGIO, delays the rising internal pulse IPR, and generates a rising delayed output enable signal OEND, which has the voltage level of the second internal voltage VGIO.

[0126] The first data receiver 330B generates a rising drive signal RDRV that occurs at the voltage level of the first internal voltage VPERI when the rising delay output enable signal OEND is input to the second internal voltage VGIO during the period when the enable period signal ENT is enabled at a logic high level.

[0127] At time T21, the delayed output enable signal generation circuit 430B converts the voltage level of the falling internal pulse IPF, which has the voltage level of the first internal voltage VPERI generated at time T20, to the voltage level of the second internal voltage VGIO, delays the falling internal pulse IPF, and generates a falling delayed output enable signal OENFD, which has the voltage level of the second internal voltage VGIO.

[0128] The first data receiver 330B generates a falling drive signal FDRV that occurs at the voltage level of the first internal voltage VPERI when the falling delay output enable signal OENFD is input to the second internal voltage VGIO during the period when the enable period signal ENT is enabled at a logic high level.

[0129] The first data receiver 330B combines a rising-point drive signal RDRV that occurs at the voltage level of the first internal voltage VPERI and a falling-point drive signal FDRV that occurs at the voltage level of the first internal voltage VPERI to generate a data control signal DCTR that occurs at the voltage level of the first internal voltage VPERI.

[0130] At time T22, the repeater enable signal generation circuit 340B delays the data control signal DCTR generated at time T21 by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN which occurs at the voltage level of the first internal voltage VPERI.

[0131] When the repeater enable signal RPEN is enabled, repeater 350B drives the input / output line IO according to the logic level of the second internal data ID2 to generate output data OUTD. Repeater 350B outputs the output data OUTD to the data input / output circuit 250A via the input / output line IO.

[0132] A memory device 20B according to this example of the present invention can ensure a margin between data and the enable signal by outputting data while compensating for the distance difference that causes a delay in the enable signal for activating the repeater 350B, and the voltage difference with respect to the different power supplies VPERI and VGIO. By outputting data while compensating for the distance difference that causes a delay in the enable signal for activating the repeater 350B, and the voltage difference with respect to the different power supplies VPERI and VGIO, the memory device 20B can prevent errors from occurring in the data.

[0133] Figure 13 is a block diagram showing an example configuration of a memory device 20 included in semiconductor system 1. The memory device 20C may include a command generation circuit 210C, an internal voltage generation circuit 220C, an output control signal generation circuit 230C, a memory circuit 240C, and a data input / output circuit 250C.

[0134] The command generation circuit 210C can generate an output command OCMD, which is enabled when the command address CA, input in synchronization with the clock CLK, is a combination of logic levels necessary for data output operation. Although the command generation circuit 210C is implemented to generate the output command OCMD, it can be implemented to generate commands to control various operations of the memory device 20C, such as active operation, data storage operation, and precharge operation.

[0135] The internal voltage generation circuit 220C can generate a first internal voltage VPERI and a second internal voltage VGIO by receiving an externally supplied power supply voltage VDD and a ground voltage VSS. The internal voltage generation circuit 220C can be implemented as a general voltage generation circuit and can generate the first internal voltage VPERI and the second internal voltage VGIO by reducing the voltage level of the externally supplied power supply voltage VDD. The first internal voltage VPERI can be set to a voltage having a higher voltage level than the second internal voltage VGIO.

[0136] The output control signal generation circuit 230C can receive a first internal voltage VPERI. The output control signal generation circuit 230C can generate an output control signal OCTR that is enabled when the output command OCMD is input. When the output command OCMD is input, the output control signal generation circuit 230C can generate an output control signal OCTR that is driven at the voltage level of the first internal voltage VPERI.

[0137] The memory circuit 240C may include a first control circuit 241C, a second control circuit 242C, a first data storage circuit 243C, and a second data storage circuit 244C.

[0138] The first control circuit 241C may be located adjacent to the data input / output circuit 250C. The first control circuit 241C can receive a first internal voltage VPERI and a second internal voltage VGIO. During data output operation, the first control circuit 241C can generate an even output enable signal EN_EV and an odd output enable signal EN_OD driven by the first internal voltage VPERI, based on the output control pulse (OCP in Figure 14) that occurs when the output control signal OCTR is enabled. During first data output operation, the first control circuit 241C can detect the rising edge of the output control pulse (OCP in Figure 14) that occurs when the output control signal OCTR is enabled, and generate an even output enable signal EN_EV driven by the first internal voltage VPERI. During second data output operation, the first control circuit 241C can detect the rising edge of the output control pulse (OCP in Figure 14) that occurs when the output control signal OCTR is enabled, and generate an odd output enable signal EN_OD. The first control circuit 241C can detect the rising edge of the output control pulse (OCP in Figure 14) that occurs when the output control signal OCTR is enabled during the third data output operation, and generate an even output enable signal EN_EV driven by the first internal voltage VPERI. The first control circuit 241C can detect the rising edge of the output control pulse (OCP in Figure 14) that occurs when the output control signal OCTR is enabled during the fourth data output operation, and generate an odd output enable signal EN_OD. The first data output operation, second data output operation, third data output operation, and fourth data output operation refer to data output operations that are performed sequentially. The first control circuit 241C can output the even output enable signal EN_EV and the odd output enable signal EN_OD to the second control circuit 242C. The first control circuit 241C can receive the even delayed output enable signal EN_EVD and the odd delayed output enable signal EN_ODD from the second control circuit 242C, which are driven by the second internal voltage VGIO.The first control circuit 241C can receive the even-delayed output enable signal EN_EVD and the odd-delayed output enable signal EN_ODD and activate the repeater (350C in Figure 14). The first control circuit 241C can generate output data OUTD from the internal data ID1 and ID2 carried on the global line (GIO in Figure 14) via the repeater (350C in Figure 14) and output it to the data input / output circuit 250C. The first control circuit 241C can adjust the timing at which the repeater (350C in Figure 14) is activated by compensating for the distance difference between the even-delayed output enable signal EN_EVD and the odd-delayed output enable signal EN_ODD being generated from the even-delayed output enable signal EN_EVD and the odd-delayed output enable signal EN_ODD, and the voltage difference between the first internal voltage VPERI and the second internal voltage VGIO.

[0139] The distance difference can be set to the sum of the distance over which the even output enable signal EN_EV and the odd output enable signal EN_OD are output from the first control circuit 241C to the first data storage circuit 243C, the second data storage circuit 244C, and the second control circuit 242C, and the distance over which the even delayed output enable signal EN_EVD and the odd delayed output enable signal EN_ODD are output from the second control circuit 242C to the second data storage circuit 244C, the first data storage circuit 243C, and the first control circuit 241C.

[0140] The second control circuit 242C may be located adjacent to the second data storage circuit 244C. The second control circuit 242C can receive a first internal voltage VPERI and a second internal voltage VGIO. When data output is in operation, the second control circuit 242C can generate an even-delayed output enable signal EN_EVD and an odd-delayed output enable signal EN_ODD based on the even-output enable signal EN_EV and the odd-output enable signal EN_OD. The second control circuit 242C can generate an even-delayed output enable signal EN_EVD and an odd-delayed output enable signal EN_ODD driven by the second internal voltage VGIO based on the even-output enable signal EN_EV and the odd-output enable signal EN_OD. The second control circuit 242C can output the even-delayed output enable signal EN_EVD and the odd-delayed output enable signal EN_ODD to the first control circuit 241C. The second control circuit 242C may be positioned at a distance equal to the distance between the first control circuit 241C, the first data storage circuit 243C, and the second data storage circuit 244C from the data input / output circuit 250C. When the output control signal OCTR is enabled, the second control circuit 242C can output the second internal data ID2 output from the second data storage circuit 244C to the global line (GIO in Figure 14).

[0141] The first data storage circuit 243C may be located adjacent to the first control circuit 241C. During the first data output operation and the third data output operation, the first data storage circuit 243C can output the first internal data ID1 stored inside it via the global line (GIO in Figure 14). Although the first data storage circuit 243C is implemented to perform data output operations, it may be implemented as a general data storage circuit that stores the first internal data ID1 in multiple memory cells during data storage operations.

[0142] The second data storage circuit 244C may be located adjacent to the first data storage circuit 243C. During the second data output operation and the fourth data output operation, the second data storage circuit 244C can output the second internal data ID2 stored inside it via the global line (GIO in Figure 14). Although the second data storage circuit 244C is implemented to perform data output operations, it may be implemented as a general data storage circuit that stores the second internal data ID2 in multiple memory cells during data storage operations.

[0143] The data input / output circuit 250C can receive output data OUTD from the first control circuit 241C during the first data output operation, second data output operation, third data output operation, and fourth data output operation. The data input / output circuit 250C can generate data DATA from the output data OUTD during the first data output operation, second data output operation, third data output operation, and fourth data output operation. The data input / output circuit 250C can output data DATA to the controller 10.

[0144] In one example of the present invention, the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA may be generated at the voltage level of the ground voltage VSS or the second internal voltage VGIO. When the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA are generated at the voltage level of the ground voltage VSS, it signifies a logic low level. When the first internal data ID1, the second internal data ID2, the output data OUTD, and the data DATA are generated at the voltage level of the second internal voltage VGIO, it signifies a logic high level.

[0145] The memory device 20C can perform first, second, third, and fourth data output operations based on the command address CA, which is input in synchronization with the clock CLK. During the first and third data output operations, the memory device 20C can detect the edge of the level transition of the output control pulse (OCP in Figure 14) and generate an even output enable signal EN_EV driven by the first internal voltage VPERI. During the second and fourth data output operations, the memory device 20C can detect the edge of the level transition of the output control pulse (OCP in Figure 14) and generate an odd output enable signal EN_OD driven by the first internal voltage VPERI. The memory device 20C can adjust the timing at which the repeater (350C in Figure 14) is activated by compensating for the distance difference between the even output enable signal EN_EV and the odd output enable signal EN_OD, which generate the even delayed output enable signal EN_EVD and the odd delayed output enable signal EN_ODD, and the voltage difference between the first internal voltage VPERI and the second internal voltage VGIO. During the first, second, third, and fourth data output operations, when the repeater (350C in Figure 14) is activated, the memory device 20C can generate output data OUTD from the internal data ID1 and ID2 carried on the global line (GIO in Figure 14). During the first, second, third, and fourth data output operations, the memory device 20C can generate data DATA from the output data OUTD. The memory device 20C can output data DATA to the controller 10.

[0146] Figure 14 is a block diagram showing an example of a first control circuit 241C included in the memory device 20C. The first control circuit 241C may include a first data control circuit 310C, an edge detection circuit 320C, a first data receiver 330C, a repeater enable signal generation circuit 340C, and a repeater 350C.

[0147] The first data control circuit 310C can receive a first internal voltage VPERI. The first data control circuit 310C can generate an output control pulse OCP which includes a pulse generated based on an output control signal OCTR. The first data control circuit 310C can generate an output control pulse OCP which includes a pulse generated each time the output control signal OCTR is enabled. For example, when a first data output operation is performed, the first data control circuit 310C can generate the first pulse of the output control pulse OCP when the output control signal OCTR is enabled once during the first data output operation. When the first data output operation and the second data output operation are performed consecutively, the first data control circuit 310C can generate the first pulse of the output control pulse OCP and then the second pulse when the output control signal OCTR is enabled twice. When the first data output operation, the second data output operation, and the third data output operation are performed consecutively, the first data control circuit 310C can generate the first pulse of the output control pulse OCP, then the second pulse, and then the third pulse, when the output control signal OCTR is enabled three times. When the first data output operation, the second data output operation, the third data output operation, and the fourth data output operation are performed consecutively, the first data control circuit 310C can generate the first pulse of the output control pulse OCP, then the second pulse, and then the third pulse, when the output control signal OCTR is enabled four times. The first data control circuit 310C can generate an output control pulse OCP that includes a pulse generated at the voltage level of the first internal voltage VPERI each time the output control signal OCTR is enabled.

[0148] The edge detection circuit 320C can receive a first internal voltage VPERI. The edge detection circuit 320B can detect the level transition edge of the output control pulse OCP and generate an even output enable signal EN_EV and an odd output enable signal EN_OD. The edge detection circuit 320C can detect the rising edge of the first pulse of the output control pulse OCP transitioning from a logic low level to a logic high level and generate an even output enable signal EN_EV. The edge detection circuit 320C can generate an even output enable signal EN_EV that occurs at the voltage level of the first internal voltage VPERI when the first pulse of the output control pulse OCP transitions from a logic low level to a logic high level. The edge detection circuit 320C can detect the rising edge of the second pulse of the output control pulse OCP transitioning from a logic low level to a logic high level and generate an odd output enable signal EN_OD. The edge detection circuit 320C can generate an odd output enable signal EN_OD, which occurs at the voltage level of the first internal voltage VPERI, when the second pulse of the output control pulse OCP transitions from a logic low level to a logic high level. The edge detection circuit 320C can generate an even output enable signal EN_EV, which occurs when the third pulse of the output control pulse OCP transitions from a logic low level to a logic high level, by detecting the rising edge. The edge detection circuit 320C can generate an even output enable signal EN_EV, which occurs at the voltage level of the first internal voltage VPERI, when the third pulse of the output control pulse OCP transitions from a logic low level to a logic high level. The edge detection circuit 320C can generate an odd output enable signal EN_OD, which occurs when the fourth pulse of the output control pulse OCP transitions from a logic low level to a logic high level, by detecting the rising edge. The edge detection circuit 320C can generate an odd output enable signal EN_OD, which occurs at the voltage level of the first internal voltage VPERI, when the fourth pulse of the output control pulse OCP transitions from a logic low level to a logic high level.

[0149] The first data receiver 330C can receive a first internal voltage VPERI. The first data receiver 330C can generate even data control signal DCTR_EV and odd data control signal DCTR_OD based on an even delayed output enable signal EN_EVD and an odd delayed output enable signal EN_ODD driven by a second internal voltage VGIO during the period in which the enable period signal ENT is enabled. The first data receiver 330C can generate an even data control signal DCTR_EV that occurs at the voltage level of the first internal voltage VPERI when the even delayed output enable signal EN_EVD is input to the second internal voltage VGIO during the period in which the enable period signal ENT is enabled. The first data receiver 330C can generate an odd data control signal DCTR_OD that occurs at the voltage level of the first internal voltage VPERI when the odd delayed output enable signal EN_ODD is input to the second internal voltage VGIO during the period in which the enable period signal ENT is enabled.

[0150] The repeater enable signal generation circuit 340C can receive a first internal voltage VPERI. The repeater enable signal generation circuit 340C can generate a repeater enable signal RPEN by delaying either the even data control signal DCTR_EV or the odd data control signal DCTR_OD by a delay amount adjusted by the delay code DCD<1:N>. The repeater enable signal generation circuit 340C can generate a repeater enable signal RPEN occurring at the voltage level of the first internal voltage VPERI by delaying either the even data control signal DCTR_EN or the odd data control signal DCTR_OD by a delay amount adjusted by the delay code DCD<1:N>. The delay code DCD<1:N> may be generated by a combination of various logic levels to adjust the distance difference. The delay code DCD<1:N> can be set by a signal input from the controller 10 or from a circuit such as a mode register set (MRS) located inside the memory device 20C.

[0151] Repeater 350C can be activated when the repeater enable signal RPEN is enabled. When the repeater enable signal RPEN is enabled, Repeater 350C can generate output data OUTD from the first internal data ID1 or the second internal data ID2 placed on the global line GIO. When the repeater enable signal RPEN is enabled, Repeater 350C can generate output data OUTD by driving the input / output line IO depending on the logic level of the first internal data ID1 or the second internal data ID2. Repeater 350C can output the output data OUTD to the data input / output circuit 250C via the input / output line IO. The first internal data ID1, the second internal data ID2, and the output data OUTD may be set to general data containing multiple bits.

[0152] Figure 15 is a block diagram showing an example of an edge detection circuit 320C included in the first control circuit 241C. The edge detection circuit 320C may include an even-odd detection circuit 510C and an output enable signal generation circuit 520C.

[0153] The even-odd detection circuit 510C may include an even-odd detection signal generation circuit 511 and a pulse signal generation circuit 512.

[0154] The even-odd detection signal generation circuit 511 can generate an even detection signal EV and an odd detection signal OD based on the pulses of the output control pulse OCP. The even-odd detection signal generation circuit 511 can generate an even detection signal EV that is enabled at the voltage level of the first internal voltage VPERI when the first pulse of the output control pulse OCP undergoes a level transition. The even-odd detection signal generation circuit 511 can generate an odd detection signal OD that is enabled at the voltage level of the first internal voltage VPERI when the second pulse of the output control pulse OCP undergoes a level transition. The even-odd detection signal generation circuit 511 can generate an even detection signal EV that is enabled at the voltage level of the first internal voltage VPERI when the third pulse of the output control pulse OCP undergoes a level transition. The even-odd detection signal generation circuit 511 can generate an odd detection signal OD that is enabled at the voltage level of the first internal voltage VPERI when the fourth pulse of the output control pulse OCP undergoes a level transition.

[0155] The pulse signal generation circuit 512 can generate an even pulse signal EVP and an odd pulse signal ODP based on an even detection signal EV, an odd detection signal OD, and an output control pulse OCP. The pulse signal generation circuit 512 can generate an even pulse signal EVP based on the output control pulse OCP during the period when the even detection signal EV is enabled. The pulse signal generation circuit 512 can generate an even pulse signal EVP when the first pulse of the output control pulse OCP occurs during the period when the even detection signal EV is enabled. The pulse signal generation circuit 512 can generate an even pulse signal EVP when the third pulse of the output control pulse OCP occurs during the period when the even detection signal EV is enabled. The pulse signal generation circuit 512 can generate an odd pulse signal ODP based on the output control pulse OCP during the period when the odd detection signal OD is enabled. The pulse signal generation circuit 512 can generate an odd pulse signal ODP when the second pulse of the output control pulse OCP occurs during the period when the odd detection signal OD is enabled. The pulse signal generation circuit 512 can generate an odd pulse signal ODP when the fourth pulse of the output control pulse OCP occurs during the period when the odd detection signal OD is enabled.

[0156] The output enable signal generation circuit 520C may include an even output enable signal generation circuit 521 and an odd output enable signal generation circuit 522.

[0157] The even output enable signal generation circuit 521 can receive a first internal voltage VPERI. The even output enable signal generation circuit 521 can generate an even output enable signal EN_EV based on an even pulse signal EVP and an odd pulse signal ODP. The even output enable signal generation circuit 521 can generate an even output enable signal EN_EV that is enabled from the time the even pulse signal EVP is enabled until the time the odd pulse signal ODP is enabled. The even output enable signal generation circuit 521 can generate an even output enable signal EN_EV that is driven at the voltage level of the first internal voltage VPERI from the time the even pulse signal EVP is enabled until the time the odd pulse signal ODP is enabled.

[0158] The odd output enable signal generation circuit 522 can receive a first internal voltage VPERI. The odd output enable signal generation circuit 522 can generate an odd output enable signal EN_OD based on an odd pulse signal ODP and an even pulse signal EVP. The odd output enable signal generation circuit 522 can generate an odd output enable signal EN_OD that is enabled from the time the odd pulse signal ODP is enabled until the time the even pulse signal EVP is enabled. The even output enable signal generation circuit 521 can generate an odd output enable signal EN_OD that is driven at the voltage level of the first internal voltage VPERI from the time the odd pulse signal ODP is enabled until the time the even pulse signal EVP is enabled.

[0159] Figure 16 is a circuit diagram showing an example of the even output enable signal generation circuit 521 and the odd output enable signal generation circuit 522 included in the output enable signal generation circuit 520C.

[0160] The even output enable signal generation circuit 521 may be implemented with inverters IV51, IV52 and NAND gates NAND51, NAND52. The even output enable signal generation circuit 521 can receive a first internal voltage VPERI. When the even pulse signal EVP is enabled at a logic high level, the even output enable signal EN_EV can be generated, which is driven at the voltage level of the first internal voltage VPERI. When the odd pulse signal ODP is enabled at a logic high level, the even output enable signal EN_EV can be generated, which is driven at the voltage level of the ground voltage VSS. The even output enable signal generation circuit 521 can generate an even output enable signal EN_EV that is enabled from the time the even pulse signal EVP is enabled at a logic high level until the time the odd pulse signal ODP is enabled at a logic high level.

[0161] The odd output enable signal generation circuit 522 may be implemented with inverters IV53, IV54 and NAND gates NAND53, NAND54. The odd output enable signal generation circuit 522 can receive a first internal voltage VPERI. When the odd pulse signal ODP is enabled at a logic high level, the odd output enable signal EN_OD can be generated, which is driven at the voltage level of the first internal voltage VPERI. When the even pulse signal EVP is enabled at a logic high level, the odd output enable signal EN_OD can be generated, which is driven at the voltage level of the ground voltage VSS. The odd output enable signal generation circuit 522 can generate an odd output enable signal EN_OD that is enabled from the time the odd pulse signal ODP is enabled at a logic high level until the time the even pulse signal EVP is enabled at a logic high level.

[0162] Figure 17 is a circuit diagram showing an example of a first data receiver 330C included in the first control circuit 241C. The first data receiver 330C may include a first drive circuit 610C and a second drive circuit 620C.

[0163] The first drive circuit 610C may be implemented by a PMOS transistor P61 located between a first internal voltage VPERI and node ND61, which drives node ND61 with the first internal voltage VPERI when the enable period signal ENT is disabled at a logic low level; an NMOS transistor N61 located between node ND61 and node ND62, which discharges the charge of node ND61 when the even-delayed output enable signal EN_EVD is input to the second internal voltage VGIO; an NMOS transistor N62 located between node ND62 and ground voltage VSS, which discharges the charge of node ND62 to ground voltage VSS when the enable period signal ENT is enabled at a logic high level; and inverters IV61 and IV62 that receive the first internal voltage VPERI, generate an even data control signal DCTR_EV that occurs at the voltage level of the first internal voltage VPERI when node ND61 is driven at ground voltage VSS, and latch the voltage level of node ND61 when the enable period signal ENT is enabled at a logic high level.

[0164] The first drive circuit 610C can receive a first internal voltage VPERI. When the enable period signal ENT is disabled at a logic low level, the first drive circuit 610C can generate an even data control signal DCTR_EV that is disabled at a logic low level. When the enable period signal ENT is enabled at a logic high level and the even delayed output enable signal EN_EVD, driven by a second internal voltage VGIO, is enabled, the first drive circuit 610C can drive node ND61 to generate an even data control signal DCTR_EV that is enabled at the first internal voltage VPERI.

[0165] The second drive circuit 620C may be implemented by a PMOS transistor P62 located between the first internal voltage VPERI and node ND63, which drives node ND63 with the first internal voltage VPERI when the enable period signal ENT is disabled at a logic low level; an NMOS transistor N63 located between node ND63 and node ND64, which discharges the charge of node ND63 when the odd delayed output enable signal EN_ODD is input to the second internal voltage VGIO; an NMOS transistor N64 located between node ND64 and ground voltage VSS, which discharges the charge of node ND64 to ground voltage VSS when the enable period signal ENT is enabled at a logic high level; and inverters IV63 and IV64 that receive the first internal voltage VPERI, generate an odd data control signal DCTR_OD that occurs at the voltage level of the first internal voltage VPERI when node ND63 is driven at ground voltage VSS, and latch the voltage level of node ND63 when the enable period signal ENT is enabled at a logic high level.

[0166] The second drive circuit 620C can receive the first internal voltage VPERI. The second drive circuit 620C can generate an odd data control signal DCTR_OD, which is disabled at a logic low level when the enable period signal ENT is disabled at a logic low level. The second drive circuit 620C can drive node ND63 to generate an odd data control signal DCTR_OD, which is enabled at the first internal voltage VPERI, when the enable period signal ENT is enabled at a logic high level and the odd delay output enable signal EN_ODD, which is driven by the second internal voltage VGIO, is enabled.

[0167] Figure 18 shows an example of a repeater enable signal generation circuit 340C included in the first control circuit 241C. The repeater enable signal generation circuit 340C may include a signal synthesis circuit 630C and a delay circuit 640C.

[0168] The signal combining circuit 630C may be implemented with an OR gate OR61. The signal combining circuit 630C can receive a first internal voltage VPERI. The signal combining circuit 630C can combine the even data control signal DCTR_EV and the odd data control signal DCTR_OD to generate a combined output enable signal SCTR. The signal combining circuit 630C can generate a combined output enable signal SCTR that is enabled by the first internal voltage VPERI when either the even data control signal DCTR_EV or the odd data control signal DCTR_OD is enabled.

[0169] The delay circuit 640C can receive a first internal voltage VPERI. The delay circuit 640C can delay the composite output enable signal SCTR by a delay amount adjusted by the delay code DCD<1:N> to generate a repeater enable signal RPEN. The delay circuit 640C can delay the composite output enable signal SCTR by a delay amount adjusted by the delay code DCD<1:N> to generate a repeater enable signal RPEN that occurs at the voltage level of the first internal voltage VPERI. The delay code DCD<1:N> may be generated by a combination of various logic levels to adjust the distance difference. The delay code DCD<1:N> can be set by a signal input from the controller 10 or from a circuit such as a mode register set (MRS) located inside the memory device 20C.

[0170] The repeater enable signal generation circuit 340C can receive a first internal voltage VPERI. The repeater enable signal generation circuit 340C can generate the repeater enable signal RPEN by delaying either the even data control signal DCTR_EV or the odd data control signal DCTR_OD by a delay amount adjusted by the delay code DCD<1:N>.

[0171] Figure 19 is a block diagram showing an example of a second control circuit 242C included in the memory device 20C. The second control circuit 242C may include a second data receiver 410C, an internal pulse generation circuit 420C, a delayed output enable signal generation circuit 430C, a second data control circuit 440C, and a global input / output line driver 450C.

[0172] The second data receiver 410C can receive a first internal voltage VPERI. The second data receiver 410C can generate an even internal control signal IC_EV and an odd internal control signal IC_OD based on an even output enable signal EN_EV and an odd output enable signal EN_OD. When the even output enable signal EN_EV is input to the first internal voltage VPERI, the second data receiver 410C can generate an even internal control signal IC_EV that occurs at the voltage level of the first internal voltage VPERI. The second data receiver 410C can delay the even output enable signal EN_EV that has the voltage level of the first internal voltage VPERI to generate an even internal control signal IC_EV that has the voltage level of the first internal voltage VPERI. When the odd output enable signal EN_OD is input to the first internal voltage VPERI, the second data receiver 410C can generate an odd internal control signal IC_OD that occurs at the voltage level of the first internal voltage VPERI. The second data receiver 410C can delay the odd output enable signal EN_OD, which has the voltage level of the first internal voltage VPERI, to generate the odd internal control signal IC_OD, which has the voltage level of the first internal voltage VPERI.

[0173] The internal pulse generation circuit 420C can receive a first internal voltage VPERI. The internal pulse generation circuit 420C can generate an even internal pulse IP_EV and an odd internal pulse IP_OD based on an even internal control signal IC_EV and an odd internal control signal IC_OD. When the even internal control signal IC_EV is input to the first internal voltage VPERI, the internal pulse generation circuit 420C can generate an even internal pulse IP_EV that occurs at the voltage level of the first internal voltage VPERI. The internal pulse generation circuit 420C can delay the even internal control signal IC_EV that has the voltage level of the first internal voltage VPERI to generate an even internal pulse IP_EV that has the voltage level of the first internal voltage VPERI. When the odd internal control signal IC_OD is input to the first internal voltage VPERI, the internal pulse generation circuit 420C can generate an odd internal pulse IP_OD that occurs at the voltage level of the first internal voltage VPERI. The internal pulse generation circuit 420C can generate an odd internal pulse IP_OD having the voltage level of the first internal voltage VPERI by delaying an odd internal control signal IC_OD having the voltage level of the first internal voltage VPERI.

[0174] The delayed output enable signal generation circuit 430C can receive a second internal voltage VGIO. Based on an even internal pulse IP_EV and an odd internal pulse IP_OD, the delayed output enable signal generation circuit 430C can generate an even delayed output enable signal EN_EVD and an odd delayed output enable signal EN_ODD. When an even internal pulse IP_EV is input to a first internal voltage VPERI, the delayed output enable signal generation circuit 430C can generate an even delayed output enable signal EN_EVD that occurs at the voltage level of the second internal voltage VGIO. The delayed output enable signal generation circuit 430C can convert the voltage level of the even internal pulse IP_EV having the voltage level of the first internal voltage VPERI to the voltage level of the second internal voltage VGIO, delay the even internal pulse IP_EV, and generate an even delayed output enable signal EN_EVD having the voltage level of the second internal voltage VGIO. The delayed output enable signal generation circuit 430C can generate an odd delayed output enable signal EN_ODD that occurs at the voltage level of the second internal voltage VGIO when an odd internal pulse IP_OD is input to the first internal voltage VPERI. The delayed output enable signal generation circuit 430C can convert the voltage level of the odd internal pulse IP_OD, which has the voltage level of the first internal voltage VPERI, to the voltage level of the second internal voltage VGIO, delay the odd internal pulse IP_OD, and generate an odd delayed output enable signal EN_ODD that has the voltage level of the second internal voltage VGIO.

[0175] The second data control circuit 440C can generate a drive signal GDRV that includes pulses generated based on the output control signal OCTR. The second data control circuit 440C can generate a drive signal GDRV that includes pulses generated when the output control signal OCTR is enabled. The second data control circuit 440C can generate a drive signal GDRV that includes pulses generated when the output control signal OCTR occurs at the voltage level of the first internal voltage VPERI.

[0176] The global input / output line driver 450C can be turned on when a pulse of the drive signal GDRV is input. When a pulse of the drive signal GDRV is input, the global input / output line driver 450C can output the second internal data ID2, which is output from the second data storage circuit 244C, to the global input / output line GIO.

[0177] Figure 20 is a circuit diagram showing an example of an internal pulse generation circuit 420C included in the second control circuit 242C. The internal pulse generation circuit 420C may include an even internal pulse generation circuit 621 and an odd internal pulse signal 622.

[0178] The even internal pulse generator circuit 621 may be implemented with inverters IV65, IV66 and NAND gates NAND61, NAND62. The even internal pulse generator circuit 621 can receive a first internal voltage VPERI. When the even internal control signal IC_EV is enabled at a logic high level, the even internal pulse generator circuit 621 can generate an even internal pulse IP_EV driven at the voltage level of the first internal voltage VPERI. When the odd internal control signal IC_OD is enabled at a logic high level, the even internal pulse generator circuit 621 can generate an even internal pulse IP_EV driven at the voltage level of the ground voltage VSS. The even internal pulse generator circuit 621 can generate an even internal pulse IP_EV that is enabled from the time the even internal control signal IC_EV is enabled at a logic high level until the time the odd internal control signal IC_OD is enabled at a logic high level.

[0179] The odd internal pulse signal 622 may be implemented by inverters IV67, IV68 and NAND gates NAND63, NAND64. The odd internal pulse signal 622 can receive a first internal voltage VPERI. When the odd internal control signal IC_OD is enabled at a logic high level, the odd internal pulse signal 622 can generate an odd internal pulse IP_OD driven at the voltage level of the first internal voltage VPERI. When the even internal control signal IC_EV is enabled at a logic high level, the odd internal pulse signal 622 can generate an odd internal pulse IP_OD driven at the voltage level of the ground voltage VSS. The odd internal pulse signal 622 can generate an odd internal pulse IP_OD that is enabled from the time the odd internal control signal IC_OD is enabled at a logic high level until the time the even internal control signal IC_EV is enabled at a logic high level.

[0180] Figures 21 and 22 are timing diagrams illustrating the operation of a memory device 20C according to an example of the present invention. Referring to Figures 21 and 22, the first to fourth data output operations of the memory device 20C will be explained, but the operation of performing the first data output operation to the first data storage circuit 243C, followed by the second data output operation to the second data storage circuit 244C, followed by the third data output operation to the first data storage circuit 243C, and then the fourth data output operation to the second data storage circuit 244C will be explained as follows.

[0181] At T31, the first data control circuit 310C generates the first pulse of the output control pulse OCP, which occurs at the voltage level of the first internal voltage VPERI, when the output control signal OCTR is enabled during the first data output operation.

[0182] The edge detection circuit 320C's even-odd detection signal generation circuit 511 generates an even detection signal EV, which is enabled at the voltage level of the first internal voltage VPERI when the first pulse of the output control pulse OCP undergoes a level transition. The pulse signal generation circuit 512 of the edge detection circuit 320C generates an even pulse signal EVP, which occurs at the voltage level of the first internal voltage VPERI, based on the output control pulse OCP, for the duration that the even detection signal EV is enabled. The edge detection circuit 320C's even output enable signal generation circuit 521 generates an even output enable signal EN_EV, which is enabled at the voltage level of the first internal voltage VPERI when the even pulse signal EVP is enabled.

[0183] At time T32, the second data receiver 410C generates an even internal control signal IC_EV that occurs at the voltage level of the first internal voltage VPERI when the even output enable signal EN_EV is input to the first internal voltage VPERI.

[0184] The internal pulse generation circuit 420C generates an even internal pulse IP_EV that occurs at the voltage level of the first internal voltage VPERI when the even internal control signal IC_EV is input to the first internal voltage VPERI.

[0185] At time T33, the delayed output enable signal generation circuit 430C converts the voltage level of an even internal pulse IP_EV having the voltage level of the first internal voltage VPERI to the voltage level of the second internal voltage VGIO, and delays the even internal pulse IP_EV generated at time T32 to generate an even delayed output enable signal EN_EVD having the voltage level of the second internal voltage VGIO.

[0186] The first data receiver 330C generates an even data control signal DCTR_EV that occurs at the voltage level of the first internal voltage VPERI when the even delay output enable signal EN_EVD is input to the second internal voltage VGIO during the period in which the enable period signal ENT is enabled.

[0187] The signal synthesis circuit 630C of the repeater enable signal generation circuit 340C generates a synthesized output enable signal SCTR, which is enabled at the first internal voltage VPERI when the even data control signal DCTR_EV is enabled.

[0188] At T34, the delay circuit 640C delays the composite output enable signal SCTR by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN, which occurs at the voltage level of the first internal voltage VPERI.

[0189] When the repeater enable signal RPEN is enabled, repeater 350C drives the input / output line IO according to the logic level of the first internal data ID1 to generate output data OUTD. Repeater 350C outputs the output data OUTD to the data input / output circuit 250C via the input / output line IO.

[0190] At T35, the first data control circuit 310C generates a second pulse of the output control pulse OCP that occurs at the voltage level of the first internal voltage VPERI when the output control signal OCTR is enabled during second data output operation.

[0191] The even-odd detection signal generation circuit 511 of the edge detection circuit 320C generates an odd detection signal OD, which is enabled at the voltage level of the first internal voltage VPERI when the second pulse of the output control pulse OCP undergoes a level transition. The pulse signal generation circuit 512 of the edge detection circuit 320C generates an odd pulse signal ODP, which occurs at the voltage level of the first internal voltage VPERI, based on the output control pulse OCP, for the duration that the odd detection signal OD is enabled. The odd output enable signal generation circuit 522 of the edge detection circuit 320C generates an odd output enable signal EN_OD, which is enabled at the voltage level of the first internal voltage VPERI when the odd pulse signal ODP is enabled.

[0192] At T36, when the odd output enable signal EN_OD is input to the first internal voltage VPERI, the second data receiver 410C generates an odd internal control signal IC_OD that occurs at the voltage level of the first internal voltage VPERI.

[0193] The internal pulse generation circuit 420C generates an odd internal pulse IP_OD that occurs at the voltage level of the first internal voltage VPERI when the odd internal control signal IC_OD is input to the first internal voltage VPERI.

[0194] At time T37, the delayed output enable signal generation circuit 430C converts the voltage level of the odd internal pulse IP_OD, which has the voltage level of the first internal voltage VPERI, to the voltage level of the second internal voltage VGIO, and delays the odd internal pulse IP_OD generated at time T36 to generate the odd delayed output enable signal EN_ODD, which has the voltage level of the second internal voltage VGIO.

[0195] The first data receiver 330C generates an odd data control signal DCTR_OD that occurs at the voltage level of the first internal voltage VPERI when the odd delay output enable signal EN_ODD is input to the second internal voltage VGIO during the period in which the enable period signal ENT is enabled.

[0196] The signal synthesis circuit 630C of the repeater enable signal generation circuit 340C generates a synthesized output enable signal SCTR, which is enabled at the first internal voltage VPERI when the odd data control signal DCTR_OD is enabled.

[0197] At T38, the delay circuit 640C delays the composite output enable signal SCTR by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN, which occurs at the voltage level of the first internal voltage VPERI.

[0198] When the repeater enable signal RPEN is enabled, repeater 350C drives the input / output line IO according to the logic level of the second internal data ID2 to generate output data OUTD. Repeater 350C outputs the output data OUTD to the data input / output circuit 250C via the input / output line IO.

[0199] At T39, the first data control circuit 310C generates the third pulse of the output control pulse OCP, which occurs at the voltage level of the first internal voltage VPERI, when the output control signal OCTR is enabled during the operation of the third data output.

[0200] The edge detection circuit 320C's even-odd detection signal generation circuit 511 generates an even detection signal EV, which is enabled at the voltage level of the first internal voltage VPERI when the third pulse of the output control pulse OCP undergoes a level transition. The pulse signal generation circuit 512 of the edge detection circuit 320C generates an even pulse signal EVP, which occurs at the voltage level of the first internal voltage VPERI, based on the output control pulse OCP, for the duration that the even detection signal EV is enabled. The edge detection circuit 320C's even output enable signal generation circuit 521 generates an even output enable signal EN_EV, which is enabled at the voltage level of the first internal voltage VPERI when the even pulse signal EVP is enabled.

[0201] At time T40, the second data receiver 410C generates an even internal control signal IC_EV that occurs at the voltage level of the first internal voltage VPERI when the even output enable signal EN_EV is input to the first internal voltage VPERI.

[0202] The internal pulse generation circuit 420C generates an even internal pulse IP_EV that occurs at the voltage level of the first internal voltage VPERI when the even internal control signal IC_EV is input to the first internal voltage VPERI.

[0203] At time T41, the delayed output enable signal generation circuit 430C converts the voltage level of an even internal pulse IP_EV having the voltage level of the first internal voltage VPERI to the voltage level of the second internal voltage VGIO, and delays the even internal pulse IP_EV generated at time T40 to generate an even delayed output enable signal EN_EVD having the voltage level of the second internal voltage VGIO.

[0204] The first data receiver 330C generates an even data control signal DCTR_EV that occurs at the voltage level of the first internal voltage VPERI when the even delay output enable signal EN_EVD is input to the second internal voltage VGIO during the period in which the enable period signal ENT is enabled.

[0205] The signal synthesis circuit 630C of the repeater enable signal generation circuit 340C generates a synthesized output enable signal SCTR, which is enabled at the first internal voltage VPERI when the even data control signal DCTR_EV is enabled.

[0206] At T42, the delay circuit 640C delays the composite output enable signal SCTR by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN, which occurs at the voltage level of the first internal voltage VPERI.

[0207] When the repeater enable signal RPEN is enabled, repeater 350C drives the input / output line IO according to the logic level of the first internal data ID1 to generate output data OUTD. Repeater 350C outputs the output data OUTD to the data input / output circuit 250C via the input / output line IO.

[0208] At T43, the first data control circuit 310C generates the fourth pulse of the output control pulse OCP, which occurs at the voltage level of the first internal voltage VPERI, when the output control signal OCTR is enabled during the fourth data output operation.

[0209] The even-odd detection signal generation circuit 511 of the edge detection circuit 320C generates an odd detection signal OD, which is enabled at the voltage level of the first internal voltage VPERI when the fourth pulse of the output control pulse OCP undergoes a level transition. The pulse signal generation circuit 512 of the edge detection circuit 320C generates an odd pulse signal ODP, which occurs at the voltage level of the first internal voltage VPERI, based on the output control pulse OCP, for the duration that the odd detection signal OD is enabled. The odd output enable signal generation circuit 522 of the edge detection circuit 320C generates an odd output enable signal EN_OD, which is enabled at the voltage level of the first internal voltage VPERI when the odd pulse signal ODP is enabled.

[0210] At T44, the second data receiver 410C generates an odd internal control signal IC_OD that occurs at the voltage level of the first internal voltage VPERI when the odd output enable signal EN_OD is input to the first internal voltage VPERI.

[0211] The internal pulse generation circuit 420C generates an odd internal pulse IP_OD that occurs at the voltage level of the first internal voltage VPERI when the odd internal control signal IC_OD is input to the first internal voltage VPERI.

[0212] At time T45, the delayed output enable signal generation circuit 430C converts the voltage level of the odd internal pulse IP_OD, which has the voltage level of the first internal voltage VPERI, to the voltage level of the second internal voltage VGIO, and delays the odd internal pulse IP_OD generated at time T44 to generate the odd delayed output enable signal EN_ODD, which has the voltage level of the second internal voltage VGIO.

[0213] The first data receiver 330C generates an odd data control signal DCTR_OD that occurs at the voltage level of the first internal voltage VPERI when the odd delay output enable signal EN_ODD is input to the second internal voltage VGIO during the period in which the enable period signal ENT is enabled.

[0214] The signal synthesis circuit 630C of the repeater enable signal generation circuit 340C generates a synthesized output enable signal SCTR, which is enabled at the first internal voltage VPERI when the odd data control signal DCTR_OD is enabled.

[0215] At T46, the delay circuit 640C delays the composite output enable signal SCTR by a delay amount adjusted by the delay code DCD<1:N> to generate the repeater enable signal RPEN, which occurs at the voltage level of the first internal voltage VPERI.

[0216] When the repeater enable signal RPEN is enabled, repeater 350C drives the input / output line IO according to the logic level of the second internal data ID2 to generate output data OUTD. Repeater 350C outputs the output data OUTD to the data input / output circuit 250C via the input / output line IO.

[0217] A memory device 20C according to this example of the present invention can ensure a margin between data and the enable signal by outputting data while compensating for the distance difference that causes a delay in the enable signal for activating the repeater 350C, and the voltage difference with respect to the different power supplies VPERI and VGIO. By outputting data while compensating for the distance difference that causes a delay in the enable signal for activating the repeater 350C, and the voltage difference with respect to the different power supplies VPERI and VGIO, the memory device 20C can prevent errors from occurring in the data. [Explanation of Symbols]

[0218] 10. Controller, 20. Memory device 240. Memory circuit, 241. First control circuit 242. Second control circuit, 243. Data storage circuit 250. Data Input / Output Circuits First Example 20A. Memory device, 210A. Command generation circuit 220A. Internal voltage generation circuit, 230A. Output control signal generation circuit 240A. Memory circuit, 241A. First control circuit 242A. Second control circuit, 243A. First data storage circuit 244A. Second data storage circuit, 250A. Data input / output circuit 310A. First data control circuit, 320A. Edge detection circuit 330A. First data receiver, 340A. Repeater enable signal generation circuit 350A. Repeater, 410A. Second Data Receiver 420A. Internal pulse generation circuit, 430A. Delayed output enable signal generation circuit 440A. Second data control circuit, 450A. Global input / output line driver Second Example 20B. Memory device, 210B. Command generation circuit 220B. Internal voltage generation circuit, 230B. Output control signal generation circuit 240B. Memory circuit, 241B. First control circuit 242B. Second control circuit, 243B. First data storage circuit 244B. Second data storage circuit, 250B. Data input / output circuit 310B. First data control circuit, 320B. Edge detection circuit 330B. First data receiver, 331. First drive circuit 332. Second drive circuit, 333. Signal synthesis circuit 340B. Repeater enable signal generation circuit, 350B. Repeater 410B. Second data receiver, 420B. Internal pulse generation circuit 430B. Delayed output enable signal generation circuit, 440B. Second data control circuit 450B. Global Input / Output Line Driver Third Example 20C. Memory device, 210C. Command generation circuit 220C. Internal voltage generation circuit, 230C. Output control signal generation circuit 240C. Memory circuit, 241C. First control circuit 242C. Second control circuit, 243C. First data storage circuit 244C. Second data storage circuit, 250C. Data input / output circuit 310C. First data control circuit, 320C. Edge detection circuit 330C. First data receiver, 340C. Repeater enable signal generation circuit 350C Repeater, 410C Second Data Receiver 420C. Internal pulse generation circuit, 430C. Delayed output enable signal generation circuit 440C. Second data control circuit, 450C. Global input / output line driver 510C. Even-odd detection circuit, 511. Even-odd detection signal generation circuit 512. Pulse signal generation circuit, 520C. Output enable signal generation circuit 521. Even Output Enable Signal Generation Circuit 522. Odd Output Enable Signal Generation Circuit 610C. First drive circuit, 620C. Second drive circuit 630C. Signal Synthesis Circuit, 640C. Delay Circuit 621. Even internal pulse generation circuit, 622. Odd internal pulse signal

Claims

1. A first control circuit is located adjacent to the data input / output circuit and generates an output enable signal driven by a first internal voltage based on an output control pulse generated during data output operation, receives a delayed output enable signal driven by a second internal voltage, generates the output data from the internal data carried on the global line via a repeater, and outputs it to the data input / output circuit. A data storage circuit is arranged adjacent to the first control circuit and outputs the internal data to the global line when the data output operation is performed, A memory device comprising a second control circuit, which is arranged adjacent to the data storage circuit and generates the delayed output enable signal based on the output enable signal during the data output operation.

2. The memory device according to claim 1, wherein the first control circuit adjusts the timing at which the repeater is activated by compensating for the distance difference between the output enable signal and the delayed output enable signal, and the voltage difference between the first internal voltage and the second internal voltage.

3. The memory device according to claim 2, wherein the distance difference is set to the sum of the distance over which the output enable signal output from the first control circuit to the data storage circuit and the second control circuit is output, and the distance over which the delayed output enable signal output from the second control circuit to the data storage circuit and the first control circuit is output.

4. The memory device according to claim 1, wherein the second control circuit is arranged at a distance from the data input / output circuit equal to the distance between the first control circuit and the data storage circuit.

5. The memory device according to claim 1, wherein the first internal voltage is a voltage generated at a voltage level higher than the second internal voltage.

6. The memory device according to claim 1, wherein the internal data is generated at the voltage level of the ground voltage or the second internal voltage.

7. The first control circuit is, A first data control circuit that receives the first internal voltage and generates the output control pulse, which includes a pulse generated based on the output control signal generated during the data output operation, An edge detection circuit that receives the first internal voltage, detects the edge at which the output control pulse undergoes a level transition, and generates the output enable signal, A first data receiver that receives the first internal voltage and generates a data control signal based on the delayed output enable signal driven by the second internal voltage, A repeater enable signal generation circuit that receives the first internal voltage and delays the data control signal by a delay amount adjusted by a delay code to generate a repeater enable signal, The memory device according to claim 1, further comprising a repeater that, when the repeater enable signal is enabled, generates output data from the internal data placed on the global line and outputs the output data to the data input / output circuit.

8. The second control circuit is, A second data receiver receives the first internal voltage and generates an internal control signal based on the output enable signal, An internal pulse generation circuit that receives the first internal voltage and generates an internal pulse including a pulse generated based on the internal control signal, The memory device according to claim 1, further comprising: a delay output enable signal generation circuit that receives the second internal voltage and adjusts the voltage level of the internal pulse to generate the delay output enable signal driven by the second internal voltage.

9. A first control circuit is positioned adjacent to the data input / output circuit and detects the edge of the level transition of the output control pulse generated during data output operation, generates a rising output enable signal and a falling output enable signal driven by a first internal voltage, receives a rising delayed output enable signal and a falling delayed output enable signal driven by a second internal voltage, generates the output data from the internal data carried on the global line via a repeater, and outputs it to the data input / output circuit. A data storage circuit is arranged adjacent to the first control circuit and outputs the internal data to the global line when the data output operation is performed, A memory device comprising a second control circuit, which is arranged adjacent to the data storage circuit, and which generates a rising-edge output enable signal and a falling-edge output enable signal based on the rising-edge output enable signal and the falling-edge output enable signal during the data output operation.

10. The memory device according to claim 9, wherein the first control circuit adjusts the timing at which the repeater is activated by compensating for the distance difference between which the rising-edge output enable signal and the falling-edge output enable signal are generated from the rising-edge delayed output enable signal and the falling-edge delayed output enable signal, and the voltage difference between the first internal voltage and the second internal voltage.

11. The first control circuit detects the rising edge of the output control pulse and generates the rising output enable signal driven by the first internal voltage. The memory device according to claim 9, wherein the first control circuit detects the falling edge of the output control pulse and generates the falling-edge output enable signal driven by the first internal voltage.

12. The first control circuit is, A first data control circuit that receives the first internal voltage and generates the output control pulse, which includes a pulse generated based on the output control signal generated during the data output operation, An edge detection circuit that receives the first internal voltage, detects the edge at which the output control pulse undergoes a level transition, and generates the rising edge output enable signal and the falling edge output enable signal, A first data receiver that receives the first internal voltage and generates a data control signal based on the rising-edge delayed output enable signal and the falling-edge delayed output enable signal, which are driven by the second internal voltage, A repeater enable signal generation circuit that receives the first internal voltage and delays the data control signal by a delay amount adjusted by a delay code to generate a repeater enable signal, The memory device according to claim 9, further comprising a repeater that, when the repeater enable signal is enabled, generates output data from the internal data placed on the global line and outputs the output data to the data input / output circuit.

13. The first data receiver is A first drive circuit that receives the first internal voltage and drives the first node to generate a rising drive signal when the rising delay output enable signal, which is driven by the enable period signal and the second internal voltage, is enabled, A second drive circuit that receives the first internal voltage and drives the second node to generate a falling-down drive signal when the falling-down delayed output enable signal, which is driven by the enable period signal and the second internal voltage, is enabled, The memory device according to claim 12, further comprising a signal synthesis circuit that receives the first internal voltage and synthesizes the rising-edge drive signal and the falling-edge drive signal to generate the data control signal.

14. The second control circuit is, A second data receiver receives the first internal voltage and generates a rising internal control signal and a falling internal control signal based on the rising output enable signal and the falling output enable signal, An internal pulse generation circuit that receives the first internal voltage and generates rising internal pulses and falling internal pulses, which include pulses generated based on the rising internal control signal and the falling internal control signal, The memory device according to claim 9, further comprising a delay output enable signal generation circuit that receives the second internal voltage and adjusts the voltage levels of the rising internal pulse and the falling internal pulse to generate the rising delayed output enable signal and the falling delayed output enable signal, which are driven by the second internal voltage.

15. A first control circuit is located adjacent to the data input / output circuit and generates an even output enable signal and an odd output enable signal driven by a first internal voltage based on output control pulses generated during the continuously performed first and second data output operations, receives an even delayed output enable signal and an odd delayed output enable signal driven by a second internal voltage, and sequentially generates first and second output data from the first and second internal data carried on the global line via a repeater and outputs them to the data input / output circuit. A data storage circuit is arranged adjacent to the first control circuit and outputs the internal data to the global line when the data output operation is performed, A memory device comprising a second control circuit, which is arranged adjacent to the data storage circuit, and which generates the even-delayed output enable signal based on the even-output enable signal during the first data output operation, and generates the odd-delayed output enable signal based on the odd-output enable signal during the second data output operation.

16. The memory device according to claim 15, wherein the first data output operation is performed when the output command is input for the first and third times, and the second data output operation is performed when the output command is input for the second and fourth times.

17. The memory device according to claim 15, wherein the first control circuit adjusts the timing at which the repeater is activated by compensating for the distance difference between which the even output enable signal and the odd output enable signal are generated from the even delay output enable signal and the odd delay output enable signal, and the voltage difference between the first internal voltage and the second internal voltage.

18. The memory device according to claim 17, wherein the distance difference is set to the sum of the distance at which the even output enable signal and the odd output enable signal output from the first control circuit to the data storage circuit and the second control circuit are output, and the distance at which the even delay output enable signal and the odd delay output enable signal output from the second control circuit to the data storage circuit and the first control circuit are output.

19. The first control circuit is, A first data control circuit that receives the first internal voltage and generates output control pulses including first and second pulses generated based on output control signals generated during the first and second data output operations, An edge detection circuit that receives the first internal voltage, detects the edge at which the first pulse of the output control pulse undergoes a level transition, generates the even output enable signal, and detects the edge at which the second pulse of the output control pulse undergoes a level transition, generates the odd output enable signal. A first data receiver that receives the first internal voltage and generates an even data control signal and an odd data control signal based on the even delay output enable signal and the odd delay output enable signal, which are driven by the second internal voltage, A repeater enable signal generation circuit that receives the first internal voltage and delays either the even data control signal or the odd data control signal by a delay amount adjusted by the delay code to generate a repeater enable signal, The memory device according to claim 15, further comprising a repeater that, when the repeater enable signal is enabled, generates the output data from the first and second internal data placed on the global line and outputs the output data to the data input / output circuit.

20. The edge detection circuit described above is An even-odd detection circuit that detects the edge where the first pulse of the output control pulse undergoes a level transition and generates an even pulse signal, and detects the edge where the second pulse of the output control pulse undergoes a level transition and generates an odd pulse signal, The memory device according to claim 19, further comprising: an output enable signal generation circuit that receives the first internal voltage and generates the even output enable signal and the odd output enable signal, which include pulses that are selectively generated based on the even pulse signal and the odd pulse signal.

21. The even-odd detection circuit described above is: An even-odd detection signal generation circuit generates an even detection signal that is enabled when the first pulse of the output control pulse undergoes a level transition, and generates an odd detection signal that is enabled when the second pulse of the output control pulse undergoes a level transition. The memory device according to claim 20, comprising: a pulse signal generation circuit that generates the even pulse signal based on a first pulse of the output control pulse during the period in which the even detection signal is enabled, and generates the odd pulse signal based on a second pulse of the output control pulse during the period in which the odd detection signal is enabled.

22. The output enable signal generation circuit is, An even output enable signal generation circuit generates an even output enable signal that is enabled from the time the even pulse signal is enabled until the time the odd pulse signal is enabled, The memory device according to claim 20, further comprising: an odd output enable signal generation circuit that generates the odd output enable signal which is enabled from the time the odd pulse signal is enabled until the time the even pulse signal is enabled.

23. The repeater enable signal generation circuit is: A signal synthesis circuit that receives the first internal voltage and synthesizes the even data control signal and the odd data control signal to generate a synthesized output enable signal, The memory device according to claim 19, further comprising a delay circuit that delays the composite output enable signal by a delay amount adjusted by the delay code, thereby generating the repeater enable signal.

24. The second control circuit is, A second data receiver receives the first internal voltage and generates an even internal control signal and an odd internal control signal based on the even output enable signal and the odd output enable signal, An internal pulse generation circuit that receives the first internal voltage and generates even internal pulses and odd internal pulses, which include pulses generated based on the even internal control signal and the odd internal control signal, The memory device according to claim 15, further comprising a delay output enable signal generation circuit that receives the second internal voltage and adjusts the voltage levels of the even internal pulse and the odd internal pulse to generate the even delayed output enable signal and the odd delayed output enable signal, which are driven by the second internal voltage.

25. The internal pulse generation circuit is, An even internal pulse generation circuit that generates the even internal pulse which is enabled from the time the even internal control signal is enabled until the time the odd internal control signal is enabled, The memory device according to claim 24, comprising an odd internal pulse signal that generates the odd internal pulse signal which is enabled from the time the odd internal control signal is enabled until the time the even internal control signal is enabled.

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