Display device

Abstract

To provide a display device that can expand the size (or area) of the light-emitting region. [Solution] A display device according to one embodiment of the present disclosure includes a substrate containing a plurality of pixels having a plurality of subpixels, a light-emitting region provided on the substrate and located in each of the plurality of subpixels, and wiring partially superimposed on the light-emitting region.

Description

Technical Field

[0001] This specification relates to a display device for displaying images.

Background Art

[0002] Organic light-emitting display devices have a high response speed, low power consumption, and do not require a separate light source (self-emitting) unlike liquid crystal display devices, so they are attracting attention as next-generation flat panel display devices without the problem of viewing angle.

[0003] Such a display device includes a plurality of sub-pixels, and the plurality of sub-pixels include a light-emitting element layer provided in a light-emitting region. The display device displays an image through the light emission of the light-emitting element layer.

[0004] On the other hand, in the display device, wirings for driving each of the plurality of sub-pixels are provided in a circuit region adjacent to the light-emitting region. This is because when the wirings are provided in the light-emitting region, the size (or area) of the light-emitting region becomes narrow and the light efficiency decreases. Therefore, there is a limit due to the wirings in expanding the size (or area) of the light-emitting region of the display device, and thus there is also a limit in improving the light efficiency.

Summary of the Invention

Problems to be Solved by the Invention

[0005] This specification makes it a technical problem to provide a display device capable of expanding the size (or area) of a light-emitting region. <动

[0006] This specification makes it a technical problem to provide a display device capable of improving light efficiency.

[0007] This specification makes it a technical problem to provide a display device capable of improving the light extraction efficiency of light emitted from a light-emitting element layer.

[0008] Furthermore, this specification aims to provide a display device that can maximize the light extraction efficiency of light emitted by a light-emitting element layer.

[0009] Furthermore, this specification aims to provide a display device that can reduce overall power consumption through light extraction in non-emissive regions.

[0010] The problems that the examples in this specification aim to solve are not limited to those mentioned above, and other problems not mentioned can be clearly understood by a person with ordinary skill in the art to which the technical concept of this specification pertains, based on the following description. [Means for solving the problem]

[0011] A display device according to one embodiment of this specification includes a substrate containing a plurality of pixels having a plurality of subpixels, a light-emitting region provided on the substrate and located in each of the plurality of subpixels, and wiring partially superimposed on the light-emitting region. [Effects of the Invention]

[0012] The display device according to this specification can expand the size (or area) of the light-emitting region by providing wiring for driving each of the multiple subpixels so as to partially overlap the non-light-emitting region (or first non-light-emitting region) provided inside each of the multiple subpixels.

[0013] The display device according to this specification can improve light efficiency by expanding the size (or area) of the light-emitting region.

[0014] The display device according to this specification can improve the light extraction efficiency of light emitted by the light-emitting layer by arranging a reflective portion (or first reflective portion) in a non-emitting region (or first non-emitting region) provided inside each of a plurality of subpixels.

[0015] The display device according to this specification is configured such that a reflector (or second reflector) can be placed in a non-emitting region (or second non-emitting region) located outside a plurality of subpixels. This allows the reflector (or second reflector) to reflect light directed toward adjacent subpixels, thereby maximizing the light extraction efficiency.

[0016] The display device according to this specification can extract light even in non-emitting regions through reflective sections (or a first reflective section and a second reflective section) provided on the inside and outside of each of the multiple subpixels. Therefore, compared to a display device that does not have reflective sections on the inside and outside of each of the multiple subpixels, it can have the same luminous efficiency at low power consumption, or even improve the luminous efficiency further, thereby reducing overall power consumption.

[0017] The effects that can be obtained herein are not limited to those mentioned above, and other effects not mentioned herein will be clearly understood by a person with ordinary skill in the art to which this specification pertains from the following description. [Brief explanation of the drawing]

[0018] [Figure 1] This is a schematic plan view of a display device according to one embodiment of this specification. [Figure 2] Figure 1 is a schematic plan view showing one pixel. [Figure 3] This is a schematic cross-sectional view of the line I-I' shown in Figure 2. [Figure 4] This is a schematic cross-sectional view of the line II-II' shown in Figure 2. [Figure 5] This is a schematic plan view showing one subpixel of a display device in a comparative example. [Figure 6] This is a schematic plan view showing one subpixel of a display device according to one embodiment of this specification. [Figure 7] This is a schematic plan view showing one subpixel of a display device according to a second embodiment of this specification. [Figure 8]It is a schematic plan view showing one sub-pixel of the display device according to the third embodiment of the present specification. [Figure 9] It is a schematic plan view showing one sub-pixel of the display device according to the fourth embodiment of the present specification.

Mode for Carrying Out the Invention

[0019] The advantages, features, and the method of achieving them of the present specification will become clear by referring to the embodiments described in detail later together with the attached drawings. However, the present specification is not limited to the embodiments disclosed below, and is embodied in various different forms. Merely, these embodiments are provided so that the disclosure of the present specification becomes complete and that those with ordinary knowledge in the technical field to which the present specification belongs can be fully informed of the scope of the invention.

[0020] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and the present specification is not limited to the matters shown in the drawings. Throughout the specification, the same drawing numbers refer to the same components. In the description of the present specification, when it is determined that the specific description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description thereof is omitted.

[0021] When terms such as "including", "having", "consisting of", etc. mentioned in the present specification are used, other parts can be added unless "only" is used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0022] In interpreting a component, even if there is no separate explicit description regarding the error range, it is interpreted as including the error range.

[0023] When describing spatial relationships, for example, when the positional relationship between two parts is described using phrases such as "above," "above," "below," or "beside," one or more other parts may be located between the two parts, unless the expressions "immediately" or "directly" are used.

[0024] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it can include non-continuous events unless expressions like "immediately" or "directly" are used.

[0025] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0026] The terms "X-axis direction," "Y-axis direction," and "Z-axis direction" should not be interpreted as referring only to geometric relationships where the relationship between them is perpendicular, but rather can mean that there are broader directions within the scope in which the configuration specified herein can function.

[0027] The term "at least one" should be understood to include all possible combinations of one or more related items. For example, "at least one of item 1, item 2, and item 3" could mean each of item 1, item 2, or item 3, as well as all possible combinations of items that can be presented from two or more of items 1, 2, and 3.

[0028] The features of each of the embodiments described herein can be combined or combined with one another, either partially or as a whole, allowing for a variety of technically diverse interdependencies and drives, and each embodiment can be implemented independently of one another or together in a related manner.

[0029] Preferred embodiments of this specification will be described in detail below with reference to the attached figures.

[0030] Figure 1 is a schematic plan view of a display device according to one embodiment of this specification, and Figure 2 is a schematic plan view showing one pixel shown in Figure 1.

[0031] In the following, the first direction (Y-axis direction) refers to the vertical direction relative to Figure 1, the second direction (X-axis direction) refers to the horizontal direction relative to Figure 1, and the third direction (Z-axis direction) refers to the thickness direction of the display device 100. The first direction (Y-axis direction) may be parallel to the data wiring (DL, shown in Figure 2). The second direction (X-axis direction) may be parallel to the gate wiring (GL, shown in Figure 2).

[0032] Referring to Figure 1, the display device 100 according to one embodiment of this specification may include a display panel including a gate drive unit (GD). The display panel may include a substrate 110 and a counter substrate 200 (shown in Figure 4) bonded together.

[0033] An example substrate 110 may include a display area (DA) on which multiple pixels (P) having multiple subpixels (SP) are arranged, and a non-display area (NDA) surrounding the display area (DA). The substrate 110 may further include a first non-emitting area (NEA1), an emitting area (EA), and wiring 120. The first non-emitting area (NEA1), the emitting area (EA), and wiring 120 may be provided in the display area (DA) of the substrate 110.

[0034] In one example, the first non-emitting region (NEA1) is provided on the substrate 110 and can be provided inside each of the multiple subpixels (SP). For example, as shown in Figure 2, the first non-emitting region (NEA1) can be provided inside each of the light-emitting regions (EAs) of the multiple subpixels (SP). Therefore, the light-emitting regions (EAs) can be provided adjacent to the first non-emitting region (NEA1). In one example, the wiring 120 can be partially superimposed on both the first non-emitting region (NEA1) and the light-emitting regions (EAs).

[0035] In typical display devices, non-emitting regions are not provided inside each of the multiple subpixels (or inside the light-emitting region). This is because providing non-emitting regions inside each of the multiple subpixels (or inside the light-emitting region) would reduce the size (or area) of the light-emitting region, thus decreasing the light efficiency.

[0036] In contrast, in the display device 100 according to one embodiment of this specification, light extraction can be performed by the first reflector 150 (shown in Figure 4) even in the first non-emitting area (NEA1) located inside each of the multiple subpixels (SP), so the light efficiency may not decrease. Therefore, the display device 100 according to one embodiment of this specification may have a structural feature in which the first non-emitting area (NEA1) is arranged inside each of the multiple subpixels (SP).

[0037] Furthermore, in the case of typical display devices, if wiring is present in the light-emitting area, the size (or area) of the light-emitting area decreases, reducing the light efficiency. Therefore, the wiring is placed in the circuit area. Consequently, in the case of typical display devices, the wiring does not overlap the light-emitting area.

[0038] In contrast, in the display device 100 according to one embodiment of this specification, since light extraction can be performed even in the first non-emitting area (NEA1) by the first reflecting section 150, the light efficiency may not decrease even if the wiring 120 partially overlaps the first non-emitting area (NEA1) and the emitting area (EA).

[0039] Furthermore, in the display device 100 according to one embodiment of this specification, the wiring 120 is arranged so as to partially overlap the light-emitting region (EA) and the first non-light-emitting region (NEA1) that does not emit light. As a result, the size (or area) of the circuit region can be reduced compared to a general display device, and the size (or area) of the light-emitting region (EA) can be relatively expanded (or enlarged). Therefore, the display device 100 according to one embodiment of this specification can improve light efficiency by expanding the size (or area) of the light-emitting region (EA). A specific explanation of this will be given later with reference to Figures 5 to 9.

[0040] Referring to Figure 1, the display device 100 according to one embodiment of this specification may further include a source drive integrated circuit (IC) 170, a flexible film 171, a circuit board 180, and a timing control unit 181.

[0041] The substrate 110 contains thin-film transistors and may be a transistor array substrate, a lower substrate, a base substrate, or a first substrate. The substrate 110 may be a transparent glass substrate or a transparent plastic substrate.

[0042] The opposing substrate 200 can be bonded to the substrate 110 via an adhesive member. For example, the opposing substrate 200 is smaller in size than the substrate 110 and can be bonded to the remaining portion of the substrate 110 excluding the pad portion. The opposing substrate 200 may be an upper substrate, a second substrate, or a sealing substrate.

[0043] The gate drive unit (GD) can supply gate signals to the gate wiring using gate control signals input from the timing control unit 181. When the source drive IC 170 is manufactured as a drive chip, the source drive IC 170 can be mounted on the flexible film 171 using the COF (chip-on-film) or COP (chip-on-panel) method.

[0044] Pads such as power pads and data pads can be formed in the non-display area of ​​the display panel. Wiring connecting the pads to the source drive IC 170 and wiring connecting the pads to the circuit board 180 can be formed on the flexible film 171. The flexible film 171 is attached to the pads using an anisotropic conductive film, thereby enabling the wiring of the pads to be connected to the flexible film 171.

[0045] Referring to Figure 1, an example substrate 110 can include a display area (DA) and a non-display area (NDA).

[0046] The display area (DA) is the area where the image is displayed, and may be a pixel array area, an active area, a pixel array section, a display section, or a screen. For example, the display area (DA) can be located in the central part of a display panel.

[0047] An example display area (DA) may include gate wiring, data wiring, pixel power wiring, and multiple pixels (P). Each of the multiple pixels (P) may include multiple subpixels (SP) which may be defined by gate wiring and data wiring. Each of the multiple subpixels (SP) may be defined as the smallest unit area from which light is actually emitted.

[0048] For example, at least four adjacent subpixels (SPs) that emit different colors from each other constitute a single unit pixel (P). A single unit pixel may, but is not limited to, include a red subpixel, a green subpixel, a blue subpixel, and a white subpixel.

[0049] Each of the subpixels (SPs) may include a thin-film transistor and an organic light-emitting element connected to the thin-film transistor. The subpixel may also include an organic light-emitting layer (or light-emitting layer) interposed between the first electrode and the second electrode.

[0050] The organic light-emitting layers arranged in each of the multiple subpixels (SPs) can individually emit light of different colors or emit white light in common. For example, if the organic light-emitting layers of each of the multiple subpixels (SPs) emit white light in common, the red, green, and blue subpixels can each include a color filter (CF) (or wavelength conversion member (CF)) that converts white light into light of a different color. In this case, the white subpixel in this example may not have a color filter. The color filter (CF) in this example may include a red color filter (CF1, shown in Figure 4), a blue color filter (CF2, shown in Figure 4), and a green color filter (not shown).

[0051] In a display device 100 according to one embodiment of this specification, a region equipped with a red color filter (CF1) may be a red sub-pixel (SP1), a region equipped with a blue color filter (CF2) may be a blue sub-pixel (SP3), a region equipped with a green color filter may be a green sub-pixel (SP4), and a region not equipped with a color filter may be a white sub-pixel (SP2). In this specification, the red sub-pixel (SP1) can be represented by a first sub-pixel equipped to emit red light, the blue sub-pixel (SP3) can be represented by a third sub-pixel equipped to emit blue light, the green sub-pixel (SP4) can be represented by a fourth sub-pixel equipped to emit green light, and the white sub-pixel (SP2) can be represented by a second sub-pixel equipped to emit white light.

[0052] Each sub-pixel (SP) uses a thin-film transistor to supply a predetermined current to the organic light-emitting element via the data voltage of the data wiring when a gate signal is input from the gate wiring. As a result, the light-emitting layer of each sub-pixel can emit light at a predetermined brightness with the predetermined current.

[0053] Figure 3 is a schematic cross-sectional view of the line I-I' shown in Figure 2, and Figure 4 is a schematic cross-sectional view of the line II-II' shown in Figure 2.

[0054] As shown in Figures 2 and 3, the display area (DA) may include an emitting area (EA) and a non-emitting area (NEA). The emitting area (EA) is the area where light is emitted by the organic light-emitting element layer (E). The non-emitting area (NEA) is the area that does not transmit most of the light incident from the outside.

[0055] For example, a non-emissive area (NEA) may be the region excluding the emissive area (EA) from which light is emitted. In one example, a non-emissive area (NEA) may include a circuit area (CA, shown in Figure 3). The circuit area (CA) may include thin-film transistors 112 for driving each of the subpixels (SP) (or each of the organic light-emitting layers (E) of the subpixels (SP)).

[0056] In a display device 100 according to one embodiment of this specification, the non-emitting area (NEA) may include a first non-emitting area (NEA1) and a second non-emitting area (NEA2).

[0057] In one example, the first non-emitting region (NEA1) can be provided inside each of multiple subpixels (SPs). For example, as shown in Figure 2, the inside of each of multiple subpixels (SPs) can mean the inside of the light-emitting region (EA) contained within one subpixel (SP). An organic light-emitting element layer (E, shown in Figure 4) can be placed in the first non-emitting region (NEA1).

[0058] A second non-emitting region (NEA2), as an example, can be provided outside each of multiple subpixels (SPs). For example, as shown in Figure 2, the area outside each of multiple subpixels (SPs) can mean the area outside the light-emitting region (EA). The area outside each of multiple subpixels (SPs) can include a circuit region (CA) adjacent to the light-emitting region (EA). Furthermore, the area outside each of multiple subpixels (SPs) can include the area between multiple subpixels (SPs) that emit light of different colors (for example, the pixel electrodes 114 of the first subpixel (SP1) and the second subpixel (SP2)).

[0059] Furthermore, multiple pixels (P) and multiple wirings for driving each of the multiple pixels (P) can be arranged in the non-emitting area (NEA). For example, multiple wirings may include multiple first signal lines and multiple second signal lines.

[0060] Multiple first signal lines can be extended in a second direction (X-axis direction). Each of the multiple first signal lines may include at least one gated trace (GL) (or scan trace).

[0061] Multiple second signal lines can be extended in the first direction (Y-axis direction). Multiple second signal lines can intersect with multiple first signal lines. Each of the multiple second signal lines may include a pixel power line (EVDD), multiple data lines (DL), and a reference line (RL). The multiple data lines (DL) may include a first data line (DL1) for driving a first sub-pixel (SP1), a second data line (DL2) for driving a second sub-pixel (SP2), a third data line (DL3) for driving a third sub-pixel (SP3), and a fourth data line (DL4) for driving a fourth sub-pixel (SP4).

[0062] Referring again to Figure 1, the non-display area (NDA) is an area where the image is not displayed, and may be a peripheral circuit area, a signal supply area, an inactive area, or a bezel area. The non-display area (NDA) can be configured to be located around the display area (DA). That is, the non-display area (NDA) can be arranged to surround the display area (DA).

[0063] A display device 100 according to one embodiment of this specification may include a pad section (PA) located in a non-display area (NDA). The pad section (PA) is for driving a plurality of pixels (P). For example, the pad section (PA) can supply power and / or signals for the plurality of pixels (P) provided in the display area (DA) to output video.

[0064] As an example, a pad (PA) can be placed in the non-display area (NDA) (or first non-display area) above the display area (DA), as shown in Figure 1. Since the first non-display area is formed above the display area (DA), it can be referred to as the upper non-display area.

[0065] The gate drive unit (GD) supplies gate signals to the gate wiring based on gate control signals input from the timing control unit 181. The gate drive unit (GD) can be formed in a GIP (gate driver in panel) manner in one side of the display area (DA) of the display panel or in the non-display areas (NDA) on both sides of the display area (DA), as shown in Figure 1.

[0066] Multiple gate drive units (GDs) can be arranged separately on the left side of the display area (DA), i.e., the second non-display area, and on the right side of the display area (DA), i.e., the third non-display area. Since the second and third non-display areas are formed on the sides of the display area (DA), they can be referred to as side non-display areas.

[0067] For example, a plurality of gate drivers (GDs) can be connected to a plurality of pixels (P) and a plurality of first signal lines for supplying signals to each of the plurality of pixels (P). The plurality of first signal lines may include at least one signal line for supplying signals to drive the pixels (P).

[0068] Multiple second signal lines can be extended in the first direction (Y-axis direction). Multiple second signal lines may include pixel power lines (EVDD) and at least one data line (DL) for supplying data voltage to pixels (P). Each of the multiple second signal lines can be connected to at least one of multiple pads, pixel power short bars, and common power short bars. Pixel power short bars and common power short bars may be located in a fourth non-display area that is positioned opposite the pad area (PA) with respect to the display area (DA). The fourth non-display area is formed below the display area (DA) and can therefore be referred to as the lower non-display area.

[0069] A pixel (P) is provided so as to superimpose on at least one of a first signal line and a second signal line, and emits a predetermined light to display an image. The light-emitting region (EA) may correspond to the region in the pixel (P) that emits light.

[0070] Referring to Figure 3, the non-emitting area (NEA) can refer to an area within the display area (DA) that does not emit light, and can therefore be described as a dead zone. For example, a dead zone may be an area containing a black matrix and / or bank, but is not limited to these, and can refer to any area that does not emit light.

[0071] In one embodiment of this specification, the display device 100 can reduce the size (or area) of the circuit area (CA) by arranging the wiring 120 in the first non-emitting area (NEA1), which is a dead zone. Therefore, since the size (or area) of the circuit area (CA) can be reduced in the display device 100 of this specification, the size (or area) of the light-emitting area (EA) can be relatively expanded (or enlarged), and the light efficiency can be improved.

[0072] In one example, wiring 120 could be a data branching wire that applies a data signal to the thin-film transistor 112. Therefore, as shown in Figure 2, wiring 120 can be connected to the thin-film transistor 112 in the circuit region (CA) and to the data wire (DL) in the second non-emitting region (NEA2). In one example, wiring 120 may include a first wiring 121 and a second wiring 122.

[0073] As shown in Figure 2, the wiring 120 can be connected to the circuit region (CA) and extended in the first direction (Y-axis direction) toward the reference wiring (RL). In this case, the wiring 120 can partially overlap the first non-emitting region (NEA1) and the emitting region (EA). For example, as shown in Figure 2, the wiring 120 extending from the circuit region (CA) can pass through (or overlap) the emitting region (EA) (or lower emitting region (EA)), the first non-emitting region (NEA1), and the emitting region (EA) (or upper emitting region (EA)) in sequence. The wiring 120 that has passed through (or overlapped) the emitting region (EA), the first non-emitting region (NEA1), and the emitting region (EA) in sequence can be bent parallel to the reference wiring (RL) and connected to the data wiring (DL) (or first data wiring (DL1)).

[0074] The first wiring 121 may be wiring that partially overlaps the first non-emitting region (NEA1) and the emitting region (EA). As shown in Figure 2, the first wiring 121 may be wiring arranged in the first direction (Y-axis direction). The second wiring 122 may be wiring that connects to the end of the first wiring 121 and connects to a data wiring (DL) (or first data wiring (DL1)) in the second non-emitting region (NEA2). That is, the second wiring 122 may be wiring that connects to the first wiring 121 and is arranged in a different direction from the first wiring 121 (for example, in the second direction (X-axis direction)).

[0075] Below, we will specifically describe the structure of each of the multiple subpixels (SPs) with reference to Figure 3.

[0076] Referring to Figure 3, a display device 100 according to one embodiment of this specification may include a buffer layer (BL), a plurality of inorganic films 111, thin-film transistors 112, a color filter (CF), a planarization layer 113, a pixel electrode 114, a bank 115, an organic light-emitting layer 116, a cathode electrode 117, and a sealing layer 118.

[0077] Each subpixel (SP) in one embodiment may be provided on the upper surface of the buffer layer (BL) and may include a plurality of inorganic films 111, including a gate insulating layer 111a, an interlayer insulating layer 111b, and a passivation layer 111c.

[0078] Furthermore, each sub-pixel (SP) may further include a color filter (CF) arranged on a plurality of inorganic films 111, and a planarization layer 113 provided on the color filter (CF). The planarization layer 113 may include a first planarization layer 1131 and a second planarization layer 1132. The second planarization layer 1132 may be arranged on the first planarization layer 1131. Pixel electrodes 114 may be arranged on the second planarization layer 1132.

[0079] Each sub-pixel (SP) may further include a bank 115 covering one end of the pixel electrode 114, an organic light-emitting layer 116 on the pixel electrode 114 and the bank 115, and a cathode electrode 117 on the organic light-emitting layer 116. A sealing layer 118 may be placed on the cathode electrode 117.

[0080] Multiple inorganic films 111 can be arranged in thin-film transistors 112 for driving subpixels (SPs). These multiple inorganic films 111 can be described in terms of circuit element layers.

[0081] The buffer layer (BL) can be included in multiple inorganic films 111 together with the gate insulating layer 111a, the interlayer insulating layer 111b, and the passivation layer 111c. The pixel electrode 114, the organic light-emitting layer 116, and the cathode electrode 117 can be included in the organic light-emitting layer (E).

[0082] A buffer layer (BL) can be formed between the substrate 110 and the gate insulating layer 111a to protect the thin-film transistor 112. The buffer layer (BL) can be placed across the entire surface (or front surface) of the substrate 110. During the manufacturing process of the thin-film transistor, the buffer layer (BL) can also serve to prevent materials contained in the substrate 110 from diffusing into the transistor layer during high-temperature processes.

[0083] An example thin-film transistor (or driving transistor) 112 may include an active layer 112a, a gate electrode 112b, a source electrode 112c, and a drain electrode 112d.

[0084] The active layer 112a may include a channel region, a drain region, and a source region formed in the thin-film transistor region of the circuit region (CA) of the subpixel (SP). The drain region and the source region can be spaced parallel to each other with the channel region in between.

[0085] The active layer 112a can be composed of a semiconductor material based on one of amorphous silicon, polycrystalline silicon, oxide, or organic material.

[0086] The gate insulating layer 111a can be formed on the channel region of the active layer 112a. For example, the gate insulating layer 111a can be formed in an island shape only on the channel region of the active layer 112a, or it can be formed on the entire front surface of the substrate 110 containing the active layer 112a or the buffer layer (BL).

[0087] The gate electrode 112b can be formed on the gate insulating layer 111a so as to overlap with the channel region of the active layer 112a.

[0088] The interlayer insulating layer 111b can be formed so as to partially overlap the gate electrode 112b and the drain and source regions of the active layer 112a. The interlayer insulating layer 111b can be formed over the entire light-emitting region where light is emitted to the circuit region (CA) and subpixel (SP), as shown in Figure 3.

[0089] The source electrode 112c can be electrically connected to the source region of the active layer 112a via a source contact hole provided in the interlayer insulating layer 111b that superimposes the source region of the active layer 112a.

[0090] The drain electrode 112d can be electrically connected to the drain region of the active layer 112a via a drain contact hole provided in the interlayer insulating layer 111b that superimposes the drain region of the active layer 112a.

[0091] The drain electrode 112d and the source electrode 112c can each be made of the same metallic material. For example, the drain electrode 112d and the source electrode 112c can each be made of a single metallic layer, a single alloy layer, or two or more layers, which may be the same as or different from the gate electrode.

[0092] Furthermore, thin-film transistors provided in the pixel region may have a characteristic in which the threshold voltage is shifted by light. To prevent this, the display panel or substrate 110 may further include a light-shielding layer (not shown) provided beneath at least one active layer 112a of the thin-film transistors 112, the first switching thin-film transistor, and the second switching thin-film transistor.

[0093] The light-shielding layer is provided between the substrate 110 and the active layer 112a, and by blocking light incident on the active layer 112a through the substrate 110, changes in the transistor's threshold voltage due to external light can be minimized. In addition, the light-shielding layer, provided between the substrate 110 and the active layer 112a, can also prevent the thin-film transistor from being visible to the user.

[0094] The passivation layer 111c can be provided on the substrate 110 so as to cover the pixel area. The passivation layer 111c covers the drain electrode 112d, source electrode 112c, gate electrode 112b, and buffer layer (BL) of the thin-film transistor 112.

[0095] A color filter (CF) can be placed on the passivation layer 111c. For example, a color filter (CF) can be placed between a plurality of inorganic films 111 and a first planarization layer 1131. The color filter (CF) may include a red color filter (CF1) placed on a red subpixel (SP1), a blue color filter (CF2) placed on a blue subpixel (SP3), and a green color filter placed on a green subpixel (SP4). A white subpixel (SP2) is provided to emit white light and therefore may not include a color filter.

[0096] The planarization layer 113 can be provided on the substrate 110 so as to cover the passivation layer 111c and the color filter (CF). In one example, the planarization layer 113 can be placed between the substrate 110 and the pixel electrode 114. The planarization layer 113 can be formed over the entire circuit region (CA) and light-emitting region (EA) where the thin-film transistors 112 are located. Alternatively, the planarization layer 113 can be formed over the entire non-display region (NDA) excluding the pad portion (PA) and the display region (DA). For example, the planarization layer 113 may extend from the display region (DA) to the remaining non-display region (NDA) excluding the pad portion (PA), or may include an extended portion (or extended portion). Therefore, the planarization layer 113 can have a size that is relatively larger than the display region (DA).

[0097] In one example, the planarization layer 113 is formed to have a relatively thick surface, and can provide a flat surface on the display area (DA) and non-display area (NDA). For example, the planarization layer 113 can be made of organic materials such as photoacrylic, benzocyclobutene, polyimide, and fluororesin.

[0098] The planarization layer 113 may include a first planarization layer 1131 and a second planarization layer 1132 placed on the first planarization layer 1131. The first planarization layer 1131 can be placed on the substrate 110. The second planarization layer 1132 can be placed on the first planarization layer 1131. In one example, the second planarization layer 1132 can be placed between the first planarization layer 1131 and the pixel electrode 114.

[0099] As shown in Figure 4, the first flattening layer 1131 is provided so as to cover the passivation layer 111c and the color filter (CF), and can be formed continuously across multiple subpixels (SP). In contrast, the second flattening layer 1132 can be formed discontinuously by forming the first pattern portion 130 inside the multiple subpixels (SP) and the second pattern portion 140 outside the multiple subpixels (SP) (or between the multiple subpixels (SP)). Therefore, as shown in Figure 4, multiple second flattening layers 1132 can be provided on the first flattening layer 1131 in an island configuration.

[0100] Referring to Figures 3 and 4, the upper surface of the second planarization layer 1132 can be made flat. As a result, the pixel electrode 114 on the second planarization layer 1132 can also be made flat, and the organic light-emitting layer 116 and cathode electrode 117 formed thereon can also be made in a flat form. Since the pixel electrode 114, the organic light-emitting layer 116 and cathode electrode 117, i.e., the organic light-emitting element layer (E), are made flat in the light-emitting region (EA), the thicknesses of the pixel electrode 114, the organic light-emitting layer 116 and cathode electrode 117 can be formed uniformly within the light-emitting region (EA). Therefore, the organic light-emitting layer 116 can emit light uniformly without deviation within the light-emitting region (EA).

[0101] The pixel electrode 114 can be formed on the second planarization layer 1132. As shown in Figure 3, the pixel electrode 114 can be connected to the drain or source electrode of a thin-film transistor via a contact hole that penetrates the first planarization layer 1131 and the passivation layer 111c. The ends of the pixel electrode 114 can be covered by a bank 115. Since Figure 3 is a cross-sectional view in the first direction (Y-axis direction), the bank 115 can be configured to cover the upper and lower ends of the pixel electrode 114 with respect to a plane (e.g., Figure 2). In contrast, as shown in Figure 4, the bank 115 may not be positioned between multiple subpixels (SPs). Therefore, the display device 100 according to one embodiment of this specification can be configured in a bankless structure in which the bank 115 is not positioned between multiple subpixels (SPs) arranged in the second direction (X-axis direction).

[0102] The pixel electrode 114 can consist of at least one of a transparent metallic material or a semi-transparent metallic material.

[0103] Since the display device 100 according to one embodiment of this specification is configured as a bottom-emitting type, the pixel electrodes 114 can be formed from a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0104] On the other hand, the material forming the pixel electrode 114 may include MoTi. Such a pixel electrode 114 can be referred to as the first electrode or anode electrode.

[0105] Bank 115 is a region that does not emit light and can be positioned adjacent to the light-emitting regions (EAs) of each of the multiple subpixels (SPs). For example, Bank 115 can be positioned in a non-light-emitting region (NEA) (or a second non-light-emitting region (NEA2) above or below the pixel electrode 114). Bank 115 can cover the edges of the pixel electrode 114. This prevents Bank 115 from contacting the pixel electrode 114 and the cathode electrode 117 at the edges of the pixel electrode 114. The exposed portion of the pixel electrode 114 that is not covered by Bank 115 can be included in the light-emitting portion (or light-emitting region (EA)).

[0106] After the bank 115 is formed, the organic light-emitting layer 116 can be formed to cover the pixel electrode 114 and the bank 115. Thus, the bank 115 can be partially located between the pixel electrode 114 and the organic light-emitting layer 116. Such a bank 115 can be referred to in terms of a pixel-defining film. In one example, the bank 115 may contain organic and / or inorganic materials.

[0107] The organic light-emitting layer 116 can be formed on the pixel electrode 114 and the bank 115. The organic light-emitting layer 116 can be placed below the cathode electrode 117. In one example, the organic light-emitting layer 116 can be placed in an emitting region (EA) and a non-emitting region (NEA) (or a first non-emitting region (NEA1) and a second non-emitting region (NEA2)). Since the organic light-emitting layer 116 is provided between the pixel electrode 114 and the cathode electrode 117, when a voltage is applied to each of the pixel electrode 114 and the cathode electrode 117, an electric field is formed between the pixel electrode 114 and the cathode electrode 117, and the organic light-emitting layer 116 can emit light. The organic light-emitting layer 116 can be formed from a plurality of subpixels (SP) and a common layer provided on the bank 115.

[0108] An example of an organic light-emitting layer 116 may be configured to emit white light. The organic light-emitting layer 116 may comprise a plurality of stacks that emit light of different hues. For example, the organic light-emitting layer 116 may comprise a first stack, a second stack, and a charge generation layer (CGL) provided between the first and second stacks. By configuring the light-emitting layer to emit white light, each of the plurality of subpixels (SPs) may include a color filter (CF) corresponding to the corresponding color.

[0109] The first stack is provided on the pixel electrode 114 and may consist of a structure in which a hole injection layer (HIL), a hole transport layer (HTL), a blue light emission layer (EML(B)), and an electron transport layer (ETL) are stacked in that order.

[0110] The charge generation layer plays the role of supplying charge to the first and second stacks. The charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack and a P-type charge generation layer for supplying holes to the second stack. The N-type charge generation layer may contain a metallic material as a dopant.

[0111] The second stack is provided on the first stack and may consist of a structure in which a hole transport layer (HTL), a yellow-green (YG) emitting layer (EML(YG)), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in that order.

[0112] In one embodiment of this specification, the display device 100 includes an organic light-emitting layer 116 as a common layer, so that the first stack, charge generation layer, and second stack can be arranged across multiple subpixels (SPs). In other examples, the organic light-emitting layer 116 can be provided in a 3-stack or 4-stack structure depending on the number of stacks that are stacked.

[0113] The cathode electrode 117 can be formed on the organic light-emitting layer 116. The cathode electrode 117 can be placed in the non-display area (NDA) (or a part of the non-display area (NDA)) and the display area (DA). In the display area (DA), the cathode electrode 117 can be placed in the light-emitting area (EA) and the non-light-emitting area (NEA) (or a first non-light-emitting area (NEA1) and a second non-light-emitting area (NEA2)). That is, the cathode electrode 117 can be provided so as to cover the entire display area (DA). Consequently, by providing the cathode electrode 117 in a size larger than the display area (DA) and smaller than the substrate 110, it can be placed in the non-display area (NDA) (or a part of the non-display area (NDA)) and the display area (DA).

[0114] In one example, the cathode electrode 117 may include a metallic material. The cathode electrode 117 can reflect light emitted from the organic light-emitting layer 116 in multiple subpixels (SPs) toward the lower surface of the substrate 110. Therefore, the display device 100 according to one embodiment of this specification can be implemented as a bottom-emitting type display device.

[0115] The display device 100 according to one embodiment of this specification is a bottom-emitting type, and since the light emitted by the organic light-emitting layer 116 must be reflected toward the substrate 110, the cathode electrode 117 can be made of a highly reflective metallic material. In one example, the cathode electrode 117 can be formed of a highly reflective metallic material such as silver (Ag), aluminum (Al), a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, and a laminated structure of Ag alloy and ITO (ITO / Ag alloy / ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. Such a cathode electrode 117 can be referred to as a second electrode, a counter electrode, or a reflective electrode.

[0116] A sealing layer 118 is formed on the cathode electrode 117. The sealing layer 118 serves to prevent oxygen and moisture from penetrating the organic light-emitting layer 116 and the cathode electrode 117. The sealing layer 118 may consist of multiple layers, each containing at least one inorganic film and at least one organic film. The sealing layer 118 may further contain an absorbent material to absorb moisture and oxygen in order to enhance its moisture-preventing effect. For example, the absorbent material may be a getter.

[0117] On the other hand, as shown in Figure 3, the sealing layer 118 can be placed not only in the light-emitting region (EA) but also in the non-light-emitting region (NEA). The sealing layer 118 can be placed between the cathode electrode 117 and the opposing substrate 200.

[0118] In a display device 100 according to one embodiment of this specification, the first planarization layer 1131 may be provided with a different refractive index from that of the second planarization layer 1132. For example, the refractive index of the second planarization layer 1132 may be greater than that of the first planarization layer 1131. As a result, as shown in Figure 4, the light emitted by the organic light-emitting layer 116 toward the substrate 110 is totally reflected due to the refractive index difference between the second planarization layer 1132 and the first planarization layer 1131, and the path of the light can be changed toward the first reflector 150 and the second reflector 160. Therefore, the light whose path is formed toward the first reflector 150 and the second reflector 160 can be emitted in the form of front-extracted light of subpixels (SPs) that are reflected and emitted by the first reflector 150 and the second reflector 160. Hereinafter, the light that is reflected by the first reflector 150 and the second reflector 160 and emitted toward the substrate 110 is defined as reflected light (EL).

[0119] As shown in Figure 4, the reflected light (EL) may include a first reflected light (EL1) and a second reflected light (EL2).

[0120] The first reflected light (EL1) is a front-extracted light that is emitted in the organic light-emitting layer 116, is waveguided via total internal reflection between the pixel electrode 114 and the cathode electrode 117 (and / or total internal reflection between the cathode electrode 117 and the second planarization layer 1132), and then reflected by the first reflector 150 and the second reflector 160 and emitted onto the substrate 110. Since the first reflected light (EL1) is emitted as waveguided light, it can be expressed in terms of WG mode extracted light (EL1).

[0121] The second reflected light (EL2) is a front-extracted light that is emitted by the organic light-emitting layer 116, undergoes total internal reflection at the interface between the first planarization layer 1131 and the second planarization layer 1132, and is then emitted by the first reflector 150 and the second reflector 160 and emitted onto the substrate 110. Since the second reflected light (EL2) emits light that is totally internally reflected and annihilated by the substrate 110, it can be expressed using the term substrate-mode extracted light (EL2).

[0122] On the other hand, in the case of a typical display device, a non-emitting region is not provided inside the light-emitting region. This is because if a non-emitting region is provided inside the light-emitting region, the size (or area) of the light-emitting region decreases, thus reducing the light efficiency. Therefore, in the case of a typical display device, a non-emitting region is not provided inside the light-emitting region. However, the light emitted in the light-emitting region can be waveguided by total internal reflection between the pixel electrode and the cathode electrode, but the waveguided light can disappear after going through numerous total internal reflection processes. The number of times the light disappears due to waveguide increases as the area of ​​the light-emitting region is larger, so the light efficiency decreases.

[0123] The display device 100 according to one embodiment of this specification can partially isolate the light-emitting regions (EAs) by providing a first non-light-emitting region (NEA1) inside each of the multiple subpixels (SPs) (or inside each of the light-emitting regions (EAs) of the multiple subpixels (SPs)). Therefore, the display device 100 according to one embodiment of this specification can minimize the light lost by the waveguide, and can instead emit light that has been wavered through the first reflector 150 provided in the first non-light-emitting region (NEA1) to the outside, thereby improving light efficiency.

[0124] Referring again to Figure 4, in a display device 100 according to one embodiment of this specification, the first non-emitting area (NEA1) may include a first planarization layer 1131, a second planarization layer 1132, a first pattern portion 130, and a first reflective portion 150. As described above, the first planarization layer 1131 may be provided on the substrate 110, and the second planarization layer 1132 may be provided on the first planarization layer 1131. The first pattern portion 130 may be provided on the second planarization layer 1132. The first reflective portion 150 may be provided on the first pattern portion 130.

[0125] For example, the first pattern portion 130 can be formed in a concave shape in the second planarization layer 1132. For instance, the first pattern portion 130 can be formed by patterning and removing a portion of the second planarization layer 1132 located inside each of the multiple subpixels (SPs). Therefore, the first pattern portion 130 can be described in terms of a home, slit, groove, trench, overcoat layer slit, or overcoat layer trench located inside each of the multiple subpixels (SPs).

[0126] As shown in Figure 4, the first pattern portion 130 can be positioned at a distance from the light-emitting region (EA). In one example, the first pattern portion 130 can be provided inside a plurality of subpixels (SP) (or light-emitting region (EA)) in the form of a slit or trench. The width of the first pattern portion 130 can be formed such that it decreases in the direction toward the substrate 110 (or in the direction toward the substrate 110) in the first reflective portion 150.

[0127] As shown in Figure 4, the first pattern portion 130 may include an inclined surface 130s positioned at an angle to the upper surface of the substrate 110, and a bottom surface 130b extending from the inclined surface 130s and positioned parallel to the upper surface of the substrate 110. The inclined surface 130s may be the inclined surface of the second planarization layer 1132. The bottom surface 130b may be part of the upper surface 1131a of the first planarization layer 1131.

[0128] As shown in Figure 4, the first pattern portion 130 can be comprised of the inclined surface 130s of the second flattening layer 1132 and the bottom surface 130b of the first flattening layer 1131, but is not necessarily limited to this. In other examples, the first pattern portion 130 can be formed only on the second flattening layer 1132. In this case, the inclined surface of the first pattern portion 130 may be the inclined surface of the second flattening layer 1132, and the bottom surface of the first pattern portion 130 may be the bottom surface of the second flattening layer 1132.

[0129] In one example, the first reflective portion 150 can be positioned on the first pattern portion 130. The first reflective portion 150 is made of a material capable of reflecting light, so that it can reflect light emitted in the light-emitting region (EA) and / or light totally reflected at the interface between the first planarization layer 1131 and the second planarization layer 1132 toward the front of the subpixel (SP) that emits light. The first reflective portion 150 can be formed along the profile of the first pattern portion 130 which is concavely formed in the first non-light-emitting region (NEA1). As shown in Figure 4, the first reflective portion 150 is part of the cathode electrode 117 positioned in the first non-light-emitting region (NEA1), and can therefore be represented by the drawing reference numeral 117'.

[0130] An example of the first reflecting section 150 may include a first flat reflecting section 151 and a first inclined reflecting section 152. The first flat reflecting section 151 can be arranged parallel to the upper surface of the substrate 110. The first inclined reflecting section 152 can be connected to the first flat reflecting section 151 and arranged to be inclined.

[0131] As shown in Figure 4, the first flat reflector 151 can be positioned between two light-emitting regions (EAs) (or two cross-sectional light-emitting regions (EAs)) provided in one sub-pixel (SP) (for example, a second sub-pixel (SP2)). That is, it can be positioned parallel to the upper surface of the substrate 110 on the first pattern portion 130 in the first non-light-emitting region (NEA1). Therefore, the first flat reflector 151 can be described in terms of a flat reflector located inside each of the multiple sub-pixels (SPs).

[0132] The first inclined reflecting portion 152 can be positioned so as to be inclined on the first pattern portion 130 located in the first non-emitting area (NEA1). Therefore, the first inclined reflecting portion 152 can be described in terms of a side reflecting portion or an inclined reflecting portion located inside each of the multiple subpixels (SPs).

[0133] Therefore, the display device 100 according to one embodiment of this specification is configured such that a reflector (or first reflector 150) can be placed in the non-emitting region (NEA) (or first non-emitting region (NEA1)) provided inside each of the plurality of subpixels (SP), thereby enabling light extraction even in the non-emitting region (NEA) (or first non-emitting region (NEA1)), and thus improving light efficiency.

[0134] Referring to Figure 4, in a display device 100 according to one embodiment of this specification, the second non-emitting area (NEA2) may include a second pattern portion 140 and a second reflective portion 160. The second pattern portion 140 may be formed concavely in the second planarization layer 1132. The second reflective portion 160 may be provided on the second pattern portion 140.

[0135] In one example, the second pattern portion 140 can be formed in a concave shape in the second planarization layer 1132. For example, the second pattern portion 140 can be formed by patterning and removing a portion of the second planarization layer 1132 located outside each of the multiple subpixels (SPs). Therefore, the second pattern portion 140 can be described using terms such as home, slit, groove, trench, overcoat layer slit, or overcoat layer trench, located outside each of the multiple subpixels (SPs).

[0136] As shown in Figure 4, the second pattern portion 140 can be positioned at a distance from the light-emitting region (EA). In one example, the second pattern portion 140 can be provided outside a plurality of subpixels (SP) (or light-emitting region (EA)) in the form of slits or trenches. The width of the second pattern portion 140 can be formed to decrease as you move from the second reflective portion 160 toward the substrate 110 (or from the pixel electrode 114 toward the substrate 110).

[0137] As shown in Figure 4, the second pattern portion 140 may include an inclined surface 140s positioned to be inclined with respect to the upper surface of the substrate 110, and a bottom surface 140b extending from the inclined surface 140s and positioned parallel to the upper surface of the substrate 110. The inclined surface 140s of the second pattern portion 140 may be an inclined surface of the second planarization layer 1132. The bottom surface 140b of the second pattern portion 140 may be part of the upper surface 1131a of the first planarization layer 1131.

[0138] As shown in Figure 4, the second pattern portion 140 can be comprised of the inclined surface 140s of the second flattening layer 1132 and the bottom surface 140b of the first flattening layer 1131, but is not necessarily limited to this. In other examples, the second pattern portion 140 can be formed only on the second flattening layer 1132. In this case, the inclined surface of the second pattern portion 140 may be the inclined surface of the second flattening layer 1132, and the bottom surface of the second pattern portion 140 may be the bottom surface of the second flattening layer 1132.

[0139] In one example, the second reflective portion 160 can be positioned on the second pattern portion 140. By comprising a material capable of reflecting light, the second reflective portion 160 can reflect light emitted in the light-emitting region (EA) and / or light totally reflected at the interface between the first planarization layer 1131 and the second planarization layer 1132 toward the front of the subpixel (SP) that emits light. The second reflective portion 160 can be formed along the profile of the second pattern portion 140 which is concavely formed in the second non-light-emitting region (NEA2). As shown in Figure 4, the second reflective portion 160 is part of the cathode electrode 117 positioned in the second non-light-emitting region (NEA2), and can therefore be represented by the drawing reference numeral 117''.

[0140] An example of a second reflective section 160 may include a second flat reflective section 161 and a second inclined reflective section 162. The second flat reflective section 161 can be arranged parallel to the upper surface of the substrate 110. The second inclined reflective section 162 can be connected to the second flat reflective section 161 and arranged to be inclined.

[0141] As shown in Figure 4, the second flat reflector 161 is located between two subpixels (SPs). For example, it can be positioned parallel to the top surface of the substrate 110 on the second pattern portion 140 in the second non-emitting area (NEA2) between the first subpixel (SP1) and the second subpixel (SP2). Therefore, the second flat reflector 161 can be described in terms of a flat reflector located outside each of the multiple subpixels (SPs).

[0142] The second inclined reflecting portion 162 can be positioned to be inclined on the second pattern portion 140 located in the second non-emitting area (NEA2). Therefore, the second inclined reflecting portion 162 can be described in terms of a side reflecting portion or an inclined reflecting portion located outside each of the multiple subpixels (SPs).

[0143] Therefore, the display device 100 according to one embodiment of this specification is configured such that a reflective portion (or second reflective portion 160) is placed in a non-emitting region (NEA) (or second non-emitting region (NEA2)) located outside a plurality of subpixels (SPs), allowing the reflective portion (or second reflective portion 160) to reflect light directed toward adjacent subpixels (SPs), thereby maximizing the light extraction efficiency.

[0144] As a result, the display device 100 according to this specification can extract light even in non-emissive areas (NEA) via reflective sections (or first reflective section 150 and second reflective section 160) provided on the inside and outside of each of the multiple subpixels (SP). Therefore, compared to a display device that does not have reflective sections on the inside and outside of each of the multiple subpixels, it can have the same luminous efficiency with lower power consumption or even improve the luminous efficiency to an even greater extent, thereby reducing overall power consumption.

[0145] On the other hand, the display device 100 according to one embodiment of this specification can reduce the size (or area) of the circuit area (CA) by arranging the wiring 120 (or first wiring 121) in the first non-emitting area (NEA1), which is a dead zone, thereby expanding the size (or area) of the light-emitting area (EA). Therefore, as shown in Figure 4, the display device 100 according to one embodiment of this specification can have a structural feature in which the wiring 120 (or first wiring 121) overlaps with the first flat reflector 151.

[0146] In the display device 100 according to one embodiment of this specification, the width (W1) of the wiring 120 (or first wiring 121) can be the same as or narrower than the width (W2) of the first flat reflector 151. If the width (W1) of the wiring 120 (or first wiring 121) is wider than the width (W2) of the first flat reflector 151, the wiring 120 (or first wiring 121) will block the reflected light that is reflected by the first inclined reflector 152 and emitted in the forward direction. Therefore, in the display device 100 according to one embodiment of this specification, by having the width (W1) of the wiring 120 (or first wiring 121) be the same as or narrower than the width (W2) of the first flat reflector 151, the reflected light that is reflected by the first inclined reflector 152 is not blocked, and thus the light extraction efficiency can be improved.

[0147] Referring to Figure 4, the substrate 110 may include data wiring (DL) (or second data wiring (DL2)) partially superimposed on the second flat reflector 161. As shown in Figure 2, the data wiring (DL) (or second data wiring (DL2)) can be connected to wiring 120. Since wiring 120 is connected to the thin-film transistor 112 in the circuit region (CA), the data wiring (DL) (or second data wiring (DL2)) can be connected to the thin-film transistor 112 via wiring 120. Therefore, data signals (or data power) applied from the pad portion (PA) to the data wiring (DL) (or second data wiring (DL2)) can be applied to the thin-film transistor 112 via wiring 120.

[0148] In a display device 100 according to one embodiment of this specification, each pixel electrode 114 of a plurality of sub-pixels (SPs) can be arranged at a distance from the respective first reflecting portion 150 of the plurality of sub-pixels (SPs). For example, with reference to Figure 4, the pixel electrode 114 of the second sub-pixel (SP2) can be arranged at a predetermined distance in the second direction (X-axis direction) from the first reflecting portion 150 provided in the first non-emitting region (NEA1). Since the first reflecting portion 150 is a cathode electrode 117' arranged on the first pattern portion 130, the pixel electrode 114 can be arranged at a distance from the first point (PT1) connecting the upper surface of the second planarization layer 1132 and the inclined surface 130s of the first pattern portion 130 to the edge of the pixel electrode (or the right edge of the pixel electrode 114).

[0149] If the pixel electrode 114 is not positioned at a distance from the first reflective portion 150, the pixel electrode 114 may be formed on the inclined surface 130s of the first pattern portion 130 during its formation. In this case, light emission can occur even on the inclined surface 130s of the first pattern portion 130, and the emitted light may be emitted towards sub-pixels (SP) of other colors (for example, a third sub-pixel (SP3)), causing color mixing.

[0150] Therefore, in the display device 100 according to one embodiment of this specification, the occurrence of color mixing can be prevented by arranging each pixel electrode 114 of the plurality of subpixels (SPs) at a distance from the first reflective section 150.

[0151] On the other hand, the first reflecting portion 150 can be positioned partially closer to the substrate 110 than the pixel electrodes 114. For example, as shown in Figure 4, a portion of the first flat reflecting portion 151 and the first inclined reflecting portion 152 of the first reflecting portion 150 can be positioned closer to the substrate 110 than the pixel electrodes 114. The display device 100 according to one embodiment of this specification is a bottom-emitting type and can improve light extraction efficiency via the first reflecting portion 150 (or first inclined reflecting portion 152) located on the first pattern portion 130 which is concavely formed inside the sub-pixel (SP). Therefore, the display device 100 according to one embodiment of this specification can have a structural feature in which a portion of the first flat reflecting portion 151 and the first inclined reflecting portion 152 of the first reflecting portion 150 is positioned closer to the substrate 110 than the pixel electrodes 114.

[0152] Referring again to Figure 4, in the display device 100 according to one embodiment of this specification, each pixel electrode 114 of a plurality of subpixels (SPs) can be arranged at a distance from the second reflecting portion 160 of each of the plurality of subpixels (SPs). For example, with reference to Figure 4, the pixel electrode 114 of the second subpixel (SP2) can be arranged at a predetermined distance in the second direction (X-axis direction) from the second reflecting portion 160 provided in the second non-emitting region (NEA2). Since the second reflecting portion 160 is a cathode electrode 117'' arranged on the second pattern portion 140, the pixel electrode 114 can be arranged at a distance from the second point (PT1) connecting the upper surface of the second planarization layer 1132 and the inclined surface 140s of the second pattern portion 140 to the edge of the pixel electrode 114 (or the left edge of the pixel electrode 114).

[0153] If the pixel electrode 114 is not positioned separately from the second reflective portion 160, the pixel electrode 114 can be formed on the inclined surface 140s of the second pattern portion 140 when it is formed. In this case, light emission can occur even on the inclined surface 140s of the second pattern portion 140, and the emitted light may be emitted towards sub-pixels (SP) of other colors (for example, the first sub-pixel (SP1)), causing color mixing.

[0154] Therefore, in the display device 100 according to one embodiment of this specification, color mixing can be prevented by arranging each pixel electrode 114 of the plurality of subpixels (SP) at a distance from the second reflective section 160.

[0155] On the other hand, the second reflecting portion 160 can be positioned closer to the substrate 110 than the pixel electrode 114 in part. For example, as shown in Figure 4, a portion of the second flat reflecting portion 161 and the second inclined reflecting portion 162 of the second reflecting portion 160 can be positioned closer to the substrate 110 than the pixel electrode 114. The display device 100 according to one embodiment of this specification is a bottom-emitting type and can improve light extraction efficiency via the second reflecting portion 160 (or second inclined reflecting portion 162) located on the second pattern portion 140 which is concavely formed on the outside of the subpixel (SP). Therefore, the display device 100 according to one embodiment of this specification can have a structural feature in which a portion of the second flat reflecting portion 161 and the second inclined reflecting portion 162 of the second reflecting portion 160 is positioned closer to the substrate 110 than the pixel electrode 114.

[0156] As a result, the display device 100 according to one embodiment of this specification can improve light efficiency because the first reflective section 150 is provided between the pixel electrodes 114 located inside a single subpixel (SP), thereby enabling light extraction even in the first non-emitting area (NEA1) where the wiring 120 is located.

[0157] Furthermore, in the display device 100 according to one embodiment of this specification, the second reflecting section 160 is provided between the pixel electrodes 114 of each of the multiple sub-pixels (SPs) that emit different colors from each other, so that light directed toward adjacent sub-pixels (SPs) can be reflected in the forward direction, thereby preventing color mixing while maximizing light extraction efficiency.

[0158] Furthermore, the wiring 120 included in the display device 100 according to one embodiment of this specification is provided so as to partially overlap the first non-emitting region (NEA1) where no light is emitted, which can reduce the size (or area) of the circuit region compared to a general display device, and thus relatively expand the size (or area) of the light-emitting region (EA). Therefore, the display device 100 according to one embodiment of this specification can improve light efficiency by expanding the size (or area) of the light-emitting region (EA).

[0159] Figure 5 is a schematic plan view showing one subpixel of a display device according to a comparative example, and Figure 6 is a schematic plan view showing one subpixel (e.g., a first subpixel (SP1)) of a display device according to one embodiment of this specification.

[0160] Referring to Figure 5, the light-emitting region (EA) (or pixel electrode) of the display device according to the comparative example. The (PE) can be provided between the circuit area (CA) and the reference wiring (RL) in the first direction (Y-axis direction). In addition, the light-emitting area (EA) (or pixel electrode (PE)) of the display device according to the comparative example can be provided between the pixel power wiring (EVDD) and the data wiring (DL) in the second direction (X-axis direction). Therefore, the light-emitting area (EA) (or pixel electrode (PE)) of the display device according to the comparative example can be provided with a size (or area) having a first light-emitting length (EVL1) in the first direction (Y-axis direction) and a first width (EW1) in the second direction (X-axis direction).

[0161] In the comparative example, the light-emitting region (EA) of the display device may be provided separated from the reference wiring (RL) by a first upper length (REL1) in the first direction (Y-axis direction). The first upper length (REL1) may be the length of the upper process margin region for forming the reference wiring (RL). The light-emitting region (EA) may also be provided separated from the gate wiring (GL) by a first lower length (BVL1) or more. The first lower length (BVL1) may be the length of the lower process margin region for forming the gate wiring (GL).

[0162] On the other hand, the circuit area (CA) of the display device according to the comparative example can be comprised of a size (or area) that includes thin-film transistors (TFTs) and data branch wiring (BRL). As shown in Figure 5, the data branch wiring (BRL) can include a first data branch wiring (BRL1) connected to the thin-film transistors (TFTs) and a second data branch wiring (BRL2) connected to the first data branch wiring (BRL1) and the data wiring (DL). The first data branch wiring (BRL1) can extend in a first direction (Y-axis direction), and the second data branch wiring (BRL2) can extend in a second direction (X-axis direction). Therefore, the circuit area (CA) of the display device according to the comparative example can be comprised of a size (or area) that has a first circuit length (CVL1) in the first direction (Y-axis direction) and a first width (EW1) in the second direction (X-axis direction).

[0163] Consequently, in the case of the display device used in the comparative example, the data branching lines (BRL) are located in the circuit area (CA), which limits the expansion of the size (or area) of the light-emitting region (EA), making it difficult to improve light efficiency.

[0164] In contrast, in the display device 100 according to one embodiment of this specification, the size (or area) of the circuit area (CA) can be reduced by arranging the wiring 120 to partially overlap the first non-emitting area (NEA1) located inside the subpixel (SP), thereby relatively expanding the size (or area) of the light-emitting area (EA).

[0165] For example, as shown in Figure 6, the first wiring 121 can extend from the thin-film transistor 112 in a first direction (Y-axis direction) and partially superimpose on the light-emitting region (EA) and the first non-light-emitting region (NEA1). The first wiring 121 can then be connected to the second wiring 122 between the light-emitting region (EA) and the reference wiring (RL). The second wiring 122 can extend in a second direction (X-axis direction) and be connected to the data wiring (DL) (for example, the first data wiring (DL1)).

[0166] Therefore, in the display device 100 according to one embodiment of this specification, since the second wiring 122 is located in the upper process margin area, the size of the circuit area (CA) can be reduced compared to a comparative example in which the second data branch wiring (BRL2) is provided in the circuit area (CA). The width of the second wiring 122 may be smaller than that of the upper process margin area. Therefore, in the display device 100 according to one embodiment of this specification, the second wiring 122 can be located in the upper process margin area.

[0167] By arranging the second wiring 122 in the upper process margin region, the circuit region (CA) can be provided with a size (or area) having a second circuit length (CVL2) in the first direction (Y-axis direction) and a second width (EW2) in the second direction (X-axis direction). The second circuit length (CVL2) may be the length obtained by subtracting the first lower length (BVL1) from the first circuit length (CVL1). The second width (EW2) may be the same as the first width (EW1).

[0168] Therefore, the display device 100 according to one embodiment of this specification may have a smaller circuit area (CA) compared to the display device according to the comparative example. Therefore, the display device 100 according to one embodiment of this specification can have an expanded light-emitting area (EA).

[0169] For example, the light-emitting region (EA) may have a size (or area) such that it has a second light-emitting length (EVL2) in the first direction (Y-axis direction) and a second width (EW2) in the second direction (X-axis direction). The second light-emitting length (EVL2) may be the sum of the first light-emitting length (EVL1) and the first lower length (BVL1). The second width (EW2) may be the same as the first width (EW1).

[0170] On the other hand, in the display device 100 according to one embodiment of this specification, a first non-emitting region (NEA1) is provided inside the light-emitting region (EA), but since light extraction can be performed by the first reflector 150, the reduction in light efficiency may be minimal.

[0171] As a result, the display device 100 according to one embodiment of this specification, by equipping the wiring 120 so as to partially overlap the first non-emitting region (NEA1) and the emitting region (EA), can expand the size (or area) of the emitting region (EA) compared to the display device according to the comparative example, and improve the light efficiency.

[0172] Referring to Figure 6, the width (LW1) (or W1) of the first wiring 121 can be narrower than the width of the first non-emitting area (NEA1). If the width (LW1) (or W1) of the first wiring 121 is the same as or greater than the width of the first non-emitting area (NEA1), it will block the light reflected and emitted by the first reflector 150, reducing the light efficiency. Therefore, in the display device 100 according to one embodiment of this specification, the width (LW1) (or W1) of the first wiring 121 is narrower than the width of the first non-emitting area (NEA1), thus preventing a decrease in light efficiency.

[0173] The width (LW2) of the second wiring 122 can be narrower than the second upper length (REL2). The second upper length (REL2) can be the same as the first upper length (REL1). If the width (LW2) of the second wiring 122 is the same as the second upper length (REL2), the manufacturing process may become difficult, and if the width of the second wiring 122 is wider than the second upper length (REL2), the light-emitting area (EA) may be obstructed and the light efficiency may decrease. Therefore, in one embodiment of this specification, the display device 100 can be manufactured more easily and a decrease in light efficiency can be prevented by providing the second wiring 122 with a width (LW2) narrower than the second upper length (REL2).

[0174] In one embodiment of this specification, the display device 100 may be provided with pixel electrodes 114 in each light-emitting region (EA) of a plurality of subpixels (SP). In one example, the pixel electrodes 114 may be provided in a closed-loop configuration or a horseshoe-shaped configuration with one side open.

[0175] For example, as shown in Figure 6, the pixel electrode 114 can be provided in a closed-loop configuration. Here, the pixel electrode 114 may include a first pixel electrode 114a, a second pixel electrode 114b, a third pixel electrode 114c, and a fourth pixel electrode 114d.

[0176] The first pixel electrode 114a can be positioned at a distance from one side 150a of the first reflector 150. For example, one side 150a of the first reflector 150 can refer to the uppermost side of the first inclined reflector 152 located to the left of the first flat reflector 151, with reference to Figure 4. The second pixel electrode 114b can be positioned at a distance from the other side 150b of the first reflector 150. The other side 150b of the first reflector 150 can refer to the uppermost side of the first inclined reflector 152 located to the right of the first flat reflector 151, with reference to Figure 4. The third pixel electrode 114c can connect one side of the first pixel electrode 114a (for example, the upper side of the first pixel electrode 114a with reference to Figure 6) and one side of the second pixel electrode 114b (for example, the upper side of the second pixel electrode 114b with reference to Figure 6). The fourth pixel electrode 114d can connect the other side of the first pixel electrode 114a (for example, the lower side of the first pixel electrode 114a with reference to Figure 6) and the other side of the second pixel electrode 114b (for example, the lower side of the second pixel electrode 114b with reference to Figure 6).

[0177] Therefore, in one embodiment of this specification, the display device 100 can be provided with each pixel electrode 114 of a plurality of subpixels (SPs) in a closed-loop configuration when viewed in a planar view. In this case, the wiring 120 can be partially superimposed on two or more of the first pixel electrode 114a, the second pixel electrode 114b, the third pixel electrode 114c, and the fourth pixel electrode 114d.

[0178] For example, as shown in Figure 6, the first wiring 121 can be positioned between the first pixel electrode 114a and the second pixel electrode 114b. The first wiring 121 can be extended in a first direction (Y-axis direction). Therefore, the first wiring 121 can partially overlap with the third pixel electrode 114c and the fourth pixel electrode 114d, respectively. Conversely, the second wiring 122 can be connected to the first wiring 121 and positioned in a different direction from the first wiring 121. For example, the second wiring 122 can be extended in a second direction (X-axis direction) while connecting to the end of the first wiring 121 that protrudes into the upper process margin region. Therefore, the second wiring 122 may not overlap with the pixel electrode 114. Thus, the display device 100 according to one embodiment of this specification can expand the size (or area) of the light-emitting region (EA) by a first lower length (BVL1) compared to the display device according to the comparative example, and can improve the light efficiency.

[0179] On the other hand, in the display device 100 according to one embodiment of this specification, the width (LW1) (or W1) of the first wiring 121 may be narrower than the width (LW2) of the second wiring 122. As described above, the first wiring 121 partially overlaps the first non-emitting region (NEA1) where the first reflector 150 is located, so if the width (LW1) (or W1) of the first wiring 121 is the same as or wider than the width (LW2) of the second wiring 122, it can block the light reflected by the first reflector 150. In contrast, the second wiring 122 is located in an upper process margin region that is relatively wider than the width of the first non-emitting region (NEA1) in the second direction (X-axis direction), so it can have a wider width than the first wiring 121. Therefore, a display device 100 according to one embodiment of this specification may have a structural feature in which the width (LW1) (or W1) of the first wiring 121 is narrower than the width (LW2) of the second wiring 122.

[0180] Figure 7 is a schematic plan view showing one subpixel of a display device according to a second embodiment of this specification.

[0181] Referring to Figure 7, the display device 100 according to the second embodiment of this specification is the same as the display device shown in Figure 6 described above, except that the structure of the pixel electrode 114 and the wiring 120 has been changed. Therefore, the same reference numerals are used for identical components, and only the different components will be described below.

[0182] In the case of the display device shown in Figure 6 described above, the first wiring 121 can be provided in the upper process margin region such that it partially overlaps with the third pixel electrode 114c and the fourth pixel electrode 114d, respectively, and the second wiring 122 does not overlap with the pixel electrode 114. Therefore, in the case of the display device shown in Figure 6, the size of the circuit region (CA) can be reduced compared to the comparative example in which the second data branch wiring (BRL2) is provided in the circuit region (CA). Furthermore, in the case of the display device shown in Figure 6, the size (or area) of the light-emitting region (EA) can be expanded by the amount by which the size of the circuit region (CA) has been reduced. For example, in the case of the display device shown in Figure 6, the light-emitting region (EA) can be provided with a size (or area) having a second light-emitting length (EVL2) in the first direction (Y-axis direction) and a second width (EW2) in the second direction (X-axis direction). The second light-emitting length (EVL2) may be the sum of the first light-emitting length (EVL1) and the first lower length (BVL1). The second width (EW2) may be the same as the first width (EW1). Therefore, in the case of the display device shown in Figure 6, the size (or area) of the light-emitting region (EA) can be expanded compared to the display device in the comparative example, and the light efficiency can be improved.

[0183] In contrast, in the display device shown in Figure 7, the first wiring 121 can partially overlap with the fourth pixel electrode 114d, and the second wiring 122 can partially overlap with the second pixel electrode 114b. For example, as shown in Figure 7, the first wiring 121 can extend from the thin-film transistor 112 and partially overlap with the fourth pixel electrode 114d. The end of the first wiring 121 can be placed in the first non-emitting area (NEA1). The second wiring 122 can connect to the end of the first wiring 121 in the first non-emitting area (NEA1) and extend in the second direction (X-axis direction) to connect to the data wiring (DL). Therefore, the second wiring 122 can partially overlap with the second pixel electrode 114b. Thus, in the display device shown in Figure 7, since the second wiring 122 is not provided in the upper process margin area, the size (or area) of the light-emitting area (EA) can be further expanded in the first direction (Y-axis direction).

[0184] For example, in the display device shown in Figure 7, the light-emitting region (EA) may have a size (or area) such that it has a third light-emitting length (EVL3) in the first direction (Y-axis direction) and a third width (EW3) in the second direction (X-axis direction). The third light-emitting length (EVL3) may be the sum of the first light-emitting length (EVL1), the first lower length (BVL1), and the first' upper length (REL1'). The first' upper length (REL1') may be shorter than the first upper length (REL1). This is because if the first' upper length (REL1') is the same as or longer than the first upper length (REL1), the light efficiency will decrease due to the pixel electrode 114 overlapping with the reference wiring (RL). The third width (EW3) may be the same as the first width (EW1). Therefore, in the case of the display device shown in Figure 7, the size (or area) of the light-emitting region (EA) can be further expanded in the first direction (Y-axis direction) compared to the display device shown in Figure 6, thereby improving the light efficiency.

[0185] On the other hand, as shown in Figure 7, the circuit region (CA) of the display device 100 according to the second embodiment of this specification may have a size (or area) having a third circuit length (CVL3) in the first direction (Y-axis direction) and a third width (EW3) in the second direction (X-axis direction). The third circuit length (CVL3) may be the length obtained by subtracting the first lower length (BVL1) from the first circuit length (CVL1). The third width (EW3) may be the same as the first width (EW1).

[0186] Figure 8 is a schematic plan view showing one subpixel of a display device according to the third embodiment of this specification.

[0187] Referring to Figure 8, the display device 100 according to the third embodiment of this specification is the same as the display device shown in Figure 6 described above, except that the structure of the pixel electrode 114 has been changed. Therefore, the same reference numerals are used for identical components, and only the different components will be described below.

[0188] In the case of the display device shown in Figure 6, the pixel electrode 114 is provided in a closed-loop configuration. Therefore, in the case of the display device shown in Figure 6, the first wiring 121 can be provided in the upper process margin region such that it partially overlaps with the third pixel electrode 114c and the fourth pixel electrode 114d, respectively, and the second wiring 122 does not overlap with the pixel electrode 114. Therefore, in the case of the display device shown in Figure 6, the size of the circuit region (CA) can be reduced compared to the display device in the comparative example, thereby relatively expanding the size (or area) of the light-emitting region (EA).

[0189] For example, in the case of the display device shown in Figure 6, the light-emitting region (EA) can be provided with a size (or area) having a second light-emitting length (EVL2) in the first direction (Y-axis direction) and a second width (EW2) in the second direction (X-axis direction). The second light-emitting length (EVL2) may be the sum of the first light-emitting length (EVL1) and the first lower length (BVL1). The second width (EW2) may be the same as the first width (EW1). Therefore, in the case of the display device shown in Figure 6, the size (or area) of the light-emitting region (EA) can be expanded compared to the display device in the comparative example, and the light efficiency can be improved.

[0190] In contrast, in the case of the display device shown in Figure 8, the pixel electrode 114 can have a horseshoe shape with one side open. For example, in the display device shown in Figure 8, the fourth pixel electrode 114d can be omitted. Therefore, the display device 100 shown in Figure 8 can have the pixel electrode 114 comprised of a first pixel electrode 114a, a second pixel electrode 114b, and a third pixel electrode 114c. As shown in Figure 8, since the pixel electrode 114 is provided in a horseshoe shape, the first non-emitting area (NEA1) can be connected to the second non-emitting area (NEA2).

[0191] In the display device shown in Figure 8, the wiring 120 can partially overlap with one of the first pixel electrode 114a, the second pixel electrode 114b, and the third pixel electrode 114c. For example, as shown in Figure 8, the first wiring 121 can extend from the thin-film transistor 112 in a first direction (Y-axis direction) and partially overlap with the third pixel electrode 114c. The end of the first wiring 121 can be placed in the upper process margin region. The second wiring 122 can be connected to the end of the first wiring 121 that protrudes into the upper process margin region. The second wiring 122 can extend in a second direction (X-axis direction) and be connected to the data wiring (DL). Therefore, the second wiring 122 may not overlap with the pixel electrode 114. Thus, in the display device shown in Figure 8, the size (or area) of the light-emitting region (EA) can be expanded by a first lower length (BVL1) compared to the display device in the comparative example, and the light efficiency can be improved.

[0192] For example, in the display device shown in Figure 8, the light-emitting region (EA) can be provided with a size (or area) having a fourth light-emitting length (EVL4) in the first direction (Y-axis direction) and a fourth width (EW4) in the second direction (X-axis direction). The fourth light-emitting length (EVL4) may be the sum of the first light-emitting length (EVL1) and the first lower length (BVL1). The fourth width (EW4) may be the same as the first width (EW1). Therefore, in the display device shown in Figure 8, the size (or area) of the light-emitting region (EA) can be further expanded in the first direction (Y-axis direction) compared to the display device in the comparative example, thereby improving the light efficiency.

[0193] On the other hand, as shown in Figure 8, the circuit region (CA) of the display device 100 according to the third embodiment of this specification may have a size (or area) having a fourth circuit length (CVL4) in the first direction (Y-axis direction) and a fourth width (EW4) in the second direction (X-axis direction). The fourth circuit length (CVL4) may be the length obtained by subtracting the first lower length (BVL1) from the first circuit length (CVL1). The fourth width (EW4) may be the same as the first width (EW1).

[0194] Figure 9 is a schematic plan view showing one subpixel of a display device according to the fourth embodiment of this specification.

[0195] Referring to Figure 9, the display device 100 according to the fourth embodiment of this specification is the same as the display device shown in Figure 7 described above, except that the structure of the pixel electrode 114 has been changed. Therefore, the same reference numerals are used for identical components, and only the different components will be described below.

[0196] In the display device shown in Figure 7, the pixel electrode 114 is provided in a closed-loop configuration. Therefore, in the display device shown in Figure 7, the first wiring 121 can partially overlap with the fourth pixel electrode 114d, and the second wiring 122 can partially overlap with the second pixel electrode 114b. Consequently, in the display device shown in Figure 7, since the second wiring 122 is not provided in the upper process margin region, the size (or area) of the light-emitting region (EA) can be further expanded in the first direction (Y-axis direction) compared to the case where the second wiring is provided in the upper process margin region.

[0197] In contrast, in the case of the display device shown in Figure 9, the pixel electrode 114 can be provided in a horseshoe shape with one side open. For example, in the case of the display device shown in Figure 9, the fourth pixel electrode 114d can be omitted. Therefore, the display device 100 shown in Figure 9 can be provided with the pixel electrode 114 as a first pixel electrode 114a, a second pixel electrode 114b, and a third pixel electrode 114c. As shown in Figure 9, by providing the pixel electrode 114 in a horseshoe shape, the first non-emitting area (NEA1) can be connected to the second non-emitting area (NEA2).

[0198] In the display device shown in Figure 9, the wiring 120 can partially overlap with one of the first pixel electrode 114a, the second pixel electrode 114b, and the third pixel electrode 114c. For example, as shown in Figure 9, the first wiring 121 can extend from the thin-film transistor 112 in a first direction (Y-axis direction) and have its end located in the first non-emitting area (NEA1). Therefore, the first wiring 121 may not overlap with the pixel electrode 114. The second wiring 122 can be connected to the end of the first wiring 121 located in the first non-emitting area (NEA1). The second wiring 122 can then extend in a second direction (X-axis direction) and be connected to the data wiring (DL). Therefore, the second wiring 122 can partially overlap with the second pixel electrode 114b. Therefore, in the case of the display device shown in Figure 9, since the second wiring 122 is not provided in the upper process margin region, the size (or area) of the light-emitting region (EA) can be further expanded in the first direction (Y-axis direction).

[0199] For example, in the display device shown in Figure 9, the light-emitting region (EA) may have a size (or area) such that it has a fifth light-emitting length (EVL5) in the first direction (Y-axis direction) and a fifth width (EW5) in the second direction (X-axis direction). The fifth light-emitting length (EVL5) may be the sum of the first light-emitting length (EVL1), the first lower length (BVL1), and the first' upper length (REL1'). The first' upper length (REL1') may be shorter than the first upper length (REL1). This is because if the first' upper length (REL1') is the same as or longer than the first upper length (REL1), the light efficiency will decrease due to the pixel electrode 114 overlapping with the reference wiring (RL). The fifth width (EW5) may be the same as the first width (EW1). Therefore, in the case of the display device shown in Figure 9, the size (or area) of the light-emitting region (EA) can be further expanded in the first direction (Y-axis direction) compared to the case in which the second wiring 122 is provided in the upper process margin region, and the light efficiency can be further improved.

[0200] On the other hand, as shown in Figure 9, the circuit region (CA) of the display device 100 according to the fourth embodiment of this specification may have a size (or area) having a fifth circuit length (CVL5) in the first direction (Y-axis direction) and a fifth width (EW5) in the second direction (X-axis direction). The fifth circuit length (CVL5) may be the length obtained by subtracting the first lower length (BVL1) from the first circuit length (CVL1). The fifth width (EW5) may be the same as the first width (EW1).

[0201] As shown in Figure 6, the display device 100 according to one embodiment of this specification may have the best light efficiency compared to other embodiments because the first wiring 121, which is narrower than the second wiring 122, is provided so as to partially overlap the third pixel electrode 114c and the fourth pixel electrode 114d. That is, the display device 100 according to one embodiment of this specification has two screen areas where the light-emitting area (EA) is blocked by the first wiring 121, but the area of ​​the screen area is the smallest compared to other embodiments, so it may have the best light efficiency compared to other embodiments.

[0202] As shown in Figure 8, the display device 100 according to the third embodiment of this specification has a horseshoe-shaped pixel electrode 114 and a screen area that occurs only once, but the fourth pixel electrode 114d is omitted, so the light efficiency (or luminous efficiency) may be lower than that of the display device 100 according to the first embodiment.

[0203] On the other hand, as shown in Figure 7, the display device 100 according to the second embodiment of this specification has a closed-loop pixel electrode 114 (or light-emitting region (EA)) that extends to a part of the upper process margin region, so the area of ​​the pixel electrode 114 (or light-emitting region (EA)) may be the largest compared to other embodiments. Therefore, because the area of ​​the pixel electrode 114 (or light-emitting region (EA)) is the largest compared to other embodiments, the display device 100 according to the second embodiment of this specification may have the lowest current density during operation, and thus the longest service life.

[0204] Although embodiments of this specification have been described in more detail above with reference to the attached figures, this specification is not necessarily limited to such embodiments, and can be modified and implemented in various ways without departing from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and such embodiments do not limit the scope of the technical concept of this specification. Accordingly, the embodiments described above should be understood in all respects to be illustrative and not limiting. The scope of protection of this specification should be interpreted as per the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this specification. [Explanation of symbols]

[0205] 100: Display device 110: Circuit board P: Pixel 111: Multiple inorganic films 112: Thin-film transistor 113: Flattening layer 114: Pixel electrode 115: Bank 116: Organic light-emitting layer 117: Cathode electrode 118: Sealing layer 120: Wiring 130: First pattern section 140: Second pattern section 150: 1st reflection section 160:Second reflection section NEA1: First non-emitting region NEA2: Second non-luminescent region

Claims

1. A substrate containing multiple pixels having multiple subpixels, The substrate is provided with a light-emitting region in each of the plurality of subpixels, Wiring partially superimposed on the aforementioned light-emitting region and Display devices, including

2. Includes a thin-film transistor for driving each of the plurality of sub-pixels, The aforementioned wiring is a branch wiring connected to the thin-film transistor. The display device according to claim 1.

3. The display device according to claim 2, wherein the branch wiring is data branch wiring.

4. The substrate is provided with a second non-emitting region located outside each of the plurality of subpixels, The aforementioned second non-emitting region is A first planarization layer provided on the substrate, A second flattening layer provided on the first flattening layer, A second pattern portion formed in a concave shape in the second planarization layer, The second reflective portion provided in the second pattern portion and The display device according to claim 1, including the following:

5. The display apparatus according to claim 4, wherein the first planarization layer has a refractive index different from that of the second planarization layer.

6. The display device according to claim 4, wherein the second reflective portion is provided between the pixel electrodes of each of the plurality of subpixels that emit light of different colors from each other.

7. Each of the plurality of sub-pixels includes a pixel electrode arranged at a distance from the second reflective portion, The second reflective portion is partially positioned closer to the substrate than the pixel electrode, The display device according to claim 4.

8. The second reflecting part is A second flat reflective portion is arranged parallel to the upper surface of the substrate, A second inclined reflecting portion is provided so as to be inclined and connected to the second flat reflecting portion. Includes, The substrate includes data wiring that is partially superimposed on the second flat reflector portion. The data wiring is connected to the wiring, The display device according to claim 4.

9. Each of the plurality of subpixels further includes a first non-emitting region located inside the light-emitting region, The aforementioned wiring is partially superimposed on the first non-emitting region. The display device according to claim 4.

10. The first non-emitting region is The first pattern portion formed in a concave shape in the second planarization layer, The first reflective portion provided in the first pattern portion and The display device according to claim 9, including the following:

11. Each of the plurality of sub-pixels includes a pixel electrode arranged at a distance from the first reflecting portion, The first reflective portion is partially positioned closer to the substrate than the pixel electrode. The display device according to claim 10.

12. The first reflecting part is A first flat reflective portion is arranged parallel to the upper surface of the substrate, A first inclined reflective portion is connected to the first flat reflective portion and is provided to be inclined, Includes, The aforementioned wiring is superimposed on the first flat reflector, The display device according to claim 10.

13. The display device according to claim 12, wherein the width of the wiring is the same as the width of the first flat reflector, or the width of the wiring is narrower than the first flat reflector.

14. Each of the plurality of sub-pixels includes a pixel electrode provided in the light-emitting region, The aforementioned pixel electrode is A first pixel electrode is positioned at a distance from one side of the first reflecting portion, A second pixel electrode is positioned at a distance from the other side of the first reflecting portion, A third pixel electrode connecting one side of the first pixel electrode and one side of the second pixel electrode, A fourth pixel electrode connecting the other side of the first pixel electrode and the other side of the second pixel electrode Includes, The wiring is partially superimposed on two or more of the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode. The display device according to claim 10.

15. The aforementioned wiring, A first wiring positioned between the first pixel electrode and the second pixel electrode, A second wiring is connected to the first wiring and arranged in a different direction from the first wiring. Includes, The first wiring partially overlaps with the fourth pixel electrode, The second wiring partially overlaps with the second pixel electrode, The display device according to claim 14.

16. The aforementioned plurality of subpixels The first subpixel and, A second sub-pixel adjacent to the first sub-pixel in the second direction, In the second direction, the third sub-pixel adjacent to the second sub-pixel and Includes, The first subpixel is a red subpixel, the second subpixel is a green subpixel, and the third subpixel is a blue subpixel. The display device according to claim 15.

17. The plurality of subpixels further include data wiring arranged in a first direction between the first subpixel and the second subpixel, The second wiring partially overlaps with the data wiring, The display device according to claim 16.

18. The plurality of subpixels further include banks that cover both ends of the pixel electrode in the first direction, The bank is not located between the first subpixel and the second subpixel, and between the second subpixel and the third subpixel. The display device according to claim 16.

19. Each of the aforementioned subpixels is A circuit region including a thin-film transistor is provided on one side of the light-emitting region, and Gate wiring arranged in the second direction between the light-emitting region and the circuit region. The display device according to claim 17, further comprising:

20. The first sub-pixel further includes a pixel power supply wiring arranged parallel to the data wiring with respect to the light-emitting region, The gate wiring partially overlaps with the pixel power wiring and the data wiring, The display device according to claim 19.

Images