Light-emitting display device

Abstract

To provide a light-emitting display device with reduced reflectivity, improved light efficiency, and enhanced display image quality. [Solution] A light-emitting display device according to one or more embodiments of this specification includes a substrate having a plurality of subpixels having light-emitting regions and non-light-emitting regions, data lines and gate lines arranged in the non-light-emitting regions on the substrate and intersecting each other, at least one insulating layer arranged on the data lines and gate lines, and a color filter arranged on the at least one insulating layer and corresponding to each subpixel, wherein at least one of the plurality of subpixels includes a low-reflection pattern superimposed on the light-emitting region.

Description

Technical Field

[0001] This specification relates to a light-emitting display device.

Background Art

[0002] As the information society develops, the requirements for display devices for displaying images are increasing in various forms. As a result, in recent years, display devices such as liquid crystal display devices (LCDs), organic light-emitting display devices (OLEDs), micro LED display devices (Micro Light Emitting Diode: Micro LED Display), and quantum dot display devices (Quantum Dot Display: QD) have been utilized.

[0003] Among display devices, an organic light-emitting display device is a self-luminance type, which injects holes and electrons into the inside of a light-emitting layer from an anode electrode for hole injection and a cathode electrode for electron injection, respectively, and emits light when excitons formed by the injected holes and electrons fall from an excited state to a ground state to display an image.

[0004] In such an organic light-emitting display device, a polarizing plate is mainly used on the display surface of the panel to reduce external light reflection. However, when a polarizing plate is used in an organic light-emitting display device, there is a problem that the transmittance decreases, resulting in a decrease in panel efficiency and an increase in power consumption.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved in this specification is to provide a light-emitting display device that can reduce the reflectance and improve the light efficiency with a pol-less structure without using a polarizing plate (polarizer).

[0006] Another problem addressed in this specification is to provide a light-emitting device that can reduce reflectivity, improve light efficiency, and improve display image quality by optimizing the cell reflectivity of the light-emitting part to conform to a poll-less structure while maintaining the area of ​​the light-emitting part.

[0007] The problems addressed by one or more embodiments of this specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A light-emitting display device according to one or more embodiments of this specification includes a substrate having a plurality of subpixels having light-emitting regions and non-light-emitting regions, data lines and gate lines arranged in the non-light-emitting regions on the substrate and intersecting each other, at least one insulating layer arranged on the data lines and gate lines, and a color filter arranged on the at least one insulating layer and corresponding to each subpixel, wherein at least one of the plurality of subpixels includes a low-reflection pattern superimposed on the light-emitting region.

[0009] Specific details, other than the solutions to the problems mentioned above, are included in the following descriptions and figures. [Effects of the Invention]

[0010] According to one or more embodiments of this specification, it is possible to provide a light-emitting device that can reduce reflectivity and improve light efficiency in a poll-less structure that does not use polarizing plates.

[0011] According to one or more embodiments of this specification, a light-emitting device can be provided that reduces reflectivity, improves light efficiency, and improves display image quality by optimizing the cell reflectivity of the light-emitting part to conform to a poll-less structure while maintaining the area of ​​the light-emitting part.

[0012] One or more embodiments of this specification of light-emitting devices can optimize cell reflectivity while maintaining the light-emitting area, even in a poll-less structure that does not use polarizing plates. This reduces the reflectivity of the light-emitting device, improves light efficiency, and enhances display quality. Furthermore, by using uni-materials for the light-emitting device, costs can be reduced, power consumption can be lowered, and reliability and display quality can be improved, thus contributing to ESG (Environmental, Social, Governance) by reducing production energy.

[0013] The effects described herein are not limited to those mentioned above, and any other effects not mentioned will be clearly understood by those skilled in the art from the following description.

[0014] Since the problem to be solved, the means of solving the problem, and the effects described above do not specify the essential features of the claims, the scope of rights of the claims is not limited by the matters described in the content of the invention. [Brief explanation of the drawing]

[0015] [Figure 1] This figure shows a light-emitting device according to an embodiment of this specification. [Figure 2] This is a circuit diagram of a subpixel of a light-emitting display device according to the embodiments described herein. [Figure 3] This figure shows a plurality of subpixels in a display panel according to an embodiment of this specification. [Figure 4] This is a cross-sectional view taken along the line I-I' shown in Figure 3 according to the embodiments of this specification. [Figure 5] This figure shows a plurality of subpixels in a display panel according to one embodiment of this specification. [Figure 6] This is a cross-sectional view taken along line II-II' shown in Figure 5 according to one embodiment of this specification. [Figure 7] This figure shows multiple subpixels in a display panel according to another embodiment of this specification. [Figure 8]It is a cross-sectional view of line III-III' shown in FIG. 7 according to other embodiments of the present specification. [Figure 9] It is a diagram showing a plurality of sub-pixels in a display panel according to other embodiments of the present specification. [Figure 10] It is a cross-sectional view of line IV-IV' shown in FIG. 9 according to other embodiments of the present specification. [Figure 11] It is a diagram showing a plurality of sub-pixels in a display panel according to other embodiments of the present specification. [Figure 12] It is a cross-sectional view of line V-V' shown in FIG. 11 according to other embodiments of the present specification. [Figure 13] It is a diagram showing a plurality of sub-pixels in a display panel according to other embodiments of the present specification. [Figure 14] It is a cross-sectional view of line VI-VI' shown in FIG. 13 according to other embodiments of the present specification. [Figure 15] It is a diagram showing a plurality of sub-pixels in a display panel according to other embodiments of the present specification. [Figure 16] It is a cross-sectional view of line VII-VII' shown in FIG. 15 according to other embodiments of the present specification.

Mode for Carrying Out the Invention

[0016] The advantages and features of the present specification, and the method for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but is embodied in various different forms, and the present embodiments are merely provided to make the disclosure of the present specification complete and to fully inform those with ordinary knowledge in the technical field to which the present specification belongs of the scope of the invention, and the present specification is only defined by the scope of the claims.

[0017] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the figures used to illustrate the embodiments of this specification are illustrative, and this specification is not limited to what is shown in the figures. Throughout the specification, the same drawing number refers to the same component. In this specification, if a specific description of the relevant prior art is deemed to unnecessarily obscure the gist of this specification, such detailed description will be omitted.

[0018] Wherever "contains," "has," "consists of," etc., as used herein, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it contains multiple components unless otherwise explicitly stated.

[0019] In interpreting the constituent elements, even if there is no separate explicit mention of the error range, it shall be interpreted as including the error range.

[0020] When describing spatial relationships, for example, if the positional relationship between two parts is described using phrases such as "above," "above," "below," or "beside," then one or more other parts may be located between the two parts, unless expressions such as "immediately" or "directly" are used.

[0021] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it can include non-continuous events unless expressions like "immediately" or "directly" are used.

[0022] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0023] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component in question.

[0024] When a component is described as “connecting,” “joining,” “attaching,” or “adhering” to another component, it should be understood that the component may directly connect, join, attach, or adhere to the other component, but that other components may also be interposed between each component that can indirectly connect, join, attach, or adhere to it, unless otherwise explicitly stated.

[0025] Where it is stated that a component or layer "contacts" or "overlaps" with another component or layer, it should be understood that while other components may directly contact or overlap with other components, unless otherwise explicitly stated, other components may also be interposed between each component that can indirectly contact or overlap.

[0026] "At least one" must be understood to include all combinations of one or more of the relevant components. For example, "at least one of the first, second, and third components" could mean not only the first, second, or third component, but also all combinations of two or more of the first, second, and third components.

[0027] Each feature of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, and various technical interdependencies and drives are possible. Each embodiment can be implemented independently of one another or in conjunction with one another.

[0028] The embodiments of this specification are described below through the attached figures and examples. The scales of the components shown in the figures are different from those of actual components for the sake of explanation and are not limited to those shown in the figures.

[0029] Figure 1 shows a light-emitting device according to an embodiment of this specification.

[0030] In the following, the X-axis indicates the direction parallel to the scan line (or gate line), the Y-axis indicates the direction parallel to the data line, and the Z-axis indicates the height direction of the light-emitting display device.

[0031] Although the light-emitting display devices described herein primarily consist of examples of organic light-emitting displays, they can also be implemented as liquid crystal displays, quantum dot light-emitting diodes, or electrophoresis displays.

[0032] Referring to Figure 1, the light-emitting display device according to the embodiment of this specification may include a display panel 110, a scan drive unit 120 (or gate drive unit) built into the display panel 110, a data drive unit 130 connected to the display panel 110, a timing control unit 160 that controls the scan drive unit 120 and the data drive unit 130, and a power supply circuit 170.

[0033] The display panel 110 may include a display area (DA) and a non-display area (NDA) arranged around the display area (DA). The display panel 110 has pixels (P) in the display area (DA) that can display an image. Each pixel (P) may contain multiple subpixels (SP). The structure of the subpixels (SP) can be varied depending on the type of light-emitting device. For example, the subpixels (SP) may be configured in a top emission, bottom emission, or dual emission manner depending on their structure. A subpixel (SP) is a unit that can form a specific type of color filter or emit its own hue without forming a color filter. A subpixel (SP) may have one or more different light-emitting areas depending on its light-emitting characteristics. For example, multiple subpixels (SPs) may be arranged in a stripe or quad configuration, but the embodiments described herein are not limited thereto. The color type, arrangement type, and arrangement order of the subpixels (SPs) can be configured in various ways depending on the light emission characteristics, element lifespan, and device specifications.

[0034] The display panel 110 may have data lines (DL) and scan lines (SL) (or gate lines) connected to subpixels (SP). The data lines (DL) may be arranged to intersect with the scan lines (SL). Each subpixel (SP) of the display panel 110 may be connected to one of the data lines (DL) and one of the scan lines (SL). The data lines (DL) may supply data voltage supplied from the data drive unit 130 to each subpixel (SP). The scan lines (SL) may supply scan signals supplied from the scan drive unit 120 to each subpixel (SP).

[0035] In each subpixel (SP), when it is turned on by the scan signal and the data voltage of the data line (DL) is supplied to the gate electrode of the drive transistor, the light-emitting element can emit light due to the drain-source current of the drive transistor. The scan drive unit 120 can receive a scan control signal (GCS) input from the timing control unit 160. The scan drive unit 120 can use the scan control signal (GCS) to supply a scan signal or an illumination control signal to the scan line (SL).

[0036] The scan drive unit 120 may be configured in a GIP (gate driver in panel) manner in the non-display area (NDA) on one or both sides of the display area (DA). Alternatively, the scan drive unit 120 may be fabricated as a drive chip, mounted on a flexible film, and attached to the non-display area (NDA) on one or both sides of the display area (DA) using a TAB (tape automated bonding) method.

[0037] The data drive unit 130 can receive digital video data (DATA) and data control signals (DCS) from the timing control unit 160. The data drive unit 130 can use the data control signals (DCS) to convert the digital video data (DATA) into analog positive / negative data voltages and supply them to the data line (DL).

[0038] The timing control unit 160 can receive digital video data (DATA) and timing signals from the host system. The timing signals may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The vertical synchronization signal is a signal that defines one frame period. The horizontal synchronization signal is a signal that defines one horizontal period required to supply data voltage to a pixel of one horizontal line on the display panel 110. The data enable signal is a signal that defines the period during which valid data is input. The dot clock is a signal that repeats at a predetermined short period.

[0039] The timing control unit 160 can generate a data control signal (DCS) to control the operating timing of the data drive unit 130 and a scan control signal (GCS) to control the operating timing of the scan drive unit 120 based on the timing signal. The timing control unit 160 can output the scan control signal (GCS) to the scan drive unit 120 and output digital video data (DATA) and data control signal (DCS) to the data drive unit 130.

[0040] The power supply circuit 170 can generate and supply multiple drive voltages necessary for the operation of all circuit configurations of the light-emitting display device using the input voltage. The power supply circuit 170 can generate and supply a first power supply voltage (EVDD) (or pixel power supply voltage), a second power supply voltage (EVSS) (or common power supply voltage), and an initialization voltage (Vref) (or reference voltage) to the display panel 110. The power supply circuit 170 can generate and supply various drive voltages necessary for the operation of the scan drive unit 120, the data drive unit 130, and the timing control unit 160.

[0041] Figure 2 is a circuit diagram of a subpixel of a light-emitting device according to an embodiment of this specification.

[0042] Referring to Figure 2, each pixel (P) includes a plurality of subpixels (SPs) that constitute a unit pixel, and each of the plurality of subpixels (SPs) may include a pixel circuit and light-emitting element (ED) having a 3T(Transistor)1C(Capacitor) structure including a drive transistor (DR), a first switching transistor (TR1), a second switching transistor (TR2), and a storage capacitor (Cst), but the embodiments herein are not limited thereto. For example, each subpixel (SP) may further include a compensation circuit, in which case it may have various structures such as 3T2C, 4T1C, 4T2C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0043] Each subpixel (SP) may have at least one thin-film transistor (DR, TR1, TR2) that includes a gate electrode, a source electrode, and a drain electrode. The source electrode and drain electrode are not fixed and can be changed by the voltage and current direction applied to the gate electrode; therefore, one of the source electrode and drain electrode may be represented as the first electrode and the other as the second electrode. At least one thin-film transistor (DR, TR1, TR2) may be made of at least one of polysilicon semiconductor, amorphous silicon semiconductor, or oxide semiconductor. The transistors (DR, TR1, TR2) may be P-type or N-type, or a mixture of P-type and N-type transistors.

[0044] A drive transistor (DR) is a transistor for driving an ED, and may include a first node (N1) to which a data voltage (Vdata) is applied, a second node (N2) connected to the pixel electrode (first electrode or anode electrode) of the ED, and a third node (N3) connected to a first power supply voltage line (VDDL) (or pixel power supply voltage line) to which a first power supply voltage (EVDD) (or pixel power supply voltage) is applied. For example, the drive transistor (DR) may play a role in generating a data current from the first power supply voltage (EVDD) supplied from the first power supply voltage line (VDDL) and supplying it to the first electrode of the ED.

[0045] The first switching transistor (TR1) is responsible for supplying the data voltage (Vdata) from the data line (DL) to the first node (N1) of the drive transistor (DR), the second switching transistor (TR2) is responsible for supplying the reference voltage (Vref) from the reference line (REFL) to the second node (N2) of the drive transistor (DR), or for outputting the voltage of the second node (N2) of the drive transistor (DR), and the storage capacitor (Cst) may be connected between the first node (N1) and the second node (N2) of the drive transistor (DR) and be responsible for maintaining the data voltage (Vdata) supplied to the drive transistor (DR) for one frame, but the embodiments herein are not limited thereto.

[0046] The pixel electrode (first electrode or anode electrode) of the light-emitting element (ED) may be connected to the second node (N2) of a drive transistor (DR), and the common electrode (second electrode or cathode electrode) of the light-emitting element (ED) may be connected to a second power supply voltage line (VSSL). A light-emitting layer (or organic light-emitting layer) provided between the first and second electrodes of the light-emitting element (ED) can emit light in response to the drive current generated by the drive transistor (DR). The pixel electrode of the light-emitting element (ED) may be an independent electrode for each light-emitting element, and the common electrode and light-emitting layer of the light-emitting element (ED) may be a common layer shared by the entire light-emitting element, but the embodiments herein are not limited thereto.

[0047] Figure 3 shows a plurality of subpixels in a display panel according to an embodiment of this specification. Figure 4 is a cross-sectional view of the line I-I' shown in Figure 3 according to an embodiment of this specification.

[0048] Referring to Figures 3 and 4, the display panel 110 according to the embodiments of this specification may be configured as a top emission system, a bottom emission system, or a dual emission system. For example, the display panel 110 may be implemented as a bottom emission system.

[0049] The display panel 110 according to the embodiments of this specification may include a plurality of subpixels (SP1, SP2, SP3, SP4), a plurality of data lines (DL1, DL2, DL3, DL4), at least one scan line (SL) (or gate line), a first power supply voltage line (VDDL), pixel circuits (CA1, CA2, CA3, CA4), and at least one color filter (CF1, CF3, CF4), and the like.

[0050] Multiple subpixels (SP1, SP2, SP3, SP4) may be unit pixels representing different colors. These subpixels (SP1, SP2, SP3, SP4) may be arranged in a stripe pattern in a first direction (or X-axis direction) or a second direction (or Y-axis direction). For example, while multiple subpixels (SP1, SP2, SP3, SP4) may be arranged in a first direction (or X-axis direction), the embodiments herein are not limited thereto, and the arrangement order and configuration can be varied.

[0051] Multiple subpixels (SP1, SP2, SP3, SP4) may include light-emitting regions (EA1, EA2, EA3, EA4) where light-emitting elements (EDs) are located and emit light, and non-light-emitting regions (NEA). For example, the non-light-emitting region (NEA) may include a first non-light-emitting region (NEA1) where pixel circuits (CA1, CA2, CA3, CA4) are located, and a second non-light-emitting region (NEA2) between adjacent subpixels (SP1, SP2, SP3, SP4). For example, the first non-light-emitting region (NEA1) may have at least one scan line (SL) extending in a first direction (or the X-axis direction), and the second non-light-emitting region (NEA2) may have multiple data lines (DL1, DL2, DL3, DL4) and a first power supply voltage line (VDDL) extending in a second direction (or the Y-axis direction).

[0052] The light-emitting regions (EA1, EA2, EA3, EA4) may correspond to the regions that emit light in each subpixel (SP1, SP2, SP3, SP4). For example, each subpixel (SP1, SP2, SP3, SP4) includes a light-emitting element (ED) consisting of a pixel electrode (AE), an emissive layer (EL), and a common electrode (CE), and the light-emitting regions (EA1, EA2, EA3, EA4) may include the light-emitting elements (ED) of each subpixel (SP1, SP2, SP3, SP4), and the light-emitting regions (EA1, EA2, EA3, EA4) may include first to fourth light-emitting regions (EA1, EA2, EA3, EA4) that emit light of different colors from each other. For example, the first to fourth light-emitting regions (EA1, EA2, EA3, EA4) may be the aperture regions of the pixel electrode (AE) defined by the bank region (BA).

[0053] The first to fourth light-emitting regions (EA1, EA2, EA3, EA4) can emit light of different colors from each other through at least one color filter (CF1, CF3, CF4). For example, at least one color filter (CF1, CF3, CF4) can emit light of different colors from each other. For example, at least one color filter (CF1, CF3, CF4) may be composed of an organic material that transmits light of different colors from each other. At least one color filter (CF1, CF3, CF4) may include a first color filter (CF1) that transmits red light, a third color filter (CF3) that transmits blue light, and a fourth color filter (CF4) that transmits green light. For example, the first light-emitting region (EA1) of the first subpixel (SP1) can emit red light through the first color filter (CF1), the second light-emitting region (EA2) of the second subpixel (SP2) can emit white light either without a color filter or through a color filter that transmits white light, the third light-emitting region (EA3) of the third subpixel (SP3) can emit blue light through the third color filter (CF3), and the fourth light-emitting region (EA4) of the fourth subpixel (SP4) can emit green light through the fourth color filter (CF4), but the embodiments herein are not limited thereto.

[0054] At least one scan line (SL) (or gate line) may be positioned to superimpose on a first non-emitting region (NEA1) where pixel circuits (CA1, CA2, CA3, CA4) are located. At least one scan line (SL) may extend in a first direction (or X-axis direction) across the first non-emitting region (NEA1). At least one scan line (SL) may supply a scan signal to at least one thin-film transistor (TR1, TR2) contained within the pixel circuits (CA1, CA2, CA3, CA4). For example, at least one scan line (SL) may be constructed in the same layer of the same material as the gate electrode of at least one thin-film transistor (DR, TR1, TR2) located within the pixel circuits (CA1, CA2, CA3, CA4). For example, at least one scan line (SL) may include a low-reflection material layer for low reflection of external light.

[0055] Multiple data lines (DL1, DL2, DL3, DL4) may be arranged to correspond to each subpixel (SP1, SP2, SP3, SP4). Multiple data lines (DL1, DL2, DL3, DL4) may be arranged to overlap the second non-emitting area (NEA2) between adjacent subpixels (SP1, SP2, SP3, SP4). Multiple data lines (DL1, DL2, DL3, DL4) may be extended in a second direction (or Y-axis direction) within the second non-emitting area (NEA2). Multiple data lines (DL1, DL2, DL3, DL4) may be arranged to the left or right of each subpixel (SP1, SP2, SP3, SP4), but the embodiments herein are not limited thereto. For example, the first data line (DL1) may be located to the left of the first subpixel (SP1) and supply a data voltage to the first subpixel (SP1); the second data line (DL2) may be located to the left of the second subpixel (SP2) and supply a data voltage to the second subpixel (SP2); the third data line (DL3) may be located to the left of the third subpixel (SP3) and supply a data voltage to the third subpixel (SP3); and the fourth data line (DL4) may be located to the left of the fourth subpixel (SP4) and supply a data voltage to the fourth subpixel (SP4). For example, each data line (DL1, DL2, DL3, DL4) may be constructed in the same layer using the same material as the light-blocking layer arranged in the pixel circuit. Each data line (DL1, DL2, DL3, DL4) may include a low-reflection material layer for low reflection of external light.

[0056] The first power supply voltage line (VDDL) may be arranged to correspond to a plurality of subpixels (SP1, SP2, SP3, SP4). The first power supply voltage line (VDDL) may be arranged to superimpose on the second non-emitting area (NEA2) to the left or right of the plurality of subpixels (SP1, SP2, SP3, SP4). Alternatively, the first power supply voltage line (VDDL) may be arranged within the plurality of subpixels (SP1, SP2, SP3, SP4). For example, the first power supply voltage line (VDDL) may be arranged to superimpose on the second non-emitting area (NEA2) between the second and third subpixels (SP2, SP3), but the embodiments herein are not limited thereto. The first power supply voltage line (VDDL) may be constructed in the same material and on the same layer as the plurality of data lines (DL1, DL2, DL3, DL4), but the embodiments herein are not limited thereto.

[0057] Referring to Figure 4, the display panel 110 according to the embodiments herein may include a substrate 111, a plurality of data lines (DL1, DL2, DL3, DL4), a first power supply voltage line (VDDL), at least one scan line (SL), at least one insulating layer (BF, GI, PAS), at least one color filter (CF1, CF3, CF4), a planarization layer (OC), a pixel electrode (AE), a light-emitting layer (EL), and a common electrode (CE). For example, the display panel 110 may further include a bank section (BA) located on the planarization layer (OC) and the pixel electrode (AE).

[0058] At least one signal line and a power supply voltage line may be arranged on the substrate 111. For example, multiple data lines (DL1, DL2, DL3, DL4) and a first power supply voltage line (VDDL) may be arranged on the substrate 111. For example, the multiple data lines (DL1, DL2, DL3, DL4) and the first power supply voltage line (VDDL) may be made of the same material and in the same layer as the light-blocking layer arranged on the pixel circuits (CA1, CA2, CA3, CA4).

[0059] Multiple data lines (DL1, DL2, DL3, DL4) and a first power supply voltage line (VDDL) located at the bottom edge of the substrate 111 include a low-reflection material layer for low reflection of external light, and may include a conductive metal layer (M1) and a low-reflection material layer (LM1) beneath the metal layer (M1). For example, the metal layer (M1) may consist of a single or multiple layer made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiments herein are not limited thereto. The low-reflection material layer (LM1) may consist of molybdenum-titanium (MoTi) or molybdenum (Mo) as a metal layer with excellent low-reflection properties, or may include a metal oxide or alloy oxide. For example, the low-reflection material layer (LM1) may include copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but the examples herein are not limited thereto. For example, the multiple data lines (DL1, DL2, DL3, DL4) and the first power supply voltage line (VDDL) may be composed of copper (Cu) and molybdenum-titanium (MoTi), or may be a bilayer structure composed of copper (Cu) and a metal oxide.

[0060] At least one insulating layer (BF, GI, PAS) may be disposed on the substrate 111. The at least one insulating layer (BF, GI, PAS) may include a buffer layer (BF), a gate insulating layer (GI), and a passivation layer (PAS). For example, a buffer layer (BF) may be disposed on the substrate 111. The buffer layer (BF) may be configured to cover at least one signal line and power supply voltage line and an optical shielding layer on the substrate 111. A gate insulating layer (GI), a passivation layer (PAS), and at least one thin-film transistor may be disposed on the buffer layer (BF). For example, the at least one insulating layer (BF, GI, PAS) may include silicon oxide (SiO X ), silicon nitride (SiN X), may consist of a single or multiple layer containing an inorganic insulating material such as aluminum oxide (Al2O3), but the examples herein are not limited thereto.

[0061] At least one scan line (SL) (or gate line) may be located on the gate insulating layer (GI). At least one scan line (SL) may be located on the gate insulating layer (GI) and patterned together with the gate insulating layer (GI). At least one scan line (SL) may be made of the same material and in the same layer as the gate electrode of at least one thin-film transistor located in the pixel circuit (CA1, CA2, CA3, CA4).

[0062] At least one scan line (SL) may include a low-reflection material layer for low reflection of external light. For example, at least one scan line (SL) may include a conductive metal layer (M2) and a low-reflection material layer (LM2) beneath the metal layer (M2). For example, the metal layer (M2) may consist of a single or multiple layer of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the examples herein are not limited thereto. The low-reflection material layer (LM2) is a metal layer with excellent low-reflection properties and may consist of molybdenum-titanium (MoTi) or molybdenum (Mo), or may include a metal oxide or alloy oxide. For example, the low-reflection material layer (LM2) may include copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but the examples herein are not limited to these. For example, at least one scanline (SL) may be composed of copper (Cu) and molybdenum-titanium (MoTi), or a bilayer structure composed of copper (Cu) and a metal oxide.

[0063] A passivation layer (PAS) may be placed on at least one scan line (SL), and at least one color filter (CF1, CF3, CF4) may be placed on the passivation layer (PAS). At least one color filter (CF1, CF3, CF4) may be placed to correspond to the first subpixel (SP1), the third subpixel (SP3), and the fourth subpixel (SP4) of the first to fourth subpixels (SP1, SP2, SP3, SP4). The second subpixel (SP2) of the first to fourth subpixels (SP1, SP2, SP3, SP4) may not have a color filter. For example, the first light-emitting region (EA1) of the first subpixel (SP1) may have a first color filter (CF1) that converts white light emitted from the light-emitting element (ED) to red. The second light-emitting region (EA2) of the second subpixel (SP2) may not have a color filter and may emit white light from the light-emitting element (ED) as is. A third color filter (CF3) that converts white light emitted from the light-emitting element (ED) into blue light may be placed in the third light-emitting region (EA3) of the third subpixel (SP3). A fourth color filter (CF4) that converts white light emitted from the light-emitting element (ED) into green light may be placed in the fourth light-emitting region (EA4) of the fourth subpixel (SP4).

[0064] A planarization layer (OC) (or overcoat layer) may be placed on the passivation layer (PAS) and at least one color filter (CF1, CF3, CF4). The planarization layer (OC) flattens the step created by at least one signal line and power supply voltage line, at least one thin-film transistor, and at least one color filter (CF1, CF3, CF4) placed on the substrate 111, and may be composed of an organic insulating material. For example, the planarization layer (OC) may be composed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin, but the examples herein are not limited thereto.

[0065] On the planarization layer (OC), pixel electrodes (AE) (first electrode or anode electrode), light-emitting layer (EL) (or organic light-emitting layer), and common electrode (CE) (second electrode or cathode electrode) that constitute the light-emitting element (ED) may be arranged. Furthermore, bank portions (BA) configured to define the aperture region (or light-emitting region) of the pixel electrode (AE) may be arranged on the planarization layer (OC).

[0066] Pixel electrodes (AEs) may be arranged on a planarization layer (OC). Pixel electrodes (AEs) may be patterned and arranged on the planarization layer (OC) for each sub-pixel (SP1, SP2, SP3, SP4). Pixel electrodes (AEs) may be composed of a transparent or semi-transparent metallic material. For example, pixel electrodes (AEs) may be composed of a transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO), which can transmit light. Pixel electrodes (AEs) may be composed of a semi-transparent metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). For example, pixel electrodes (AEs) made of a semi-transparent metallic material can have their light extraction efficiency improved by a microcavity. Pixel electrodes (AEs) may be the anode electrodes of a light-emitting element (ED). According to the examples herein, the pixel electrode (AE) may further include a low-reflection metal layer. For example, the low-reflection metal layer may include a metal oxide or an alloy oxide. For example, the low-reflection metal layer may include copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but the examples herein are not limited to these.

[0067] A bank (BA) may be positioned on the pixel electrode (AE) and the planarization layer (OC). The bank (BA) may be positioned on the planarization layer (OC) so as to cover a portion of the edge of the pixel electrode (AE). The bank (BA) may be configured to define the aperture region (or light-emitting region) of the pixel electrode (AE). For example, the bank (BA) may be positioned between the pixel electrode (AE) and the light-emitting layer (EL). The aperture region of the pixel electrode (AE) may correspond to the light-emitting regions (EA1, EA2, EA3, EA4) of each subpixel (SP1, SP2, SP3, SP4). For example, the pixel electrode (AE) exposed by the bank (BA) can be electrically connected to the light-emitting layer (EL) and the common electrode (CE) by direct contact, thereby forming a light-emitting element (ED). For example, the bank (BA) may be omitted.

[0068] A bank (BA) may be located in the non-emitting area (NEA) of each subpixel (SP1, SP2, SP3, SP4). The bank (BA) may be superimposed on the pixel circuits (CA1, CA2, CA3, CA4) and at least one signal line and a power supply voltage line. For example, the bank (BA) may consist of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. For example, the bank (BA) may be a black bank containing at least one of a light-absorbing material or a black material. For example, the bank (BA) may contain a black resin or an insulating light-absorbing material such as graphite, but the examples herein are not limited thereto.

[0069] A light-emitting layer (EL) (or organic light-emitting layer) may be placed on the pixel electrode (AE) and the bank portion (BA). The light-emitting layer (EL) may include a hole transporting layer, an emission material layer, and an electron transporting layer. For example, when a voltage is applied to the pixel electrode (AE) and the common electrode (CE), holes and electrons move to the light-emitting layer (EL) via the hole transporting layer and electron transporting layer, respectively, and can combine with each other in the light-emitting layer (EL) to emit light. The light-emitting layer (EL) may be a common layer formed in common for multiple subpixels (SP1, SP2, SP3, SP4). For example, the light-emitting layer (EL) may be a white light-emitting layer that emits white light.

[0070] A common electrode (CE) may be placed on the light-emitting layer (EL). The common electrode (CE) may be a common layer formed in common for multiple subpixels (SP1, SP2, SP3, SP4). The common electrode (CE) can be placed on the pixel electrodes (AE) and light-emitting layer (EL) that are in contact with each other to constitute a light-emitting element (ED). For example, the common electrode (CE) may be formed from a highly reflective metallic material such as an aluminum-titanium laminated structure (Ti / Al / Ti), an aluminum-ITO laminated structure (ITO / Al / ITO), an Ag alloy, an Ag alloy-ITO laminated structure (ITO / Ag alloy / ITO), a MoTi alloy, and a MoTi alloy-ITO laminated structure (ITO / MoTi alloy / ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu). The MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). The common electrode (CE) may be the cathode electrode of the light-emitting element (ED). According to the examples herein, the common electrode (CE) may further include a low-reflection metal layer. For example, the low-reflection metal layer may include a metal oxide or an alloy oxide. For example, the low-reflection metal layer may include copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but the examples herein are not limited thereto.

[0071] According to the embodiments of this specification, the substrate 111 may further include a transmittance control film on its back surface. For example, the transmittance control film may include, but is not limited to, at least one of a transparent film or an absorbent film.

[0072] Figure 5 shows a plurality of subpixels in a display panel according to one embodiment of this specification. Figure 6 is a cross-sectional view taken along line II-II' shown in Figure 5, according to one embodiment of this specification. Figures 5 and 6 show one embodiment of this specification in which a low-reflection pattern configuration is added to the light-emitting device described with reference to Figures 1 to 4. In the following description with reference to Figures 5 and 6, the same reference numerals are used for the remaining identical components, except for the added low-reflection pattern, and redundant descriptions are omitted or simplified.

[0073] Referring to Figures 5 and 6, a display panel 110 according to one embodiment of this specification may include at least one light-emitting region (EA1, EA2, EA3, EA4) among a plurality of subpixels (SP1, SP2, SP3, SP4) and an overlaid low-reflection pattern (LP). The low-reflection pattern (LP) may be arranged among some or all of the plurality of subpixels (SP1, SP2, SP3, SP4).

[0074] A low-reflection pattern (LP) according to one embodiment of this specification may be configured to optimize the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) to accommodate a pol-less structure that does not use polarizers while maintaining the area of ​​the light-emitting regions (EA1, EA2, EA3, EA4). The low-reflection pattern (LP) may include a low-reflection material layer for low reflection of external light.

[0075] A low-reflection pattern (LP) according to one embodiment of this specification may be arranged to overlap with at least one color filter (CF1, CF3, CF4) in the light-emitting region (EA1, EA2, EA3, EA4). Alternatively, the low-reflection pattern (LP) may be arranged to overlap with a pixel electrode (AE) in the light-emitting region (EA1, EA2, EA3, EA4). At least one color filter (CF1, CF3, CF4) may be placed between the pixel electrode (AE) and the low-reflection pattern (LP).

[0076] A low-reflection pattern (LP) according to one embodiment of this specification may be constructed in the same layer as at least one of the data lines (DL1, DL2, DL3, DL4) and scan lines (SL) using the same material. The low-reflection pattern (LP) may be configured to be connected to the data lines (DL1, DL2, DL3, DL4) or to be configured to be separated from the data lines (DL1, DL2, DL3, DL4). For example, the low-reflection pattern (LP) may be configured integrally with the data lines (DL1, DL2, DL3, DL4) or to be a separate pattern separated from the data lines (DL1, DL2, DL3, DL4). Furthermore, the low-reflection pattern (LP) may be connected to the scan lines (SL) or to be configured to be separated from the scan lines (SL). For example, the low-reflection pattern (LP) may be configured integrally with the scan lines (SL) or to be a separate pattern separated from the scan lines (SL).

[0077] Referring to Figure 5, a low-reflection pattern (LP) according to one embodiment of this specification may extend from each data line (DL1, DL2, DL3, DL4) in a first direction (or X-axis direction) and be positioned to overlap with the light-emitting regions (EA1, EA2, EA3, EA4).

[0078] A low-reflection pattern (LP) extending in a first direction from the first data line (DL1) may be arranged in the first light-emitting region (EA1) of the first subpixel (SP1), a low-reflection pattern (LP) extending in a first direction from the second data line (DL2) may be arranged in the second light-emitting region (EA2) of the second subpixel (SP2), a low-reflection pattern (LP) extending in a first direction from the second data line (DL2) may be arranged in the third light-emitting region (EA3) of the third subpixel (SP3), a low-reflection pattern (LP) extending in a first direction from the third data line (DL3) may be arranged in the fourth light-emitting region (EA4) of the fourth subpixel (SP4), a low-reflection pattern (LP) extending in a first direction from the fourth data line (DL4).

[0079] Low-reflection patterns (LPs) extending from the first and third data lines (DL1, DL3) may be positioned above each light-emitting region (EA1, EA3) with reference to the second direction (or Y-axis direction), and low-reflection patterns (LPs) extending from the second and fourth data lines (DL2, DL4) may be positioned above each light-emitting region (EA2, EA4) with reference to the second direction (or Y-axis direction).

[0080] According to one embodiment of this specification, one or more low-reflection patterns (LPs) may extend from each data line (DL1, DL2, DL3, DL4), one or more low-reflection patterns (LPs) may be arranged in each light-emitting region (EA1, EA2, EA3, EA4), or the low-reflection patterns (LPs) may be arranged in only a portion of the light-emitting regions (EA1, EA2, EA3, EA4), but the embodiments of this specification are not limited thereto.

[0081] Referring to Figure 6, a low-reflection pattern (LP) according to one embodiment of this specification may be placed on a substrate 111. The low-reflection pattern (LP) may be constructed in the same layer as the data lines (DL1, DL2, DL3, DL4) and the first power supply voltage line (VDDL) on the substrate 111, using the same material. The low-reflection pattern (LP) may include a low-reflection material layer for low reflection of external light. The low-reflection pattern (LP) may include a conductive metal layer (M1) and a low-reflection material layer (LM1) beneath the metal layer (M1). For example, the metal layer (M1) may consist of a single or multiple layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiments herein are not limited thereto. The low-reflection material layer (LM1) may consist of a metal layer with excellent low-reflection properties, such as molybdenum-titanium (MoTi) or molybdenum (Mo), or it may contain a metal oxide or alloy oxide. For example, the low-reflection material layer (LM1) may contain copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but the examples herein are not limited to these. For example, the low-reflection pattern (LP) may consist of copper (Cu) and molybdenum-titanium (MoTi), or it may be a bilayer structure consisting of copper (Cu) and a metal oxide.

[0082] One end of the low-reflection pattern (LP) is connected to each data line (DL1, DL2, DL3, DL4), and the other end of the low-reflection pattern (LP) may be electrically floating. The low-reflection pattern (LP) may be superimposed on at least one color filter (CF1, CF3, CF4) and on the pixel electrode (AE) of each subpixel (SP1, SP2, SP3, SP4). At least one color filter (CF1, CF3, CF4) may be placed between the pixel electrode (AE) and the low-reflection pattern (LP).

[0083] The low-reflection pattern (LP) may include a low-reflection material layer (LM1) at its lower end, which has a lower reflectivity than the pixel electrodes (AE) and common electrodes (CE). By reflecting or absorbing a portion of the external light incident from the outside through the lower part of the low-reflection pattern (LP) with low reflectivity before reaching the pixel electrodes (AE), the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) can be reduced. Furthermore, a metal layer (M1) is placed on top of the low-reflection pattern (LP), which can improve light extraction efficiency by inducing internal re-reflection of light emitted from the light-emitting element (ED) through the upper part of the low-reflection pattern (LP).

[0084] According to one embodiment of this specification, while maintaining an optimized area of ​​the light-emitting regions (EA1, EA2, EA3, EA4) so ​​as not to increase current density or cause a decrease in display quality such as afterimages, the reflectivity to light incident from the outside can be reduced through a low-reflection pattern (LP) superimposed on the light-emitting regions (EA1, EA2, EA3, EA4), thereby inducing internal rereflection of light emitted from the light-emitting element (ED) and improving light extraction efficiency. This makes it possible to provide a light-emitting display device that can optimize the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) suitable for a poll-less structure and improve light efficiency.

[0085] Figure 7 shows a plurality of subpixels in a display panel according to another embodiment of this specification. Figure 8 is a cross-sectional view taken along line III-III' shown in Figure 7 according to another embodiment of this specification. Figures 7 and 8 show another embodiment of this specification in which the configuration of the low-reflection pattern is modified in the light-emitting device described with reference to Figures 1 to 6. In the following description with reference to Figures 7 and 8, the same reference numerals are used for the remaining identical components except for the modified low-reflection pattern, and redundant descriptions are omitted or simplified.

[0086] Referring to Figures 7 and 8, the display panel 110 according to other embodiments of this specification may include first and second low-reflection patterns (LPs) consisting of island patterns extending in different directions in at least one light-emitting region (EA1, EA2, EA3, EA4) of a plurality of subpixels (SP1, SP2, SP3, SP4). The first and second low-reflection patterns (LP1, LP2) may be arranged in some or all of the plurality of subpixels (SP1, SP2, SP3, SP4).

[0087] Referring to Figure 7, the first and second low-reflectance patterns (LP1, LP2) according to other embodiments of this specification may be island patterns that are separated from each data line (DL1, DL2, DL3, DL4) and extend in a first direction (or X-axis direction) or a second direction (or Y-axis direction) in the light-emitting regions (EA1, EA2, EA3, EA4).

[0088] The first light-emitting region (EA1) of the first subpixel (SP1) is provided with at least one first low-reflection pattern (LP1) consisting of an island pattern extending in a second direction; the second light-emitting region (EA2) of the second subpixel (SP2) is provided with one or more second low-reflection patterns (LP2) consisting of an island pattern extending in a first direction; the third light-emitting region (EA3) of the third subpixel (SP3) is provided with at least one first low-reflection pattern (LP1) consisting of an island pattern extending in a second direction; and the fourth light-emitting region (EA4) of the fourth subpixel (SP4) is provided with one or more second low-reflection patterns (LP2) consisting of an island pattern extending in a first direction. For example, the first and second low-reflection patterns (LP1, LP2) may have one end and the other end electrically floating.

[0089] The first low-reflection patterns (LP1) located in the first and third light-emitting regions (EA1, EA3) are positioned in the center of each light-emitting region (EA1, EA3) with respect to the first direction (or the X-axis direction), and the second low-reflection patterns (LP2) located in the second and fourth light-emitting regions (EA2, EA4) may be positioned multiple times on the upper and lower parts of each light-emitting region (EA2, EA4) with respect to the second direction (or the Y-axis direction).

[0090] According to other embodiments of this specification, one or more first low-reflectance patterns (LP1) are arranged in each light-emitting region (EA1, EA2, EA3, EA4), and one or more second low-reflectance patterns (LP2) are arranged in each light-emitting region (EA1, EA2, EA3, EA4), and the first and second low-reflectance patterns (LP1, LP2) may be arranged in some or all of the light-emitting regions (EA1, EA2, EA3, EA4), but the embodiments of this specification are not limited thereto.

[0091] Referring to Figure 8, the first and second low-reflection patterns (LP1, LP2) according to other embodiments of this specification may be arranged on the substrate 111. The first and second low-reflection patterns (LP1, LP2) may be constructed in the same material and on the same layer as the data lines (DL1, DL2, DL3, DL4) and the first power supply voltage line (VDDL) on the substrate 111. The first and second low-reflection patterns (LP1, LP2) may consist of electrically floating island patterns within each light-emitting region (EA1, EA2, EA3, EA4). The first and second low-reflection patterns (LP1, LP2) may be superimposed on at least one color filter (CF1, CF3, CF4) and on the pixel electrode (AE) of each sub-pixel (SP1, SP2, SP3, SP4). At least one color filter (CF1, CF3, CF4) may be placed between the pixel electrode (AE) and the first and second low-reflection patterns (LP1, LP2).

[0092] The lower parts of the first and second low-reflection patterns (LP1, LP2) include a low-reflection material layer (LM1) having a lower reflectivity than the pixel electrodes (AE) and common electrodes (CE). By reflecting or absorbing a portion of the external light incident from the outside through the lower parts of the first and second low-reflection patterns (LP1, LP2) with low reflectivity before reaching the pixel electrodes (AE), the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) can be reduced. Furthermore, a metal layer (M1) is placed above the first and second low-reflection patterns (LP1, LP2), which can induce internal re-reflection of light emitted from the light-emitting element (ED) through the upper parts of the first and second low-reflection patterns (LP1, LP2) to improve light extraction efficiency.

[0093] According to other embodiments of this specification, while maintaining an optimized area of ​​the light-emitting regions (EA1, EA2, EA3, EA4) so ​​as not to increase current density or cause a decrease in display quality such as afterimages, the reflectivity to incident light from the outside can be reduced through first and second low-reflection patterns (LP1, LP2) superimposed on the light-emitting regions (EA1, EA2, EA3, EA4), thereby inducing internal rereflection of light emitted from the light-emitting element (ED) and improving light extraction efficiency. This makes it possible to provide a light-emitting display device that can optimize the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) suitable for a poll-less structure and improve light efficiency.

[0094] Figure 9 shows a plurality of subpixels in a display panel according to another embodiment of this specification. Figure 10 is a cross-sectional view of the line IV-IV' shown in Figure 9 according to another embodiment of this specification. Figures 9 and 10 show another embodiment of this specification in which the configuration of the low-reflection pattern is modified in the light-emitting device described with reference to Figures 1 to 8. In the following description with reference to Figures 9 and 10, the same reference numerals are used for the remaining identical components except for the modified low-reflection pattern, and redundant descriptions are omitted or simplified.

[0095] Referring to Figures 9 and 10, the display panel 110 according to other embodiments of this specification may include first and second low-reflection patterns (LP1, LP2) superimposed on at least one light-emitting region (EA1, EA2, EA3, EA4) among a plurality of subpixels (SP1, SP2, SP3, SP4). The first and second low-reflection patterns (LP1, LP2) may be arranged on some or all of the plurality of subpixels (SP1, SP2, SP3, SP4).

[0096] Referring to Figure 9, the first and second low-reflectance patterns (LP1, LP2) according to other embodiments of this specification may be arranged to extend from each data line (DL1, DL2, DL3, DL4) on both sides in the first direction (or X-axis direction) and overlap with the light-emitting regions (EA1, EA2, EA3, EA4).

[0097] The first light-emitting region (EA1) of the first subpixel (SP1) has a first low-reflection pattern (LP1) extending to the right in the first direction from the first data line (DL1) and a second low-reflection pattern (LP2) extending to the left in the first direction from the second data line (DL2). The second light-emitting region (EA2) of the second subpixel (SP2) has a first low-reflection pattern (LP1) extending to the right in the first direction from the second data line (DL2) and a third low-reflection pattern extending to the left in the first direction from the third data line (DL3). A second low-reflection pattern (LP2) is arranged, and in the third light-emitting region (EA3) of the third subpixel (SP3), a first low-reflection pattern (LP1) extending to the right in the first direction from the third data line (DL3) and a second low-reflection pattern (LP2) extending to the left in the first direction from the fourth data line (DL4) are arranged, and in the fourth light-emitting region (EA4) of the fourth subpixel (SP4), a first low-reflection pattern (LP1) extending to the right in the first direction from the fourth data line (DL4) may be arranged. For example, one end of the first and second low-reflection patterns (LP1, LP2) may be integrally connected to each data line (DL1, DL2, DL3, DL4), and the other end of the first and second low-reflection patterns (LP1, LP2) may be electrically floating.

[0098] The first and second low-reflection patterns (LP1, LP2) extending from the first and third data lines (DL1, DL3) are positioned above each light-emitting region (EA1, EA2, EA3) based on the second direction (or Y-axis direction), and the first and second low-reflection patterns (LP1, LP2) extending from the second and fourth data lines (DL2, DL4) may be positioned below each light-emitting region (EA1, EA2, EA3, EA4) with respect to the second direction.

[0099] According to other embodiments of this specification, one or more of the first and second low-reflection patterns (LP1, LP2) may extend from each data line (DL1, DL2, DL3, DL4), and the first and second low-reflection patterns (LP1, LP2) may be placed in one or more of each light-emitting region (EA1, EA2, EA3, EA4). The first and second low-reflection patterns (LP1, LP2) may be placed in only a portion of the light-emitting regions (EA1, EA2, EA3, EA4), but the embodiments of this specification are not limited thereto.

[0100] Referring to Figure 10, the first and second low-reflection patterns (LP1, LP2) according to other embodiments of this specification may be arranged on the substrate 111. The first and second low-reflection patterns (LP1, LP2) may be constructed in the same layer as the data lines (DL1, DL2, DL3, DL4) and the first power supply voltage line (VDDL) on the substrate 111 using the same material. One end of the first and second low-reflection patterns (LP1, LP2) may be connected to each data line (DL1, DL2, DL3, DL4), and the other end of the first and second low-reflection patterns (LP1, LP2) may be electrically floating. The first and second low-reflection patterns (LP1, LP2) may be superimposed on at least one color filter (CF1, CF3, CF4) and on the pixel electrodes (AE) of each sub-pixel (SP1, SP2, SP3, SP4). At least one color filter (CF1, CF3, CF4) may be placed between the pixel electrode (AE) and the first and second low-reflection patterns (LP1, LP2).

[0101] The lower parts of the first and second low-reflection patterns (LP1, LP2) include a low-reflection material layer (LM1) having a lower reflectivity than the pixel electrodes (AE) and common electrodes (CE). By reflecting or absorbing a portion of the external light incident from the outside through the lower parts of the first and second low-reflection patterns (LP1, LP2) with low reflectivity before reaching the pixel electrodes (AE), the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) can be reduced. Furthermore, a metal layer (M1) is placed above the first and second low-reflection patterns (LP1, LP2), which can induce internal re-reflection of light emitted from the light-emitting element (ED) through the upper parts of the first and second low-reflection patterns (LP1, LP2) to improve light extraction efficiency.

[0102] According to other embodiments of this specification, while maintaining an optimized area of ​​the light-emitting regions (EA1, EA2, EA3, EA4) so ​​as not to increase current density or cause a decrease in display quality such as afterimages, the reflectivity to light incident from the outside can be reduced through first and second low-reflection patterns (LP1, LP2) superimposed on the light-emitting regions (EA1, EA2, EA3, EA4), thereby inducing internal rereflection of light emitted from the light-emitting element (ED) and improving light extraction efficiency. This makes it possible to provide a light-emitting display device that can optimize the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) suitable for a poll-less structure and improve light efficiency.

[0103] Figure 11 shows a plurality of subpixels in a display panel according to another embodiment of this specification. Figure 12 is a cross-sectional view of the line V-V' shown in Figure 11 according to another embodiment of this specification. Figures 11 and 12 show another embodiment of this specification in which the configuration of the low-reflection pattern is modified in the light-emitting device described with reference to Figures 1 to 10. In the following description with reference to Figures 11 and 12, the same reference numerals are used for the remaining identical components except for the modified low-reflection pattern, and redundant descriptions are omitted or simplified.

[0104] Referring to Figures 11 and 12, the display panel 110 according to other embodiments of this specification may include a low-reflection pattern (LP) extending in a second direction (or Y-axis direction) from the scan line (SL) in at least one light-emitting region (EA1, EA2, EA3, EA4) among a plurality of subpixels (SP1, SP2, SP3, SP4).

[0105] Referring to Figure 11, low-reflection patterns (LPs) according to other embodiments of this specification may be arranged to extend from at least one scan line (SL) (or gate line) in a second direction (or Y-axis direction) and overlap with the light-emitting regions (EA1, EA2, EA3, EA4).

[0106] The first light-emitting region (EA1) of the first subpixel (SP1) may have a low-reflection pattern (LP) extending in a second direction from at least one scan line (SL); the second light-emitting region (EA2) of the second subpixel (SP2) may have a low-reflection pattern (LP) extending in a second direction from at least one scan line (SL); the third light-emitting region (EA3) of the third subpixel (SP3) may have a low-reflection pattern (LP) extending in a second direction from at least one scan line (SL); and the fourth light-emitting region (EA4) of the fourth subpixel (SP4) may have a low-reflection pattern (LP) extending in a second direction from at least one scan line (SL).

[0107] The low-reflection patterns (LPs) placed in each light-emitting region (EA1, EA2, EA3, EA4) may be positioned to the left of each light-emitting region (EA1, EA2, EA3, EA4) with reference to the first direction (or the X-axis direction).

[0108] In other embodiments of this specification, one or more low-reflection patterns (LPs) may be placed in each light-emitting region (EA1, EA2, EA3, EA4), and the low-reflection patterns (LPs) may be placed in some or all of the light-emitting regions (EA1, EA2, EA3, EA4), but the embodiments of this specification are not limited thereto.

[0109] Referring to Figure 12, low-reflection patterns (LPs) according to other embodiments herein may be located on a buffer layer (BF). The low-reflection pattern (LP) may be constructed in the same layer as at least one scan line (SL) on the buffer layer (BF) using the same material. The low-reflection pattern (LP) may include a low-reflection material layer for low reflection of external light. The low-reflection pattern (LP) may include a conductive metal layer (M2) and a low-reflection material layer (LM2) beneath the metal layer (M2). For example, the metal layer (M2) may consist of a single or multiple layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but the embodiments herein are not limited thereto. The low-reflection material layer (LM2) is a metal layer with excellent low-reflection properties and may consist of molybdenum-titanium (MoTi) or molybdenum (Mo), or may contain metal oxides or alloy oxides. For example, the low-reflection material layer (LM2) may contain copper oxide (CuOx), nickel oxide (NiOx), molybdenum oxide (MoOx), or tungsten oxide (WOx), but the examples herein are not limited to these. For example, the low-reflection pattern (LP) may consist of copper (Cu) and molybdenum-titanium (MoTi), or it may be a bilayer structure consisting of copper (Cu) and a metal oxide.

[0110] One end of the low-reflection pattern (LP) is connected to at least one scan line (SL), and the other end of the low-reflection pattern (LP) may be electrically floating. The low-reflection pattern (LP) may be superimposed on at least one color filter (CF1, CF3, CF4) and on the pixel electrode (AE) of each subpixel (SP1, SP2, SP3, SP4). At least one color filter (CF1, CF3, CF4) may be placed between the pixel electrode (AE) and the low-reflection pattern (LP).

[0111] The lower part of the low-reflection pattern (LP) includes a low-reflection material layer (LM2) having a lower reflectivity than the pixel electrodes (AE) and common electrodes (CE). By reflecting or absorbing a portion of the external light incident from the outside through the lower part of the low-reflection pattern (LP) with low reflectivity before reaching the pixel electrodes (AE), the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) can be reduced. Furthermore, the upper part of the low-reflection pattern (LP) has a metal layer (M2) which can induce internal re-reflection of light emitted from the light-emitting element (ED) through the upper part of the low-reflection pattern (LP) to improve light extraction efficiency.

[0112] According to other embodiments of this specification, while maintaining an optimized area of ​​the light-emitting regions (EA1, EA2, EA3, EA4) so ​​as not to increase current density or cause a decrease in display quality such as afterimages, the reflectivity to light incident from the outside can be reduced through a low-reflection pattern (LP) superimposed on the light-emitting regions (EA1, EA2, EA3, EA4), thereby inducing internal rereflection of light emitted by the light-emitting elements (ED) and improving light extraction efficiency. This makes it possible to provide a light-emitting display device that can optimize the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) suitable for a poll-less structure and improve light efficiency.

[0113] Figure 13 shows a plurality of subpixels in a display panel according to another embodiment of this specification. Figure 14 is a cross-sectional view of the line VI-VI' shown in Figure 13 according to another embodiment of this specification. Figures 13 and 14 show another embodiment of this specification in which the configuration of the low-reflection pattern is modified in the light-emitting device described with reference to Figures 1 to 12. In the following description with reference to Figures 13 and 14, the same reference numerals are used for the remaining identical components except for the modified low-reflection pattern, and redundant descriptions are omitted or simplified.

[0114] Referring to Figures 13 and 14, the display panel 110 according to other embodiments of this specification may include a low-reflection pattern (LP) consisting of an island pattern extending in a first direction (or the X-axis direction) in at least one light-emitting region (EA1, EA2, EA3, EA4) of a plurality of subpixels (SP1, SP2, SP3, SP4). For example, the low-reflection pattern (LP) may consist of an island pattern extending in a second direction (or the Y-axis direction). The low-reflection pattern (LP) may also be arranged in some or all of the plurality of subpixels (SP1, SP2, SP3, SP4).

[0115] Referring to Figure 13, the low-reflection patterns (LPs) according to other embodiments herein may be island patterns that are separated from at least one scan line (SL) and extend in a first direction (or X-axis direction) in the light-emitting regions (EA1, EA2, EA3, EA4).

[0116] The first light-emitting region (EA1) of the first subpixel (SP1) may have at least one low-reflection pattern (LP) consisting of an island pattern extending in a first direction, the second light-emitting region (EA2) of the second subpixel (SP2) may have at least one low-reflection pattern (LP) consisting of an island pattern extending in a first direction, the third light-emitting region (EA3) of the third subpixel (SP3) may have at least one low-reflection pattern (LP) consisting of an island pattern extending in a first direction, and the fourth light-emitting region (EA4) of the fourth subpixel (SP4) may have at least one low-reflection pattern (LP) consisting of an island pattern extending in a first direction. For example, one end and the other end of the low-reflection pattern (LP) may be electrically floating.

[0117] The low-reflection patterns (LPs) located in the first and third light-emitting regions (EA1, EA3) are positioned above each light-emitting region (EA1, EA3) with respect to the second direction (or the Y-axis direction), and the low-reflection patterns (LPs) located in the second and fourth light-emitting regions (EA2, EA4) may be positioned below each light-emitting region (EA2, EA4) with respect to the second direction.

[0118] In other embodiments of this specification, one or more low-reflection patterns (LPs) may be placed in each light-emitting region (EA1, EA2, EA3, EA4), and the low-reflection patterns (LPs) may be placed in some or all of the light-emitting regions (EA1, EA2, EA3, EA4), but the embodiments of this specification are not limited thereto.

[0119] Referring to Figure 14, the low-reflection patterns (LPs) according to other embodiments herein may be placed on a buffer layer (BF). The low-reflection patterns (LPs) may be constructed in the same layer as at least one scan line (SL) on the buffer layer (BF) using the same material. The low-reflection patterns (LPs) may consist of electrically floating island patterns within each light-emitting region (EA1, EA2, EA3, EA4). The low-reflection patterns (LPs) may be superimposed on at least one color filter (CF1, CF3, CF4) and on the pixel electrodes (AEs) of each subpixel (SP1, SP2, SP3, SP4). At least one color filter (CF1, CF3, CF4) may be placed between the pixel electrodes (AEs) and the low-reflection patterns (LPs).

[0120] The lower part of the low-reflection pattern (LP) includes a low-reflection material layer (LM2) having a lower reflectivity than the pixel electrodes (AE) and common electrodes (CE). By reflecting or absorbing a portion of the external light incident from the outside through the lower part of the low-reflection pattern (LP) with low reflectivity before reaching the pixel electrodes (AE), the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) can be reduced. Furthermore, a metal layer (M2) is placed above the low-reflection pattern (LP), which can improve light extraction efficiency by inducing internal re-reflection of light emitted from the light-emitting element (ED) through the upper part of the low-reflection pattern (LP).

[0121] According to other embodiments of this specification, it is possible to improve light extraction efficiency by inducing re-reflection of light incident from the outside through a low-reflection pattern (LP) superimposed on the light-emitting regions (EA1, EA2, EA3, EA4) while maintaining an optimized area of ​​the light-emitting regions (EA1, EA2, EA3, EA4) so ​​as not to increase current density or cause a decrease in display quality such as afterimages. This makes it possible to provide a light-emitting display device that can optimize the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) suitable for a poll-less structure and improve light efficiency.

[0122] Figure 15 shows a plurality of subpixels in a display panel according to another embodiment of this specification. Figure 16 is a cross-sectional view of the line VII-VII' shown in Figure 15 according to another embodiment of this specification. Figures 15 and 16 show another embodiment of this specification in which the configuration of the low-reflection pattern is modified in the light-emitting device described with reference to Figures 1 to 14. In the following description with reference to Figures 15 and 16, the same reference numerals are used for the remaining identical components, except for the modified low-reflection pattern, and redundant descriptions are omitted or simplified.

[0123] Referring to Figures 15 and 16, the display panel 110 according to other embodiments of this specification may include first and second low-reflection patterns (LP1, LP2) superimposed on at least one light-emitting region (EA1, EA2, EA3, EA4) of a plurality of subpixels (SP1, SP2, SP3, SP4). The first and second low-reflection patterns (LP1, LP2) may be arranged on some or all of the plurality of subpixels (SP1, SP2, SP3, SP4).

[0124] Referring to Figure 15, a first low-reflection pattern (LP1) according to other embodiments herein may be positioned to extend from each data line (DL1, DL2, DL3, DL4) in a first direction (or X-axis direction) and overlap with the light-emitting regions (EA1, EA2, EA3, EA4). A second low-reflection pattern (SL2) may be an island pattern separated from at least one scan line (SL) and extending in a first direction (or X-axis direction) within the light-emitting regions (EA1, EA2, EA3, EA4).

[0125] In the first light-emitting region (EA1) of the first subpixel (SP1), a second low-reflection pattern (LP2) consisting of a first low-reflection pattern (LP1) extending in a first direction from the first data line (DL1) and an island pattern extending in the first direction is arranged; in the second light-emitting region (EA2) of the second subpixel (SP2), a second low-reflection pattern (LP2) consisting of a first low-reflection pattern (LP1) extending in a first direction from the second data line (DL2) and an island pattern extending in the first direction is arranged. The third light-emitting region (EA3) of the third subpixel (SP3) is provided with a first low-reflection pattern (LP1) extending in a first direction from the third data line (DL3) and a second low-reflection pattern (LP2) consisting of an island pattern extending in the first direction. The fourth light-emitting region (EA4) of the fourth subpixel (SP4) may be provided with a first low-reflection pattern (LP1) extending in a first direction from the fourth data line (DL4) and a second low-reflection pattern (LP2) consisting of an island pattern extending in the first direction.

[0126] The first low-reflection patterns (LP1) extending from the first and third data lines (DL1, DL3) may be positioned above each light-emitting region (EA1, EA3) with reference to the second direction (or Y-axis direction), and the first low-reflection patterns (LP1) extending from the second and fourth data lines (DL2, DL4) may be positioned below each light-emitting region (EA2, EA4) with reference to the second direction. Furthermore, the second low-reflection patterns (LP2) positioned in the first and third light-emitting regions (EA1, EA3) may be positioned below each light-emitting region (EA1, EA3) with reference to the second direction, and the second low-reflection patterns (LP2) positioned in the second and fourth light-emitting regions (EA2, EA4) may be positioned above each light-emitting region (EA2, EA4) with reference to the second direction.

[0127] Other embodiments of this specification may include, but are not limited thereto, one or more first low-reflectance patterns (LP1) extending from each data line (DL1, DL2, DL3, DL4), one or more first and second low-reflectance patterns (LP1, LP2) being arranged in each light-emitting region (EA1, EA2, EA3, EA4), and the first and second low-reflectance patterns (LP1, LP2) being arranged in only a portion of the light-emitting regions (EA1, EA2, EA3, EA4).

[0128] Referring to Figure 16, in other embodiments herein, the first low-reflection pattern (LP1) may be placed on the substrate 111, and the second low-reflection pattern (LP2) may be placed on the buffer layer (BF). The first low-reflection pattern (LP1) may be made of the same material and in the same layer as the data lines (DL1, DL2, DL3, DL4) and the first power supply voltage line (VDDL) on the substrate 111. The second low-reflection pattern (LP2) may be made of the same material and in the same layer as at least one scan line (SL) on the buffer layer (BF). One end of the first low-reflection pattern (LP1) may be connected to each data line (DL1, DL2, DL3, DL4), and the other end of the first low-reflection pattern (LP1) may be electrically floating. The second low-reflection pattern (LP2) may also consist of an electrically floating island pattern within each light-emitting region (EA1, EA2, EA3, EA4). The first and second low-reflection patterns (LP1, LP2) may be superimposed on at least one color filter (CF1, CF3, CF4) and on the pixel electrode (AE) of each subpixel (SP1, SP2, SP3, SP4). At least one color filter (CF1, CF3, CF4) may be placed between the pixel electrode (AE) and the first and second low-reflection patterns (LP1, LP2).

[0129] The lower parts of the first and second low-reflection patterns (LP1, LP2) include low-reflection material layers (LM1, LM2) having a lower reflectivity than the pixel electrodes (AE) and common electrodes (CE). By reflecting or absorbing a portion of the external light incident from the outside through the lower parts of the first and second low-reflection patterns (LP1, LP2) with low reflectivity before reaching the pixel electrodes (AE), the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) can be reduced. Furthermore, the upper parts of the first and second low-reflection patterns (LP1, LP2) are arranged with metal layers (M1, M2), which can induce internal re-reflection of light emitted from the light-emitting element (ED) through the upper parts of the first and second low-reflection patterns (LP1, LP2) to improve light extraction efficiency.

[0130] According to other embodiments of this specification, while maintaining an optimized area of ​​the light-emitting regions (EA1, EA2, EA3, EA4) so ​​as not to increase current density or cause a decrease in display quality such as afterimages, the reflectivity to light incident from the outside can be reduced through first and second low-reflection patterns (LP1, LP2) superimposed on the light-emitting regions (EA1, EA2, EA3, EA4), thereby inducing internal rereflection of light emitted from the light-emitting element (ED) and improving light extraction efficiency. This makes it possible to provide a light-emitting display device that can optimize the cell reflectivity of the light-emitting regions (EA1, EA2, EA3, EA4) suitable for a poll-less structure and improve light efficiency.

[0131] A light-emitting display device according to one or more embodiments of this specification can be described as follows:

[0132] A light-emitting display device according to one or more embodiments of this specification includes a substrate containing a plurality of subpixels having light-emitting regions and non-light-emitting regions; data lines and gate lines arranged in the non-light-emitting regions on the substrate and intersecting each other; at least one insulating layer arranged on the data lines and gate lines; and a color filter arranged on at least one insulating layer and corresponding to at least one of the plurality of subpixels, wherein at least one or more of the plurality of subpixels may include a low-reflection pattern superimposed on the light-emitting region.

[0133] According to one or more examples of this specification, a low-reflection pattern may include a low-reflection material layer.

[0134] According to one or more embodiments of this specification, a low-reflection pattern may be superimposed on a color filter.

[0135] According to one or more embodiments of this specification, a low-reflection pattern may be constructed in the same layer as at least one of the data lines or gate lines, using the same material.

[0136] According to one or more embodiments of this specification, the low-reflectance pattern may be linked to or separated from the data line.

[0137] According to one or more embodiments of this specification, the low-reflection pattern may be connected to or separated from the gate line.

[0138] According to one or more examples of this specification, the low-reflection pattern may include a metal layer and a low-reflection material layer beneath the metal layer.

[0139] According to one or more embodiments of this specification, each subpixel includes a light-emitting element comprising a pixel electrode, a light-emitting layer, and a common electrode, and the light-emitting region may be superimposed on the light-emitting element.

[0140] According to one or more embodiments of this specification, the low-reflection pattern may be superimposed on the pixel electrode, and the color filter may be placed between the pixel electrode and the low-reflection pattern.

[0141] According to one or more embodiments of this specification, each subpixel includes a pixel circuit having at least one thin-film transistor and a capacitor, and the non-emitting region may include a first non-emitting region where the pixel circuit is located and a second non-emitting region between adjacent subpixels.

[0142] According to one or more embodiments of this specification, the gate line may extend in a first direction in a first non-emitting region, and the data line may extend in a second direction intersecting the first direction in a second non-emitting region.

[0143] According to one or more embodiments of this specification, a low-reflection pattern may be positioned to extend from the data line in a first direction and overlap with the light-emitting region.

[0144] According to one or more embodiments of this specification, one end of the low-reflection pattern may be connected to a data line, and the other end of the low-reflection pattern may be electrically floating.

[0145] According to one or more embodiments of this specification, the low-reflection pattern may be an island pattern that is separated from the data line and extends in a first or second direction in the light-emitting region.

[0146] According to one or more embodiments of this specification, the low-reflection pattern may be positioned to extend from the gate line in a second direction and overlap with the light-emitting region.

[0147] According to one or more embodiments of this specification, one end of the low-reflection pattern may be connected to a gate line, and the other end of the low-reflection pattern may be electrically floating.

[0148] According to one or more embodiments of this specification, the low-reflection pattern may be an island pattern that is separated from the gate line and extends in a first or second direction in the light-emitting region.

[0149] According to one or more embodiments of this specification, the system further includes a bank portion that defines the light-emitting region of each subpixel, the bank portion being located between the pixel electrode and the light-emitting layer.

[0150] According to one or more examples of this specification, the bank portion may include at least one of a light-absorbing substance and a black substance.

[0151] According to one or more embodiments of this specification, a transmittance control film disposed on the back surface of the substrate may further be included.

[0152] According to one or more examples of this specification, the transmittance control film may include at least one of a transparent film or an absorbent film.

[0153] Although embodiments of this specification have been described in more detail above with reference to the attached figures, this specification is not necessarily limited to such embodiments, and can be modified and implemented in various ways without departing from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and such embodiments do not limit the scope of the technical concept of this specification. Accordingly, the embodiments described above should be understood in all respects to be illustrative and not limiting. The scope of protection of this specification should be interpreted as per the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this specification. [Explanation of symbols]

[0154] 110: Display Panel 120: Scan drive unit 130: Data-driven unit 160: Timing Control Unit 170: Power supply circuit

Claims

1. A substrate including a plurality of subpixels having light-emitting regions and non-light-emitting regions, Arranged in the non-emitting region on the substrate, data lines and gate lines intersecting each other, At least one insulating layer disposed on the data line and the gate line, Disposed on the at least one insulating layer and a color filter corresponding to at least one of the plurality of subpixels Includes, One or more of the aforementioned subpixels include a low-reflection pattern superimposed on the light-emitting region, Light-emitting display device.

2. The light-emitting device according to claim 1, wherein the low-reflection pattern includes a low-reflection material layer.

3. The light-emitting display device according to claim 1, wherein the low-reflection pattern is superimposed on the color filter.

4. The light-emitting device according to claim 1, wherein the low-reflection pattern is formed in the same layer as at least one of the data lines and the gate lines using the same material.

5. The light-emitting display device according to claim 4, wherein the low-reflection pattern is connected to or separated from the data line.

6. The light-emitting display device according to claim 4, wherein the low-reflection pattern is connected to or separated from the gate line.

7. The light-emitting device according to claim 1, wherein the low-reflection pattern includes a metal layer and a low-reflection material layer beneath the metal layer.

8. Each of the subpixels includes a light-emitting element consisting of a pixel electrode, a light-emitting layer, and a common electrode. The light-emitting region is superimposed on the light-emitting element. The light-emitting display device according to claim 1.

9. The low-reflection pattern is superimposed on the pixel electrode, The color filter is positioned between the pixel electrode and the low-reflection pattern. The light-emitting display device according to claim 8.

10. Each of the subpixels includes a pixel circuit having at least one thin-film transistor and a capacitor, The light-emitting display device according to claim 1, wherein the non-light-emitting region includes a first non-light-emitting region in which the pixel circuit is arranged and a second non-light-emitting region between adjacent sub-pixels.

11. The gate line extends in a first direction in the first non-emitting region, The light-emitting display device according to claim 10, wherein the data line extends in a second direction that intersects the first direction in the second non-light-emitting region.

12. The light-emitting device according to claim 11, wherein the low-reflection pattern is arranged to extend from the data line in the first direction and overlap with the light-emitting region.

13. One end of the low-reflection pattern is connected to the data line, The other end of the low-reflection pattern is electrically floating. The light-emitting display device according to claim 12.

14. The low-reflection pattern is separated from the data line, The low-reflection pattern is an island pattern extending in the first or second direction within the light-emitting region. The light-emitting display device according to claim 11.

15. The light-emitting device according to claim 11, wherein the low-reflection pattern is arranged to extend from the gate line in the second direction and overlap with the light-emitting region.

16. One end of the low-reflection pattern is connected to the gate line, The other end of the low-reflection pattern is electrically floating. The light-emitting display device according to claim 15.

17. The low-reflection pattern is spaced away from the gate line, The low-reflection pattern is an island pattern extending in the first or second direction within the light-emitting region. The light-emitting display device according to claim 11.

18. The system further includes a bank section that defines the light-emitting region of each of the subpixels, The bank portion is disposed between the pixel electrode and the light-emitting layer. The light-emitting display device according to claim 8.

19. The light-emitting device according to claim 18, wherein the bank portion includes at least one of a light-absorbing substance and a black substance.

20. The light-emitting device according to claim 1, further comprising a transmittance control film disposed on the back surface of the substrate.

21. The light-emitting device according to claim 20, wherein the transmittance control film includes at least one of a transparent film and a light-absorbing film.

22. The low-reflection pattern includes a metal layer and a low-reflection material layer beneath the metal layer. The low-reflectance material layer has a lower reflectivity than the pixel electrode and the common electrode, respectively. The light-emitting display device according to claim 8.

Images